getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #ifdef linux
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_ITANIUM2       */
 135 /* #define FORCE_SPARC          */
 136 /* #define FORCE_SPARCV7        */
 137 /* #define FORCE_GENERIC        */
 138
 139 #ifdef FORCE_P2
 140 #define FORCE
 141 #define FORCE_INTEL
 142 #define ARCHITECTURE    "X86"
 143 #define SUBARCHITECTURE "PENTIUM2"
 144 #define ARCHCONFIG   "-DPENTIUM2 " \
 145                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 146                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 147                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 148                      "-DHAVE_CMOV -DHAVE_MMX"
 149 #define LIBNAME   "p2"
 150 #define CORENAME  "P5"
 151 #endif
 152
 153 #ifdef FORCE_KATMAI
 154 #define FORCE
 155 #define FORCE_INTEL
 156 #define ARCHITECTURE    "X86"
 157 #define SUBARCHITECTURE "PENTIUM3"
 158 #define ARCHCONFIG   "-DPENTIUM3 " \
 159                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 160                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 161                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 162                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 163 #define LIBNAME   "katmai"
 164 #define CORENAME  "KATMAI"
 165 #endif
 166
 167 #ifdef FORCE_COPPERMINE
 168 #define FORCE
 169 #define FORCE_INTEL
 170 #define ARCHITECTURE    "X86"
 171 #define SUBARCHITECTURE "PENTIUM3"
 172 #define ARCHCONFIG   "-DPENTIUM3 " \
 173                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 174                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 175                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 176                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 177 #define LIBNAME   "coppermine"
 178 #define CORENAME  "COPPERMINE"
 179 #endif
 180
 181 #ifdef FORCE_NORTHWOOD
 182 #define FORCE
 183 #define FORCE_INTEL
 184 #define ARCHITECTURE    "X86"
 185 #define SUBARCHITECTURE "PENTIUM4"
 186 #define ARCHCONFIG   "-DPENTIUM4 " \
 187                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 188                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 189                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 190                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 191 #define LIBNAME   "northwood"
 192 #define CORENAME  "NORTHWOOD"
 193 #endif
 194
 195 #ifdef FORCE_PRESCOTT
 196 #define FORCE
 197 #define FORCE_INTEL
 198 #define ARCHITECTURE    "X86"
 199 #define SUBARCHITECTURE "PENTIUM4"
 200 #define ARCHCONFIG   "-DPENTIUM4 " \
 201                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 202                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 203                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 204                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 205 #define LIBNAME   "prescott"
 206 #define CORENAME  "PRESCOTT"
 207 #endif
 208
 209 #ifdef FORCE_BANIAS
 210 #define FORCE
 211 #define FORCE_INTEL
 212 #define ARCHITECTURE    "X86"
 213 #define SUBARCHITECTURE "BANIAS"
 214 #define ARCHCONFIG   "-DPENTIUMM " \
 215                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 216                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 217                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 218                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 219 #define LIBNAME   "banias"
 220 #define CORENAME  "BANIAS"
 221 #endif
 222
 223 #ifdef FORCE_YONAH
 224 #define FORCE
 225 #define FORCE_INTEL
 226 #define ARCHITECTURE    "X86"
 227 #define SUBARCHITECTURE "YONAH"
 228 #define ARCHCONFIG   "-DPENTIUMM " \
 229                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 230                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 231                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 232                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 233 #define LIBNAME   "yonah"
 234 #define CORENAME  "YONAH"
 235 #endif
 236
 237 #ifdef FORCE_CORE2
 238 #define FORCE
 239 #define FORCE_INTEL
 240 #define ARCHITECTURE    "X86"
 241 #define SUBARCHITECTURE "CONRORE"
 242 #define ARCHCONFIG   "-DCORE2 " \
 243                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 244                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 245                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 246                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 247 #define LIBNAME   "core2"
 248 #define CORENAME  "CORE2"
 249 #endif
 250
 251 #ifdef FORCE_PENRYN
 252 #define FORCE
 253 #define FORCE_INTEL
 254 #define ARCHITECTURE    "X86"
 255 #define SUBARCHITECTURE "PENRYN"
 256 #define ARCHCONFIG   "-DPENRYN " \
 257                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 258                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 259                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 260                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 261 #define LIBNAME   "penryn"
 262 #define CORENAME  "PENRYN"
 263 #endif
 264
 265 #ifdef FORCE_DUNNINGTON
 266 #define FORCE
 267 #define FORCE_INTEL
 268 #define ARCHITECTURE    "X86"
 269 #define SUBARCHITECTURE "DUNNINGTON"
 270 #define ARCHCONFIG   "-DDUNNINGTON " \
 271                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 272                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 273                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 274                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 275                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 276 #define LIBNAME   "dunnington"
 277 #define CORENAME  "DUNNINGTON"
 278 #endif
 279
 280 #ifdef FORCE_NEHALEM
 281 #define FORCE
 282 #define FORCE_INTEL
 283 #define ARCHITECTURE    "X86"
 284 #define SUBARCHITECTURE "NEHALEM"
 285 #define ARCHCONFIG   "-DNEHALEM " \
 286                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 287                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 288                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 289                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 290 #define LIBNAME   "nehalem"
 291 #define CORENAME  "NEHALEM"
 292 #endif
 293
 294 #ifdef FORCE_SANDYBRIDGE
 295 #define FORCE
 296 #define FORCE_INTEL
 297 #define ARCHITECTURE    "X86"
 298 #define SUBARCHITECTURE "SANDYBRIDGE"
 299 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 300                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 301                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 302                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 303                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 304 #define LIBNAME   "sandybridge"
 305 #define CORENAME  "SANDYBRIDGE"
 306 #endif
 307
 308 #ifdef FORCE_HASWELL
 309 #define FORCE
 310 #define FORCE_INTEL
 311 #define ARCHITECTURE    "X86"
 312 #define SUBARCHITECTURE "HASWELL"
 313 #define ARCHCONFIG   "-DHASWELL " \
 314                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 315                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 316                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 317                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 318                      "-DFMA3"
 319 #define LIBNAME   "haswell"
 320 #define CORENAME  "HASWELL"
 321 #endif
 322
 323 #ifdef FORCE_ATOM
 324 #define FORCE
 325 #define FORCE_INTEL
 326 #define ARCHITECTURE    "X86"
 327 #define SUBARCHITECTURE "ATOM"
 328 #define ARCHCONFIG   "-DATOM " \
 329                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 330                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 331                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 332                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 333 #define LIBNAME   "atom"
 334 #define CORENAME  "ATOM"
 335 #endif
 336
 337 #ifdef FORCE_ATHLON
 338 #define FORCE
 339 #define FORCE_INTEL
 340 #define ARCHITECTURE    "X86"
 341 #define SUBARCHITECTURE "ATHLON"
 342 #define ARCHCONFIG   "-DATHLON " \
 343                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 344                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 345                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 346                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 347 #define LIBNAME   "athlon"
 348 #define CORENAME  "ATHLON"
 349 #endif
 350
 351 #ifdef FORCE_OPTERON
 352 #define FORCE
 353 #define FORCE_INTEL
 354 #define ARCHITECTURE    "X86"
 355 #define SUBARCHITECTURE "OPTERON"
 356 #define ARCHCONFIG   "-DOPTERON " \
 357                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 358                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 359                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 360                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 361 #define LIBNAME   "opteron"
 362 #define CORENAME  "OPTERON"
 363 #endif
 364
 365 #ifdef FORCE_OPTERON_SSE3
 366 #define FORCE
 367 #define FORCE_INTEL
 368 #define ARCHITECTURE    "X86"
 369 #define SUBARCHITECTURE "OPTERON"
 370 #define ARCHCONFIG   "-DOPTERON " \
 371                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 372                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 373                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 374                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 375 #define LIBNAME   "opteron"
 376 #define CORENAME  "OPTERON"
 377 #endif
 378
 379 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 380 #define FORCE
 381 #define FORCE_INTEL
 382 #define ARCHITECTURE    "X86"
 383 #define SUBARCHITECTURE "BARCELONA"
 384 #define ARCHCONFIG   "-DBARCELONA " \
 385                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 386                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 387                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 388                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 389                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 390 #define LIBNAME   "barcelona"
 391 #define CORENAME  "BARCELONA"
 392 #endif
 393
 394 #if defined(FORCE_BOBCAT)
 395 #define FORCE
 396 #define FORCE_INTEL
 397 #define ARCHITECTURE    "X86"
 398 #define SUBARCHITECTURE "BOBCAT"
 399 #define ARCHCONFIG   "-DBOBCAT " \
 400                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 401                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 402                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 403                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 404                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 405 #define LIBNAME   "bobcat"
 406 #define CORENAME  "BOBCAT"
 407 #endif
 408
 409 #if defined (FORCE_BULLDOZER)
 410 #define FORCE
 411 #define FORCE_INTEL
 412 #define ARCHITECTURE    "X86"
 413 #define SUBARCHITECTURE "BULLDOZER"
 414 #define ARCHCONFIG   "-DBULLDOZER " \
 415                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 416                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 417                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 418                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 419                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 420                      "-DHAVE_AVX -DHAVE_FMA4"
 421 #define LIBNAME   "bulldozer"
 422 #define CORENAME  "BULLDOZER"
 423 #endif
 424
 425 #if defined (FORCE_PILEDRIVER)
 426 #define FORCE
 427 #define FORCE_INTEL
 428 #define ARCHITECTURE    "X86"
 429 #define SUBARCHITECTURE "PILEDRIVER"
 430 #define ARCHCONFIG   "-DPILEDRIVER " \
 431                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 432                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 433                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 434                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 435                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 436                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 437 #define LIBNAME   "piledriver"
 438 #define CORENAME  "PILEDRIVER"
 439 #endif
 440
 441 #if defined (FORCE_STEAMROLLER)
 442 #define FORCE
 443 #define FORCE_INTEL
 444 #define ARCHITECTURE    "X86"
 445 #define SUBARCHITECTURE "STEAMROLLER"
 446 #define ARCHCONFIG   "-DSTEAMROLLER " \
 447                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 448                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 449                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 450                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 451                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 452                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 453 #define LIBNAME   "steamroller"
 454 #define CORENAME  "STEAMROLLER"
 455 #endif
 456
 457 #if defined (FORCE_EXCAVATOR)
 458 #define FORCE
 459 #define FORCE_INTEL
 460 #define ARCHITECTURE    "X86"
 461 #define SUBARCHITECTURE "EXCAVATOR"
 462 #define ARCHCONFIG   "-DEXCAVATOR " \
 463                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 464                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 465                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 466                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 467                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 468                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 469 #define LIBNAME   "excavator"
 470 #define CORENAME  "EXCAVATOR"
 471 #endif
 472
 473
 474 #ifdef FORCE_SSE_GENERIC
 475 #define FORCE
 476 #define FORCE_INTEL
 477 #define ARCHITECTURE    "X86"
 478 #define SUBARCHITECTURE "GENERIC"
 479 #define ARCHCONFIG   "-DGENERIC " \
 480                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 481                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 482                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 483                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 484 #define LIBNAME   "generic"
 485 #define CORENAME  "GENERIC"
 486 #endif
 487
 488 #ifdef FORCE_VIAC3
 489 #define FORCE
 490 #define FORCE_INTEL
 491 #define ARCHITECTURE    "X86"
 492 #define SUBARCHITECTURE "VIAC3"
 493 #define ARCHCONFIG   "-DVIAC3 " \
 494                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 495                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 496                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 497                      "-DHAVE_MMX -DHAVE_SSE "
 498 #define LIBNAME   "viac3"
 499 #define CORENAME  "VIAC3"
 500 #endif
 501
 502 #ifdef FORCE_NANO
 503 #define FORCE
 504 #define FORCE_INTEL
 505 #define ARCHITECTURE    "X86"
 506 #define SUBARCHITECTURE "NANO"
 507 #define ARCHCONFIG   "-DNANO " \
 508                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 509                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 510                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 511                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 512 #define LIBNAME   "nano"
 513 #define CORENAME  "NANO"
 514 #endif
 515
 516 #ifdef FORCE_POWER3
 517 #define FORCE
 518 #define ARCHITECTURE    "POWER"
 519 #define SUBARCHITECTURE "POWER3"
 520 #define SUBDIRNAME      "power"
 521 #define ARCHCONFIG   "-DPOWER3 " \
 522                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 523                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 524                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 525 #define LIBNAME   "power3"
 526 #define CORENAME  "POWER3"
 527 #endif
 528
 529 #ifdef FORCE_POWER4
 530 #define FORCE
 531 #define ARCHITECTURE    "POWER"
 532 #define SUBARCHITECTURE "POWER4"
 533 #define SUBDIRNAME      "power"
 534 #define ARCHCONFIG   "-DPOWER4 " \
 535                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 536                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 537                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 538 #define LIBNAME   "power4"
 539 #define CORENAME  "POWER4"
 540 #endif
 541
 542 #ifdef FORCE_POWER5
 543 #define FORCE
 544 #define ARCHITECTURE    "POWER"
 545 #define SUBARCHITECTURE "POWER5"
 546 #define SUBDIRNAME      "power"
 547 #define ARCHCONFIG   "-DPOWER5 " \
 548                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 549                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 550                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 551 #define LIBNAME   "power5"
 552 #define CORENAME  "POWER5"
 553 #endif
 554
 555 #if defined(FORCE_POWER6) || defined(FORCE_POWER7) || defined(FORCE_POWER8)
 556 #define FORCE
 557 #define ARCHITECTURE    "POWER"
 558 #define SUBARCHITECTURE "POWER6"
 559 #define SUBDIRNAME      "power"
 560 #define ARCHCONFIG   "-DPOWER6 " \
 561                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 562                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 563                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 564 #define LIBNAME   "power6"
 565 #define CORENAME  "POWER6"
 566 #endif
 567
 568 #ifdef FORCE_PPCG4
 569 #define FORCE
 570 #define ARCHITECTURE    "POWER"
 571 #define SUBARCHITECTURE "PPCG4"
 572 #define SUBDIRNAME      "power"
 573 #define ARCHCONFIG   "-DPPCG4 " \
 574                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 575                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 576                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 577 #define LIBNAME   "ppcg4"
 578 #define CORENAME  "PPCG4"
 579 #endif
 580
 581 #ifdef FORCE_PPC970
 582 #define FORCE
 583 #define ARCHITECTURE    "POWER"
 584 #define SUBARCHITECTURE "PPC970"
 585 #define SUBDIRNAME      "power"
 586 #define ARCHCONFIG   "-DPPC970 " \
 587                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 588                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 589                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 590 #define LIBNAME   "ppc970"
 591 #define CORENAME  "PPC970"
 592 #endif
 593
 594 #ifdef FORCE_PPC970MP
 595 #define FORCE
 596 #define ARCHITECTURE    "POWER"
 597 #define SUBARCHITECTURE "PPC970"
 598 #define SUBDIRNAME      "power"
 599 #define ARCHCONFIG   "-DPPC970 " \
 600                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 601                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 602                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 603 #define LIBNAME   "ppc970mp"
 604 #define CORENAME  "PPC970"
 605 #endif
 606
 607 #ifdef FORCE_PPC440
 608 #define FORCE
 609 #define ARCHITECTURE    "POWER"
 610 #define SUBARCHITECTURE "PPC440"
 611 #define SUBDIRNAME      "power"
 612 #define ARCHCONFIG   "-DPPC440 " \
 613                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 614                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 615                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 616 #define LIBNAME   "ppc440"
 617 #define CORENAME  "PPC440"
 618 #endif
 619
 620 #ifdef FORCE_PPC440FP2
 621 #define FORCE
 622 #define ARCHITECTURE    "POWER"
 623 #define SUBARCHITECTURE "PPC440FP2"
 624 #define SUBDIRNAME      "power"
 625 #define ARCHCONFIG   "-DPPC440FP2 " \
 626                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 627                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 628                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 629 #define LIBNAME   "ppc440FP2"
 630 #define CORENAME  "PPC440FP2"
 631 #endif
 632
 633 #ifdef FORCE_CELL
 634 #define FORCE
 635 #define ARCHITECTURE    "POWER"
 636 #define SUBARCHITECTURE "CELL"
 637 #define SUBDIRNAME      "power"
 638 #define ARCHCONFIG   "-DCELL " \
 639                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 640                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 641                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 642 #define LIBNAME   "cell"
 643 #define CORENAME  "CELL"
 644 #endif
 645
 646 #ifdef FORCE_SICORTEX
 647 #define FORCE
 648 #define ARCHITECTURE    "MIPS"
 649 #define SUBARCHITECTURE "SICORTEX"
 650 #define SUBDIRNAME      "mips"
 651 #define ARCHCONFIG   "-DSICORTEX " \
 652                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 653                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 654                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 655 #define LIBNAME   "mips"
 656 #define CORENAME  "sicortex"
 657 #endif
 658
 659
 660 #ifdef FORCE_LOONGSON3A
 661 #define FORCE
 662 #define ARCHITECTURE    "MIPS"
 663 #define SUBARCHITECTURE "LOONGSON3A"
 664 #define SUBDIRNAME      "mips64"
 665 #define ARCHCONFIG   "-DLOONGSON3A " \
 666        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 667        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 668        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 669 #define LIBNAME   "loongson3a"
 670 #define CORENAME  "LOONGSON3A"
 671 #else
 672 #endif
 673
 674 #ifdef FORCE_LOONGSON3B
 675 #define FORCE
 676 #define ARCHITECTURE    "MIPS"
 677 #define SUBARCHITECTURE "LOONGSON3B"
 678 #define SUBDIRNAME      "mips64"
 679 #define ARCHCONFIG   "-DLOONGSON3B " \
 680        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 681        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 682        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 683 #define LIBNAME   "loongson3b"
 684 #define CORENAME  "LOONGSON3B"
 685 #else
 686 #endif
 687
 688 #ifdef FORCE_ITANIUM2
 689 #define FORCE
 690 #define ARCHITECTURE    "IA64"
 691 #define SUBARCHITECTURE "ITANIUM2"
 692 #define SUBDIRNAME      "ia64"
 693 #define ARCHCONFIG   "-DITANIUM2 " \
 694                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 695                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 696 #define LIBNAME   "itanium2"
 697 #define CORENAME  "itanium2"
 698 #endif
 699
 700 #ifdef FORCE_SPARC
 701 #define FORCE
 702 #define ARCHITECTURE    "SPARC"
 703 #define SUBARCHITECTURE "SPARC"
 704 #define SUBDIRNAME      "sparc"
 705 #define ARCHCONFIG   "-DSPARC -DV9 " \
 706                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 707                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 708 #define LIBNAME   "sparc"
 709 #define CORENAME  "sparc"
 710 #endif
 711
 712 #ifdef FORCE_SPARCV7
 713 #define FORCE
 714 #define ARCHITECTURE    "SPARC"
 715 #define SUBARCHITECTURE "SPARC"
 716 #define SUBDIRNAME      "sparc"
 717 #define ARCHCONFIG   "-DSPARC -DV7 " \
 718                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 719                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 720 #define LIBNAME   "sparcv7"
 721 #define CORENAME  "sparcv7"
 722 #endif
 723
 724 #ifdef FORCE_GENERIC
 725 #define FORCE
 726 #define ARCHITECTURE    "GENERIC"
 727 #define SUBARCHITECTURE "GENERIC"
 728 #define SUBDIRNAME      "generic"
 729 #define ARCHCONFIG   "-DGENERIC " \
 730                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 731                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 732                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 733 #define LIBNAME   "generic"
 734 #define CORENAME  "generic"
 735 #endif
 736
 737 #ifdef FORCE_ARMV7
 738 #define FORCE
 739 #define ARCHITECTURE    "ARM"
 740 #define SUBARCHITECTURE "ARMV7"
 741 #define SUBDIRNAME      "arm"
 742 #define ARCHCONFIG   "-DARMV7 " \
 743        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 744        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 745        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 746        "-DHAVE_VFPV3 -DHAVE_VFP"
 747 #define LIBNAME   "armv7"
 748 #define CORENAME  "ARMV7"
 749 #else
 750 #endif
 751
 752 #ifdef FORCE_CORTEXA9
 753 #define FORCE
 754 #define ARCHITECTURE    "ARM"
 755 #define SUBARCHITECTURE "CORTEXA9"
 756 #define SUBDIRNAME      "arm"
 757 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 758        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 759        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 760        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 761        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 762 #define LIBNAME   "cortexa9"
 763 #define CORENAME  "CORTEXA9"
 764 #else
 765 #endif
 766
 767 #ifdef FORCE_CORTEXA15
 768 #define FORCE
 769 #define ARCHITECTURE    "ARM"
 770 #define SUBARCHITECTURE "CORTEXA15"
 771 #define SUBDIRNAME      "arm"
 772 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 773        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 774        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 775        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 776        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 777 #define LIBNAME   "cortexa15"
 778 #define CORENAME  "CORTEXA15"
 779 #else
 780 #endif
 781
 782 #ifdef FORCE_ARMV6
 783 #define FORCE
 784 #define ARCHITECTURE    "ARM"
 785 #define SUBARCHITECTURE "ARMV6"
 786 #define SUBDIRNAME      "arm"
 787 #define ARCHCONFIG   "-DARMV6 " \
 788        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 789        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 790        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 791        "-DHAVE_VFP"
 792 #define LIBNAME   "armv6"
 793 #define CORENAME  "ARMV6"
 794 #else
 795 #endif
 796
 797 #ifdef FORCE_ARMV5
 798 #define FORCE
 799 #define ARCHITECTURE    "ARM"
 800 #define SUBARCHITECTURE "ARMV5"
 801 #define SUBDIRNAME      "arm"
 802 #define ARCHCONFIG   "-DARMV5 " \
 803        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 804        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 805        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 806 #define LIBNAME   "armv5"
 807 #define CORENAME  "ARMV5"
 808 #else
 809 #endif
 810
 811
 812 #ifdef FORCE_ARMV8
 813 #define FORCE
 814 #define ARCHITECTURE    "ARM64"
 815 #define SUBARCHITECTURE "ARMV8"
 816 #define SUBDIRNAME      "arm64"
 817 #define ARCHCONFIG   "-DARMV8 " \
 818        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 819        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 820        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 821 #define LIBNAME   "armv8"
 822 #define CORENAME  "XGENE1"
 823 #else
 824 #endif
 825
 826
 827 #ifndef FORCE
 828
 829 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 830     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 831 #ifndef POWER
 832 #define POWER
 833 #endif
 834 #define OPENBLAS_SUPPORTED
 835 #endif
 836
 837 #ifdef INTEL_AMD
 838 #include "cpuid_x86.c"
 839 #define OPENBLAS_SUPPORTED
 840 #endif
 841
 842 #ifdef __ia64__
 843 #include "cpuid_ia64.c"
 844 #define OPENBLAS_SUPPORTED
 845 #endif
 846
 847 #ifdef __alpha
 848 #include "cpuid_alpha.c"
 849 #define OPENBLAS_SUPPORTED
 850 #endif
 851
 852 #ifdef POWER
 853 #include "cpuid_power.c"
 854 #define OPENBLAS_SUPPORTED
 855 #endif
 856
 857 #ifdef sparc
 858 #include "cpuid_sparc.c"
 859 #define OPENBLAS_SUPPORTED
 860 #endif
 861
 862 #ifdef __mips__
 863 #include "cpuid_mips.c"
 864 #define OPENBLAS_SUPPORTED
 865 #endif
 866
 867 #ifdef __arm__
 868 #include "cpuid_arm.c"
 869 #define OPENBLAS_SUPPORTED
 870 #endif
 871
 872 #ifdef __aarch64__
 873 #include "cpuid_arm64.c"
 874 #define OPENBLAS_SUPPORTED
 875 #endif
 876
 877
 878 #ifndef OPENBLAS_SUPPORTED
 879 #error "This arch/CPU is not supported by OpenBLAS."
 880 #endif
 881
 882 #else
 883
 884 #endif
 885
 886 static int get_num_cores(void) {
 887
 888 #ifdef OS_WINDOWS
 889   SYSTEM_INFO sysinfo;
 890 #elif defined(__FreeBSD__) || defined(__APPLE__)
 891   int m[2], count;
 892   size_t len;
 893 #endif
 894
 895 #ifdef linux
 896   //returns the number of processors which are currently online
 897   return sysconf(_SC_NPROCESSORS_ONLN);
 898
 899 #elif defined(OS_WINDOWS)
 900
 901   GetSystemInfo(&sysinfo);
 902   return sysinfo.dwNumberOfProcessors;
 903
 904 #elif defined(__FreeBSD__) || defined(__APPLE__)
 905   m[0] = CTL_HW;
 906   m[1] = HW_NCPU;
 907   len = sizeof(int);
 908   sysctl(m, 2, &count, &len, NULL, 0);
 909
 910   return count;
 911 #else
 912   return 2;
 913 #endif
 914 }
 915
 916 int main(int argc, char *argv[]){
 917
 918 #ifdef FORCE
 919   char buffer[8192], *p, *q;
 920   int length;
 921 #endif
 922
 923   if (argc == 1) return 0;
 924
 925   switch (argv[1][0]) {
 926
 927   case '0' : /* for Makefile */
 928
 929 #ifdef FORCE
 930     printf("CORE=%s\n", CORENAME);
 931 #else
 932 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 933     printf("CORE=%s\n", get_corename());
 934 #endif
 935 #endif
 936
 937 #ifdef FORCE
 938     printf("LIBCORE=%s\n", LIBNAME);
 939 #else
 940     printf("LIBCORE=");
 941     get_libname();
 942     printf("\n");
 943 #endif
 944
 945     printf("NUM_CORES=%d\n", get_num_cores());
 946
 947 #if defined(__arm__) && !defined(FORCE)
 948         get_features();
 949 #endif
 950
 951
 952 #ifdef INTEL_AMD
 953 #ifndef FORCE
 954     get_sse();
 955 #else
 956
 957     sprintf(buffer, "%s", ARCHCONFIG);
 958
 959     p = &buffer[0];
 960
 961     while (*p) {
 962       if ((*p == '-') && (*(p + 1) == 'D')) {
 963         p += 2;
 964
 965         while ((*p != ' ') && (*p != '\0')) {
 966
 967           if (*p == '=') {
 968             printf("=");
 969             p ++;
 970             while ((*p != ' ') && (*p != '\0')) {
 971               printf("%c", *p);
 972               p ++;
 973             }
 974           } else {
 975             printf("%c", *p);
 976             p ++;
 977             if ((*p == ' ') || (*p =='\0')) printf("=1");
 978           }
 979         }
 980
 981         printf("\n");
 982       } else p ++;
 983     }
 984 #endif
 985 #endif
 986
 987 #if NO_PARALLEL_MAKE==1
 988     printf("MAKE += -j 1\n");
 989 #else
 990 #ifndef OS_WINDOWS
 991     printf("MAKE += -j %d\n", get_num_cores());
 992 #endif
 993 #endif
 994
 995     break;
 996
 997   case '1' : /* For config.h */
 998 #ifdef FORCE
 999     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1000
1001     p = &buffer[0];
1002     while (*p) {
1003       if ((*p == '-') && (*(p + 1) == 'D')) {
1004         p += 2;
1005         printf("#define ");
1006
1007         while ((*p != ' ') && (*p != '\0')) {
1008
1009           if (*p == '=') {
1010             printf(" ");
1011             p ++;
1012             while ((*p != ' ') && (*p != '\0')) {
1013               printf("%c", *p);
1014               p ++;
1015             }
1016           } else {
1017             printf("%c", *p);
1018             p ++;
1019           }
1020         }
1021
1022         printf("\n");
1023       } else p ++;
1024     }
1025 #else
1026     get_cpuconfig();
1027 #endif
1028
1029 #ifdef FORCE
1030     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1031 #else
1032 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1033     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1034 #endif
1035 #endif
1036
1037  break;
1038
1039   case '2' : /* SMP */
1040     if (get_num_cores() > 1) printf("SMP=1\n");
1041     break;
1042   }
1043
1044   fflush(stdout);
1045
1046   return 0;
1047 }
1048