getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #include <stdio.h>
  77 #include <string.h>
  78 #ifdef OS_WINDOWS
  79 #include <windows.h>
  80 #endif
  81 #if defined(__FreeBSD__) || defined(__APPLE__)
  82 #include <sys/types.h>
  83 #include <sys/sysctl.h>
  84 #endif
  85 #ifdef linux
  86 #include <sys/sysinfo.h>
  87 #include <unistd.h>
  88 #endif
  89
  90 /* #define FORCE_P2             */
  91 /* #define FORCE_KATMAI         */
  92 /* #define FORCE_COPPERMINE     */
  93 /* #define FORCE_NORTHWOOD      */
  94 /* #define FORCE_PRESCOTT       */
  95 /* #define FORCE_BANIAS         */
  96 /* #define FORCE_YONAH          */
  97 /* #define FORCE_CORE2          */
  98 /* #define FORCE_PENRYN         */
  99 /* #define FORCE_DUNNINGTON     */
 100 /* #define FORCE_NEHALEM        */
 101 /* #define FORCE_SANDYBRIDGE    */
 102 /* #define FORCE_ATOM           */
 103 /* #define FORCE_ATHLON         */
 104 /* #define FORCE_OPTERON        */
 105 /* #define FORCE_OPTERON_SSE3   */
 106 /* #define FORCE_BARCELONA      */
 107 /* #define FORCE_SHANGHAI       */
 108 /* #define FORCE_ISTANBUL       */
 109 /* #define FORCE_BOBCAT         */
 110 /* #define FORCE_BULLDOZER      */
 111 /* #define FORCE_PILEDRIVER     */
 112 /* #define FORCE_SSE_GENERIC    */
 113 /* #define FORCE_VIAC3          */
 114 /* #define FORCE_NANO           */
 115 /* #define FORCE_POWER3         */
 116 /* #define FORCE_POWER4         */
 117 /* #define FORCE_POWER5         */
 118 /* #define FORCE_POWER6         */
 119 /* #define FORCE_POWER7         */
 120 /* #define FORCE_POWER8         */
 121 /* #define FORCE_PPCG4          */
 122 /* #define FORCE_PPC970         */
 123 /* #define FORCE_PPC970MP       */
 124 /* #define FORCE_PPC440         */
 125 /* #define FORCE_PPC440FP2      */
 126 /* #define FORCE_CELL           */
 127 /* #define FORCE_SICORTEX       */
 128 /* #define FORCE_LOONGSON3A     */
 129 /* #define FORCE_LOONGSON3B     */
 130 /* #define FORCE_ITANIUM2       */
 131 /* #define FORCE_SPARC          */
 132 /* #define FORCE_SPARCV7        */
 133 /* #define FORCE_GENERIC        */
 134
 135 #ifdef FORCE_P2
 136 #define FORCE
 137 #define FORCE_INTEL
 138 #define ARCHITECTURE    "X86"
 139 #define SUBARCHITECTURE "PENTIUM2"
 140 #define ARCHCONFIG   "-DPENTIUM2 " \
 141                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 142                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 143                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 144                      "-DHAVE_CMOV -DHAVE_MMX"
 145 #define LIBNAME   "p2"
 146 #define CORENAME  "P5"
 147 #endif
 148
 149 #ifdef FORCE_KATMAI
 150 #define FORCE
 151 #define FORCE_INTEL
 152 #define ARCHITECTURE    "X86"
 153 #define SUBARCHITECTURE "PENTIUM3"
 154 #define ARCHCONFIG   "-DPENTIUM3 " \
 155                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 156                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 157                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 158                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 159 #define LIBNAME   "katmai"
 160 #define CORENAME  "KATMAI"
 161 #endif
 162
 163 #ifdef FORCE_COPPERMINE
 164 #define FORCE
 165 #define FORCE_INTEL
 166 #define ARCHITECTURE    "X86"
 167 #define SUBARCHITECTURE "PENTIUM3"
 168 #define ARCHCONFIG   "-DPENTIUM3 " \
 169                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 170                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 171                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 172                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 173 #define LIBNAME   "coppermine"
 174 #define CORENAME  "COPPERMINE"
 175 #endif
 176
 177 #ifdef FORCE_NORTHWOOD
 178 #define FORCE
 179 #define FORCE_INTEL
 180 #define ARCHITECTURE    "X86"
 181 #define SUBARCHITECTURE "PENTIUM4"
 182 #define ARCHCONFIG   "-DPENTIUM4 " \
 183                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 184                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 185                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 186                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 187 #define LIBNAME   "northwood"
 188 #define CORENAME  "NORTHWOOD"
 189 #endif
 190
 191 #ifdef FORCE_PRESCOTT
 192 #define FORCE
 193 #define FORCE_INTEL
 194 #define ARCHITECTURE    "X86"
 195 #define SUBARCHITECTURE "PENTIUM4"
 196 #define ARCHCONFIG   "-DPENTIUM4 " \
 197                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 198                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 199                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 200                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 201 #define LIBNAME   "prescott"
 202 #define CORENAME  "PRESCOTT"
 203 #endif
 204
 205 #ifdef FORCE_BANIAS
 206 #define FORCE
 207 #define FORCE_INTEL
 208 #define ARCHITECTURE    "X86"
 209 #define SUBARCHITECTURE "BANIAS"
 210 #define ARCHCONFIG   "-DPENTIUMM " \
 211                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 212                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 213                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 214                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 215 #define LIBNAME   "banias"
 216 #define CORENAME  "BANIAS"
 217 #endif
 218
 219 #ifdef FORCE_YONAH
 220 #define FORCE
 221 #define FORCE_INTEL
 222 #define ARCHITECTURE    "X86"
 223 #define SUBARCHITECTURE "YONAH"
 224 #define ARCHCONFIG   "-DPENTIUMM " \
 225                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 226                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 227                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 228                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 229 #define LIBNAME   "yonah"
 230 #define CORENAME  "YONAH"
 231 #endif
 232
 233 #ifdef FORCE_CORE2
 234 #define FORCE
 235 #define FORCE_INTEL
 236 #define ARCHITECTURE    "X86"
 237 #define SUBARCHITECTURE "CONRORE"
 238 #define ARCHCONFIG   "-DCORE2 " \
 239                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 240                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 241                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 242                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 243 #define LIBNAME   "core2"
 244 #define CORENAME  "CORE2"
 245 #endif
 246
 247 #ifdef FORCE_PENRYN
 248 #define FORCE
 249 #define FORCE_INTEL
 250 #define ARCHITECTURE    "X86"
 251 #define SUBARCHITECTURE "PENRYN"
 252 #define ARCHCONFIG   "-DPENRYN " \
 253                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 254                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 255                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 256                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 257 #define LIBNAME   "penryn"
 258 #define CORENAME  "PENRYN"
 259 #endif
 260
 261 #ifdef FORCE_DUNNINGTON
 262 #define FORCE
 263 #define FORCE_INTEL
 264 #define ARCHITECTURE    "X86"
 265 #define SUBARCHITECTURE "DUNNINGTON"
 266 #define ARCHCONFIG   "-DDUNNINGTON " \
 267                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 268                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 269                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 270                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 271                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 272 #define LIBNAME   "dunnington"
 273 #define CORENAME  "DUNNINGTON"
 274 #endif
 275
 276 #ifdef FORCE_NEHALEM
 277 #define FORCE
 278 #define FORCE_INTEL
 279 #define ARCHITECTURE    "X86"
 280 #define SUBARCHITECTURE "NEHALEM"
 281 #define ARCHCONFIG   "-DNEHALEM " \
 282                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 283                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 284                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 285                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 286 #define LIBNAME   "nehalem"
 287 #define CORENAME  "NEHALEM"
 288 #endif
 289
 290 #ifdef FORCE_SANDYBRIDGE
 291 #define FORCE
 292 #define FORCE_INTEL
 293 #define ARCHITECTURE    "X86"
 294 #define SUBARCHITECTURE "SANDYBRIDGE"
 295 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 296                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 297                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 298                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 299                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 300 #define LIBNAME   "sandybridge"
 301 #define CORENAME  "SANDYBRIDGE"
 302 #endif
 303
 304 #ifdef FORCE_HASWELL
 305 #define FORCE
 306 #define FORCE_INTEL
 307 #define ARCHITECTURE    "X86"
 308 #define SUBARCHITECTURE "HASWELL"
 309 #define ARCHCONFIG   "-DHASWELL " \
 310                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 311                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 312                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 313                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 314                      "-DFMA3"
 315 #define LIBNAME   "haswell"
 316 #define CORENAME  "HASWELL"
 317 #endif
 318
 319 #ifdef FORCE_ATOM
 320 #define FORCE
 321 #define FORCE_INTEL
 322 #define ARCHITECTURE    "X86"
 323 #define SUBARCHITECTURE "ATOM"
 324 #define ARCHCONFIG   "-DATOM " \
 325                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 326                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 327                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 328                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 329 #define LIBNAME   "atom"
 330 #define CORENAME  "ATOM"
 331 #endif
 332
 333 #ifdef FORCE_ATHLON
 334 #define FORCE
 335 #define FORCE_INTEL
 336 #define ARCHITECTURE    "X86"
 337 #define SUBARCHITECTURE "ATHLON"
 338 #define ARCHCONFIG   "-DATHLON " \
 339                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 340                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 341                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 342                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 343 #define LIBNAME   "athlon"
 344 #define CORENAME  "ATHLON"
 345 #endif
 346
 347 #ifdef FORCE_OPTERON
 348 #define FORCE
 349 #define FORCE_INTEL
 350 #define ARCHITECTURE    "X86"
 351 #define SUBARCHITECTURE "OPTERON"
 352 #define ARCHCONFIG   "-DOPTERON " \
 353                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 354                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 355                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 356                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 357 #define LIBNAME   "opteron"
 358 #define CORENAME  "OPTERON"
 359 #endif
 360
 361 #ifdef FORCE_OPTERON_SSE3
 362 #define FORCE
 363 #define FORCE_INTEL
 364 #define ARCHITECTURE    "X86"
 365 #define SUBARCHITECTURE "OPTERON"
 366 #define ARCHCONFIG   "-DOPTERON " \
 367                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 368                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 369                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 370                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 371 #define LIBNAME   "opteron"
 372 #define CORENAME  "OPTERON"
 373 #endif
 374
 375 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 376 #define FORCE
 377 #define FORCE_INTEL
 378 #define ARCHITECTURE    "X86"
 379 #define SUBARCHITECTURE "BARCELONA"
 380 #define ARCHCONFIG   "-DBARCELONA " \
 381                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 382                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 383                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 384                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 385                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 386 #define LIBNAME   "barcelona"
 387 #define CORENAME  "BARCELONA"
 388 #endif
 389
 390 #if defined(FORCE_BOBCAT)
 391 #define FORCE
 392 #define FORCE_INTEL
 393 #define ARCHITECTURE    "X86"
 394 #define SUBARCHITECTURE "BOBCAT"
 395 #define ARCHCONFIG   "-DBOBCAT " \
 396                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 397                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 398                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 399                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 400                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 401 #define LIBNAME   "bobcat"
 402 #define CORENAME  "BOBCAT"
 403 #endif
 404
 405 #if defined (FORCE_BULLDOZER)
 406 #define FORCE
 407 #define FORCE_INTEL
 408 #define ARCHITECTURE    "X86"
 409 #define SUBARCHITECTURE "BULLDOZER"
 410 #define ARCHCONFIG   "-DBULLDOZER " \
 411                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 412                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 413                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 414                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 415                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 416                      "-DHAVE_AVX -DHAVE_FMA4"
 417 #define LIBNAME   "bulldozer"
 418 #define CORENAME  "BULLDOZER"
 419 #endif
 420
 421 #if defined (FORCE_PILEDRIVER)
 422 #define FORCE
 423 #define FORCE_INTEL
 424 #define ARCHITECTURE    "X86"
 425 #define SUBARCHITECTURE "PILEDRIVER"
 426 #define ARCHCONFIG   "-DPILEDRIVER " \
 427                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 428                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 429                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 430                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 431                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 432                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 433 #define LIBNAME   "piledriver"
 434 #define CORENAME  "PILEDRIVER"
 435 #endif
 436
 437 #if defined (FORCE_STEAMROLLER)
 438 #define FORCE
 439 #define FORCE_INTEL
 440 #define ARCHITECTURE    "X86"
 441 #define SUBARCHITECTURE "STEAMROLLER"
 442 #define ARCHCONFIG   "-DSTEAMROLLER " \
 443                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 444                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 445                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 446                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 447                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 448                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 449 #define LIBNAME   "steamroller"
 450 #define CORENAME  "STEAMROLLER"
 451 #endif
 452
 453 #if defined (FORCE_EXCAVATOR)
 454 #define FORCE
 455 #define FORCE_INTEL
 456 #define ARCHITECTURE    "X86"
 457 #define SUBARCHITECTURE "EXCAVATOR"
 458 #define ARCHCONFIG   "-DEXCAVATOR " \
 459                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 460                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 461                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 462                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 463                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 464                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 465 #define LIBNAME   "excavator"
 466 #define CORENAME  "EXCAVATOR"
 467 #endif
 468
 469
 470 #ifdef FORCE_SSE_GENERIC
 471 #define FORCE
 472 #define FORCE_INTEL
 473 #define ARCHITECTURE    "X86"
 474 #define SUBARCHITECTURE "GENERIC"
 475 #define ARCHCONFIG   "-DGENERIC " \
 476                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 477                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 478                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 479                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 480 #define LIBNAME   "generic"
 481 #define CORENAME  "GENERIC"
 482 #endif
 483
 484 #ifdef FORCE_VIAC3
 485 #define FORCE
 486 #define FORCE_INTEL
 487 #define ARCHITECTURE    "X86"
 488 #define SUBARCHITECTURE "VIAC3"
 489 #define ARCHCONFIG   "-DVIAC3 " \
 490                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 491                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 492                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 493                      "-DHAVE_MMX -DHAVE_SSE "
 494 #define LIBNAME   "viac3"
 495 #define CORENAME  "VIAC3"
 496 #endif
 497
 498 #ifdef FORCE_NANO
 499 #define FORCE
 500 #define FORCE_INTEL
 501 #define ARCHITECTURE    "X86"
 502 #define SUBARCHITECTURE "NANO"
 503 #define ARCHCONFIG   "-DNANO " \
 504                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 505                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 506                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 507                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 508 #define LIBNAME   "nano"
 509 #define CORENAME  "NANO"
 510 #endif
 511
 512 #ifdef FORCE_POWER3
 513 #define FORCE
 514 #define ARCHITECTURE    "POWER"
 515 #define SUBARCHITECTURE "POWER3"
 516 #define SUBDIRNAME      "power"
 517 #define ARCHCONFIG   "-DPOWER3 " \
 518                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 519                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 520                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 521 #define LIBNAME   "power3"
 522 #define CORENAME  "POWER3"
 523 #endif
 524
 525 #ifdef FORCE_POWER4
 526 #define FORCE
 527 #define ARCHITECTURE    "POWER"
 528 #define SUBARCHITECTURE "POWER4"
 529 #define SUBDIRNAME      "power"
 530 #define ARCHCONFIG   "-DPOWER4 " \
 531                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 532                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 533                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 534 #define LIBNAME   "power4"
 535 #define CORENAME  "POWER4"
 536 #endif
 537
 538 #ifdef FORCE_POWER5
 539 #define FORCE
 540 #define ARCHITECTURE    "POWER"
 541 #define SUBARCHITECTURE "POWER5"
 542 #define SUBDIRNAME      "power"
 543 #define ARCHCONFIG   "-DPOWER5 " \
 544                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 545                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 546                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 547 #define LIBNAME   "power5"
 548 #define CORENAME  "POWER5"
 549 #endif
 550
 551 #if defined(FORCE_POWER6) || defined(FORCE_POWER7) || defined(FORCE_POWER8)
 552 #define FORCE
 553 #define ARCHITECTURE    "POWER"
 554 #define SUBARCHITECTURE "POWER6"
 555 #define SUBDIRNAME      "power"
 556 #define ARCHCONFIG   "-DPOWER6 " \
 557                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 558                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 559                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 560 #define LIBNAME   "power6"
 561 #define CORENAME  "POWER6"
 562 #endif
 563
 564 #ifdef FORCE_PPCG4
 565 #define FORCE
 566 #define ARCHITECTURE    "POWER"
 567 #define SUBARCHITECTURE "PPCG4"
 568 #define SUBDIRNAME      "power"
 569 #define ARCHCONFIG   "-DPPCG4 " \
 570                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 571                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 572                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 573 #define LIBNAME   "ppcg4"
 574 #define CORENAME  "PPCG4"
 575 #endif
 576
 577 #ifdef FORCE_PPC970
 578 #define FORCE
 579 #define ARCHITECTURE    "POWER"
 580 #define SUBARCHITECTURE "PPC970"
 581 #define SUBDIRNAME      "power"
 582 #define ARCHCONFIG   "-DPPC970 " \
 583                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 584                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 585                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 586 #define LIBNAME   "ppc970"
 587 #define CORENAME  "PPC970"
 588 #endif
 589
 590 #ifdef FORCE_PPC970MP
 591 #define FORCE
 592 #define ARCHITECTURE    "POWER"
 593 #define SUBARCHITECTURE "PPC970"
 594 #define SUBDIRNAME      "power"
 595 #define ARCHCONFIG   "-DPPC970 " \
 596                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 597                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 598                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 599 #define LIBNAME   "ppc970mp"
 600 #define CORENAME  "PPC970"
 601 #endif
 602
 603 #ifdef FORCE_PPC440
 604 #define FORCE
 605 #define ARCHITECTURE    "POWER"
 606 #define SUBARCHITECTURE "PPC440"
 607 #define SUBDIRNAME      "power"
 608 #define ARCHCONFIG   "-DPPC440 " \
 609                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 610                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 611                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 612 #define LIBNAME   "ppc440"
 613 #define CORENAME  "PPC440"
 614 #endif
 615
 616 #ifdef FORCE_PPC440FP2
 617 #define FORCE
 618 #define ARCHITECTURE    "POWER"
 619 #define SUBARCHITECTURE "PPC440FP2"
 620 #define SUBDIRNAME      "power"
 621 #define ARCHCONFIG   "-DPPC440FP2 " \
 622                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 623                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 624                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 625 #define LIBNAME   "ppc440FP2"
 626 #define CORENAME  "PPC440FP2"
 627 #endif
 628
 629 #ifdef FORCE_CELL
 630 #define FORCE
 631 #define ARCHITECTURE    "POWER"
 632 #define SUBARCHITECTURE "CELL"
 633 #define SUBDIRNAME      "power"
 634 #define ARCHCONFIG   "-DCELL " \
 635                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 636                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 637                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 638 #define LIBNAME   "cell"
 639 #define CORENAME  "CELL"
 640 #endif
 641
 642 #ifdef FORCE_SICORTEX
 643 #define FORCE
 644 #define ARCHITECTURE    "MIPS"
 645 #define SUBARCHITECTURE "SICORTEX"
 646 #define SUBDIRNAME      "mips"
 647 #define ARCHCONFIG   "-DSICORTEX " \
 648                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 649                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 650                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 651 #define LIBNAME   "mips"
 652 #define CORENAME  "sicortex"
 653 #endif
 654
 655
 656 #ifdef FORCE_LOONGSON3A
 657 #define FORCE
 658 #define ARCHITECTURE    "MIPS"
 659 #define SUBARCHITECTURE "LOONGSON3A"
 660 #define SUBDIRNAME      "mips64"
 661 #define ARCHCONFIG   "-DLOONGSON3A " \
 662        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 663        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 664        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 665 #define LIBNAME   "loongson3a"
 666 #define CORENAME  "LOONGSON3A"
 667 #else
 668 #endif
 669
 670 #ifdef FORCE_LOONGSON3B
 671 #define FORCE
 672 #define ARCHITECTURE    "MIPS"
 673 #define SUBARCHITECTURE "LOONGSON3B"
 674 #define SUBDIRNAME      "mips64"
 675 #define ARCHCONFIG   "-DLOONGSON3B " \
 676        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 677        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 678        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 679 #define LIBNAME   "loongson3b"
 680 #define CORENAME  "LOONGSON3B"
 681 #else
 682 #endif
 683
 684 #ifdef FORCE_ITANIUM2
 685 #define FORCE
 686 #define ARCHITECTURE    "IA64"
 687 #define SUBARCHITECTURE "ITANIUM2"
 688 #define SUBDIRNAME      "ia64"
 689 #define ARCHCONFIG   "-DITANIUM2 " \
 690                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 691                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 692 #define LIBNAME   "itanium2"
 693 #define CORENAME  "itanium2"
 694 #endif
 695
 696 #ifdef FORCE_SPARC
 697 #define FORCE
 698 #define ARCHITECTURE    "SPARC"
 699 #define SUBARCHITECTURE "SPARC"
 700 #define SUBDIRNAME      "sparc"
 701 #define ARCHCONFIG   "-DSPARC -DV9 " \
 702                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 703                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 704 #define LIBNAME   "sparc"
 705 #define CORENAME  "sparc"
 706 #endif
 707
 708 #ifdef FORCE_SPARCV7
 709 #define FORCE
 710 #define ARCHITECTURE    "SPARC"
 711 #define SUBARCHITECTURE "SPARC"
 712 #define SUBDIRNAME      "sparc"
 713 #define ARCHCONFIG   "-DSPARC -DV7 " \
 714                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 715                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 716 #define LIBNAME   "sparcv7"
 717 #define CORENAME  "sparcv7"
 718 #endif
 719
 720 #ifdef FORCE_GENERIC
 721 #define FORCE
 722 #define ARCHITECTURE    "GENERIC"
 723 #define SUBARCHITECTURE "GENERIC"
 724 #define SUBDIRNAME      "generic"
 725 #define ARCHCONFIG   "-DGENERIC " \
 726                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 727                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 728                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 729 #define LIBNAME   "generic"
 730 #define CORENAME  "generic"
 731 #endif
 732
 733 #ifdef FORCE_ARMV7
 734 #define FORCE
 735 #define ARCHITECTURE    "ARM"
 736 #define SUBARCHITECTURE "ARMV7"
 737 #define SUBDIRNAME      "arm"
 738 #define ARCHCONFIG   "-DARMV7 " \
 739        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 740        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 741        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 742        "-DHAVE_VFPV3 -DHAVE_VFP"
 743 #define LIBNAME   "armv7"
 744 #define CORENAME  "ARMV7"
 745 #else
 746 #endif
 747
 748 #ifdef FORCE_CORTEXA9
 749 #define FORCE
 750 #define ARCHITECTURE    "ARM"
 751 #define SUBARCHITECTURE "CORTEXA9"
 752 #define SUBDIRNAME      "arm"
 753 #define ARCHCONFIG   "-DCORTEXA9 " \
 754        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 755        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 756        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 757        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 758 #define LIBNAME   "cortexa9"
 759 #define CORENAME  "CORTEXA9"
 760 #else
 761 #endif
 762
 763 #ifdef FORCE_CORTEXA15
 764 #define FORCE
 765 #define ARCHITECTURE    "ARM"
 766 #define SUBARCHITECTURE "CORTEXA15"
 767 #define SUBDIRNAME      "arm"
 768 #define ARCHCONFIG   "-DCORTEXA15 " \
 769        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 770        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 771        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 772        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 773 #define LIBNAME   "cortexa15"
 774 #define CORENAME  "CORTEXA15"
 775 #else
 776 #endif
 777
 778 #ifdef FORCE_ARMV6
 779 #define FORCE
 780 #define ARCHITECTURE    "ARM"
 781 #define SUBARCHITECTURE "ARMV6"
 782 #define SUBDIRNAME      "arm"
 783 #define ARCHCONFIG   "-DARMV6 " \
 784        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 785        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 786        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 787        "-DHAVE_VFP"
 788 #define LIBNAME   "armv6"
 789 #define CORENAME  "ARMV6"
 790 #else
 791 #endif
 792
 793 #ifdef FORCE_ARMV5
 794 #define FORCE
 795 #define ARCHITECTURE    "ARM"
 796 #define SUBARCHITECTURE "ARMV5"
 797 #define SUBDIRNAME      "arm"
 798 #define ARCHCONFIG   "-DARMV5 " \
 799        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 800        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 801        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 802 #define LIBNAME   "armv5"
 803 #define CORENAME  "ARMV5"
 804 #else
 805 #endif
 806
 807
 808 #ifdef FORCE_ARMV8
 809 #define FORCE
 810 #define ARCHITECTURE    "ARM64"
 811 #define SUBARCHITECTURE "ARMV8"
 812 #define SUBDIRNAME      "arm64"
 813 #define ARCHCONFIG   "-DARMV8 " \
 814        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 815        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 816        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 817 #define LIBNAME   "armv8"
 818 #define CORENAME  "XGENE1"
 819 #else
 820 #endif
 821
 822
 823 #ifndef FORCE
 824
 825 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 826     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 827 #ifndef POWER
 828 #define POWER
 829 #endif
 830 #define OPENBLAS_SUPPORTED
 831 #endif
 832
 833 #if defined(__i386__) || (__x86_64__)
 834 #include "cpuid_x86.c"
 835 #define OPENBLAS_SUPPORTED
 836 #endif
 837
 838 #ifdef __ia64__
 839 #include "cpuid_ia64.c"
 840 #define OPENBLAS_SUPPORTED
 841 #endif
 842
 843 #ifdef __alpha
 844 #include "cpuid_alpha.c"
 845 #define OPENBLAS_SUPPORTED
 846 #endif
 847
 848 #ifdef POWER
 849 #include "cpuid_power.c"
 850 #define OPENBLAS_SUPPORTED
 851 #endif
 852
 853 #ifdef sparc
 854 #include "cpuid_sparc.c"
 855 #define OPENBLAS_SUPPORTED
 856 #endif
 857
 858 #ifdef __mips__
 859 #include "cpuid_mips.c"
 860 #define OPENBLAS_SUPPORTED
 861 #endif
 862
 863 #ifdef __arm__
 864 #include "cpuid_arm.c"
 865 #define OPENBLAS_SUPPORTED
 866 #endif
 867
 868 #ifdef __aarch64__
 869 #include "cpuid_arm64.c"
 870 #define OPENBLAS_SUPPORTED
 871 #endif
 872
 873
 874 #ifndef OPENBLAS_SUPPORTED
 875 #error "This arch/CPU is not supported by OpenBLAS."
 876 #endif
 877
 878 #else
 879
 880 #endif
 881
 882 static int get_num_cores(void) {
 883
 884 #ifdef OS_WINDOWS
 885   SYSTEM_INFO sysinfo;
 886 #elif defined(__FreeBSD__) || defined(__APPLE__)
 887   int m[2], count;
 888   size_t len;
 889 #endif
 890
 891 #ifdef linux
 892   //returns the number of processors which are currently online
 893   return sysconf(_SC_NPROCESSORS_ONLN);
 894
 895 #elif defined(OS_WINDOWS)
 896
 897   GetSystemInfo(&sysinfo);
 898   return sysinfo.dwNumberOfProcessors;
 899
 900 #elif defined(__FreeBSD__) || defined(__APPLE__)
 901   m[0] = CTL_HW;
 902   m[1] = HW_NCPU;
 903   len = sizeof(int);
 904   sysctl(m, 2, &count, &len, NULL, 0);
 905
 906   return count;
 907 #else
 908   return 2;
 909 #endif
 910 }
 911
 912 int main(int argc, char *argv[]){
 913
 914 #ifdef FORCE
 915   char buffer[8192], *p, *q;
 916   int length;
 917 #endif
 918
 919   if (argc == 1) return 0;
 920
 921   switch (argv[1][0]) {
 922
 923   case '0' : /* for Makefile */
 924
 925 #ifdef FORCE
 926     printf("CORE=%s\n", CORENAME);
 927 #else
 928 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 929     printf("CORE=%s\n", get_corename());
 930 #endif
 931 #endif
 932
 933 #ifdef FORCE
 934     printf("LIBCORE=%s\n", LIBNAME);
 935 #else
 936     printf("LIBCORE=");
 937     get_libname();
 938     printf("\n");
 939 #endif
 940
 941     printf("NUM_CORES=%d\n", get_num_cores());
 942
 943 #if defined(__arm__) && !defined(FORCE)
 944         get_features();
 945 #endif
 946
 947
 948 #if defined(__i386__) || defined(__x86_64__)
 949 #ifndef FORCE
 950     get_sse();
 951 #else
 952
 953     sprintf(buffer, "%s", ARCHCONFIG);
 954
 955     p = &buffer[0];
 956
 957     while (*p) {
 958       if ((*p == '-') && (*(p + 1) == 'D')) {
 959         p += 2;
 960
 961         while ((*p != ' ') && (*p != '\0')) {
 962
 963           if (*p == '=') {
 964             printf("=");
 965             p ++;
 966             while ((*p != ' ') && (*p != '\0')) {
 967               printf("%c", *p);
 968               p ++;
 969             }
 970           } else {
 971             printf("%c", *p);
 972             p ++;
 973             if ((*p == ' ') || (*p =='\0')) printf("=1");
 974           }
 975         }
 976
 977         printf("\n");
 978       } else p ++;
 979     }
 980 #endif
 981 #endif
 982
 983 #if NO_PARALLEL_MAKE==1
 984     printf("MAKE += -j 1\n");
 985 #else
 986 #ifndef OS_WINDOWS
 987     printf("MAKE += -j %d\n", get_num_cores());
 988 #endif
 989 #endif
 990
 991     break;
 992
 993   case '1' : /* For config.h */
 994 #ifdef FORCE
 995     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 996
 997     p = &buffer[0];
 998     while (*p) {
 999       if ((*p == '-') && (*(p + 1) == 'D')) {
1000         p += 2;
1001         printf("#define ");
1002
1003         while ((*p != ' ') && (*p != '\0')) {
1004
1005           if (*p == '=') {
1006             printf(" ");
1007             p ++;
1008             while ((*p != ' ') && (*p != '\0')) {
1009               printf("%c", *p);
1010               p ++;
1011             }
1012           } else {
1013             printf("%c", *p);
1014             p ++;
1015           }
1016         }
1017
1018         printf("\n");
1019       } else p ++;
1020     }
1021 #else
1022     get_cpuconfig();
1023 #endif
1024
1025 #ifdef FORCE
1026     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1027 #else
1028 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1029     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1030 #endif
1031 #endif
1032
1033  break;
1034
1035   case '2' : /* SMP */
1036     if (get_num_cores() > 1) printf("SMP=1\n");
1037     break;
1038   }
1039
1040   fflush(stdout);
1041
1042   return 0;
1043 }
1044