getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #include <stdio.h>
  77 #include <string.h>
  78 #ifdef OS_WINDOWS
  79 #include <windows.h>
  80 #endif
  81 #if defined(__FreeBSD__) || defined(__APPLE__)
  82 #include <sys/types.h>
  83 #include <sys/sysctl.h>
  84 #endif
  85 #ifdef linux
  86 #include <sys/sysinfo.h>
  87 #include <unistd.h>
  88 #endif
  89
  90 /* #define FORCE_P2             */
  91 /* #define FORCE_KATMAI         */
  92 /* #define FORCE_COPPERMINE     */
  93 /* #define FORCE_NORTHWOOD      */
  94 /* #define FORCE_PRESCOTT       */
  95 /* #define FORCE_BANIAS         */
  96 /* #define FORCE_YONAH          */
  97 /* #define FORCE_CORE2          */
  98 /* #define FORCE_PENRYN         */
  99 /* #define FORCE_DUNNINGTON     */
 100 /* #define FORCE_NEHALEM        */
 101 /* #define FORCE_SANDYBRIDGE    */
 102 /* #define FORCE_ATOM           */
 103 /* #define FORCE_ATHLON         */
 104 /* #define FORCE_OPTERON        */
 105 /* #define FORCE_OPTERON_SSE3   */
 106 /* #define FORCE_BARCELONA      */
 107 /* #define FORCE_SHANGHAI       */
 108 /* #define FORCE_ISTANBUL       */
 109 /* #define FORCE_BOBCAT         */
 110 /* #define FORCE_BULLDOZER      */
 111 /* #define FORCE_PILEDRIVER     */
 112 /* #define FORCE_SSE_GENERIC    */
 113 /* #define FORCE_VIAC3          */
 114 /* #define FORCE_NANO           */
 115 /* #define FORCE_POWER3         */
 116 /* #define FORCE_POWER4         */
 117 /* #define FORCE_POWER5         */
 118 /* #define FORCE_POWER6         */
 119 /* #define FORCE_PPCG4          */
 120 /* #define FORCE_PPC970         */
 121 /* #define FORCE_PPC970MP       */
 122 /* #define FORCE_PPC440         */
 123 /* #define FORCE_PPC440FP2      */
 124 /* #define FORCE_CELL           */
 125 /* #define FORCE_SICORTEX       */
 126 /* #define FORCE_LOONGSON3A     */
 127 /* #define FORCE_LOONGSON3B     */
 128 /* #define FORCE_ITANIUM2       */
 129 /* #define FORCE_SPARC          */
 130 /* #define FORCE_SPARCV7        */
 131 /* #define FORCE_GENERIC        */
 132
 133 #ifdef FORCE_P2
 134 #define FORCE
 135 #define FORCE_INTEL
 136 #define ARCHITECTURE    "X86"
 137 #define SUBARCHITECTURE "PENTIUM2"
 138 #define ARCHCONFIG   "-DPENTIUM2 " \
 139                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 140                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 141                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 142                      "-DHAVE_CMOV -DHAVE_MMX"
 143 #define LIBNAME   "p2"
 144 #define CORENAME  "P5"
 145 #endif
 146
 147 #ifdef FORCE_KATMAI
 148 #define FORCE
 149 #define FORCE_INTEL
 150 #define ARCHITECTURE    "X86"
 151 #define SUBARCHITECTURE "PENTIUM3"
 152 #define ARCHCONFIG   "-DPENTIUM3 " \
 153                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 154                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 155                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 156                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 157 #define LIBNAME   "katmai"
 158 #define CORENAME  "KATMAI"
 159 #endif
 160
 161 #ifdef FORCE_COPPERMINE
 162 #define FORCE
 163 #define FORCE_INTEL
 164 #define ARCHITECTURE    "X86"
 165 #define SUBARCHITECTURE "PENTIUM3"
 166 #define ARCHCONFIG   "-DPENTIUM3 " \
 167                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 168                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 169                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 170                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 171 #define LIBNAME   "coppermine"
 172 #define CORENAME  "COPPERMINE"
 173 #endif
 174
 175 #ifdef FORCE_NORTHWOOD
 176 #define FORCE
 177 #define FORCE_INTEL
 178 #define ARCHITECTURE    "X86"
 179 #define SUBARCHITECTURE "PENTIUM4"
 180 #define ARCHCONFIG   "-DPENTIUM4 " \
 181                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 182                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 183                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 184                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 185 #define LIBNAME   "northwood"
 186 #define CORENAME  "NORTHWOOD"
 187 #endif
 188
 189 #ifdef FORCE_PRESCOTT
 190 #define FORCE
 191 #define FORCE_INTEL
 192 #define ARCHITECTURE    "X86"
 193 #define SUBARCHITECTURE "PENTIUM4"
 194 #define ARCHCONFIG   "-DPENTIUM4 " \
 195                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 196                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 197                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 198                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 199 #define LIBNAME   "prescott"
 200 #define CORENAME  "PRESCOTT"
 201 #endif
 202
 203 #ifdef FORCE_BANIAS
 204 #define FORCE
 205 #define FORCE_INTEL
 206 #define ARCHITECTURE    "X86"
 207 #define SUBARCHITECTURE "BANIAS"
 208 #define ARCHCONFIG   "-DPENTIUMM " \
 209                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 210                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 211                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 212                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 213 #define LIBNAME   "banias"
 214 #define CORENAME  "BANIAS"
 215 #endif
 216
 217 #ifdef FORCE_YONAH
 218 #define FORCE
 219 #define FORCE_INTEL
 220 #define ARCHITECTURE    "X86"
 221 #define SUBARCHITECTURE "YONAH"
 222 #define ARCHCONFIG   "-DPENTIUMM " \
 223                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 224                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 225                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 226                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 227 #define LIBNAME   "yonah"
 228 #define CORENAME  "YONAH"
 229 #endif
 230
 231 #ifdef FORCE_CORE2
 232 #define FORCE
 233 #define FORCE_INTEL
 234 #define ARCHITECTURE    "X86"
 235 #define SUBARCHITECTURE "CONRORE"
 236 #define ARCHCONFIG   "-DCORE2 " \
 237                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 238                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 239                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 240                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 241 #define LIBNAME   "core2"
 242 #define CORENAME  "CORE2"
 243 #endif
 244
 245 #ifdef FORCE_PENRYN
 246 #define FORCE
 247 #define FORCE_INTEL
 248 #define ARCHITECTURE    "X86"
 249 #define SUBARCHITECTURE "PENRYN"
 250 #define ARCHCONFIG   "-DPENRYN " \
 251                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 252                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 253                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 254                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 255 #define LIBNAME   "penryn"
 256 #define CORENAME  "PENRYN"
 257 #endif
 258
 259 #ifdef FORCE_DUNNINGTON
 260 #define FORCE
 261 #define FORCE_INTEL
 262 #define ARCHITECTURE    "X86"
 263 #define SUBARCHITECTURE "DUNNINGTON"
 264 #define ARCHCONFIG   "-DDUNNINGTON " \
 265                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 266                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 267                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 268                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 269                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 270 #define LIBNAME   "dunnington"
 271 #define CORENAME  "DUNNINGTON"
 272 #endif
 273
 274 #ifdef FORCE_NEHALEM
 275 #define FORCE
 276 #define FORCE_INTEL
 277 #define ARCHITECTURE    "X86"
 278 #define SUBARCHITECTURE "NEHALEM"
 279 #define ARCHCONFIG   "-DNEHALEM " \
 280                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 281                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 282                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 283                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 284 #define LIBNAME   "nehalem"
 285 #define CORENAME  "NEHALEM"
 286 #endif
 287
 288 #ifdef FORCE_SANDYBRIDGE
 289 #define FORCE
 290 #define FORCE_INTEL
 291 #define ARCHITECTURE    "X86"
 292 #define SUBARCHITECTURE "SANDYBRIDGE"
 293 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 294                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 295                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 296                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 297                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 298 #define LIBNAME   "sandybridge"
 299 #define CORENAME  "SANDYBRIDGE"
 300 #endif
 301
 302 #ifdef FORCE_HASWELL
 303 #define FORCE
 304 #define FORCE_INTEL
 305 #define ARCHITECTURE    "X86"
 306 #define SUBARCHITECTURE "HASWELL"
 307 #define ARCHCONFIG   "-DHASWELL " \
 308                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 309                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 310                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 311                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 312                      "-DFMA3"
 313 #define LIBNAME   "haswell"
 314 #define CORENAME  "HASWELL"
 315 #endif
 316
 317 #ifdef FORCE_ATOM
 318 #define FORCE
 319 #define FORCE_INTEL
 320 #define ARCHITECTURE    "X86"
 321 #define SUBARCHITECTURE "ATOM"
 322 #define ARCHCONFIG   "-DATOM " \
 323                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 324                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 325                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 326                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 327 #define LIBNAME   "atom"
 328 #define CORENAME  "ATOM"
 329 #endif
 330
 331 #ifdef FORCE_ATHLON
 332 #define FORCE
 333 #define FORCE_INTEL
 334 #define ARCHITECTURE    "X86"
 335 #define SUBARCHITECTURE "ATHLON"
 336 #define ARCHCONFIG   "-DATHLON " \
 337                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 338                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 339                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 340                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 341 #define LIBNAME   "athlon"
 342 #define CORENAME  "ATHLON"
 343 #endif
 344
 345 #ifdef FORCE_OPTERON
 346 #define FORCE
 347 #define FORCE_INTEL
 348 #define ARCHITECTURE    "X86"
 349 #define SUBARCHITECTURE "OPTERON"
 350 #define ARCHCONFIG   "-DOPTERON " \
 351                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 352                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 353                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 354                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 355 #define LIBNAME   "opteron"
 356 #define CORENAME  "OPTERON"
 357 #endif
 358
 359 #ifdef FORCE_OPTERON_SSE3
 360 #define FORCE
 361 #define FORCE_INTEL
 362 #define ARCHITECTURE    "X86"
 363 #define SUBARCHITECTURE "OPTERON"
 364 #define ARCHCONFIG   "-DOPTERON " \
 365                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 366                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 367                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 368                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 369 #define LIBNAME   "opteron"
 370 #define CORENAME  "OPTERON"
 371 #endif
 372
 373 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 374 #define FORCE
 375 #define FORCE_INTEL
 376 #define ARCHITECTURE    "X86"
 377 #define SUBARCHITECTURE "BARCELONA"
 378 #define ARCHCONFIG   "-DBARCELONA " \
 379                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 380                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 381                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 382                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 383                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 384 #define LIBNAME   "barcelona"
 385 #define CORENAME  "BARCELONA"
 386 #endif
 387
 388 #if defined(FORCE_BOBCAT)
 389 #define FORCE
 390 #define FORCE_INTEL
 391 #define ARCHITECTURE    "X86"
 392 #define SUBARCHITECTURE "BOBCAT"
 393 #define ARCHCONFIG   "-DBOBCAT " \
 394                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 395                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 396                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 397                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 398                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 399 #define LIBNAME   "bobcat"
 400 #define CORENAME  "BOBCAT"
 401 #endif
 402
 403 #if defined (FORCE_BULLDOZER)
 404 #define FORCE
 405 #define FORCE_INTEL
 406 #define ARCHITECTURE    "X86"
 407 #define SUBARCHITECTURE "BULLDOZER"
 408 #define ARCHCONFIG   "-DBULLDOZER " \
 409                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 410                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 411                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 412                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 413                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 414                      "-DHAVE_AVX -DHAVE_FMA4"
 415 #define LIBNAME   "bulldozer"
 416 #define CORENAME  "BULLDOZER"
 417 #endif
 418
 419 #if defined (FORCE_PILEDRIVER)
 420 #define FORCE
 421 #define FORCE_INTEL
 422 #define ARCHITECTURE    "X86"
 423 #define SUBARCHITECTURE "PILEDRIVER"
 424 #define ARCHCONFIG   "-DPILEDRIVER " \
 425                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 426                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 427                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 428                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 429                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 430                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 431 #define LIBNAME   "piledriver"
 432 #define CORENAME  "PILEDRIVER"
 433 #endif
 434
 435 #if defined (FORCE_STEAMROLLER)
 436 #define FORCE
 437 #define FORCE_INTEL
 438 #define ARCHITECTURE    "X86"
 439 #define SUBARCHITECTURE "STEAMROLLER"
 440 #define ARCHCONFIG   "-DSTEAMROLLER " \
 441                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 442                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 443                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 444                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 445                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 446                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 447 #define LIBNAME   "steamroller"
 448 #define CORENAME  "STEAMROLLER"
 449 #endif
 450
 451
 452 #ifdef FORCE_SSE_GENERIC
 453 #define FORCE
 454 #define FORCE_INTEL
 455 #define ARCHITECTURE    "X86"
 456 #define SUBARCHITECTURE "GENERIC"
 457 #define ARCHCONFIG   "-DGENERIC " \
 458                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 459                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 460                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 461                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 462 #define LIBNAME   "generic"
 463 #define CORENAME  "GENERIC"
 464 #endif
 465
 466 #ifdef FORCE_VIAC3
 467 #define FORCE
 468 #define FORCE_INTEL
 469 #define ARCHITECTURE    "X86"
 470 #define SUBARCHITECTURE "VIAC3"
 471 #define ARCHCONFIG   "-DVIAC3 " \
 472                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 473                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 474                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 475                      "-DHAVE_MMX -DHAVE_SSE "
 476 #define LIBNAME   "viac3"
 477 #define CORENAME  "VIAC3"
 478 #endif
 479
 480 #ifdef FORCE_NANO
 481 #define FORCE
 482 #define FORCE_INTEL
 483 #define ARCHITECTURE    "X86"
 484 #define SUBARCHITECTURE "NANO"
 485 #define ARCHCONFIG   "-DNANO " \
 486                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 487                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 488                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 489                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 490 #define LIBNAME   "nano"
 491 #define CORENAME  "NANO"
 492 #endif
 493
 494 #ifdef FORCE_POWER3
 495 #define FORCE
 496 #define ARCHITECTURE    "POWER"
 497 #define SUBARCHITECTURE "POWER3"
 498 #define SUBDIRNAME      "power"
 499 #define ARCHCONFIG   "-DPOWER3 " \
 500                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 501                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 502                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 503 #define LIBNAME   "power3"
 504 #define CORENAME  "POWER3"
 505 #endif
 506
 507 #ifdef FORCE_POWER4
 508 #define FORCE
 509 #define ARCHITECTURE    "POWER"
 510 #define SUBARCHITECTURE "POWER4"
 511 #define SUBDIRNAME      "power"
 512 #define ARCHCONFIG   "-DPOWER4 " \
 513                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 514                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 515                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 516 #define LIBNAME   "power4"
 517 #define CORENAME  "POWER4"
 518 #endif
 519
 520 #ifdef FORCE_POWER5
 521 #define FORCE
 522 #define ARCHITECTURE    "POWER"
 523 #define SUBARCHITECTURE "POWER5"
 524 #define SUBDIRNAME      "power"
 525 #define ARCHCONFIG   "-DPOWER5 " \
 526                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 527                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 528                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 529 #define LIBNAME   "power5"
 530 #define CORENAME  "POWER5"
 531 #endif
 532
 533 #ifdef FORCE_POWER6
 534 #define FORCE
 535 #define ARCHITECTURE    "POWER"
 536 #define SUBARCHITECTURE "POWER6"
 537 #define SUBDIRNAME      "power"
 538 #define ARCHCONFIG   "-DPOWER6 " \
 539                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 540                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 541                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 542 #define LIBNAME   "power6"
 543 #define CORENAME  "POWER6"
 544 #endif
 545
 546 #ifdef FORCE_PPCG4
 547 #define FORCE
 548 #define ARCHITECTURE    "POWER"
 549 #define SUBARCHITECTURE "PPCG4"
 550 #define SUBDIRNAME      "power"
 551 #define ARCHCONFIG   "-DPPCG4 " \
 552                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 553                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 554                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 555 #define LIBNAME   "ppcg4"
 556 #define CORENAME  "PPCG4"
 557 #endif
 558
 559 #ifdef FORCE_PPC970
 560 #define FORCE
 561 #define ARCHITECTURE    "POWER"
 562 #define SUBARCHITECTURE "PPC970"
 563 #define SUBDIRNAME      "power"
 564 #define ARCHCONFIG   "-DPPC970 " \
 565                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 566                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 567                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 568 #define LIBNAME   "ppc970"
 569 #define CORENAME  "PPC970"
 570 #endif
 571
 572 #ifdef FORCE_PPC970MP
 573 #define FORCE
 574 #define ARCHITECTURE    "POWER"
 575 #define SUBARCHITECTURE "PPC970"
 576 #define SUBDIRNAME      "power"
 577 #define ARCHCONFIG   "-DPPC970 " \
 578                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 579                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 580                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 581 #define LIBNAME   "ppc970mp"
 582 #define CORENAME  "PPC970"
 583 #endif
 584
 585 #ifdef FORCE_PPC440
 586 #define FORCE
 587 #define ARCHITECTURE    "POWER"
 588 #define SUBARCHITECTURE "PPC440"
 589 #define SUBDIRNAME      "power"
 590 #define ARCHCONFIG   "-DPPC440 " \
 591                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 592                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 593                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 594 #define LIBNAME   "ppc440"
 595 #define CORENAME  "PPC440"
 596 #endif
 597
 598 #ifdef FORCE_PPC440FP2
 599 #define FORCE
 600 #define ARCHITECTURE    "POWER"
 601 #define SUBARCHITECTURE "PPC440FP2"
 602 #define SUBDIRNAME      "power"
 603 #define ARCHCONFIG   "-DPPC440FP2 " \
 604                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 605                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 606                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 607 #define LIBNAME   "ppc440FP2"
 608 #define CORENAME  "PPC440FP2"
 609 #endif
 610
 611 #ifdef FORCE_CELL
 612 #define FORCE
 613 #define ARCHITECTURE    "POWER"
 614 #define SUBARCHITECTURE "CELL"
 615 #define SUBDIRNAME      "power"
 616 #define ARCHCONFIG   "-DCELL " \
 617                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 618                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 619                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 620 #define LIBNAME   "cell"
 621 #define CORENAME  "CELL"
 622 #endif
 623
 624 #ifdef FORCE_SICORTEX
 625 #define FORCE
 626 #define ARCHITECTURE    "MIPS"
 627 #define SUBARCHITECTURE "SICORTEX"
 628 #define SUBDIRNAME      "mips"
 629 #define ARCHCONFIG   "-DSICORTEX " \
 630                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 631                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 632                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 633 #define LIBNAME   "mips"
 634 #define CORENAME  "sicortex"
 635 #endif
 636
 637
 638 #ifdef FORCE_LOONGSON3A
 639 #define FORCE
 640 #define ARCHITECTURE    "MIPS"
 641 #define SUBARCHITECTURE "LOONGSON3A"
 642 #define SUBDIRNAME      "mips64"
 643 #define ARCHCONFIG   "-DLOONGSON3A " \
 644        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 645        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 646        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 647 #define LIBNAME   "loongson3a"
 648 #define CORENAME  "LOONGSON3A"
 649 #else
 650 #endif
 651
 652 #ifdef FORCE_LOONGSON3B
 653 #define FORCE
 654 #define ARCHITECTURE    "MIPS"
 655 #define SUBARCHITECTURE "LOONGSON3B"
 656 #define SUBDIRNAME      "mips64"
 657 #define ARCHCONFIG   "-DLOONGSON3B " \
 658        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 659        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 660        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 661 #define LIBNAME   "loongson3b"
 662 #define CORENAME  "LOONGSON3B"
 663 #else
 664 #endif
 665
 666 #ifdef FORCE_ITANIUM2
 667 #define FORCE
 668 #define ARCHITECTURE    "IA64"
 669 #define SUBARCHITECTURE "ITANIUM2"
 670 #define SUBDIRNAME      "ia64"
 671 #define ARCHCONFIG   "-DITANIUM2 " \
 672                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 673                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 674 #define LIBNAME   "itanium2"
 675 #define CORENAME  "itanium2"
 676 #endif
 677
 678 #ifdef FORCE_SPARC
 679 #define FORCE
 680 #define ARCHITECTURE    "SPARC"
 681 #define SUBARCHITECTURE "SPARC"
 682 #define SUBDIRNAME      "sparc"
 683 #define ARCHCONFIG   "-DSPARC -DV9 " \
 684                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 685                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 686 #define LIBNAME   "sparc"
 687 #define CORENAME  "sparc"
 688 #endif
 689
 690 #ifdef FORCE_SPARCV7
 691 #define FORCE
 692 #define ARCHITECTURE    "SPARC"
 693 #define SUBARCHITECTURE "SPARC"
 694 #define SUBDIRNAME      "sparc"
 695 #define ARCHCONFIG   "-DSPARC -DV7 " \
 696                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 697                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 698 #define LIBNAME   "sparcv7"
 699 #define CORENAME  "sparcv7"
 700 #endif
 701
 702 #ifdef FORCE_GENERIC
 703 #define FORCE
 704 #define ARCHITECTURE    "GENERIC"
 705 #define SUBARCHITECTURE "GENERIC"
 706 #define SUBDIRNAME      "generic"
 707 #define ARCHCONFIG   "-DGENERIC " \
 708                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 709                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 710                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 711 #define LIBNAME   "generic"
 712 #define CORENAME  "generic"
 713 #endif
 714
 715 #ifdef FORCE_ARMV7
 716 #define FORCE
 717 #define ARCHITECTURE    "ARM"
 718 #define SUBARCHITECTURE "ARMV7"
 719 #define SUBDIRNAME      "arm"
 720 #define ARCHCONFIG   "-DARMV7 " \
 721        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 722        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 723        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 724        "-DHAVE_VFPV3 -DHAVE_VFP"
 725 #define LIBNAME   "armv7"
 726 #define CORENAME  "ARMV7"
 727 #else
 728 #endif
 729
 730 #ifdef FORCE_CORTEXA9
 731 #define FORCE
 732 #define ARCHITECTURE    "ARM"
 733 #define SUBARCHITECTURE "CORTEXA9"
 734 #define SUBDIRNAME      "arm"
 735 #define ARCHCONFIG   "-DCORTEXA9 " \
 736        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 737        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 738        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 739        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 740 #define LIBNAME   "cortexa9"
 741 #define CORENAME  "CORTEXA9"
 742 #else
 743 #endif
 744
 745 #ifdef FORCE_CORTEXA15
 746 #define FORCE
 747 #define ARCHITECTURE    "ARM"
 748 #define SUBARCHITECTURE "CORTEXA15"
 749 #define SUBDIRNAME      "arm"
 750 #define ARCHCONFIG   "-DCORTEXA15 " \
 751        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 752        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 753        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 754        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 755 #define LIBNAME   "cortexa15"
 756 #define CORENAME  "CORTEXA15"
 757 #else
 758 #endif
 759
 760 #ifdef FORCE_ARMV6
 761 #define FORCE
 762 #define ARCHITECTURE    "ARM"
 763 #define SUBARCHITECTURE "ARMV6"
 764 #define SUBDIRNAME      "arm"
 765 #define ARCHCONFIG   "-DARMV6 " \
 766        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 767        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 768        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 769        "-DHAVE_VFP"
 770 #define LIBNAME   "armv6"
 771 #define CORENAME  "ARMV6"
 772 #else
 773 #endif
 774
 775 #ifdef FORCE_ARMV5
 776 #define FORCE
 777 #define ARCHITECTURE    "ARM"
 778 #define SUBARCHITECTURE "ARMV5"
 779 #define SUBDIRNAME      "arm"
 780 #define ARCHCONFIG   "-DARMV5 " \
 781        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 782        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 783        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 784        "-DHAVE_VFP"
 785 #define LIBNAME   "armv5"
 786 #define CORENAME  "ARMV5"
 787 #else
 788 #endif
 789
 790
 791 #ifdef FORCE_ARMV8
 792 #define FORCE
 793 #define ARCHITECTURE    "ARM64"
 794 #define SUBARCHITECTURE "ARMV8"
 795 #define SUBDIRNAME      "arm64"
 796 #define ARCHCONFIG   "-DARMV8 " \
 797        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 798        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 799        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 800 #define LIBNAME   "armv8"
 801 #define CORENAME  "XGENE1"
 802 #else
 803 #endif
 804
 805
 806 #ifndef FORCE
 807
 808 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 809     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 810 #ifndef POWER
 811 #define POWER
 812 #endif
 813 #define OPENBLAS_SUPPORTED
 814 #endif
 815
 816 #if defined(__i386__) || (__x86_64__)
 817 #include "cpuid_x86.c"
 818 #define OPENBLAS_SUPPORTED
 819 #endif
 820
 821 #ifdef __ia64__
 822 #include "cpuid_ia64.c"
 823 #define OPENBLAS_SUPPORTED
 824 #endif
 825
 826 #ifdef __alpha
 827 #include "cpuid_alpha.c"
 828 #define OPENBLAS_SUPPORTED
 829 #endif
 830
 831 #ifdef POWER
 832 #include "cpuid_power.c"
 833 #define OPENBLAS_SUPPORTED
 834 #endif
 835
 836 #ifdef sparc
 837 #include "cpuid_sparc.c"
 838 #define OPENBLAS_SUPPORTED
 839 #endif
 840
 841 #ifdef __mips__
 842 #include "cpuid_mips.c"
 843 #define OPENBLAS_SUPPORTED
 844 #endif
 845
 846 #ifdef __arm__
 847 #include "cpuid_arm.c"
 848 #define OPENBLAS_SUPPORTED
 849 #endif
 850
 851 #ifdef __aarch64__
 852 #include "cpuid_arm64.c"
 853 #define OPENBLAS_SUPPORTED
 854 #endif
 855
 856
 857 #ifndef OPENBLAS_SUPPORTED
 858 #error "This arch/CPU is not supported by OpenBLAS."
 859 #endif
 860
 861 #else
 862
 863 #endif
 864
 865 static int get_num_cores(void) {
 866
 867 #ifdef OS_WINDOWS
 868   SYSTEM_INFO sysinfo;
 869 #elif defined(__FreeBSD__) || defined(__APPLE__)
 870   int m[2], count;
 871   size_t len;
 872 #endif
 873
 874 #ifdef linux
 875   //returns the number of processors which are currently online
 876   return sysconf(_SC_NPROCESSORS_ONLN);
 877
 878 #elif defined(OS_WINDOWS)
 879
 880   GetSystemInfo(&sysinfo);
 881   return sysinfo.dwNumberOfProcessors;
 882
 883 #elif defined(__FreeBSD__) || defined(__APPLE__)
 884   m[0] = CTL_HW;
 885   m[1] = HW_NCPU;
 886   len = sizeof(int);
 887   sysctl(m, 2, &count, &len, NULL, 0);
 888
 889   return count;
 890 #else
 891   return 2;
 892 #endif
 893 }
 894
 895 int main(int argc, char *argv[]){
 896
 897 #ifdef FORCE
 898   char buffer[8192], *p, *q;
 899   int length;
 900 #endif
 901
 902   if (argc == 1) return 0;
 903
 904   switch (argv[1][0]) {
 905
 906   case '0' : /* for Makefile */
 907
 908 #ifdef FORCE
 909     printf("CORE=%s\n", CORENAME);
 910 #else
 911 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 912     printf("CORE=%s\n", get_corename());
 913 #endif
 914 #endif
 915
 916 #ifdef FORCE
 917     printf("LIBCORE=%s\n", LIBNAME);
 918 #else
 919     printf("LIBCORE=");
 920     get_libname();
 921     printf("\n");
 922 #endif
 923
 924     printf("NUM_CORES=%d\n", get_num_cores());
 925
 926 #if defined(__arm__) && !defined(FORCE)
 927         get_features();
 928 #endif
 929
 930
 931 #if defined(__i386__) || defined(__x86_64__)
 932 #ifndef FORCE
 933     get_sse();
 934 #else
 935
 936     sprintf(buffer, "%s", ARCHCONFIG);
 937
 938     p = &buffer[0];
 939
 940     while (*p) {
 941       if ((*p == '-') && (*(p + 1) == 'D')) {
 942         p += 2;
 943
 944         while ((*p != ' ') && (*p != '\0')) {
 945
 946           if (*p == '=') {
 947             printf("=");
 948             p ++;
 949             while ((*p != ' ') && (*p != '\0')) {
 950               printf("%c", *p);
 951               p ++;
 952             }
 953           } else {
 954             printf("%c", *p);
 955             p ++;
 956             if ((*p == ' ') || (*p =='\0')) printf("=1");
 957           }
 958         }
 959
 960         printf("\n");
 961       } else p ++;
 962     }
 963 #endif
 964 #endif
 965
 966 #if NO_PARALLEL_MAKE==1
 967     printf("MAKE += -j 1\n");
 968 #else
 969 #ifndef OS_WINDOWS
 970     printf("MAKE += -j %d\n", get_num_cores());
 971 #endif
 972 #endif
 973
 974     break;
 975
 976   case '1' : /* For config.h */
 977 #ifdef FORCE
 978     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 979
 980     p = &buffer[0];
 981     while (*p) {
 982       if ((*p == '-') && (*(p + 1) == 'D')) {
 983         p += 2;
 984         printf("#define ");
 985
 986         while ((*p != ' ') && (*p != '\0')) {
 987
 988           if (*p == '=') {
 989             printf(" ");
 990             p ++;
 991             while ((*p != ' ') && (*p != '\0')) {
 992               printf("%c", *p);
 993               p ++;
 994             }
 995           } else {
 996             printf("%c", *p);
 997             p ++;
 998           }
 999         }
1000
1001         printf("\n");
1002       } else p ++;
1003     }
1004 #else
1005     get_cpuconfig();
1006 #endif
1007
1008 #ifdef FORCE
1009     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1010 #else
1011 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1012     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1013 #endif
1014 #endif
1015
1016  break;
1017
1018   case '2' : /* SMP */
1019     if (get_num_cores() > 1) printf("SMP=1\n");
1020     break;
1021   }
1022
1023   fflush(stdout);
1024
1025   return 0;
1026 }
1027