getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #include <stdio.h>
  77 #include <string.h>
  78 #ifdef OS_WINDOWS
  79 #include <windows.h>
  80 #endif
  81 #if defined(__FreeBSD__) || defined(__APPLE__)
  82 #include <sys/types.h>
  83 #include <sys/sysctl.h>
  84 #endif
  85 #ifdef linux
  86 #include <sys/sysinfo.h>
  87 #include <unistd.h>
  88 #endif
  89
  90 /* #define FORCE_P2             */
  91 /* #define FORCE_KATMAI         */
  92 /* #define FORCE_COPPERMINE     */
  93 /* #define FORCE_NORTHWOOD      */
  94 /* #define FORCE_PRESCOTT       */
  95 /* #define FORCE_BANIAS         */
  96 /* #define FORCE_YONAH          */
  97 /* #define FORCE_CORE2          */
  98 /* #define FORCE_PENRYN         */
  99 /* #define FORCE_DUNNINGTON     */
 100 /* #define FORCE_NEHALEM        */
 101 /* #define FORCE_SANDYBRIDGE    */
 102 /* #define FORCE_ATOM           */
 103 /* #define FORCE_ATHLON         */
 104 /* #define FORCE_OPTERON        */
 105 /* #define FORCE_OPTERON_SSE3   */
 106 /* #define FORCE_BARCELONA      */
 107 /* #define FORCE_SHANGHAI       */
 108 /* #define FORCE_ISTANBUL       */
 109 /* #define FORCE_BOBCAT         */
 110 /* #define FORCE_BULLDOZER      */
 111 /* #define FORCE_PILEDRIVER     */
 112 /* #define FORCE_SSE_GENERIC    */
 113 /* #define FORCE_VIAC3          */
 114 /* #define FORCE_NANO           */
 115 /* #define FORCE_POWER3         */
 116 /* #define FORCE_POWER4         */
 117 /* #define FORCE_POWER5         */
 118 /* #define FORCE_POWER6         */
 119 /* #define FORCE_PPCG4          */
 120 /* #define FORCE_PPC970         */
 121 /* #define FORCE_PPC970MP       */
 122 /* #define FORCE_PPC440         */
 123 /* #define FORCE_PPC440FP2      */
 124 /* #define FORCE_CELL           */
 125 /* #define FORCE_SICORTEX       */
 126 /* #define FORCE_LOONGSON3A     */
 127 /* #define FORCE_LOONGSON3B     */
 128 /* #define FORCE_ITANIUM2       */
 129 /* #define FORCE_SPARC          */
 130 /* #define FORCE_SPARCV7        */
 131 /* #define FORCE_GENERIC        */
 132
 133 #ifdef FORCE_P2
 134 #define FORCE
 135 #define FORCE_INTEL
 136 #define ARCHITECTURE    "X86"
 137 #define SUBARCHITECTURE "PENTIUM2"
 138 #define ARCHCONFIG   "-DPENTIUM2 " \
 139                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 140                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 141                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 142                      "-DHAVE_CMOV -DHAVE_MMX"
 143 #define LIBNAME   "p2"
 144 #define CORENAME  "P5"
 145 #endif
 146
 147 #ifdef FORCE_KATMAI
 148 #define FORCE
 149 #define FORCE_INTEL
 150 #define ARCHITECTURE    "X86"
 151 #define SUBARCHITECTURE "PENTIUM3"
 152 #define ARCHCONFIG   "-DPENTIUM3 " \
 153                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 154                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 155                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 156                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 157 #define LIBNAME   "katmai"
 158 #define CORENAME  "KATMAI"
 159 #endif
 160
 161 #ifdef FORCE_COPPERMINE
 162 #define FORCE
 163 #define FORCE_INTEL
 164 #define ARCHITECTURE    "X86"
 165 #define SUBARCHITECTURE "PENTIUM3"
 166 #define ARCHCONFIG   "-DPENTIUM3 " \
 167                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 168                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 169                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 170                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 171 #define LIBNAME   "coppermine"
 172 #define CORENAME  "COPPERMINE"
 173 #endif
 174
 175 #ifdef FORCE_NORTHWOOD
 176 #define FORCE
 177 #define FORCE_INTEL
 178 #define ARCHITECTURE    "X86"
 179 #define SUBARCHITECTURE "PENTIUM4"
 180 #define ARCHCONFIG   "-DPENTIUM4 " \
 181                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 182                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 183                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 184                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 185 #define LIBNAME   "northwood"
 186 #define CORENAME  "NORTHWOOD"
 187 #endif
 188
 189 #ifdef FORCE_PRESCOTT
 190 #define FORCE
 191 #define FORCE_INTEL
 192 #define ARCHITECTURE    "X86"
 193 #define SUBARCHITECTURE "PENTIUM4"
 194 #define ARCHCONFIG   "-DPENTIUM4 " \
 195                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 196                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 197                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 198                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 199 #define LIBNAME   "prescott"
 200 #define CORENAME  "PRESCOTT"
 201 #endif
 202
 203 #ifdef FORCE_BANIAS
 204 #define FORCE
 205 #define FORCE_INTEL
 206 #define ARCHITECTURE    "X86"
 207 #define SUBARCHITECTURE "BANIAS"
 208 #define ARCHCONFIG   "-DPENTIUMM " \
 209                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 210                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 211                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 212                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 213 #define LIBNAME   "banias"
 214 #define CORENAME  "BANIAS"
 215 #endif
 216
 217 #ifdef FORCE_YONAH
 218 #define FORCE
 219 #define FORCE_INTEL
 220 #define ARCHITECTURE    "X86"
 221 #define SUBARCHITECTURE "YONAH"
 222 #define ARCHCONFIG   "-DPENTIUMM " \
 223                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 224                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 225                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 226                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 227 #define LIBNAME   "yonah"
 228 #define CORENAME  "YONAH"
 229 #endif
 230
 231 #ifdef FORCE_CORE2
 232 #define FORCE
 233 #define FORCE_INTEL
 234 #define ARCHITECTURE    "X86"
 235 #define SUBARCHITECTURE "CONRORE"
 236 #define ARCHCONFIG   "-DCORE2 " \
 237                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 238                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 239                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 240                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 241 #define LIBNAME   "core2"
 242 #define CORENAME  "CORE2"
 243 #endif
 244
 245 #ifdef FORCE_PENRYN
 246 #define FORCE
 247 #define FORCE_INTEL
 248 #define ARCHITECTURE    "X86"
 249 #define SUBARCHITECTURE "PENRYN"
 250 #define ARCHCONFIG   "-DPENRYN " \
 251                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 252                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 253                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 254                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 255 #define LIBNAME   "penryn"
 256 #define CORENAME  "PENRYN"
 257 #endif
 258
 259 #ifdef FORCE_DUNNINGTON
 260 #define FORCE
 261 #define FORCE_INTEL
 262 #define ARCHITECTURE    "X86"
 263 #define SUBARCHITECTURE "DUNNINGTON"
 264 #define ARCHCONFIG   "-DDUNNINGTON " \
 265                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 266                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 267                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 268                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 269                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 270 #define LIBNAME   "dunnington"
 271 #define CORENAME  "DUNNINGTON"
 272 #endif
 273
 274 #ifdef FORCE_NEHALEM
 275 #define FORCE
 276 #define FORCE_INTEL
 277 #define ARCHITECTURE    "X86"
 278 #define SUBARCHITECTURE "NEHALEM"
 279 #define ARCHCONFIG   "-DNEHALEM " \
 280                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 281                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 282                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 283                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 284 #define LIBNAME   "nehalem"
 285 #define CORENAME  "NEHALEM"
 286 #endif
 287
 288 #ifdef FORCE_SANDYBRIDGE
 289 #define FORCE
 290 #define FORCE_INTEL
 291 #define ARCHITECTURE    "X86"
 292 #define SUBARCHITECTURE "SANDYBRIDGE"
 293 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 294                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 295                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 296                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 297                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 298 #define LIBNAME   "sandybridge"
 299 #define CORENAME  "SANDYBRIDGE"
 300 #endif
 301
 302 #ifdef FORCE_HASWELL
 303 #define FORCE
 304 #define FORCE_INTEL
 305 #define ARCHITECTURE    "X86"
 306 #define SUBARCHITECTURE "HASWELL"
 307 #define ARCHCONFIG   "-DHASWELL " \
 308                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 309                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 310                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 311                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 312                      "-DFMA3"
 313 #define LIBNAME   "haswell"
 314 #define CORENAME  "HASWELL"
 315 #endif
 316
 317 #ifdef FORCE_ATOM
 318 #define FORCE
 319 #define FORCE_INTEL
 320 #define ARCHITECTURE    "X86"
 321 #define SUBARCHITECTURE "ATOM"
 322 #define ARCHCONFIG   "-DATOM " \
 323                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 324                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 325                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 326                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 327 #define LIBNAME   "atom"
 328 #define CORENAME  "ATOM"
 329 #endif
 330
 331 #ifdef FORCE_ATHLON
 332 #define FORCE
 333 #define FORCE_INTEL
 334 #define ARCHITECTURE    "X86"
 335 #define SUBARCHITECTURE "ATHLON"
 336 #define ARCHCONFIG   "-DATHLON " \
 337                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 338                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 339                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 340                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 341 #define LIBNAME   "athlon"
 342 #define CORENAME  "ATHLON"
 343 #endif
 344
 345 #ifdef FORCE_OPTERON
 346 #define FORCE
 347 #define FORCE_INTEL
 348 #define ARCHITECTURE    "X86"
 349 #define SUBARCHITECTURE "OPTERON"
 350 #define ARCHCONFIG   "-DOPTERON " \
 351                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 352                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 353                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 354                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 355 #define LIBNAME   "opteron"
 356 #define CORENAME  "OPTERON"
 357 #endif
 358
 359 #ifdef FORCE_OPTERON_SSE3
 360 #define FORCE
 361 #define FORCE_INTEL
 362 #define ARCHITECTURE    "X86"
 363 #define SUBARCHITECTURE "OPTERON"
 364 #define ARCHCONFIG   "-DOPTERON " \
 365                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 366                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 367                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 368                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 369 #define LIBNAME   "opteron"
 370 #define CORENAME  "OPTERON"
 371 #endif
 372
 373 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 374 #define FORCE
 375 #define FORCE_INTEL
 376 #define ARCHITECTURE    "X86"
 377 #define SUBARCHITECTURE "BARCELONA"
 378 #define ARCHCONFIG   "-DBARCELONA " \
 379                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 380                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 381                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 382                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 383                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 384 #define LIBNAME   "barcelona"
 385 #define CORENAME  "BARCELONA"
 386 #endif
 387
 388 #if defined(FORCE_BOBCAT)
 389 #define FORCE
 390 #define FORCE_INTEL
 391 #define ARCHITECTURE    "X86"
 392 #define SUBARCHITECTURE "BOBCAT"
 393 #define ARCHCONFIG   "-DBOBCAT " \
 394                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 395                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 396                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 397                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 398                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 399 #define LIBNAME   "bobcat"
 400 #define CORENAME  "BOBCAT"
 401 #endif
 402
 403 #if defined (FORCE_BULLDOZER)
 404 #define FORCE
 405 #define FORCE_INTEL
 406 #define ARCHITECTURE    "X86"
 407 #define SUBARCHITECTURE "BULLDOZER"
 408 #define ARCHCONFIG   "-DBULLDOZER " \
 409                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 410                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 411                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 412                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 413                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 414                      "-DHAVE_AVX -DHAVE_FMA4"
 415 #define LIBNAME   "bulldozer"
 416 #define CORENAME  "BULLDOZER"
 417 #endif
 418
 419 #if defined (FORCE_PILEDRIVER)
 420 #define FORCE
 421 #define FORCE_INTEL
 422 #define ARCHITECTURE    "X86"
 423 #define SUBARCHITECTURE "PILEDRIVER"
 424 #define ARCHCONFIG   "-DPILEDRIVER " \
 425                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 426                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 427                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 428                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 429                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 430                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 431 #define LIBNAME   "piledriver"
 432 #define CORENAME  "PILEDRIVER"
 433 #endif
 434
 435 #if defined (FORCE_STEAMROLLER)
 436 #define FORCE
 437 #define FORCE_INTEL
 438 #define ARCHITECTURE    "X86"
 439 #define SUBARCHITECTURE "STEAMROLLER"
 440 #define ARCHCONFIG   "-DSTEAMROLLER " \
 441                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 442                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 443                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 444                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 445                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 446                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 447 #define LIBNAME   "steamroller"
 448 #define CORENAME  "STEAMROLLER"
 449 #endif
 450
 451 #if defined (FORCE_EXCAVATOR)
 452 #define FORCE
 453 #define FORCE_INTEL
 454 #define ARCHITECTURE    "X86"
 455 #define SUBARCHITECTURE "EXCAVATOR"
 456 #define ARCHCONFIG   "-DEXCAVATOR " \
 457                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 458                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 459                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 460                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 461                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 462                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 463 #define LIBNAME   "excavator"
 464 #define CORENAME  "EXCAVATOR"
 465 #endif
 466
 467
 468 #ifdef FORCE_SSE_GENERIC
 469 #define FORCE
 470 #define FORCE_INTEL
 471 #define ARCHITECTURE    "X86"
 472 #define SUBARCHITECTURE "GENERIC"
 473 #define ARCHCONFIG   "-DGENERIC " \
 474                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 475                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 476                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 477                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 478 #define LIBNAME   "generic"
 479 #define CORENAME  "GENERIC"
 480 #endif
 481
 482 #ifdef FORCE_VIAC3
 483 #define FORCE
 484 #define FORCE_INTEL
 485 #define ARCHITECTURE    "X86"
 486 #define SUBARCHITECTURE "VIAC3"
 487 #define ARCHCONFIG   "-DVIAC3 " \
 488                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 489                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 490                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 491                      "-DHAVE_MMX -DHAVE_SSE "
 492 #define LIBNAME   "viac3"
 493 #define CORENAME  "VIAC3"
 494 #endif
 495
 496 #ifdef FORCE_NANO
 497 #define FORCE
 498 #define FORCE_INTEL
 499 #define ARCHITECTURE    "X86"
 500 #define SUBARCHITECTURE "NANO"
 501 #define ARCHCONFIG   "-DNANO " \
 502                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 503                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 504                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 505                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 506 #define LIBNAME   "nano"
 507 #define CORENAME  "NANO"
 508 #endif
 509
 510 #ifdef FORCE_POWER3
 511 #define FORCE
 512 #define ARCHITECTURE    "POWER"
 513 #define SUBARCHITECTURE "POWER3"
 514 #define SUBDIRNAME      "power"
 515 #define ARCHCONFIG   "-DPOWER3 " \
 516                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 517                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 518                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 519 #define LIBNAME   "power3"
 520 #define CORENAME  "POWER3"
 521 #endif
 522
 523 #ifdef FORCE_POWER4
 524 #define FORCE
 525 #define ARCHITECTURE    "POWER"
 526 #define SUBARCHITECTURE "POWER4"
 527 #define SUBDIRNAME      "power"
 528 #define ARCHCONFIG   "-DPOWER4 " \
 529                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 530                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 531                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 532 #define LIBNAME   "power4"
 533 #define CORENAME  "POWER4"
 534 #endif
 535
 536 #ifdef FORCE_POWER5
 537 #define FORCE
 538 #define ARCHITECTURE    "POWER"
 539 #define SUBARCHITECTURE "POWER5"
 540 #define SUBDIRNAME      "power"
 541 #define ARCHCONFIG   "-DPOWER5 " \
 542                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 543                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 544                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 545 #define LIBNAME   "power5"
 546 #define CORENAME  "POWER5"
 547 #endif
 548
 549 #ifdef FORCE_POWER6
 550 #define FORCE
 551 #define ARCHITECTURE    "POWER"
 552 #define SUBARCHITECTURE "POWER6"
 553 #define SUBDIRNAME      "power"
 554 #define ARCHCONFIG   "-DPOWER6 " \
 555                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 556                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 557                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 558 #define LIBNAME   "power6"
 559 #define CORENAME  "POWER6"
 560 #endif
 561
 562 #ifdef FORCE_PPCG4
 563 #define FORCE
 564 #define ARCHITECTURE    "POWER"
 565 #define SUBARCHITECTURE "PPCG4"
 566 #define SUBDIRNAME      "power"
 567 #define ARCHCONFIG   "-DPPCG4 " \
 568                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 569                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 570                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 571 #define LIBNAME   "ppcg4"
 572 #define CORENAME  "PPCG4"
 573 #endif
 574
 575 #ifdef FORCE_PPC970
 576 #define FORCE
 577 #define ARCHITECTURE    "POWER"
 578 #define SUBARCHITECTURE "PPC970"
 579 #define SUBDIRNAME      "power"
 580 #define ARCHCONFIG   "-DPPC970 " \
 581                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 582                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 583                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 584 #define LIBNAME   "ppc970"
 585 #define CORENAME  "PPC970"
 586 #endif
 587
 588 #ifdef FORCE_PPC970MP
 589 #define FORCE
 590 #define ARCHITECTURE    "POWER"
 591 #define SUBARCHITECTURE "PPC970"
 592 #define SUBDIRNAME      "power"
 593 #define ARCHCONFIG   "-DPPC970 " \
 594                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 595                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 596                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 597 #define LIBNAME   "ppc970mp"
 598 #define CORENAME  "PPC970"
 599 #endif
 600
 601 #ifdef FORCE_PPC440
 602 #define FORCE
 603 #define ARCHITECTURE    "POWER"
 604 #define SUBARCHITECTURE "PPC440"
 605 #define SUBDIRNAME      "power"
 606 #define ARCHCONFIG   "-DPPC440 " \
 607                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 608                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 609                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 610 #define LIBNAME   "ppc440"
 611 #define CORENAME  "PPC440"
 612 #endif
 613
 614 #ifdef FORCE_PPC440FP2
 615 #define FORCE
 616 #define ARCHITECTURE    "POWER"
 617 #define SUBARCHITECTURE "PPC440FP2"
 618 #define SUBDIRNAME      "power"
 619 #define ARCHCONFIG   "-DPPC440FP2 " \
 620                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 621                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 622                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 623 #define LIBNAME   "ppc440FP2"
 624 #define CORENAME  "PPC440FP2"
 625 #endif
 626
 627 #ifdef FORCE_CELL
 628 #define FORCE
 629 #define ARCHITECTURE    "POWER"
 630 #define SUBARCHITECTURE "CELL"
 631 #define SUBDIRNAME      "power"
 632 #define ARCHCONFIG   "-DCELL " \
 633                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 634                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 635                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 636 #define LIBNAME   "cell"
 637 #define CORENAME  "CELL"
 638 #endif
 639
 640 #ifdef FORCE_SICORTEX
 641 #define FORCE
 642 #define ARCHITECTURE    "MIPS"
 643 #define SUBARCHITECTURE "SICORTEX"
 644 #define SUBDIRNAME      "mips"
 645 #define ARCHCONFIG   "-DSICORTEX " \
 646                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 647                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 648                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 649 #define LIBNAME   "mips"
 650 #define CORENAME  "sicortex"
 651 #endif
 652
 653
 654 #ifdef FORCE_LOONGSON3A
 655 #define FORCE
 656 #define ARCHITECTURE    "MIPS"
 657 #define SUBARCHITECTURE "LOONGSON3A"
 658 #define SUBDIRNAME      "mips64"
 659 #define ARCHCONFIG   "-DLOONGSON3A " \
 660        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 661        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 662        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 663 #define LIBNAME   "loongson3a"
 664 #define CORENAME  "LOONGSON3A"
 665 #else
 666 #endif
 667
 668 #ifdef FORCE_LOONGSON3B
 669 #define FORCE
 670 #define ARCHITECTURE    "MIPS"
 671 #define SUBARCHITECTURE "LOONGSON3B"
 672 #define SUBDIRNAME      "mips64"
 673 #define ARCHCONFIG   "-DLOONGSON3B " \
 674        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 675        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 676        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 677 #define LIBNAME   "loongson3b"
 678 #define CORENAME  "LOONGSON3B"
 679 #else
 680 #endif
 681
 682 #ifdef FORCE_ITANIUM2
 683 #define FORCE
 684 #define ARCHITECTURE    "IA64"
 685 #define SUBARCHITECTURE "ITANIUM2"
 686 #define SUBDIRNAME      "ia64"
 687 #define ARCHCONFIG   "-DITANIUM2 " \
 688                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 689                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 690 #define LIBNAME   "itanium2"
 691 #define CORENAME  "itanium2"
 692 #endif
 693
 694 #ifdef FORCE_SPARC
 695 #define FORCE
 696 #define ARCHITECTURE    "SPARC"
 697 #define SUBARCHITECTURE "SPARC"
 698 #define SUBDIRNAME      "sparc"
 699 #define ARCHCONFIG   "-DSPARC -DV9 " \
 700                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 701                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 702 #define LIBNAME   "sparc"
 703 #define CORENAME  "sparc"
 704 #endif
 705
 706 #ifdef FORCE_SPARCV7
 707 #define FORCE
 708 #define ARCHITECTURE    "SPARC"
 709 #define SUBARCHITECTURE "SPARC"
 710 #define SUBDIRNAME      "sparc"
 711 #define ARCHCONFIG   "-DSPARC -DV7 " \
 712                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 713                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 714 #define LIBNAME   "sparcv7"
 715 #define CORENAME  "sparcv7"
 716 #endif
 717
 718 #ifdef FORCE_GENERIC
 719 #define FORCE
 720 #define ARCHITECTURE    "GENERIC"
 721 #define SUBARCHITECTURE "GENERIC"
 722 #define SUBDIRNAME      "generic"
 723 #define ARCHCONFIG   "-DGENERIC " \
 724                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 725                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 726                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 727 #define LIBNAME   "generic"
 728 #define CORENAME  "generic"
 729 #endif
 730
 731 #ifdef FORCE_ARMV7
 732 #define FORCE
 733 #define ARCHITECTURE    "ARM"
 734 #define SUBARCHITECTURE "ARMV7"
 735 #define SUBDIRNAME      "arm"
 736 #define ARCHCONFIG   "-DARMV7 " \
 737        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 738        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 739        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 740        "-DHAVE_VFPV3 -DHAVE_VFP"
 741 #define LIBNAME   "armv7"
 742 #define CORENAME  "ARMV7"
 743 #else
 744 #endif
 745
 746 #ifdef FORCE_CORTEXA9
 747 #define FORCE
 748 #define ARCHITECTURE    "ARM"
 749 #define SUBARCHITECTURE "CORTEXA9"
 750 #define SUBDIRNAME      "arm"
 751 #define ARCHCONFIG   "-DCORTEXA9 " \
 752        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 753        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 754        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 755        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 756 #define LIBNAME   "cortexa9"
 757 #define CORENAME  "CORTEXA9"
 758 #else
 759 #endif
 760
 761 #ifdef FORCE_CORTEXA15
 762 #define FORCE
 763 #define ARCHITECTURE    "ARM"
 764 #define SUBARCHITECTURE "CORTEXA15"
 765 #define SUBDIRNAME      "arm"
 766 #define ARCHCONFIG   "-DCORTEXA15 " \
 767        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 768        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 769        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 770        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 771 #define LIBNAME   "cortexa15"
 772 #define CORENAME  "CORTEXA15"
 773 #else
 774 #endif
 775
 776 #ifdef FORCE_ARMV6
 777 #define FORCE
 778 #define ARCHITECTURE    "ARM"
 779 #define SUBARCHITECTURE "ARMV6"
 780 #define SUBDIRNAME      "arm"
 781 #define ARCHCONFIG   "-DARMV6 " \
 782        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 783        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 784        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 785        "-DHAVE_VFP"
 786 #define LIBNAME   "armv6"
 787 #define CORENAME  "ARMV6"
 788 #else
 789 #endif
 790
 791 #ifdef FORCE_ARMV5
 792 #define FORCE
 793 #define ARCHITECTURE    "ARM"
 794 #define SUBARCHITECTURE "ARMV5"
 795 #define SUBDIRNAME      "arm"
 796 #define ARCHCONFIG   "-DARMV5 " \
 797        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 798        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 799        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 800        "-DHAVE_VFP"
 801 #define LIBNAME   "armv5"
 802 #define CORENAME  "ARMV5"
 803 #else
 804 #endif
 805
 806
 807 #ifdef FORCE_ARMV8
 808 #define FORCE
 809 #define ARCHITECTURE    "ARM64"
 810 #define SUBARCHITECTURE "ARMV8"
 811 #define SUBDIRNAME      "arm64"
 812 #define ARCHCONFIG   "-DARMV8 " \
 813        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 814        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 815        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 816 #define LIBNAME   "armv8"
 817 #define CORENAME  "XGENE1"
 818 #else
 819 #endif
 820
 821
 822 #ifndef FORCE
 823
 824 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 825     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 826 #ifndef POWER
 827 #define POWER
 828 #endif
 829 #define OPENBLAS_SUPPORTED
 830 #endif
 831
 832 #if defined(__i386__) || (__x86_64__)
 833 #include "cpuid_x86.c"
 834 #define OPENBLAS_SUPPORTED
 835 #endif
 836
 837 #ifdef __ia64__
 838 #include "cpuid_ia64.c"
 839 #define OPENBLAS_SUPPORTED
 840 #endif
 841
 842 #ifdef __alpha
 843 #include "cpuid_alpha.c"
 844 #define OPENBLAS_SUPPORTED
 845 #endif
 846
 847 #ifdef POWER
 848 #include "cpuid_power.c"
 849 #define OPENBLAS_SUPPORTED
 850 #endif
 851
 852 #ifdef sparc
 853 #include "cpuid_sparc.c"
 854 #define OPENBLAS_SUPPORTED
 855 #endif
 856
 857 #ifdef __mips__
 858 #include "cpuid_mips.c"
 859 #define OPENBLAS_SUPPORTED
 860 #endif
 861
 862 #ifdef __arm__
 863 #include "cpuid_arm.c"
 864 #define OPENBLAS_SUPPORTED
 865 #endif
 866
 867 #ifdef __aarch64__
 868 #include "cpuid_arm64.c"
 869 #define OPENBLAS_SUPPORTED
 870 #endif
 871
 872
 873 #ifndef OPENBLAS_SUPPORTED
 874 #error "This arch/CPU is not supported by OpenBLAS."
 875 #endif
 876
 877 #else
 878
 879 #endif
 880
 881 static int get_num_cores(void) {
 882
 883 #ifdef OS_WINDOWS
 884   SYSTEM_INFO sysinfo;
 885 #elif defined(__FreeBSD__) || defined(__APPLE__)
 886   int m[2], count;
 887   size_t len;
 888 #endif
 889
 890 #ifdef linux
 891   //returns the number of processors which are currently online
 892   return sysconf(_SC_NPROCESSORS_ONLN);
 893
 894 #elif defined(OS_WINDOWS)
 895
 896   GetSystemInfo(&sysinfo);
 897   return sysinfo.dwNumberOfProcessors;
 898
 899 #elif defined(__FreeBSD__) || defined(__APPLE__)
 900   m[0] = CTL_HW;
 901   m[1] = HW_NCPU;
 902   len = sizeof(int);
 903   sysctl(m, 2, &count, &len, NULL, 0);
 904
 905   return count;
 906 #else
 907   return 2;
 908 #endif
 909 }
 910
 911 int main(int argc, char *argv[]){
 912
 913 #ifdef FORCE
 914   char buffer[8192], *p, *q;
 915   int length;
 916 #endif
 917
 918   if (argc == 1) return 0;
 919
 920   switch (argv[1][0]) {
 921
 922   case '0' : /* for Makefile */
 923
 924 #ifdef FORCE
 925     printf("CORE=%s\n", CORENAME);
 926 #else
 927 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 928     printf("CORE=%s\n", get_corename());
 929 #endif
 930 #endif
 931
 932 #ifdef FORCE
 933     printf("LIBCORE=%s\n", LIBNAME);
 934 #else
 935     printf("LIBCORE=");
 936     get_libname();
 937     printf("\n");
 938 #endif
 939
 940     printf("NUM_CORES=%d\n", get_num_cores());
 941
 942 #if defined(__arm__) && !defined(FORCE)
 943         get_features();
 944 #endif
 945
 946
 947 #if defined(__i386__) || defined(__x86_64__)
 948 #ifndef FORCE
 949     get_sse();
 950 #else
 951
 952     sprintf(buffer, "%s", ARCHCONFIG);
 953
 954     p = &buffer[0];
 955
 956     while (*p) {
 957       if ((*p == '-') && (*(p + 1) == 'D')) {
 958         p += 2;
 959
 960         while ((*p != ' ') && (*p != '\0')) {
 961
 962           if (*p == '=') {
 963             printf("=");
 964             p ++;
 965             while ((*p != ' ') && (*p != '\0')) {
 966               printf("%c", *p);
 967               p ++;
 968             }
 969           } else {
 970             printf("%c", *p);
 971             p ++;
 972             if ((*p == ' ') || (*p =='\0')) printf("=1");
 973           }
 974         }
 975
 976         printf("\n");
 977       } else p ++;
 978     }
 979 #endif
 980 #endif
 981
 982 #if NO_PARALLEL_MAKE==1
 983     printf("MAKE += -j 1\n");
 984 #else
 985 #ifndef OS_WINDOWS
 986     printf("MAKE += -j %d\n", get_num_cores());
 987 #endif
 988 #endif
 989
 990     break;
 991
 992   case '1' : /* For config.h */
 993 #ifdef FORCE
 994     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 995
 996     p = &buffer[0];
 997     while (*p) {
 998       if ((*p == '-') && (*(p + 1) == 'D')) {
 999         p += 2;
1000         printf("#define ");
1001
1002         while ((*p != ' ') && (*p != '\0')) {
1003
1004           if (*p == '=') {
1005             printf(" ");
1006             p ++;
1007             while ((*p != ' ') && (*p != '\0')) {
1008               printf("%c", *p);
1009               p ++;
1010             }
1011           } else {
1012             printf("%c", *p);
1013             p ++;
1014           }
1015         }
1016
1017         printf("\n");
1018       } else p ++;
1019     }
1020 #else
1021     get_cpuconfig();
1022 #endif
1023
1024 #ifdef FORCE
1025     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1026 #else
1027 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1028     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1029 #endif
1030 #endif
1031
1032  break;
1033
1034   case '2' : /* SMP */
1035     if (get_num_cores() > 1) printf("SMP=1\n");
1036     break;
1037   }
1038
1039   fflush(stdout);
1040
1041   return 0;
1042 }
1043