getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P6600          */
 136 /* #define FORCE_P5600          */
 137 /* #define FORCE_ITANIUM2       */
 138 /* #define FORCE_SPARC          */
 139 /* #define FORCE_SPARCV7        */
 140 /* #define FORCE_GENERIC        */
 141
 142 #ifdef FORCE_P2
 143 #define FORCE
 144 #define FORCE_INTEL
 145 #define ARCHITECTURE    "X86"
 146 #define SUBARCHITECTURE "PENTIUM2"
 147 #define ARCHCONFIG   "-DPENTIUM2 " \
 148                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 149                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 150                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 151                      "-DHAVE_CMOV -DHAVE_MMX"
 152 #define LIBNAME   "p2"
 153 #define CORENAME  "P5"
 154 #endif
 155
 156 #ifdef FORCE_KATMAI
 157 #define FORCE
 158 #define FORCE_INTEL
 159 #define ARCHITECTURE    "X86"
 160 #define SUBARCHITECTURE "PENTIUM3"
 161 #define ARCHCONFIG   "-DPENTIUM3 " \
 162                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 163                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 164                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 165                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 166 #define LIBNAME   "katmai"
 167 #define CORENAME  "KATMAI"
 168 #endif
 169
 170 #ifdef FORCE_COPPERMINE
 171 #define FORCE
 172 #define FORCE_INTEL
 173 #define ARCHITECTURE    "X86"
 174 #define SUBARCHITECTURE "PENTIUM3"
 175 #define ARCHCONFIG   "-DPENTIUM3 " \
 176                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 177                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 178                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 179                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 180 #define LIBNAME   "coppermine"
 181 #define CORENAME  "COPPERMINE"
 182 #endif
 183
 184 #ifdef FORCE_NORTHWOOD
 185 #define FORCE
 186 #define FORCE_INTEL
 187 #define ARCHITECTURE    "X86"
 188 #define SUBARCHITECTURE "PENTIUM4"
 189 #define ARCHCONFIG   "-DPENTIUM4 " \
 190                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 191                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 192                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 193                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 194 #define LIBNAME   "northwood"
 195 #define CORENAME  "NORTHWOOD"
 196 #endif
 197
 198 #ifdef FORCE_PRESCOTT
 199 #define FORCE
 200 #define FORCE_INTEL
 201 #define ARCHITECTURE    "X86"
 202 #define SUBARCHITECTURE "PENTIUM4"
 203 #define ARCHCONFIG   "-DPENTIUM4 " \
 204                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 205                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 206                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 207                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 208 #define LIBNAME   "prescott"
 209 #define CORENAME  "PRESCOTT"
 210 #endif
 211
 212 #ifdef FORCE_BANIAS
 213 #define FORCE
 214 #define FORCE_INTEL
 215 #define ARCHITECTURE    "X86"
 216 #define SUBARCHITECTURE "BANIAS"
 217 #define ARCHCONFIG   "-DPENTIUMM " \
 218                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 219                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 220                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 221                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 222 #define LIBNAME   "banias"
 223 #define CORENAME  "BANIAS"
 224 #endif
 225
 226 #ifdef FORCE_YONAH
 227 #define FORCE
 228 #define FORCE_INTEL
 229 #define ARCHITECTURE    "X86"
 230 #define SUBARCHITECTURE "YONAH"
 231 #define ARCHCONFIG   "-DPENTIUMM " \
 232                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 233                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 234                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 235                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 236 #define LIBNAME   "yonah"
 237 #define CORENAME  "YONAH"
 238 #endif
 239
 240 #ifdef FORCE_CORE2
 241 #define FORCE
 242 #define FORCE_INTEL
 243 #define ARCHITECTURE    "X86"
 244 #define SUBARCHITECTURE "CONRORE"
 245 #define ARCHCONFIG   "-DCORE2 " \
 246                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 247                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 248                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 249                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 250 #define LIBNAME   "core2"
 251 #define CORENAME  "CORE2"
 252 #endif
 253
 254 #ifdef FORCE_PENRYN
 255 #define FORCE
 256 #define FORCE_INTEL
 257 #define ARCHITECTURE    "X86"
 258 #define SUBARCHITECTURE "PENRYN"
 259 #define ARCHCONFIG   "-DPENRYN " \
 260                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 261                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 262                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 263                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 264 #define LIBNAME   "penryn"
 265 #define CORENAME  "PENRYN"
 266 #endif
 267
 268 #ifdef FORCE_DUNNINGTON
 269 #define FORCE
 270 #define FORCE_INTEL
 271 #define ARCHITECTURE    "X86"
 272 #define SUBARCHITECTURE "DUNNINGTON"
 273 #define ARCHCONFIG   "-DDUNNINGTON " \
 274                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 275                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 276                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 277                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 278                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 279 #define LIBNAME   "dunnington"
 280 #define CORENAME  "DUNNINGTON"
 281 #endif
 282
 283 #ifdef FORCE_NEHALEM
 284 #define FORCE
 285 #define FORCE_INTEL
 286 #define ARCHITECTURE    "X86"
 287 #define SUBARCHITECTURE "NEHALEM"
 288 #define ARCHCONFIG   "-DNEHALEM " \
 289                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 290                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 291                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 292                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 293 #define LIBNAME   "nehalem"
 294 #define CORENAME  "NEHALEM"
 295 #endif
 296
 297 #ifdef FORCE_SANDYBRIDGE
 298 #define FORCE
 299 #define FORCE_INTEL
 300 #define ARCHITECTURE    "X86"
 301 #define SUBARCHITECTURE "SANDYBRIDGE"
 302 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 303                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 304                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 305                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 306                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 307 #define LIBNAME   "sandybridge"
 308 #define CORENAME  "SANDYBRIDGE"
 309 #endif
 310
 311 #ifdef FORCE_HASWELL
 312 #define FORCE
 313 #define FORCE_INTEL
 314 #define ARCHITECTURE    "X86"
 315 #define SUBARCHITECTURE "HASWELL"
 316 #define ARCHCONFIG   "-DHASWELL " \
 317                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 318                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 319                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 320                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 321                      "-DFMA3"
 322 #define LIBNAME   "haswell"
 323 #define CORENAME  "HASWELL"
 324 #endif
 325
 326 #ifdef FORCE_ATOM
 327 #define FORCE
 328 #define FORCE_INTEL
 329 #define ARCHITECTURE    "X86"
 330 #define SUBARCHITECTURE "ATOM"
 331 #define ARCHCONFIG   "-DATOM " \
 332                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 333                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 334                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 335                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 336 #define LIBNAME   "atom"
 337 #define CORENAME  "ATOM"
 338 #endif
 339
 340 #ifdef FORCE_ATHLON
 341 #define FORCE
 342 #define FORCE_INTEL
 343 #define ARCHITECTURE    "X86"
 344 #define SUBARCHITECTURE "ATHLON"
 345 #define ARCHCONFIG   "-DATHLON " \
 346                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 347                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 348                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 349                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 350 #define LIBNAME   "athlon"
 351 #define CORENAME  "ATHLON"
 352 #endif
 353
 354 #ifdef FORCE_OPTERON
 355 #define FORCE
 356 #define FORCE_INTEL
 357 #define ARCHITECTURE    "X86"
 358 #define SUBARCHITECTURE "OPTERON"
 359 #define ARCHCONFIG   "-DOPTERON " \
 360                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 361                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 362                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 363                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 364 #define LIBNAME   "opteron"
 365 #define CORENAME  "OPTERON"
 366 #endif
 367
 368 #ifdef FORCE_OPTERON_SSE3
 369 #define FORCE
 370 #define FORCE_INTEL
 371 #define ARCHITECTURE    "X86"
 372 #define SUBARCHITECTURE "OPTERON"
 373 #define ARCHCONFIG   "-DOPTERON " \
 374                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 375                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 376                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 377                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 378 #define LIBNAME   "opteron"
 379 #define CORENAME  "OPTERON"
 380 #endif
 381
 382 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 383 #define FORCE
 384 #define FORCE_INTEL
 385 #define ARCHITECTURE    "X86"
 386 #define SUBARCHITECTURE "BARCELONA"
 387 #define ARCHCONFIG   "-DBARCELONA " \
 388                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 389                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 390                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 391                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 392                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 393 #define LIBNAME   "barcelona"
 394 #define CORENAME  "BARCELONA"
 395 #endif
 396
 397 #if defined(FORCE_BOBCAT)
 398 #define FORCE
 399 #define FORCE_INTEL
 400 #define ARCHITECTURE    "X86"
 401 #define SUBARCHITECTURE "BOBCAT"
 402 #define ARCHCONFIG   "-DBOBCAT " \
 403                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 404                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 405                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 406                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 407                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 408 #define LIBNAME   "bobcat"
 409 #define CORENAME  "BOBCAT"
 410 #endif
 411
 412 #if defined (FORCE_BULLDOZER)
 413 #define FORCE
 414 #define FORCE_INTEL
 415 #define ARCHITECTURE    "X86"
 416 #define SUBARCHITECTURE "BULLDOZER"
 417 #define ARCHCONFIG   "-DBULLDOZER " \
 418                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 419                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 420                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 421                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 422                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 423                      "-DHAVE_AVX -DHAVE_FMA4"
 424 #define LIBNAME   "bulldozer"
 425 #define CORENAME  "BULLDOZER"
 426 #endif
 427
 428 #if defined (FORCE_PILEDRIVER)
 429 #define FORCE
 430 #define FORCE_INTEL
 431 #define ARCHITECTURE    "X86"
 432 #define SUBARCHITECTURE "PILEDRIVER"
 433 #define ARCHCONFIG   "-DPILEDRIVER " \
 434                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 435                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 436                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 437                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 438                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 439                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 440 #define LIBNAME   "piledriver"
 441 #define CORENAME  "PILEDRIVER"
 442 #endif
 443
 444 #if defined (FORCE_STEAMROLLER)
 445 #define FORCE
 446 #define FORCE_INTEL
 447 #define ARCHITECTURE    "X86"
 448 #define SUBARCHITECTURE "STEAMROLLER"
 449 #define ARCHCONFIG   "-DSTEAMROLLER " \
 450                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 451                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 452                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 453                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 454                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 455                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 456 #define LIBNAME   "steamroller"
 457 #define CORENAME  "STEAMROLLER"
 458 #endif
 459
 460 #if defined (FORCE_EXCAVATOR)
 461 #define FORCE
 462 #define FORCE_INTEL
 463 #define ARCHITECTURE    "X86"
 464 #define SUBARCHITECTURE "EXCAVATOR"
 465 #define ARCHCONFIG   "-DEXCAVATOR " \
 466                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 467                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 468                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 469                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 470                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 471                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 472 #define LIBNAME   "excavator"
 473 #define CORENAME  "EXCAVATOR"
 474 #endif
 475
 476 #if defined (FORCE_ZEN)
 477 #define FORCE
 478 #define FORCE_INTEL
 479 #define ARCHITECTURE    "X86"
 480 #define SUBARCHITECTURE "ZEN"
 481 #define ARCHCONFIG   "-DZEN " \
 482                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 483                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 484                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 485                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 486                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 487                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 488                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 489                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 490                      "-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
 491 #define LIBNAME   "zen"
 492 #define CORENAME  "ZEN"
 493 #endif
 494
 495
 496 #ifdef FORCE_SSE_GENERIC
 497 #define FORCE
 498 #define FORCE_INTEL
 499 #define ARCHITECTURE    "X86"
 500 #define SUBARCHITECTURE "GENERIC"
 501 #define ARCHCONFIG   "-DGENERIC " \
 502                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 503                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 504                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 505                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 506 #define LIBNAME   "generic"
 507 #define CORENAME  "GENERIC"
 508 #endif
 509
 510 #ifdef FORCE_VIAC3
 511 #define FORCE
 512 #define FORCE_INTEL
 513 #define ARCHITECTURE    "X86"
 514 #define SUBARCHITECTURE "VIAC3"
 515 #define ARCHCONFIG   "-DVIAC3 " \
 516                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 517                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 518                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 519                      "-DHAVE_MMX -DHAVE_SSE "
 520 #define LIBNAME   "viac3"
 521 #define CORENAME  "VIAC3"
 522 #endif
 523
 524 #ifdef FORCE_NANO
 525 #define FORCE
 526 #define FORCE_INTEL
 527 #define ARCHITECTURE    "X86"
 528 #define SUBARCHITECTURE "NANO"
 529 #define ARCHCONFIG   "-DNANO " \
 530                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 531                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 532                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 533                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 534 #define LIBNAME   "nano"
 535 #define CORENAME  "NANO"
 536 #endif
 537
 538 #ifdef FORCE_POWER3
 539 #define FORCE
 540 #define ARCHITECTURE    "POWER"
 541 #define SUBARCHITECTURE "POWER3"
 542 #define SUBDIRNAME      "power"
 543 #define ARCHCONFIG   "-DPOWER3 " \
 544                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 545                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 546                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 547 #define LIBNAME   "power3"
 548 #define CORENAME  "POWER3"
 549 #endif
 550
 551 #ifdef FORCE_POWER4
 552 #define FORCE
 553 #define ARCHITECTURE    "POWER"
 554 #define SUBARCHITECTURE "POWER4"
 555 #define SUBDIRNAME      "power"
 556 #define ARCHCONFIG   "-DPOWER4 " \
 557                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 558                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 559                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 560 #define LIBNAME   "power4"
 561 #define CORENAME  "POWER4"
 562 #endif
 563
 564 #ifdef FORCE_POWER5
 565 #define FORCE
 566 #define ARCHITECTURE    "POWER"
 567 #define SUBARCHITECTURE "POWER5"
 568 #define SUBDIRNAME      "power"
 569 #define ARCHCONFIG   "-DPOWER5 " \
 570                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 571                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 572                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 573 #define LIBNAME   "power5"
 574 #define CORENAME  "POWER5"
 575 #endif
 576
 577 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 578 #define FORCE
 579 #define ARCHITECTURE    "POWER"
 580 #define SUBARCHITECTURE "POWER6"
 581 #define SUBDIRNAME      "power"
 582 #define ARCHCONFIG   "-DPOWER6 " \
 583                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 584                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 585                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 586 #define LIBNAME   "power6"
 587 #define CORENAME  "POWER6"
 588 #endif
 589
 590 #if defined(FORCE_POWER8)
 591 #define FORCE
 592 #define ARCHITECTURE    "POWER"
 593 #define SUBARCHITECTURE "POWER8"
 594 #define SUBDIRNAME      "power"
 595 #define ARCHCONFIG   "-DPOWER8 " \
 596                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 597                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 598                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 599 #define LIBNAME   "power8"
 600 #define CORENAME  "POWER8"
 601 #endif
 602
 603
 604 #ifdef FORCE_PPCG4
 605 #define FORCE
 606 #define ARCHITECTURE    "POWER"
 607 #define SUBARCHITECTURE "PPCG4"
 608 #define SUBDIRNAME      "power"
 609 #define ARCHCONFIG   "-DPPCG4 " \
 610                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 611                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 612                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 613 #define LIBNAME   "ppcg4"
 614 #define CORENAME  "PPCG4"
 615 #endif
 616
 617 #ifdef FORCE_PPC970
 618 #define FORCE
 619 #define ARCHITECTURE    "POWER"
 620 #define SUBARCHITECTURE "PPC970"
 621 #define SUBDIRNAME      "power"
 622 #define ARCHCONFIG   "-DPPC970 " \
 623                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 624                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 625                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 626 #define LIBNAME   "ppc970"
 627 #define CORENAME  "PPC970"
 628 #endif
 629
 630 #ifdef FORCE_PPC970MP
 631 #define FORCE
 632 #define ARCHITECTURE    "POWER"
 633 #define SUBARCHITECTURE "PPC970"
 634 #define SUBDIRNAME      "power"
 635 #define ARCHCONFIG   "-DPPC970 " \
 636                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 637                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 638                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 639 #define LIBNAME   "ppc970mp"
 640 #define CORENAME  "PPC970"
 641 #endif
 642
 643 #ifdef FORCE_PPC440
 644 #define FORCE
 645 #define ARCHITECTURE    "POWER"
 646 #define SUBARCHITECTURE "PPC440"
 647 #define SUBDIRNAME      "power"
 648 #define ARCHCONFIG   "-DPPC440 " \
 649                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 650                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 651                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 652 #define LIBNAME   "ppc440"
 653 #define CORENAME  "PPC440"
 654 #endif
 655
 656 #ifdef FORCE_PPC440FP2
 657 #define FORCE
 658 #define ARCHITECTURE    "POWER"
 659 #define SUBARCHITECTURE "PPC440FP2"
 660 #define SUBDIRNAME      "power"
 661 #define ARCHCONFIG   "-DPPC440FP2 " \
 662                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 663                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 664                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 665 #define LIBNAME   "ppc440FP2"
 666 #define CORENAME  "PPC440FP2"
 667 #endif
 668
 669 #ifdef FORCE_CELL
 670 #define FORCE
 671 #define ARCHITECTURE    "POWER"
 672 #define SUBARCHITECTURE "CELL"
 673 #define SUBDIRNAME      "power"
 674 #define ARCHCONFIG   "-DCELL " \
 675                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 676                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 677                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 678 #define LIBNAME   "cell"
 679 #define CORENAME  "CELL"
 680 #endif
 681
 682 #ifdef FORCE_SICORTEX
 683 #define FORCE
 684 #define ARCHITECTURE    "MIPS"
 685 #define SUBARCHITECTURE "SICORTEX"
 686 #define SUBDIRNAME      "mips"
 687 #define ARCHCONFIG   "-DSICORTEX " \
 688                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 689                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 690                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 691 #define LIBNAME   "mips"
 692 #define CORENAME  "sicortex"
 693 #endif
 694
 695
 696 #ifdef FORCE_LOONGSON3A
 697 #define FORCE
 698 #define ARCHITECTURE    "MIPS"
 699 #define SUBARCHITECTURE "LOONGSON3A"
 700 #define SUBDIRNAME      "mips64"
 701 #define ARCHCONFIG   "-DLOONGSON3A " \
 702        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 703        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 704        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 705 #define LIBNAME   "loongson3a"
 706 #define CORENAME  "LOONGSON3A"
 707 #else
 708 #endif
 709
 710 #ifdef FORCE_LOONGSON3B
 711 #define FORCE
 712 #define ARCHITECTURE    "MIPS"
 713 #define SUBARCHITECTURE "LOONGSON3B"
 714 #define SUBDIRNAME      "mips64"
 715 #define ARCHCONFIG   "-DLOONGSON3B " \
 716        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 717        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 718        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 719 #define LIBNAME   "loongson3b"
 720 #define CORENAME  "LOONGSON3B"
 721 #else
 722 #endif
 723
 724 #ifdef FORCE_I6400
 725 #define FORCE
 726 #define ARCHITECTURE    "MIPS"
 727 #define SUBARCHITECTURE "I6400"
 728 #define SUBDIRNAME      "mips64"
 729 #define ARCHCONFIG   "-DI6400 " \
 730        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 731        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 732        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 733 #define LIBNAME   "i6400"
 734 #define CORENAME  "I6400"
 735 #else
 736 #endif
 737
 738 #ifdef FORCE_P6600
 739 #define FORCE
 740 #define ARCHITECTURE    "MIPS"
 741 #define SUBARCHITECTURE "P6600"
 742 #define SUBDIRNAME      "mips64"
 743 #define ARCHCONFIG   "-DP6600 " \
 744        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 745        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 746        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 747 #define LIBNAME   "p6600"
 748 #define CORENAME  "P6600"
 749 #else
 750 #endif
 751
 752 #ifdef FORCE_P5600
 753 #define FORCE
 754 #define ARCHITECTURE    "MIPS"
 755 #define SUBARCHITECTURE "P5600"
 756 #define SUBDIRNAME      "mips"
 757 #define ARCHCONFIG   "-DP5600 " \
 758        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 759        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 760        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 761 #define LIBNAME   "p5600"
 762 #define CORENAME  "P5600"
 763 #else
 764 #endif
 765
 766 #ifdef FORCE_ITANIUM2
 767 #define FORCE
 768 #define ARCHITECTURE    "IA64"
 769 #define SUBARCHITECTURE "ITANIUM2"
 770 #define SUBDIRNAME      "ia64"
 771 #define ARCHCONFIG   "-DITANIUM2 " \
 772                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 773                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 774 #define LIBNAME   "itanium2"
 775 #define CORENAME  "itanium2"
 776 #endif
 777
 778 #ifdef FORCE_SPARC
 779 #define FORCE
 780 #define ARCHITECTURE    "SPARC"
 781 #define SUBARCHITECTURE "SPARC"
 782 #define SUBDIRNAME      "sparc"
 783 #define ARCHCONFIG   "-DSPARC -DV9 " \
 784                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 785                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 786 #define LIBNAME   "sparc"
 787 #define CORENAME  "sparc"
 788 #endif
 789
 790 #ifdef FORCE_SPARCV7
 791 #define FORCE
 792 #define ARCHITECTURE    "SPARC"
 793 #define SUBARCHITECTURE "SPARC"
 794 #define SUBDIRNAME      "sparc"
 795 #define ARCHCONFIG   "-DSPARC -DV7 " \
 796                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 797                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 798 #define LIBNAME   "sparcv7"
 799 #define CORENAME  "sparcv7"
 800 #endif
 801
 802 #ifdef FORCE_GENERIC
 803 #define FORCE
 804 #define ARCHITECTURE    "GENERIC"
 805 #define SUBARCHITECTURE "GENERIC"
 806 #define SUBDIRNAME      "generic"
 807 #define ARCHCONFIG   "-DGENERIC " \
 808                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 809                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 810                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 811 #define LIBNAME   "generic"
 812 #define CORENAME  "generic"
 813 #endif
 814
 815 #ifdef FORCE_ARMV7
 816 #define FORCE
 817 #define ARCHITECTURE    "ARM"
 818 #define SUBARCHITECTURE "ARMV7"
 819 #define SUBDIRNAME      "arm"
 820 #define ARCHCONFIG   "-DARMV7 " \
 821        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 822        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 823        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 824        "-DHAVE_VFPV3 -DHAVE_VFP"
 825 #define LIBNAME   "armv7"
 826 #define CORENAME  "ARMV7"
 827 #else
 828 #endif
 829
 830 #ifdef FORCE_CORTEXA9
 831 #define FORCE
 832 #define ARCHITECTURE    "ARM"
 833 #define SUBARCHITECTURE "CORTEXA9"
 834 #define SUBDIRNAME      "arm"
 835 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 836        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 837        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 838        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 839        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 840 #define LIBNAME   "cortexa9"
 841 #define CORENAME  "CORTEXA9"
 842 #else
 843 #endif
 844
 845 #ifdef FORCE_CORTEXA15
 846 #define FORCE
 847 #define ARCHITECTURE    "ARM"
 848 #define SUBARCHITECTURE "CORTEXA15"
 849 #define SUBDIRNAME      "arm"
 850 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 851        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 852        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 853        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 854        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 855 #define LIBNAME   "cortexa15"
 856 #define CORENAME  "CORTEXA15"
 857 #else
 858 #endif
 859
 860 #ifdef FORCE_ARMV6
 861 #define FORCE
 862 #define ARCHITECTURE    "ARM"
 863 #define SUBARCHITECTURE "ARMV6"
 864 #define SUBDIRNAME      "arm"
 865 #define ARCHCONFIG   "-DARMV6 " \
 866        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 867        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 868        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 869        "-DHAVE_VFP"
 870 #define LIBNAME   "armv6"
 871 #define CORENAME  "ARMV6"
 872 #else
 873 #endif
 874
 875 #ifdef FORCE_ARMV5
 876 #define FORCE
 877 #define ARCHITECTURE    "ARM"
 878 #define SUBARCHITECTURE "ARMV5"
 879 #define SUBDIRNAME      "arm"
 880 #define ARCHCONFIG   "-DARMV5 " \
 881        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 882        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 883        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 884 #define LIBNAME   "armv5"
 885 #define CORENAME  "ARMV5"
 886 #else
 887 #endif
 888
 889
 890 #ifdef FORCE_ARMV8
 891 #define FORCE
 892 #define ARCHITECTURE    "ARM64"
 893 #define SUBARCHITECTURE "ARMV8"
 894 #define SUBDIRNAME      "arm64"
 895 #define ARCHCONFIG   "-DARMV8 " \
 896        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 897        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 898        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 899 #define LIBNAME   "armv8"
 900 #define CORENAME  "ARMV8"
 901 #endif
 902
 903 #ifdef FORCE_CORTEXA57
 904 #define FORCE
 905 #define ARCHITECTURE    "ARM64"
 906 #define SUBARCHITECTURE "CORTEXA57"
 907 #define SUBDIRNAME      "arm64"
 908 #define ARCHCONFIG   "-DCORTEXA57 " \
 909        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 910        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 911        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 912        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 913        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 914 #define LIBNAME   "cortexa57"
 915 #define CORENAME  "CORTEXA57"
 916 #else
 917 #endif
 918
 919 #ifdef FORCE_VULCAN
 920 #define FORCE
 921 #define ARCHITECTURE    "ARM64"
 922 #define SUBARCHITECTURE "VULCAN"
 923 #define SUBDIRNAME      "arm64"
 924 #define ARCHCONFIG   "-DVULCAN " \
 925        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 926        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 927        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 928        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 929        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 930        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 931 #define LIBNAME   "vulcan"
 932 #define CORENAME  "VULCAN"
 933 #else
 934 #endif
 935
 936 #ifdef FORCE_THUNDERX
 937 #define FORCE
 938 #define ARCHITECTURE    "ARM64"
 939 #define SUBARCHITECTURE "THUNDERX"
 940 #define SUBDIRNAME      "arm64"
 941 #define ARCHCONFIG   "-DTHUNDERX " \
 942        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 943        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
 944        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 "
 945 #define LIBNAME   "thunderx"
 946 #define CORENAME  "THUNDERX"
 947 #else
 948 #endif
 949
 950 #ifdef FORCE_THUNDERX2T99
 951 #define FORCE
 952 #define ARCHITECTURE    "ARM64"
 953 #define SUBARCHITECTURE "THUNDERX2T99"
 954 #define SUBDIRNAME      "arm64"
 955 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
 956        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 957        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 958        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 959        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 960        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 961        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 962 #define LIBNAME   "thunderx2t99"
 963 #define CORENAME  "THUNDERX2T99"
 964 #else
 965 #endif
 966
 967 #ifndef FORCE
 968
 969 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 970     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 971 #ifndef POWER
 972 #define POWER
 973 #endif
 974 #define OPENBLAS_SUPPORTED
 975 #endif
 976
 977 #if defined(__zarch__) || defined(__s390x__)
 978 #define ZARCH
 979 #include "cpuid_zarch.c"
 980 #define OPENBLAS_SUPPORTED
 981 #endif
 982
 983 #ifdef INTEL_AMD
 984 #include "cpuid_x86.c"
 985 #define OPENBLAS_SUPPORTED
 986 #endif
 987
 988 #ifdef __ia64__
 989 #include "cpuid_ia64.c"
 990 #define OPENBLAS_SUPPORTED
 991 #endif
 992
 993 #ifdef __alpha
 994 #include "cpuid_alpha.c"
 995 #define OPENBLAS_SUPPORTED
 996 #endif
 997
 998 #ifdef POWER
 999 #include "cpuid_power.c"
1000 #define OPENBLAS_SUPPORTED
1001 #endif
1002
1003 #ifdef sparc
1004 #include "cpuid_sparc.c"
1005 #define OPENBLAS_SUPPORTED
1006 #endif
1007
1008 #ifdef __mips__
1009 #ifdef __mips64
1010 #include "cpuid_mips64.c"
1011 #else
1012 #include "cpuid_mips.c"
1013 #endif
1014 #define OPENBLAS_SUPPORTED
1015 #endif
1016
1017 #ifdef __arm__
1018 #include "cpuid_arm.c"
1019 #define OPENBLAS_SUPPORTED
1020 #endif
1021
1022 #ifdef __aarch64__
1023 #include "cpuid_arm64.c"
1024 #define OPENBLAS_SUPPORTED
1025 #endif
1026
1027
1028 #ifndef OPENBLAS_SUPPORTED
1029 #error "This arch/CPU is not supported by OpenBLAS."
1030 #endif
1031
1032 #else
1033
1034 #endif
1035
1036 static int get_num_cores(void) {
1037
1038 #ifdef OS_WINDOWS
1039   SYSTEM_INFO sysinfo;
1040 #elif defined(__FreeBSD__) || defined(__APPLE__)
1041   int m[2], count;
1042   size_t len;
1043 #endif
1044
1045 #if defined(linux) || defined(__sun__)
1046   //returns the number of processors which are currently online
1047   return sysconf(_SC_NPROCESSORS_CONF);
1048
1049 #elif defined(OS_WINDOWS)
1050
1051   GetSystemInfo(&sysinfo);
1052   return sysinfo.dwNumberOfProcessors;
1053
1054 #elif defined(__FreeBSD__) || defined(__APPLE__)
1055   m[0] = CTL_HW;
1056   m[1] = HW_NCPU;
1057   len = sizeof(int);
1058   sysctl(m, 2, &count, &len, NULL, 0);
1059
1060   return count;
1061 #else
1062   return 2;
1063 #endif
1064 }
1065
1066 int main(int argc, char *argv[]){
1067
1068 #ifdef FORCE
1069   char buffer[8192], *p, *q;
1070   int length;
1071 #endif
1072
1073   if (argc == 1) return 0;
1074
1075   switch (argv[1][0]) {
1076
1077   case '0' : /* for Makefile */
1078
1079 #ifdef FORCE
1080     printf("CORE=%s\n", CORENAME);
1081 #else
1082 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH)
1083     printf("CORE=%s\n", get_corename());
1084 #endif
1085 #endif
1086
1087 #ifdef FORCE
1088     printf("LIBCORE=%s\n", LIBNAME);
1089 #else
1090     printf("LIBCORE=");
1091     get_libname();
1092     printf("\n");
1093 #endif
1094
1095     printf("NUM_CORES=%d\n", get_num_cores());
1096
1097 #if defined(__arm__) && !defined(FORCE)
1098         get_features();
1099 #endif
1100
1101
1102 #ifdef INTEL_AMD
1103 #ifndef FORCE
1104     get_sse();
1105 #else
1106
1107     sprintf(buffer, "%s", ARCHCONFIG);
1108
1109     p = &buffer[0];
1110
1111     while (*p) {
1112       if ((*p == '-') && (*(p + 1) == 'D')) {
1113         p += 2;
1114
1115         while ((*p != ' ') && (*p != '\0')) {
1116
1117           if (*p == '=') {
1118             printf("=");
1119             p ++;
1120             while ((*p != ' ') && (*p != '\0')) {
1121               printf("%c", *p);
1122               p ++;
1123             }
1124           } else {
1125             printf("%c", *p);
1126             p ++;
1127             if ((*p == ' ') || (*p =='\0')) printf("=1");
1128           }
1129         }
1130
1131         printf("\n");
1132       } else p ++;
1133     }
1134 #endif
1135 #endif
1136
1137 #ifdef MAKE_NB_JOBS
1138   #if MAKE_NB_JOBS > 0
1139     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1140   #else
1141     // Let make use parent -j argument or -j1 if there
1142     // is no make parent
1143   #endif
1144 #elif NO_PARALLEL_MAKE==1
1145     printf("MAKE += -j 1\n");
1146 #else
1147 #ifndef OS_WINDOWS
1148     printf("MAKE += -j %d\n", get_num_cores());
1149 #endif
1150 #endif
1151
1152     break;
1153
1154   case '1' : /* For config.h */
1155 #ifdef FORCE
1156     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1157
1158     p = &buffer[0];
1159     while (*p) {
1160       if ((*p == '-') && (*(p + 1) == 'D')) {
1161         p += 2;
1162         printf("#define ");
1163
1164         while ((*p != ' ') && (*p != '\0')) {
1165
1166           if (*p == '=') {
1167             printf(" ");
1168             p ++;
1169             while ((*p != ' ') && (*p != '\0')) {
1170               printf("%c", *p);
1171               p ++;
1172             }
1173           } else {
1174             if (*p != '\n')
1175             printf("%c", *p);
1176             p ++;
1177           }
1178         }
1179
1180         printf("\n");
1181       } else p ++;
1182     }
1183 #else
1184     get_cpuconfig();
1185 #endif
1186
1187 #ifdef FORCE
1188     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1189 #else
1190 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH)
1191     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1192 #endif
1193 #endif
1194
1195  break;
1196
1197   case '2' : /* SMP */
1198     if (get_num_cores() > 1) printf("SMP=1\n");
1199     break;
1200   }
1201
1202   fflush(stdout);
1203
1204   return 0;
1205 }
1206