getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P6600          */
 136 /* #define FORCE_P5600          */
 137 /* #define FORCE_ITANIUM2       */
 138 /* #define FORCE_SPARC          */
 139 /* #define FORCE_SPARCV7        */
 140 /* #define FORCE_GENERIC        */
 141
 142 #ifdef FORCE_P2
 143 #define FORCE
 144 #define FORCE_INTEL
 145 #define ARCHITECTURE    "X86"
 146 #define SUBARCHITECTURE "PENTIUM2"
 147 #define ARCHCONFIG   "-DPENTIUM2 " \
 148                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 149                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 150                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 151                      "-DHAVE_CMOV -DHAVE_MMX"
 152 #define LIBNAME   "p2"
 153 #define CORENAME  "P5"
 154 #endif
 155
 156 #ifdef FORCE_KATMAI
 157 #define FORCE
 158 #define FORCE_INTEL
 159 #define ARCHITECTURE    "X86"
 160 #define SUBARCHITECTURE "PENTIUM3"
 161 #define ARCHCONFIG   "-DPENTIUM3 " \
 162                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 163                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 164                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 165                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 166 #define LIBNAME   "katmai"
 167 #define CORENAME  "KATMAI"
 168 #endif
 169
 170 #ifdef FORCE_COPPERMINE
 171 #define FORCE
 172 #define FORCE_INTEL
 173 #define ARCHITECTURE    "X86"
 174 #define SUBARCHITECTURE "PENTIUM3"
 175 #define ARCHCONFIG   "-DPENTIUM3 " \
 176                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 177                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 178                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 179                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 180 #define LIBNAME   "coppermine"
 181 #define CORENAME  "COPPERMINE"
 182 #endif
 183
 184 #ifdef FORCE_NORTHWOOD
 185 #define FORCE
 186 #define FORCE_INTEL
 187 #define ARCHITECTURE    "X86"
 188 #define SUBARCHITECTURE "PENTIUM4"
 189 #define ARCHCONFIG   "-DPENTIUM4 " \
 190                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 191                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 192                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 193                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 194 #define LIBNAME   "northwood"
 195 #define CORENAME  "NORTHWOOD"
 196 #endif
 197
 198 #ifdef FORCE_PRESCOTT
 199 #define FORCE
 200 #define FORCE_INTEL
 201 #define ARCHITECTURE    "X86"
 202 #define SUBARCHITECTURE "PENTIUM4"
 203 #define ARCHCONFIG   "-DPENTIUM4 " \
 204                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 205                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 206                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 207                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 208 #define LIBNAME   "prescott"
 209 #define CORENAME  "PRESCOTT"
 210 #endif
 211
 212 #ifdef FORCE_BANIAS
 213 #define FORCE
 214 #define FORCE_INTEL
 215 #define ARCHITECTURE    "X86"
 216 #define SUBARCHITECTURE "BANIAS"
 217 #define ARCHCONFIG   "-DPENTIUMM " \
 218                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 219                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 220                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 221                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 222 #define LIBNAME   "banias"
 223 #define CORENAME  "BANIAS"
 224 #endif
 225
 226 #ifdef FORCE_YONAH
 227 #define FORCE
 228 #define FORCE_INTEL
 229 #define ARCHITECTURE    "X86"
 230 #define SUBARCHITECTURE "YONAH"
 231 #define ARCHCONFIG   "-DPENTIUMM " \
 232                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 233                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 234                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 235                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 236 #define LIBNAME   "yonah"
 237 #define CORENAME  "YONAH"
 238 #endif
 239
 240 #ifdef FORCE_CORE2
 241 #define FORCE
 242 #define FORCE_INTEL
 243 #define ARCHITECTURE    "X86"
 244 #define SUBARCHITECTURE "CONRORE"
 245 #define ARCHCONFIG   "-DCORE2 " \
 246                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 247                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 248                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 249                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 250 #define LIBNAME   "core2"
 251 #define CORENAME  "CORE2"
 252 #endif
 253
 254 #ifdef FORCE_PENRYN
 255 #define FORCE
 256 #define FORCE_INTEL
 257 #define ARCHITECTURE    "X86"
 258 #define SUBARCHITECTURE "PENRYN"
 259 #define ARCHCONFIG   "-DPENRYN " \
 260                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 261                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 262                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 263                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 264 #define LIBNAME   "penryn"
 265 #define CORENAME  "PENRYN"
 266 #endif
 267
 268 #ifdef FORCE_DUNNINGTON
 269 #define FORCE
 270 #define FORCE_INTEL
 271 #define ARCHITECTURE    "X86"
 272 #define SUBARCHITECTURE "DUNNINGTON"
 273 #define ARCHCONFIG   "-DDUNNINGTON " \
 274                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 275                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 276                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 277                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 278                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 279 #define LIBNAME   "dunnington"
 280 #define CORENAME  "DUNNINGTON"
 281 #endif
 282
 283 #ifdef FORCE_NEHALEM
 284 #define FORCE
 285 #define FORCE_INTEL
 286 #define ARCHITECTURE    "X86"
 287 #define SUBARCHITECTURE "NEHALEM"
 288 #define ARCHCONFIG   "-DNEHALEM " \
 289                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 290                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 291                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 292                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 293 #define LIBNAME   "nehalem"
 294 #define CORENAME  "NEHALEM"
 295 #endif
 296
 297 #ifdef FORCE_SANDYBRIDGE
 298 #define FORCE
 299 #define FORCE_INTEL
 300 #define ARCHITECTURE    "X86"
 301 #define SUBARCHITECTURE "SANDYBRIDGE"
 302 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 303                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 304                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 305                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 306                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 307 #define LIBNAME   "sandybridge"
 308 #define CORENAME  "SANDYBRIDGE"
 309 #endif
 310
 311 #ifdef FORCE_HASWELL
 312 #define FORCE
 313 #define FORCE_INTEL
 314 #define ARCHITECTURE    "X86"
 315 #define SUBARCHITECTURE "HASWELL"
 316 #define ARCHCONFIG   "-DHASWELL " \
 317                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 318                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 319                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 320                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 321                      "-DFMA3"
 322 #define LIBNAME   "haswell"
 323 #define CORENAME  "HASWELL"
 324 #endif
 325
 326 #ifdef FORCE_ATOM
 327 #define FORCE
 328 #define FORCE_INTEL
 329 #define ARCHITECTURE    "X86"
 330 #define SUBARCHITECTURE "ATOM"
 331 #define ARCHCONFIG   "-DATOM " \
 332                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 333                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 334                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 335                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 336 #define LIBNAME   "atom"
 337 #define CORENAME  "ATOM"
 338 #endif
 339
 340 #ifdef FORCE_ATHLON
 341 #define FORCE
 342 #define FORCE_INTEL
 343 #define ARCHITECTURE    "X86"
 344 #define SUBARCHITECTURE "ATHLON"
 345 #define ARCHCONFIG   "-DATHLON " \
 346                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 347                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 348                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 349                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 350 #define LIBNAME   "athlon"
 351 #define CORENAME  "ATHLON"
 352 #endif
 353
 354 #ifdef FORCE_OPTERON
 355 #define FORCE
 356 #define FORCE_INTEL
 357 #define ARCHITECTURE    "X86"
 358 #define SUBARCHITECTURE "OPTERON"
 359 #define ARCHCONFIG   "-DOPTERON " \
 360                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 361                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 362                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 363                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 364 #define LIBNAME   "opteron"
 365 #define CORENAME  "OPTERON"
 366 #endif
 367
 368 #ifdef FORCE_OPTERON_SSE3
 369 #define FORCE
 370 #define FORCE_INTEL
 371 #define ARCHITECTURE    "X86"
 372 #define SUBARCHITECTURE "OPTERON"
 373 #define ARCHCONFIG   "-DOPTERON " \
 374                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 375                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 376                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 377                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 378 #define LIBNAME   "opteron"
 379 #define CORENAME  "OPTERON"
 380 #endif
 381
 382 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 383 #define FORCE
 384 #define FORCE_INTEL
 385 #define ARCHITECTURE    "X86"
 386 #define SUBARCHITECTURE "BARCELONA"
 387 #define ARCHCONFIG   "-DBARCELONA " \
 388                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 389                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 390                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 391                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 392                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 393 #define LIBNAME   "barcelona"
 394 #define CORENAME  "BARCELONA"
 395 #endif
 396
 397 #if defined(FORCE_BOBCAT)
 398 #define FORCE
 399 #define FORCE_INTEL
 400 #define ARCHITECTURE    "X86"
 401 #define SUBARCHITECTURE "BOBCAT"
 402 #define ARCHCONFIG   "-DBOBCAT " \
 403                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 404                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 405                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 406                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 407                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 408 #define LIBNAME   "bobcat"
 409 #define CORENAME  "BOBCAT"
 410 #endif
 411
 412 #if defined (FORCE_BULLDOZER)
 413 #define FORCE
 414 #define FORCE_INTEL
 415 #define ARCHITECTURE    "X86"
 416 #define SUBARCHITECTURE "BULLDOZER"
 417 #define ARCHCONFIG   "-DBULLDOZER " \
 418                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 419                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 420                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 421                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 422                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 423                      "-DHAVE_AVX -DHAVE_FMA4"
 424 #define LIBNAME   "bulldozer"
 425 #define CORENAME  "BULLDOZER"
 426 #endif
 427
 428 #if defined (FORCE_PILEDRIVER)
 429 #define FORCE
 430 #define FORCE_INTEL
 431 #define ARCHITECTURE    "X86"
 432 #define SUBARCHITECTURE "PILEDRIVER"
 433 #define ARCHCONFIG   "-DPILEDRIVER " \
 434                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 435                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 436                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 437                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 438                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 439                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 440 #define LIBNAME   "piledriver"
 441 #define CORENAME  "PILEDRIVER"
 442 #endif
 443
 444 #if defined (FORCE_STEAMROLLER)
 445 #define FORCE
 446 #define FORCE_INTEL
 447 #define ARCHITECTURE    "X86"
 448 #define SUBARCHITECTURE "STEAMROLLER"
 449 #define ARCHCONFIG   "-DSTEAMROLLER " \
 450                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 451                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 452                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 453                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 454                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 455                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 456 #define LIBNAME   "steamroller"
 457 #define CORENAME  "STEAMROLLER"
 458 #endif
 459
 460 #if defined (FORCE_EXCAVATOR)
 461 #define FORCE
 462 #define FORCE_INTEL
 463 #define ARCHITECTURE    "X86"
 464 #define SUBARCHITECTURE "EXCAVATOR"
 465 #define ARCHCONFIG   "-DEXCAVATOR " \
 466                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 467                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 468                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 469                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 470                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 471                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 472 #define LIBNAME   "excavator"
 473 #define CORENAME  "EXCAVATOR"
 474 #endif
 475
 476
 477 #ifdef FORCE_SSE_GENERIC
 478 #define FORCE
 479 #define FORCE_INTEL
 480 #define ARCHITECTURE    "X86"
 481 #define SUBARCHITECTURE "GENERIC"
 482 #define ARCHCONFIG   "-DGENERIC " \
 483                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 484                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 485                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 486                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 487 #define LIBNAME   "generic"
 488 #define CORENAME  "GENERIC"
 489 #endif
 490
 491 #ifdef FORCE_VIAC3
 492 #define FORCE
 493 #define FORCE_INTEL
 494 #define ARCHITECTURE    "X86"
 495 #define SUBARCHITECTURE "VIAC3"
 496 #define ARCHCONFIG   "-DVIAC3 " \
 497                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 498                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 499                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 500                      "-DHAVE_MMX -DHAVE_SSE "
 501 #define LIBNAME   "viac3"
 502 #define CORENAME  "VIAC3"
 503 #endif
 504
 505 #ifdef FORCE_NANO
 506 #define FORCE
 507 #define FORCE_INTEL
 508 #define ARCHITECTURE    "X86"
 509 #define SUBARCHITECTURE "NANO"
 510 #define ARCHCONFIG   "-DNANO " \
 511                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 512                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 513                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 514                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 515 #define LIBNAME   "nano"
 516 #define CORENAME  "NANO"
 517 #endif
 518
 519 #ifdef FORCE_POWER3
 520 #define FORCE
 521 #define ARCHITECTURE    "POWER"
 522 #define SUBARCHITECTURE "POWER3"
 523 #define SUBDIRNAME      "power"
 524 #define ARCHCONFIG   "-DPOWER3 " \
 525                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 526                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 527                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 528 #define LIBNAME   "power3"
 529 #define CORENAME  "POWER3"
 530 #endif
 531
 532 #ifdef FORCE_POWER4
 533 #define FORCE
 534 #define ARCHITECTURE    "POWER"
 535 #define SUBARCHITECTURE "POWER4"
 536 #define SUBDIRNAME      "power"
 537 #define ARCHCONFIG   "-DPOWER4 " \
 538                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 539                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 540                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 541 #define LIBNAME   "power4"
 542 #define CORENAME  "POWER4"
 543 #endif
 544
 545 #ifdef FORCE_POWER5
 546 #define FORCE
 547 #define ARCHITECTURE    "POWER"
 548 #define SUBARCHITECTURE "POWER5"
 549 #define SUBDIRNAME      "power"
 550 #define ARCHCONFIG   "-DPOWER5 " \
 551                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 552                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 553                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 554 #define LIBNAME   "power5"
 555 #define CORENAME  "POWER5"
 556 #endif
 557
 558 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 559 #define FORCE
 560 #define ARCHITECTURE    "POWER"
 561 #define SUBARCHITECTURE "POWER6"
 562 #define SUBDIRNAME      "power"
 563 #define ARCHCONFIG   "-DPOWER6 " \
 564                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 565                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 566                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 567 #define LIBNAME   "power6"
 568 #define CORENAME  "POWER6"
 569 #endif
 570
 571 #if defined(FORCE_POWER8)
 572 #define FORCE
 573 #define ARCHITECTURE    "POWER"
 574 #define SUBARCHITECTURE "POWER8"
 575 #define SUBDIRNAME      "power"
 576 #define ARCHCONFIG   "-DPOWER8 " \
 577                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 578                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 579                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 580 #define LIBNAME   "power8"
 581 #define CORENAME  "POWER8"
 582 #endif
 583
 584
 585 #ifdef FORCE_PPCG4
 586 #define FORCE
 587 #define ARCHITECTURE    "POWER"
 588 #define SUBARCHITECTURE "PPCG4"
 589 #define SUBDIRNAME      "power"
 590 #define ARCHCONFIG   "-DPPCG4 " \
 591                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 592                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 593                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 594 #define LIBNAME   "ppcg4"
 595 #define CORENAME  "PPCG4"
 596 #endif
 597
 598 #ifdef FORCE_PPC970
 599 #define FORCE
 600 #define ARCHITECTURE    "POWER"
 601 #define SUBARCHITECTURE "PPC970"
 602 #define SUBDIRNAME      "power"
 603 #define ARCHCONFIG   "-DPPC970 " \
 604                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 605                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 606                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 607 #define LIBNAME   "ppc970"
 608 #define CORENAME  "PPC970"
 609 #endif
 610
 611 #ifdef FORCE_PPC970MP
 612 #define FORCE
 613 #define ARCHITECTURE    "POWER"
 614 #define SUBARCHITECTURE "PPC970"
 615 #define SUBDIRNAME      "power"
 616 #define ARCHCONFIG   "-DPPC970 " \
 617                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 618                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 619                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 620 #define LIBNAME   "ppc970mp"
 621 #define CORENAME  "PPC970"
 622 #endif
 623
 624 #ifdef FORCE_PPC440
 625 #define FORCE
 626 #define ARCHITECTURE    "POWER"
 627 #define SUBARCHITECTURE "PPC440"
 628 #define SUBDIRNAME      "power"
 629 #define ARCHCONFIG   "-DPPC440 " \
 630                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 631                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 632                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 633 #define LIBNAME   "ppc440"
 634 #define CORENAME  "PPC440"
 635 #endif
 636
 637 #ifdef FORCE_PPC440FP2
 638 #define FORCE
 639 #define ARCHITECTURE    "POWER"
 640 #define SUBARCHITECTURE "PPC440FP2"
 641 #define SUBDIRNAME      "power"
 642 #define ARCHCONFIG   "-DPPC440FP2 " \
 643                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 644                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 645                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 646 #define LIBNAME   "ppc440FP2"
 647 #define CORENAME  "PPC440FP2"
 648 #endif
 649
 650 #ifdef FORCE_CELL
 651 #define FORCE
 652 #define ARCHITECTURE    "POWER"
 653 #define SUBARCHITECTURE "CELL"
 654 #define SUBDIRNAME      "power"
 655 #define ARCHCONFIG   "-DCELL " \
 656                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 657                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 658                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 659 #define LIBNAME   "cell"
 660 #define CORENAME  "CELL"
 661 #endif
 662
 663 #ifdef FORCE_SICORTEX
 664 #define FORCE
 665 #define ARCHITECTURE    "MIPS"
 666 #define SUBARCHITECTURE "SICORTEX"
 667 #define SUBDIRNAME      "mips"
 668 #define ARCHCONFIG   "-DSICORTEX " \
 669                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 670                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 671                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 672 #define LIBNAME   "mips"
 673 #define CORENAME  "sicortex"
 674 #endif
 675
 676
 677 #ifdef FORCE_LOONGSON3A
 678 #define FORCE
 679 #define ARCHITECTURE    "MIPS"
 680 #define SUBARCHITECTURE "LOONGSON3A"
 681 #define SUBDIRNAME      "mips64"
 682 #define ARCHCONFIG   "-DLOONGSON3A " \
 683        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 684        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 685        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 686 #define LIBNAME   "loongson3a"
 687 #define CORENAME  "LOONGSON3A"
 688 #else
 689 #endif
 690
 691 #ifdef FORCE_LOONGSON3B
 692 #define FORCE
 693 #define ARCHITECTURE    "MIPS"
 694 #define SUBARCHITECTURE "LOONGSON3B"
 695 #define SUBDIRNAME      "mips64"
 696 #define ARCHCONFIG   "-DLOONGSON3B " \
 697        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 698        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 699        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 700 #define LIBNAME   "loongson3b"
 701 #define CORENAME  "LOONGSON3B"
 702 #else
 703 #endif
 704
 705 #ifdef FORCE_I6400
 706 #define FORCE
 707 #define ARCHITECTURE    "MIPS"
 708 #define SUBARCHITECTURE "I6400"
 709 #define SUBDIRNAME      "mips64"
 710 #define ARCHCONFIG   "-DI6400 " \
 711        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 712        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 713        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 714 #define LIBNAME   "i6400"
 715 #define CORENAME  "I6400"
 716 #else
 717 #endif
 718
 719 #ifdef FORCE_P6600
 720 #define FORCE
 721 #define ARCHITECTURE    "MIPS"
 722 #define SUBARCHITECTURE "P6600"
 723 #define SUBDIRNAME      "mips64"
 724 #define ARCHCONFIG   "-DP6600 " \
 725        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 726        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 727        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 728 #define LIBNAME   "p6600"
 729 #define CORENAME  "P6600"
 730 #else
 731 #endif
 732
 733 #ifdef FORCE_P5600
 734 #define FORCE
 735 #define ARCHITECTURE    "MIPS"
 736 #define SUBARCHITECTURE "P5600"
 737 #define SUBDIRNAME      "mips"
 738 #define ARCHCONFIG   "-DP5600 " \
 739        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 740        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 741        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 742 #define LIBNAME   "p5600"
 743 #define CORENAME  "P5600"
 744 #else
 745 #endif
 746
 747 #ifdef FORCE_ITANIUM2
 748 #define FORCE
 749 #define ARCHITECTURE    "IA64"
 750 #define SUBARCHITECTURE "ITANIUM2"
 751 #define SUBDIRNAME      "ia64"
 752 #define ARCHCONFIG   "-DITANIUM2 " \
 753                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 754                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 755 #define LIBNAME   "itanium2"
 756 #define CORENAME  "itanium2"
 757 #endif
 758
 759 #ifdef FORCE_SPARC
 760 #define FORCE
 761 #define ARCHITECTURE    "SPARC"
 762 #define SUBARCHITECTURE "SPARC"
 763 #define SUBDIRNAME      "sparc"
 764 #define ARCHCONFIG   "-DSPARC -DV9 " \
 765                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 766                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 767 #define LIBNAME   "sparc"
 768 #define CORENAME  "sparc"
 769 #endif
 770
 771 #ifdef FORCE_SPARCV7
 772 #define FORCE
 773 #define ARCHITECTURE    "SPARC"
 774 #define SUBARCHITECTURE "SPARC"
 775 #define SUBDIRNAME      "sparc"
 776 #define ARCHCONFIG   "-DSPARC -DV7 " \
 777                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 778                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 779 #define LIBNAME   "sparcv7"
 780 #define CORENAME  "sparcv7"
 781 #endif
 782
 783 #ifdef FORCE_GENERIC
 784 #define FORCE
 785 #define ARCHITECTURE    "GENERIC"
 786 #define SUBARCHITECTURE "GENERIC"
 787 #define SUBDIRNAME      "generic"
 788 #define ARCHCONFIG   "-DGENERIC " \
 789                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 790                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 791                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 792 #define LIBNAME   "generic"
 793 #define CORENAME  "generic"
 794 #endif
 795
 796 #ifdef FORCE_ARMV7
 797 #define FORCE
 798 #define ARCHITECTURE    "ARM"
 799 #define SUBARCHITECTURE "ARMV7"
 800 #define SUBDIRNAME      "arm"
 801 #define ARCHCONFIG   "-DARMV7 " \
 802        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 803        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 804        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 805        "-DHAVE_VFPV3 -DHAVE_VFP"
 806 #define LIBNAME   "armv7"
 807 #define CORENAME  "ARMV7"
 808 #else
 809 #endif
 810
 811 #ifdef FORCE_CORTEXA9
 812 #define FORCE
 813 #define ARCHITECTURE    "ARM"
 814 #define SUBARCHITECTURE "CORTEXA9"
 815 #define SUBDIRNAME      "arm"
 816 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 817        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 818        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 819        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 820        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 821 #define LIBNAME   "cortexa9"
 822 #define CORENAME  "CORTEXA9"
 823 #else
 824 #endif
 825
 826 #ifdef FORCE_CORTEXA15
 827 #define FORCE
 828 #define ARCHITECTURE    "ARM"
 829 #define SUBARCHITECTURE "CORTEXA15"
 830 #define SUBDIRNAME      "arm"
 831 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 832        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 833        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 834        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 835        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 836 #define LIBNAME   "cortexa15"
 837 #define CORENAME  "CORTEXA15"
 838 #else
 839 #endif
 840
 841 #ifdef FORCE_ARMV6
 842 #define FORCE
 843 #define ARCHITECTURE    "ARM"
 844 #define SUBARCHITECTURE "ARMV6"
 845 #define SUBDIRNAME      "arm"
 846 #define ARCHCONFIG   "-DARMV6 " \
 847        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 848        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 849        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 850        "-DHAVE_VFP"
 851 #define LIBNAME   "armv6"
 852 #define CORENAME  "ARMV6"
 853 #else
 854 #endif
 855
 856 #ifdef FORCE_ARMV5
 857 #define FORCE
 858 #define ARCHITECTURE    "ARM"
 859 #define SUBARCHITECTURE "ARMV5"
 860 #define SUBDIRNAME      "arm"
 861 #define ARCHCONFIG   "-DARMV5 " \
 862        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 863        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 864        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 865 #define LIBNAME   "armv5"
 866 #define CORENAME  "ARMV5"
 867 #else
 868 #endif
 869
 870
 871 #ifdef FORCE_ARMV8
 872 #define FORCE
 873 #define ARCHITECTURE    "ARM64"
 874 #define SUBARCHITECTURE "ARMV8"
 875 #define SUBDIRNAME      "arm64"
 876 #define ARCHCONFIG   "-DARMV8 " \
 877        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 878        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 879        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 880 #define LIBNAME   "armv8"
 881 #define CORENAME  "ARMV8"
 882 #endif
 883
 884 #ifdef FORCE_CORTEXA57
 885 #define FORCE
 886 #define ARCHITECTURE    "ARM64"
 887 #define SUBARCHITECTURE "ARMV8"
 888 #define SUBDIRNAME      "arm64"
 889 #define ARCHCONFIG   "-DCORTEXA57 " \
 890        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 891        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 892        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 893        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 894        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 895 #define LIBNAME   "cortexa57"
 896 #define CORENAME  "CORTEXA57"
 897 #else
 898 #endif
 899
 900 #ifdef FORCE_VULCAN
 901 #define FORCE
 902 #define ARCHITECTURE    "ARM64"
 903 #define SUBARCHITECTURE "ARMV8"
 904 #define SUBDIRNAME      "arm64"
 905 #define ARCHCONFIG   "-DVULCAN " \
 906        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 907        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 908        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 909        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 910        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 911        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 912 #define LIBNAME   "vulcan"
 913 #define CORENAME  "VULCAN"
 914 #else
 915 #endif
 916
 917 #ifndef FORCE
 918
 919 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 920     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 921 #ifndef POWER
 922 #define POWER
 923 #endif
 924 #define OPENBLAS_SUPPORTED
 925 #endif
 926
 927 #if defined(__zarch__) || defined(__s390x__)
 928 #define ZARCH
 929 #include "cpuid_zarch.c"
 930 #define OPENBLAS_SUPPORTED
 931 #endif
 932
 933 #ifdef INTEL_AMD
 934 #include "cpuid_x86.c"
 935 #define OPENBLAS_SUPPORTED
 936 #endif
 937
 938 #ifdef __ia64__
 939 #include "cpuid_ia64.c"
 940 #define OPENBLAS_SUPPORTED
 941 #endif
 942
 943 #ifdef __alpha
 944 #include "cpuid_alpha.c"
 945 #define OPENBLAS_SUPPORTED
 946 #endif
 947
 948 #ifdef POWER
 949 #include "cpuid_power.c"
 950 #define OPENBLAS_SUPPORTED
 951 #endif
 952
 953 #ifdef sparc
 954 #include "cpuid_sparc.c"
 955 #define OPENBLAS_SUPPORTED
 956 #endif
 957
 958 #ifdef __mips__
 959 #ifdef __mips64
 960 #include "cpuid_mips64.c"
 961 #else
 962 #include "cpuid_mips.c"
 963 #endif
 964 #define OPENBLAS_SUPPORTED
 965 #endif
 966
 967 #ifdef __arm__
 968 #include "cpuid_arm.c"
 969 #define OPENBLAS_SUPPORTED
 970 #endif
 971
 972 #ifdef __aarch64__
 973 #include "cpuid_arm64.c"
 974 #define OPENBLAS_SUPPORTED
 975 #endif
 976
 977
 978 #ifndef OPENBLAS_SUPPORTED
 979 #error "This arch/CPU is not supported by OpenBLAS."
 980 #endif
 981
 982 #else
 983
 984 #endif
 985
 986 static int get_num_cores(void) {
 987
 988 #ifdef OS_WINDOWS
 989   SYSTEM_INFO sysinfo;
 990 #elif defined(__FreeBSD__) || defined(__APPLE__)
 991   int m[2], count;
 992   size_t len;
 993 #endif
 994
 995 #if defined(linux) || defined(__sun__)
 996   //returns the number of processors which are currently online
 997   return sysconf(_SC_NPROCESSORS_CONF);
 998
 999 #elif defined(OS_WINDOWS)
1000
1001   GetSystemInfo(&sysinfo);
1002   return sysinfo.dwNumberOfProcessors;
1003
1004 #elif defined(__FreeBSD__) || defined(__APPLE__)
1005   m[0] = CTL_HW;
1006   m[1] = HW_NCPU;
1007   len = sizeof(int);
1008   sysctl(m, 2, &count, &len, NULL, 0);
1009
1010   return count;
1011 #else
1012   return 2;
1013 #endif
1014 }
1015
1016 int main(int argc, char *argv[]){
1017
1018 #ifdef FORCE
1019   char buffer[8192], *p, *q;
1020   int length;
1021 #endif
1022
1023   if (argc == 1) return 0;
1024
1025   switch (argv[1][0]) {
1026
1027   case '0' : /* for Makefile */
1028
1029 #ifdef FORCE
1030     printf("CORE=%s\n", CORENAME);
1031 #else
1032 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH)
1033     printf("CORE=%s\n", get_corename());
1034 #endif
1035 #endif
1036
1037 #ifdef FORCE
1038     printf("LIBCORE=%s\n", LIBNAME);
1039 #else
1040     printf("LIBCORE=");
1041     get_libname();
1042     printf("\n");
1043 #endif
1044
1045     printf("NUM_CORES=%d\n", get_num_cores());
1046
1047 #if defined(__arm__) && !defined(FORCE)
1048         get_features();
1049 #endif
1050
1051
1052 #ifdef INTEL_AMD
1053 #ifndef FORCE
1054     get_sse();
1055 #else
1056
1057     sprintf(buffer, "%s", ARCHCONFIG);
1058
1059     p = &buffer[0];
1060
1061     while (*p) {
1062       if ((*p == '-') && (*(p + 1) == 'D')) {
1063         p += 2;
1064
1065         while ((*p != ' ') && (*p != '\0')) {
1066
1067           if (*p == '=') {
1068             printf("=");
1069             p ++;
1070             while ((*p != ' ') && (*p != '\0')) {
1071               printf("%c", *p);
1072               p ++;
1073             }
1074           } else {
1075             printf("%c", *p);
1076             p ++;
1077             if ((*p == ' ') || (*p =='\0')) printf("=1");
1078           }
1079         }
1080
1081         printf("\n");
1082       } else p ++;
1083     }
1084 #endif
1085 #endif
1086
1087 #ifdef MAKE_NB_JOBS
1088   #if MAKE_NB_JOBS > 0
1089     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1090   #else
1091     // Let make use parent -j argument or -j1 if there
1092     // is no make parent
1093   #endif
1094 #elif NO_PARALLEL_MAKE==1
1095     printf("MAKE += -j 1\n");
1096 #else
1097 #ifndef OS_WINDOWS
1098     printf("MAKE += -j %d\n", get_num_cores());
1099 #endif
1100 #endif
1101
1102     break;
1103
1104   case '1' : /* For config.h */
1105 #ifdef FORCE
1106     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1107
1108     p = &buffer[0];
1109     while (*p) {
1110       if ((*p == '-') && (*(p + 1) == 'D')) {
1111         p += 2;
1112         printf("#define ");
1113
1114         while ((*p != ' ') && (*p != '\0')) {
1115
1116           if (*p == '=') {
1117             printf(" ");
1118             p ++;
1119             while ((*p != ' ') && (*p != '\0')) {
1120               printf("%c", *p);
1121               p ++;
1122             }
1123           } else {
1124             if (*p != '\n')
1125             printf("%c", *p);
1126             p ++;
1127           }
1128         }
1129
1130         printf("\n");
1131       } else p ++;
1132     }
1133 #else
1134     get_cpuconfig();
1135 #endif
1136
1137 #ifdef FORCE
1138     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1139 #else
1140 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH)
1141     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1142 #endif
1143 #endif
1144
1145  break;
1146
1147   case '2' : /* SMP */
1148     if (get_num_cores() > 1) printf("SMP=1\n");
1149     break;
1150   }
1151
1152   fflush(stdout);
1153
1154   return 0;
1155 }
1156