1 /*****************************************************************************
2 Copyright (c) 2011-2014, The OpenBLAS Project
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are
9 1. Redistributions of source code must retain the above copyright
10 notice, this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in
14 the documentation and/or other materials provided with the
16 3. Neither the name of the OpenBLAS project nor the names of
17 its contributors may be used to endorse or promote products
18 derived from this software without specific prior written
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 **********************************************************************************/
34 /*********************************************************************/
35 /* Copyright 2009, 2010 The University of Texas at Austin. */
36 /* All rights reserved. */
38 /* Redistribution and use in source and binary forms, with or */
39 /* without modification, are permitted provided that the following */
40 /* conditions are met: */
42 /* 1. Redistributions of source code must retain the above */
43 /* copyright notice, this list of conditions and the following */
46 /* 2. Redistributions in binary form must reproduce the above */
47 /* copyright notice, this list of conditions and the following */
48 /* disclaimer in the documentation and/or other materials */
49 /* provided with the distribution. */
51 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
52 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
53 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
54 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
55 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
56 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
57 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
58 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
59 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
60 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
61 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
62 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
63 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
64 /* POSSIBILITY OF SUCH DAMAGE. */
66 /* The views and conclusions contained in the software and */
67 /* documentation are those of the authors and should not be */
68 /* interpreted as representing official policies, either expressed */
69 /* or implied, of The University of Texas at Austin. */
70 /*********************************************************************/
72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
85 #if defined(__FreeBSD__) || defined(__APPLE__)
86 #include <sys/types.h>
87 #include <sys/sysctl.h>
89 #if defined(linux) || defined(__sun__)
90 #include <sys/sysinfo.h>
94 /* #define FORCE_P2 */
95 /* #define FORCE_KATMAI */
96 /* #define FORCE_COPPERMINE */
97 /* #define FORCE_NORTHWOOD */
98 /* #define FORCE_PRESCOTT */
99 /* #define FORCE_BANIAS */
100 /* #define FORCE_YONAH */
101 /* #define FORCE_CORE2 */
102 /* #define FORCE_PENRYN */
103 /* #define FORCE_DUNNINGTON */
104 /* #define FORCE_NEHALEM */
105 /* #define FORCE_SANDYBRIDGE */
106 /* #define FORCE_ATOM */
107 /* #define FORCE_ATHLON */
108 /* #define FORCE_OPTERON */
109 /* #define FORCE_OPTERON_SSE3 */
110 /* #define FORCE_BARCELONA */
111 /* #define FORCE_SHANGHAI */
112 /* #define FORCE_ISTANBUL */
113 /* #define FORCE_BOBCAT */
114 /* #define FORCE_BULLDOZER */
115 /* #define FORCE_PILEDRIVER */
116 /* #define FORCE_SSE_GENERIC */
117 /* #define FORCE_VIAC3 */
118 /* #define FORCE_NANO */
119 /* #define FORCE_POWER3 */
120 /* #define FORCE_POWER4 */
121 /* #define FORCE_POWER5 */
122 /* #define FORCE_POWER6 */
123 /* #define FORCE_POWER7 */
124 /* #define FORCE_POWER8 */
125 /* #define FORCE_PPCG4 */
126 /* #define FORCE_PPC970 */
127 /* #define FORCE_PPC970MP */
128 /* #define FORCE_PPC440 */
129 /* #define FORCE_PPC440FP2 */
130 /* #define FORCE_CELL */
131 /* #define FORCE_SICORTEX */
132 /* #define FORCE_LOONGSON3A */
133 /* #define FORCE_LOONGSON3B */
134 /* #define FORCE_I6400 */
135 /* #define FORCE_P6600 */
136 /* #define FORCE_P5600 */
137 /* #define FORCE_ITANIUM2 */
138 /* #define FORCE_SPARC */
139 /* #define FORCE_SPARCV7 */
140 /* #define FORCE_GENERIC */
145 #define ARCHITECTURE "X86"
146 #define SUBARCHITECTURE "PENTIUM2"
147 #define ARCHCONFIG "-DPENTIUM2 " \
148 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
149 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
150 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
151 "-DHAVE_CMOV -DHAVE_MMX"
153 #define CORENAME "P5"
159 #define ARCHITECTURE "X86"
160 #define SUBARCHITECTURE "PENTIUM3"
161 #define ARCHCONFIG "-DPENTIUM3 " \
162 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
163 "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
164 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
165 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
166 #define LIBNAME "katmai"
167 #define CORENAME "KATMAI"
170 #ifdef FORCE_COPPERMINE
173 #define ARCHITECTURE "X86"
174 #define SUBARCHITECTURE "PENTIUM3"
175 #define ARCHCONFIG "-DPENTIUM3 " \
176 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
177 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
178 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
179 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
180 #define LIBNAME "coppermine"
181 #define CORENAME "COPPERMINE"
184 #ifdef FORCE_NORTHWOOD
187 #define ARCHITECTURE "X86"
188 #define SUBARCHITECTURE "PENTIUM4"
189 #define ARCHCONFIG "-DPENTIUM4 " \
190 "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
191 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
192 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
193 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
194 #define LIBNAME "northwood"
195 #define CORENAME "NORTHWOOD"
198 #ifdef FORCE_PRESCOTT
201 #define ARCHITECTURE "X86"
202 #define SUBARCHITECTURE "PENTIUM4"
203 #define ARCHCONFIG "-DPENTIUM4 " \
204 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
205 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
206 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
207 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
208 #define LIBNAME "prescott"
209 #define CORENAME "PRESCOTT"
215 #define ARCHITECTURE "X86"
216 #define SUBARCHITECTURE "BANIAS"
217 #define ARCHCONFIG "-DPENTIUMM " \
218 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
219 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
220 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
221 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
222 #define LIBNAME "banias"
223 #define CORENAME "BANIAS"
229 #define ARCHITECTURE "X86"
230 #define SUBARCHITECTURE "YONAH"
231 #define ARCHCONFIG "-DPENTIUMM " \
232 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
233 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
234 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
235 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
236 #define LIBNAME "yonah"
237 #define CORENAME "YONAH"
243 #define ARCHITECTURE "X86"
244 #define SUBARCHITECTURE "CONRORE"
245 #define ARCHCONFIG "-DCORE2 " \
246 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
247 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
248 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
249 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
250 #define LIBNAME "core2"
251 #define CORENAME "CORE2"
257 #define ARCHITECTURE "X86"
258 #define SUBARCHITECTURE "PENRYN"
259 #define ARCHCONFIG "-DPENRYN " \
260 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
261 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
262 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
263 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
264 #define LIBNAME "penryn"
265 #define CORENAME "PENRYN"
268 #ifdef FORCE_DUNNINGTON
271 #define ARCHITECTURE "X86"
272 #define SUBARCHITECTURE "DUNNINGTON"
273 #define ARCHCONFIG "-DDUNNINGTON " \
274 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
275 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
276 "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
277 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
278 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
279 #define LIBNAME "dunnington"
280 #define CORENAME "DUNNINGTON"
286 #define ARCHITECTURE "X86"
287 #define SUBARCHITECTURE "NEHALEM"
288 #define ARCHCONFIG "-DNEHALEM " \
289 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
290 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
291 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
292 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
293 #define LIBNAME "nehalem"
294 #define CORENAME "NEHALEM"
297 #ifdef FORCE_SANDYBRIDGE
300 #define ARCHITECTURE "X86"
301 #define SUBARCHITECTURE "SANDYBRIDGE"
302 #define ARCHCONFIG "-DSANDYBRIDGE " \
303 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
304 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
305 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
306 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
307 #define LIBNAME "sandybridge"
308 #define CORENAME "SANDYBRIDGE"
314 #define ARCHITECTURE "X86"
315 #define SUBARCHITECTURE "HASWELL"
316 #define ARCHCONFIG "-DHASWELL " \
317 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
318 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
319 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
320 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
322 #define LIBNAME "haswell"
323 #define CORENAME "HASWELL"
329 #define ARCHITECTURE "X86"
330 #define SUBARCHITECTURE "ATOM"
331 #define ARCHCONFIG "-DATOM " \
332 "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
333 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
334 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
335 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
336 #define LIBNAME "atom"
337 #define CORENAME "ATOM"
343 #define ARCHITECTURE "X86"
344 #define SUBARCHITECTURE "ATHLON"
345 #define ARCHCONFIG "-DATHLON " \
346 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
347 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
348 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
349 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
350 #define LIBNAME "athlon"
351 #define CORENAME "ATHLON"
357 #define ARCHITECTURE "X86"
358 #define SUBARCHITECTURE "OPTERON"
359 #define ARCHCONFIG "-DOPTERON " \
360 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
361 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
362 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
363 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
364 #define LIBNAME "opteron"
365 #define CORENAME "OPTERON"
368 #ifdef FORCE_OPTERON_SSE3
371 #define ARCHITECTURE "X86"
372 #define SUBARCHITECTURE "OPTERON"
373 #define ARCHCONFIG "-DOPTERON " \
374 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
375 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
376 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
377 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
378 #define LIBNAME "opteron"
379 #define CORENAME "OPTERON"
382 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
385 #define ARCHITECTURE "X86"
386 #define SUBARCHITECTURE "BARCELONA"
387 #define ARCHCONFIG "-DBARCELONA " \
388 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
389 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL3_SIZE=2097152 " \
390 "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
391 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
392 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
393 #define LIBNAME "barcelona"
394 #define CORENAME "BARCELONA"
397 #if defined(FORCE_BOBCAT)
400 #define ARCHITECTURE "X86"
401 #define SUBARCHITECTURE "BOBCAT"
402 #define ARCHCONFIG "-DBOBCAT " \
403 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
404 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
405 "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
406 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
407 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
408 #define LIBNAME "bobcat"
409 #define CORENAME "BOBCAT"
412 #if defined (FORCE_BULLDOZER)
415 #define ARCHITECTURE "X86"
416 #define SUBARCHITECTURE "BULLDOZER"
417 #define ARCHCONFIG "-DBULLDOZER " \
418 "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
419 "-DL2_SIZE=1024000 -DL2_LINESIZE=64 -DL3_SIZE=16777216 " \
420 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
421 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
422 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
423 "-DHAVE_AVX -DHAVE_FMA4"
424 #define LIBNAME "bulldozer"
425 #define CORENAME "BULLDOZER"
428 #if defined (FORCE_PILEDRIVER)
431 #define ARCHITECTURE "X86"
432 #define SUBARCHITECTURE "PILEDRIVER"
433 #define ARCHCONFIG "-DPILEDRIVER " \
434 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
435 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
436 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
437 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
438 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
439 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
440 #define LIBNAME "piledriver"
441 #define CORENAME "PILEDRIVER"
444 #if defined (FORCE_STEAMROLLER)
447 #define ARCHITECTURE "X86"
448 #define SUBARCHITECTURE "STEAMROLLER"
449 #define ARCHCONFIG "-DSTEAMROLLER " \
450 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
451 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
452 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
453 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
454 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
455 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
456 #define LIBNAME "steamroller"
457 #define CORENAME "STEAMROLLER"
460 #if defined (FORCE_EXCAVATOR)
463 #define ARCHITECTURE "X86"
464 #define SUBARCHITECTURE "EXCAVATOR"
465 #define ARCHCONFIG "-DEXCAVATOR " \
466 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
467 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
468 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
469 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
470 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
471 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
472 #define LIBNAME "excavator"
473 #define CORENAME "EXCAVATOR"
477 #ifdef FORCE_SSE_GENERIC
480 #define ARCHITECTURE "X86"
481 #define SUBARCHITECTURE "GENERIC"
482 #define ARCHCONFIG "-DGENERIC " \
483 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
484 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
485 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
486 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
487 #define LIBNAME "generic"
488 #define CORENAME "GENERIC"
494 #define ARCHITECTURE "X86"
495 #define SUBARCHITECTURE "VIAC3"
496 #define ARCHCONFIG "-DVIAC3 " \
497 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
498 "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
499 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
500 "-DHAVE_MMX -DHAVE_SSE "
501 #define LIBNAME "viac3"
502 #define CORENAME "VIAC3"
508 #define ARCHITECTURE "X86"
509 #define SUBARCHITECTURE "NANO"
510 #define ARCHCONFIG "-DNANO " \
511 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
512 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
513 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
514 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
515 #define LIBNAME "nano"
516 #define CORENAME "NANO"
521 #define ARCHITECTURE "POWER"
522 #define SUBARCHITECTURE "POWER3"
523 #define SUBDIRNAME "power"
524 #define ARCHCONFIG "-DPOWER3 " \
525 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
526 "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
527 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
528 #define LIBNAME "power3"
529 #define CORENAME "POWER3"
534 #define ARCHITECTURE "POWER"
535 #define SUBARCHITECTURE "POWER4"
536 #define SUBDIRNAME "power"
537 #define ARCHCONFIG "-DPOWER4 " \
538 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
539 "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
540 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
541 #define LIBNAME "power4"
542 #define CORENAME "POWER4"
547 #define ARCHITECTURE "POWER"
548 #define SUBARCHITECTURE "POWER5"
549 #define SUBDIRNAME "power"
550 #define ARCHCONFIG "-DPOWER5 " \
551 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
552 "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
553 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
554 #define LIBNAME "power5"
555 #define CORENAME "POWER5"
558 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
560 #define ARCHITECTURE "POWER"
561 #define SUBARCHITECTURE "POWER6"
562 #define SUBDIRNAME "power"
563 #define ARCHCONFIG "-DPOWER6 " \
564 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
565 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
566 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
567 #define LIBNAME "power6"
568 #define CORENAME "POWER6"
571 #if defined(FORCE_POWER8)
573 #define ARCHITECTURE "POWER"
574 #define SUBARCHITECTURE "POWER8"
575 #define SUBDIRNAME "power"
576 #define ARCHCONFIG "-DPOWER8 " \
577 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
578 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
579 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
580 #define LIBNAME "power8"
581 #define CORENAME "POWER8"
587 #define ARCHITECTURE "POWER"
588 #define SUBARCHITECTURE "PPCG4"
589 #define SUBDIRNAME "power"
590 #define ARCHCONFIG "-DPPCG4 " \
591 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
592 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
593 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
594 #define LIBNAME "ppcg4"
595 #define CORENAME "PPCG4"
600 #define ARCHITECTURE "POWER"
601 #define SUBARCHITECTURE "PPC970"
602 #define SUBDIRNAME "power"
603 #define ARCHCONFIG "-DPPC970 " \
604 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
605 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
606 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
607 #define LIBNAME "ppc970"
608 #define CORENAME "PPC970"
611 #ifdef FORCE_PPC970MP
613 #define ARCHITECTURE "POWER"
614 #define SUBARCHITECTURE "PPC970"
615 #define SUBDIRNAME "power"
616 #define ARCHCONFIG "-DPPC970 " \
617 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
618 "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
619 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
620 #define LIBNAME "ppc970mp"
621 #define CORENAME "PPC970"
626 #define ARCHITECTURE "POWER"
627 #define SUBARCHITECTURE "PPC440"
628 #define SUBDIRNAME "power"
629 #define ARCHCONFIG "-DPPC440 " \
630 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
631 "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
632 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
633 #define LIBNAME "ppc440"
634 #define CORENAME "PPC440"
637 #ifdef FORCE_PPC440FP2
639 #define ARCHITECTURE "POWER"
640 #define SUBARCHITECTURE "PPC440FP2"
641 #define SUBDIRNAME "power"
642 #define ARCHCONFIG "-DPPC440FP2 " \
643 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
644 "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
645 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
646 #define LIBNAME "ppc440FP2"
647 #define CORENAME "PPC440FP2"
652 #define ARCHITECTURE "POWER"
653 #define SUBARCHITECTURE "CELL"
654 #define SUBDIRNAME "power"
655 #define ARCHCONFIG "-DCELL " \
656 "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
657 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
658 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
659 #define LIBNAME "cell"
660 #define CORENAME "CELL"
663 #ifdef FORCE_SICORTEX
665 #define ARCHITECTURE "MIPS"
666 #define SUBARCHITECTURE "SICORTEX"
667 #define SUBDIRNAME "mips"
668 #define ARCHCONFIG "-DSICORTEX " \
669 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
670 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
671 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
672 #define LIBNAME "mips"
673 #define CORENAME "sicortex"
677 #ifdef FORCE_LOONGSON3A
679 #define ARCHITECTURE "MIPS"
680 #define SUBARCHITECTURE "LOONGSON3A"
681 #define SUBDIRNAME "mips64"
682 #define ARCHCONFIG "-DLOONGSON3A " \
683 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
684 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
685 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
686 #define LIBNAME "loongson3a"
687 #define CORENAME "LOONGSON3A"
691 #ifdef FORCE_LOONGSON3B
693 #define ARCHITECTURE "MIPS"
694 #define SUBARCHITECTURE "LOONGSON3B"
695 #define SUBDIRNAME "mips64"
696 #define ARCHCONFIG "-DLOONGSON3B " \
697 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
698 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
699 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
700 #define LIBNAME "loongson3b"
701 #define CORENAME "LOONGSON3B"
707 #define ARCHITECTURE "MIPS"
708 #define SUBARCHITECTURE "I6400"
709 #define SUBDIRNAME "mips64"
710 #define ARCHCONFIG "-DI6400 " \
711 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
712 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
713 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
714 #define LIBNAME "i6400"
715 #define CORENAME "I6400"
721 #define ARCHITECTURE "MIPS"
722 #define SUBARCHITECTURE "P6600"
723 #define SUBDIRNAME "mips64"
724 #define ARCHCONFIG "-DP6600 " \
725 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
726 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
727 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
728 #define LIBNAME "p6600"
729 #define CORENAME "P6600"
735 #define ARCHITECTURE "MIPS"
736 #define SUBARCHITECTURE "P5600"
737 #define SUBDIRNAME "mips"
738 #define ARCHCONFIG "-DP5600 " \
739 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
740 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
741 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
742 #define LIBNAME "p5600"
743 #define CORENAME "P5600"
747 #ifdef FORCE_ITANIUM2
749 #define ARCHITECTURE "IA64"
750 #define SUBARCHITECTURE "ITANIUM2"
751 #define SUBDIRNAME "ia64"
752 #define ARCHCONFIG "-DITANIUM2 " \
753 "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
754 "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
755 #define LIBNAME "itanium2"
756 #define CORENAME "itanium2"
761 #define ARCHITECTURE "SPARC"
762 #define SUBARCHITECTURE "SPARC"
763 #define SUBDIRNAME "sparc"
764 #define ARCHCONFIG "-DSPARC -DV9 " \
765 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
766 "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
767 #define LIBNAME "sparc"
768 #define CORENAME "sparc"
773 #define ARCHITECTURE "SPARC"
774 #define SUBARCHITECTURE "SPARC"
775 #define SUBDIRNAME "sparc"
776 #define ARCHCONFIG "-DSPARC -DV7 " \
777 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
778 "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
779 #define LIBNAME "sparcv7"
780 #define CORENAME "sparcv7"
785 #define ARCHITECTURE "GENERIC"
786 #define SUBARCHITECTURE "GENERIC"
787 #define SUBDIRNAME "generic"
788 #define ARCHCONFIG "-DGENERIC " \
789 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
790 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
791 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
792 #define LIBNAME "generic"
793 #define CORENAME "generic"
798 #define ARCHITECTURE "ARM"
799 #define SUBARCHITECTURE "ARMV7"
800 #define SUBDIRNAME "arm"
801 #define ARCHCONFIG "-DARMV7 " \
802 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
803 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
804 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
805 "-DHAVE_VFPV3 -DHAVE_VFP"
806 #define LIBNAME "armv7"
807 #define CORENAME "ARMV7"
811 #ifdef FORCE_CORTEXA9
813 #define ARCHITECTURE "ARM"
814 #define SUBARCHITECTURE "CORTEXA9"
815 #define SUBDIRNAME "arm"
816 #define ARCHCONFIG "-DCORTEXA9 -DARMV7 " \
817 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
818 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
819 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
820 "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
821 #define LIBNAME "cortexa9"
822 #define CORENAME "CORTEXA9"
826 #ifdef FORCE_CORTEXA15
828 #define ARCHITECTURE "ARM"
829 #define SUBARCHITECTURE "CORTEXA15"
830 #define SUBDIRNAME "arm"
831 #define ARCHCONFIG "-DCORTEXA15 -DARMV7 " \
832 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
833 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
834 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
835 "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
836 #define LIBNAME "cortexa15"
837 #define CORENAME "CORTEXA15"
843 #define ARCHITECTURE "ARM"
844 #define SUBARCHITECTURE "ARMV6"
845 #define SUBDIRNAME "arm"
846 #define ARCHCONFIG "-DARMV6 " \
847 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
848 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
849 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
851 #define LIBNAME "armv6"
852 #define CORENAME "ARMV6"
858 #define ARCHITECTURE "ARM"
859 #define SUBARCHITECTURE "ARMV5"
860 #define SUBDIRNAME "arm"
861 #define ARCHCONFIG "-DARMV5 " \
862 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
863 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
864 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
865 #define LIBNAME "armv5"
866 #define CORENAME "ARMV5"
873 #define ARCHITECTURE "ARM64"
874 #define SUBARCHITECTURE "ARMV8"
875 #define SUBDIRNAME "arm64"
876 #define ARCHCONFIG "-DARMV8 " \
877 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
878 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
879 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
880 #define LIBNAME "armv8"
881 #define CORENAME "ARMV8"
884 #ifdef FORCE_CORTEXA57
886 #define ARCHITECTURE "ARM64"
887 #define SUBARCHITECTURE "CORTEXA57"
888 #define SUBDIRNAME "arm64"
889 #define ARCHCONFIG "-DCORTEXA57 " \
890 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
891 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
892 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
893 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
894 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
895 #define LIBNAME "cortexa57"
896 #define CORENAME "CORTEXA57"
902 #define ARCHITECTURE "ARM64"
903 #define SUBARCHITECTURE "VULCAN"
904 #define SUBDIRNAME "arm64"
905 #define ARCHCONFIG "-DVULCAN " \
906 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
907 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
908 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
909 "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
910 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
911 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
912 #define LIBNAME "vulcan"
913 #define CORENAME "VULCAN"
917 #ifdef FORCE_THUNDERX
919 #define ARCHITECTURE "ARM64"
920 #define SUBARCHITECTURE "THUNDERX"
921 #define SUBDIRNAME "arm64"
922 #define ARCHCONFIG "-DTHUNDERX " \
923 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
924 "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
925 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 "
926 #define LIBNAME "thunderx"
927 #define CORENAME "THUNDERX"
931 #ifdef FORCE_THUNDERX2T99
933 #define ARCHITECTURE "ARM64"
934 #define SUBARCHITECTURE "THUNDERX2T99"
935 #define SUBDIRNAME "arm64"
936 #define ARCHCONFIG "-DTHUNDERX2T99 " \
937 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
938 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
939 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
940 "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
941 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
942 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
943 #define LIBNAME "thunderx2t99"
944 #define CORENAME "THUNDERX2T99"
950 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
951 defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
955 #define OPENBLAS_SUPPORTED
958 #if defined(__zarch__) || defined(__s390x__)
960 #include "cpuid_zarch.c"
961 #define OPENBLAS_SUPPORTED
965 #include "cpuid_x86.c"
966 #define OPENBLAS_SUPPORTED
970 #include "cpuid_ia64.c"
971 #define OPENBLAS_SUPPORTED
975 #include "cpuid_alpha.c"
976 #define OPENBLAS_SUPPORTED
980 #include "cpuid_power.c"
981 #define OPENBLAS_SUPPORTED
985 #include "cpuid_sparc.c"
986 #define OPENBLAS_SUPPORTED
991 #include "cpuid_mips64.c"
993 #include "cpuid_mips.c"
995 #define OPENBLAS_SUPPORTED
999 #include "cpuid_arm.c"
1000 #define OPENBLAS_SUPPORTED
1004 #include "cpuid_arm64.c"
1005 #define OPENBLAS_SUPPORTED
1009 #ifndef OPENBLAS_SUPPORTED
1010 #error "This arch/CPU is not supported by OpenBLAS."
1017 static int get_num_cores(void) {
1020 SYSTEM_INFO sysinfo;
1021 #elif defined(__FreeBSD__) || defined(__APPLE__)
1026 #if defined(linux) || defined(__sun__)
1027 //returns the number of processors which are currently online
1028 return sysconf(_SC_NPROCESSORS_CONF);
1030 #elif defined(OS_WINDOWS)
1032 GetSystemInfo(&sysinfo);
1033 return sysinfo.dwNumberOfProcessors;
1035 #elif defined(__FreeBSD__) || defined(__APPLE__)
1039 sysctl(m, 2, &count, &len, NULL, 0);
1047 int main(int argc, char *argv[]){
1050 char buffer[8192], *p, *q;
1054 if (argc == 1) return 0;
1056 switch (argv[1][0]) {
1058 case '0' : /* for Makefile */
1061 printf("CORE=%s\n", CORENAME);
1063 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH)
1064 printf("CORE=%s\n", get_corename());
1069 printf("LIBCORE=%s\n", LIBNAME);
1076 printf("NUM_CORES=%d\n", get_num_cores());
1078 #if defined(__arm__) && !defined(FORCE)
1088 sprintf(buffer, "%s", ARCHCONFIG);
1093 if ((*p == '-') && (*(p + 1) == 'D')) {
1096 while ((*p != ' ') && (*p != '\0')) {
1101 while ((*p != ' ') && (*p != '\0')) {
1108 if ((*p == ' ') || (*p =='\0')) printf("=1");
1119 #if MAKE_NB_JOBS > 0
1120 printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1122 // Let make use parent -j argument or -j1 if there
1123 // is no make parent
1125 #elif NO_PARALLEL_MAKE==1
1126 printf("MAKE += -j 1\n");
1129 printf("MAKE += -j %d\n", get_num_cores());
1135 case '1' : /* For config.h */
1137 sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1141 if ((*p == '-') && (*(p + 1) == 'D')) {
1145 while ((*p != ' ') && (*p != '\0')) {
1150 while ((*p != ' ') && (*p != '\0')) {
1169 printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1171 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH)
1172 printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1178 case '2' : /* SMP */
1179 if (get_num_cores() > 1) printf("SMP=1\n");