getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #include <stdio.h>
  77 #include <string.h>
  78 #ifdef OS_WINDOWS
  79 #include <windows.h>
  80 #endif
  81 #if defined(__FreeBSD__) || defined(__APPLE__)
  82 #include <sys/types.h>
  83 #include <sys/sysctl.h>
  84 #endif
  85 #ifdef linux
  86 #include <sys/sysinfo.h>
  87 #include <unistd.h>
  88 #endif
  89
  90 /* #define FORCE_P2             */
  91 /* #define FORCE_KATMAI         */
  92 /* #define FORCE_COPPERMINE     */
  93 /* #define FORCE_NORTHWOOD      */
  94 /* #define FORCE_PRESCOTT       */
  95 /* #define FORCE_BANIAS         */
  96 /* #define FORCE_YONAH          */
  97 /* #define FORCE_CORE2          */
  98 /* #define FORCE_PENRYN         */
  99 /* #define FORCE_DUNNINGTON     */
 100 /* #define FORCE_NEHALEM        */
 101 /* #define FORCE_SANDYBRIDGE    */
 102 /* #define FORCE_ATOM           */
 103 /* #define FORCE_ATHLON         */
 104 /* #define FORCE_OPTERON        */
 105 /* #define FORCE_OPTERON_SSE3   */
 106 /* #define FORCE_BARCELONA      */
 107 /* #define FORCE_SHANGHAI       */
 108 /* #define FORCE_ISTANBUL       */
 109 /* #define FORCE_BOBCAT         */
 110 /* #define FORCE_BULLDOZER      */
 111 /* #define FORCE_PILEDRIVER     */
 112 /* #define FORCE_SSE_GENERIC    */
 113 /* #define FORCE_VIAC3          */
 114 /* #define FORCE_NANO           */
 115 /* #define FORCE_POWER3         */
 116 /* #define FORCE_POWER4         */
 117 /* #define FORCE_POWER5         */
 118 /* #define FORCE_POWER6         */
 119 /* #define FORCE_PPCG4          */
 120 /* #define FORCE_PPC970         */
 121 /* #define FORCE_PPC970MP       */
 122 /* #define FORCE_PPC440         */
 123 /* #define FORCE_PPC440FP2      */
 124 /* #define FORCE_CELL           */
 125 /* #define FORCE_SICORTEX       */
 126 /* #define FORCE_LOONGSON3A     */
 127 /* #define FORCE_LOONGSON3B     */
 128 /* #define FORCE_ITANIUM2       */
 129 /* #define FORCE_SPARC          */
 130 /* #define FORCE_SPARCV7        */
 131 /* #define FORCE_GENERIC        */
 132
 133 #ifdef FORCE_P2
 134 #define FORCE
 135 #define FORCE_INTEL
 136 #define ARCHITECTURE    "X86"
 137 #define SUBARCHITECTURE "PENTIUM2"
 138 #define ARCHCONFIG   "-DPENTIUM2 " \
 139                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 140                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 141                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 142                      "-DHAVE_CMOV -DHAVE_MMX"
 143 #define LIBNAME   "p2"
 144 #define CORENAME  "P5"
 145 #endif
 146
 147 #ifdef FORCE_KATMAI
 148 #define FORCE
 149 #define FORCE_INTEL
 150 #define ARCHITECTURE    "X86"
 151 #define SUBARCHITECTURE "PENTIUM3"
 152 #define ARCHCONFIG   "-DPENTIUM3 " \
 153                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 154                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 155                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 156                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 157 #define LIBNAME   "katmai"
 158 #define CORENAME  "KATMAI"
 159 #endif
 160
 161 #ifdef FORCE_COPPERMINE
 162 #define FORCE
 163 #define FORCE_INTEL
 164 #define ARCHITECTURE    "X86"
 165 #define SUBARCHITECTURE "PENTIUM3"
 166 #define ARCHCONFIG   "-DPENTIUM3 " \
 167                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 168                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 169                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 170                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 171 #define LIBNAME   "coppermine"
 172 #define CORENAME  "COPPERMINE"
 173 #endif
 174
 175 #ifdef FORCE_NORTHWOOD
 176 #define FORCE
 177 #define FORCE_INTEL
 178 #define ARCHITECTURE    "X86"
 179 #define SUBARCHITECTURE "PENTIUM4"
 180 #define ARCHCONFIG   "-DPENTIUM4 " \
 181                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 182                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 183                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 184                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 185 #define LIBNAME   "northwood"
 186 #define CORENAME  "NORTHWOOD"
 187 #endif
 188
 189 #ifdef FORCE_PRESCOTT
 190 #define FORCE
 191 #define FORCE_INTEL
 192 #define ARCHITECTURE    "X86"
 193 #define SUBARCHITECTURE "PENTIUM4"
 194 #define ARCHCONFIG   "-DPENTIUM4 " \
 195                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 196                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 197                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 198                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 199 #define LIBNAME   "prescott"
 200 #define CORENAME  "PRESCOTT"
 201 #endif
 202
 203 #ifdef FORCE_BANIAS
 204 #define FORCE
 205 #define FORCE_INTEL
 206 #define ARCHITECTURE    "X86"
 207 #define SUBARCHITECTURE "BANIAS"
 208 #define ARCHCONFIG   "-DPENTIUMM " \
 209                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 210                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 211                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 212                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 213 #define LIBNAME   "banias"
 214 #define CORENAME  "BANIAS"
 215 #endif
 216
 217 #ifdef FORCE_YONAH
 218 #define FORCE
 219 #define FORCE_INTEL
 220 #define ARCHITECTURE    "X86"
 221 #define SUBARCHITECTURE "YONAH"
 222 #define ARCHCONFIG   "-DPENTIUMM " \
 223                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 224                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 225                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 226                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 227 #define LIBNAME   "yonah"
 228 #define CORENAME  "YONAH"
 229 #endif
 230
 231 #ifdef FORCE_CORE2
 232 #define FORCE
 233 #define FORCE_INTEL
 234 #define ARCHITECTURE    "X86"
 235 #define SUBARCHITECTURE "CONRORE"
 236 #define ARCHCONFIG   "-DCORE2 " \
 237                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 238                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 239                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 240                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 241 #define LIBNAME   "core2"
 242 #define CORENAME  "CORE2"
 243 #endif
 244
 245 #ifdef FORCE_PENRYN
 246 #define FORCE
 247 #define FORCE_INTEL
 248 #define ARCHITECTURE    "X86"
 249 #define SUBARCHITECTURE "PENRYN"
 250 #define ARCHCONFIG   "-DPENRYN " \
 251                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 252                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 253                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 254                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 255 #define LIBNAME   "penryn"
 256 #define CORENAME  "PENRYN"
 257 #endif
 258
 259 #ifdef FORCE_DUNNINGTON
 260 #define FORCE
 261 #define FORCE_INTEL
 262 #define ARCHITECTURE    "X86"
 263 #define SUBARCHITECTURE "DUNNINGTON"
 264 #define ARCHCONFIG   "-DDUNNINGTON " \
 265                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 266                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 267                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 268                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 269                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 270 #define LIBNAME   "dunnington"
 271 #define CORENAME  "DUNNINGTON"
 272 #endif
 273
 274 #ifdef FORCE_NEHALEM
 275 #define FORCE
 276 #define FORCE_INTEL
 277 #define ARCHITECTURE    "X86"
 278 #define SUBARCHITECTURE "NEHALEM"
 279 #define ARCHCONFIG   "-DNEHALEM " \
 280                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 281                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 282                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 283                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 284 #define LIBNAME   "nehalem"
 285 #define CORENAME  "NEHALEM"
 286 #endif
 287
 288 #ifdef FORCE_SANDYBRIDGE
 289 #define FORCE
 290 #define FORCE_INTEL
 291 #define ARCHITECTURE    "X86"
 292 #define SUBARCHITECTURE "SANDYBRIDGE"
 293 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 294                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 295                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 296                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 297                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 298 #define LIBNAME   "sandybridge"
 299 #define CORENAME  "SANDYBRIDGE"
 300 #endif
 301
 302 #ifdef FORCE_HASWELL
 303 #define FORCE
 304 #define FORCE_INTEL
 305 #define ARCHITECTURE    "X86"
 306 #define SUBARCHITECTURE "HASWELL"
 307 #define ARCHCONFIG   "-DHASWELL " \
 308                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 309                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 310                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 311                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 312                      "-DFMA3"
 313 #define LIBNAME   "haswell"
 314 #define CORENAME  "HASWELL"
 315 #endif
 316
 317 #ifdef FORCE_ATOM
 318 #define FORCE
 319 #define FORCE_INTEL
 320 #define ARCHITECTURE    "X86"
 321 #define SUBARCHITECTURE "ATOM"
 322 #define ARCHCONFIG   "-DATOM " \
 323                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 324                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 325                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 326                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 327 #define LIBNAME   "atom"
 328 #define CORENAME  "ATOM"
 329 #endif
 330
 331 #ifdef FORCE_ATHLON
 332 #define FORCE
 333 #define FORCE_INTEL
 334 #define ARCHITECTURE    "X86"
 335 #define SUBARCHITECTURE "ATHLON"
 336 #define ARCHCONFIG   "-DATHLON " \
 337                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 338                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 339                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 340                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 341 #define LIBNAME   "athlon"
 342 #define CORENAME  "ATHLON"
 343 #endif
 344
 345 #ifdef FORCE_OPTERON
 346 #define FORCE
 347 #define FORCE_INTEL
 348 #define ARCHITECTURE    "X86"
 349 #define SUBARCHITECTURE "OPTERON"
 350 #define ARCHCONFIG   "-DOPTERON " \
 351                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 352                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 353                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 354                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 355 #define LIBNAME   "opteron"
 356 #define CORENAME  "OPTERON"
 357 #endif
 358
 359 #ifdef FORCE_OPTERON_SSE3
 360 #define FORCE
 361 #define FORCE_INTEL
 362 #define ARCHITECTURE    "X86"
 363 #define SUBARCHITECTURE "OPTERON"
 364 #define ARCHCONFIG   "-DOPTERON " \
 365                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 366                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 367                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 368                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 369 #define LIBNAME   "opteron"
 370 #define CORENAME  "OPTERON"
 371 #endif
 372
 373 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 374 #define FORCE
 375 #define FORCE_INTEL
 376 #define ARCHITECTURE    "X86"
 377 #define SUBARCHITECTURE "BARCELONA"
 378 #define ARCHCONFIG   "-DBARCELONA " \
 379                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 380                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 381                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 382                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 383                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 384 #define LIBNAME   "barcelona"
 385 #define CORENAME  "BARCELONA"
 386 #endif
 387
 388 #if defined(FORCE_BOBCAT)
 389 #define FORCE
 390 #define FORCE_INTEL
 391 #define ARCHITECTURE    "X86"
 392 #define SUBARCHITECTURE "BOBCAT"
 393 #define ARCHCONFIG   "-DBOBCAT " \
 394                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 395                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 396                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 397                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 398                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 399 #define LIBNAME   "bobcat"
 400 #define CORENAME  "BOBCAT"
 401 #endif
 402
 403 #if defined (FORCE_BULLDOZER)
 404 #define FORCE
 405 #define FORCE_INTEL
 406 #define ARCHITECTURE    "X86"
 407 #define SUBARCHITECTURE "BULLDOZER"
 408 #define ARCHCONFIG   "-DBULLDOZER " \
 409                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 410                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 411                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 412                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 413                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 414                      "-DHAVE_AVX -DHAVE_FMA4"
 415 #define LIBNAME   "bulldozer"
 416 #define CORENAME  "BULLDOZER"
 417 #endif
 418
 419 #if defined (FORCE_PILEDRIVER)
 420 #define FORCE
 421 #define FORCE_INTEL
 422 #define ARCHITECTURE    "X86"
 423 #define SUBARCHITECTURE "PILEDRIVER"
 424 #define ARCHCONFIG   "-DPILEDRIVER " \
 425                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 426                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 427                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 428                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 429                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 430                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 431 #define LIBNAME   "piledriver"
 432 #define CORENAME  "PILEDRIVER"
 433 #endif
 434
 435 #ifdef FORCE_SSE_GENERIC
 436 #define FORCE
 437 #define FORCE_INTEL
 438 #define ARCHITECTURE    "X86"
 439 #define SUBARCHITECTURE "GENERIC"
 440 #define ARCHCONFIG   "-DGENERIC " \
 441                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 442                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 443                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 444                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 445 #define LIBNAME   "generic"
 446 #define CORENAME  "GENERIC"
 447 #endif
 448
 449 #ifdef FORCE_VIAC3
 450 #define FORCE
 451 #define FORCE_INTEL
 452 #define ARCHITECTURE    "X86"
 453 #define SUBARCHITECTURE "VIAC3"
 454 #define ARCHCONFIG   "-DVIAC3 " \
 455                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 456                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 457                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 458                      "-DHAVE_MMX -DHAVE_SSE "
 459 #define LIBNAME   "viac3"
 460 #define CORENAME  "VIAC3"
 461 #endif
 462
 463 #ifdef FORCE_NANO
 464 #define FORCE
 465 #define FORCE_INTEL
 466 #define ARCHITECTURE    "X86"
 467 #define SUBARCHITECTURE "NANO"
 468 #define ARCHCONFIG   "-DNANO " \
 469                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 470                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 471                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 472                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 473 #define LIBNAME   "nano"
 474 #define CORENAME  "NANO"
 475 #endif
 476
 477 #ifdef FORCE_POWER3
 478 #define FORCE
 479 #define ARCHITECTURE    "POWER"
 480 #define SUBARCHITECTURE "POWER3"
 481 #define SUBDIRNAME      "power"
 482 #define ARCHCONFIG   "-DPOWER3 " \
 483                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 484                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 485                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 486 #define LIBNAME   "power3"
 487 #define CORENAME  "POWER3"
 488 #endif
 489
 490 #ifdef FORCE_POWER4
 491 #define FORCE
 492 #define ARCHITECTURE    "POWER"
 493 #define SUBARCHITECTURE "POWER4"
 494 #define SUBDIRNAME      "power"
 495 #define ARCHCONFIG   "-DPOWER4 " \
 496                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 497                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 498                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 499 #define LIBNAME   "power4"
 500 #define CORENAME  "POWER4"
 501 #endif
 502
 503 #ifdef FORCE_POWER5
 504 #define FORCE
 505 #define ARCHITECTURE    "POWER"
 506 #define SUBARCHITECTURE "POWER5"
 507 #define SUBDIRNAME      "power"
 508 #define ARCHCONFIG   "-DPOWER5 " \
 509                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 510                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 511                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 512 #define LIBNAME   "power5"
 513 #define CORENAME  "POWER5"
 514 #endif
 515
 516 #ifdef FORCE_POWER6
 517 #define FORCE
 518 #define ARCHITECTURE    "POWER"
 519 #define SUBARCHITECTURE "POWER6"
 520 #define SUBDIRNAME      "power"
 521 #define ARCHCONFIG   "-DPOWER6 " \
 522                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 523                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 524                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 525 #define LIBNAME   "power6"
 526 #define CORENAME  "POWER6"
 527 #endif
 528
 529 #ifdef FORCE_PPCG4
 530 #define FORCE
 531 #define ARCHITECTURE    "POWER"
 532 #define SUBARCHITECTURE "PPCG4"
 533 #define SUBDIRNAME      "power"
 534 #define ARCHCONFIG   "-DPPCG4 " \
 535                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 536                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 537                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 538 #define LIBNAME   "ppcg4"
 539 #define CORENAME  "PPCG4"
 540 #endif
 541
 542 #ifdef FORCE_PPC970
 543 #define FORCE
 544 #define ARCHITECTURE    "POWER"
 545 #define SUBARCHITECTURE "PPC970"
 546 #define SUBDIRNAME      "power"
 547 #define ARCHCONFIG   "-DPPC970 " \
 548                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 549                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 550                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 551 #define LIBNAME   "ppc970"
 552 #define CORENAME  "PPC970"
 553 #endif
 554
 555 #ifdef FORCE_PPC970MP
 556 #define FORCE
 557 #define ARCHITECTURE    "POWER"
 558 #define SUBARCHITECTURE "PPC970"
 559 #define SUBDIRNAME      "power"
 560 #define ARCHCONFIG   "-DPPC970 " \
 561                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 562                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 563                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 564 #define LIBNAME   "ppc970mp"
 565 #define CORENAME  "PPC970"
 566 #endif
 567
 568 #ifdef FORCE_PPC440
 569 #define FORCE
 570 #define ARCHITECTURE    "POWER"
 571 #define SUBARCHITECTURE "PPC440"
 572 #define SUBDIRNAME      "power"
 573 #define ARCHCONFIG   "-DPPC440 " \
 574                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 575                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 576                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 577 #define LIBNAME   "ppc440"
 578 #define CORENAME  "PPC440"
 579 #endif
 580
 581 #ifdef FORCE_PPC440FP2
 582 #define FORCE
 583 #define ARCHITECTURE    "POWER"
 584 #define SUBARCHITECTURE "PPC440FP2"
 585 #define SUBDIRNAME      "power"
 586 #define ARCHCONFIG   "-DPPC440FP2 " \
 587                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 588                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 589                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 590 #define LIBNAME   "ppc440FP2"
 591 #define CORENAME  "PPC440FP2"
 592 #endif
 593
 594 #ifdef FORCE_CELL
 595 #define FORCE
 596 #define ARCHITECTURE    "POWER"
 597 #define SUBARCHITECTURE "CELL"
 598 #define SUBDIRNAME      "power"
 599 #define ARCHCONFIG   "-DCELL " \
 600                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 601                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 602                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 603 #define LIBNAME   "cell"
 604 #define CORENAME  "CELL"
 605 #endif
 606
 607 #ifdef FORCE_SICORTEX
 608 #define FORCE
 609 #define ARCHITECTURE    "MIPS"
 610 #define SUBARCHITECTURE "SICORTEX"
 611 #define SUBDIRNAME      "mips"
 612 #define ARCHCONFIG   "-DSICORTEX " \
 613                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 614                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 615                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 616 #define LIBNAME   "mips"
 617 #define CORENAME  "sicortex"
 618 #endif
 619
 620
 621 #ifdef FORCE_LOONGSON3A
 622 #define FORCE
 623 #define ARCHITECTURE    "MIPS"
 624 #define SUBARCHITECTURE "LOONGSON3A"
 625 #define SUBDIRNAME      "mips64"
 626 #define ARCHCONFIG   "-DLOONGSON3A " \
 627        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 628        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 629        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 630 #define LIBNAME   "loongson3a"
 631 #define CORENAME  "LOONGSON3A"
 632 #else
 633 #endif
 634
 635 #ifdef FORCE_LOONGSON3B
 636 #define FORCE
 637 #define ARCHITECTURE    "MIPS"
 638 #define SUBARCHITECTURE "LOONGSON3B"
 639 #define SUBDIRNAME      "mips64"
 640 #define ARCHCONFIG   "-DLOONGSON3B " \
 641        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 642        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 643        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 644 #define LIBNAME   "loongson3b"
 645 #define CORENAME  "LOONGSON3B"
 646 #else
 647 #endif
 648
 649 #ifdef FORCE_ITANIUM2
 650 #define FORCE
 651 #define ARCHITECTURE    "IA64"
 652 #define SUBARCHITECTURE "ITANIUM2"
 653 #define SUBDIRNAME      "ia64"
 654 #define ARCHCONFIG   "-DITANIUM2 " \
 655                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 656                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 657 #define LIBNAME   "itanium2"
 658 #define CORENAME  "itanium2"
 659 #endif
 660
 661 #ifdef FORCE_SPARC
 662 #define FORCE
 663 #define ARCHITECTURE    "SPARC"
 664 #define SUBARCHITECTURE "SPARC"
 665 #define SUBDIRNAME      "sparc"
 666 #define ARCHCONFIG   "-DSPARC -DV9 " \
 667                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 668                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 669 #define LIBNAME   "sparc"
 670 #define CORENAME  "sparc"
 671 #endif
 672
 673 #ifdef FORCE_SPARCV7
 674 #define FORCE
 675 #define ARCHITECTURE    "SPARC"
 676 #define SUBARCHITECTURE "SPARC"
 677 #define SUBDIRNAME      "sparc"
 678 #define ARCHCONFIG   "-DSPARC -DV7 " \
 679                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 680                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 681 #define LIBNAME   "sparcv7"
 682 #define CORENAME  "sparcv7"
 683 #endif
 684
 685 #ifdef FORCE_GENERIC
 686 #define FORCE
 687 #define ARCHITECTURE    "GENERIC"
 688 #define SUBARCHITECTURE "GENERIC"
 689 #define SUBDIRNAME      "generic"
 690 #define ARCHCONFIG   "-DGENERIC " \
 691                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 692                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 693                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 694 #define LIBNAME   "generic"
 695 #define CORENAME  "generic"
 696 #endif
 697
 698 #ifdef FORCE_ARMV7
 699 #define FORCE
 700 #define ARCHITECTURE    "ARM"
 701 #define SUBARCHITECTURE "ARMV7"
 702 #define SUBDIRNAME      "arm"
 703 #define ARCHCONFIG   "-DARMV7 " \
 704        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 705        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 706        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 707        "-DHAVE_VFPV3 -DHAVE_VFP"
 708 #define LIBNAME   "armv7"
 709 #define CORENAME  "ARMV7"
 710 #else
 711 #endif
 712
 713 #ifdef FORCE_ARMV6
 714 #define FORCE
 715 #define ARCHITECTURE    "ARM"
 716 #define SUBARCHITECTURE "ARMV6"
 717 #define SUBDIRNAME      "arm"
 718 #define ARCHCONFIG   "-DARMV6 " \
 719        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 720        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 721        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 722        "-DHAVE_VFP"
 723 #define LIBNAME   "armv6"
 724 #define CORENAME  "ARMV6"
 725 #else
 726 #endif
 727
 728 #ifdef FORCE_ARMV5
 729 #define FORCE
 730 #define ARCHITECTURE    "ARM"
 731 #define SUBARCHITECTURE "ARMV5"
 732 #define SUBDIRNAME      "arm"
 733 #define ARCHCONFIG   "-DARMV5 " \
 734        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 735        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 736        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 737        "-DHAVE_VFP"
 738 #define LIBNAME   "armv5"
 739 #define CORENAME  "ARMV5"
 740 #else
 741 #endif
 742
 743
 744 #ifdef FORCE_ARMV8
 745 #define FORCE
 746 #define ARCHITECTURE    "ARM64"
 747 #define SUBARCHITECTURE "ARMV8"
 748 #define SUBDIRNAME      "arm64"
 749 #define ARCHCONFIG   "-DARMV8 " \
 750        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 751        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 752        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 753 #define LIBNAME   "armv8"
 754 #define CORENAME  "XGENE1"
 755 #else
 756 #endif
 757
 758
 759 #ifndef FORCE
 760
 761 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 762     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 763 #ifndef POWER
 764 #define POWER
 765 #endif
 766 #define OPENBLAS_SUPPORTED
 767 #endif
 768
 769 #if defined(__i386__) || (__x86_64__)
 770 #include "cpuid_x86.c"
 771 #define OPENBLAS_SUPPORTED
 772 #endif
 773
 774 #ifdef __ia64__
 775 #include "cpuid_ia64.c"
 776 #define OPENBLAS_SUPPORTED
 777 #endif
 778
 779 #ifdef __alpha
 780 #include "cpuid_alpha.c"
 781 #define OPENBLAS_SUPPORTED
 782 #endif
 783
 784 #ifdef POWER
 785 #include "cpuid_power.c"
 786 #define OPENBLAS_SUPPORTED
 787 #endif
 788
 789 #ifdef sparc
 790 #include "cpuid_sparc.c"
 791 #define OPENBLAS_SUPPORTED
 792 #endif
 793
 794 #ifdef __mips__
 795 #include "cpuid_mips.c"
 796 #define OPENBLAS_SUPPORTED
 797 #endif
 798
 799 #ifdef __arm__
 800 #include "cpuid_arm.c"
 801 #define OPENBLAS_SUPPORTED
 802 #endif
 803
 804 #ifdef __aarch64__
 805 #include "cpuid_arm64.c"
 806 #define OPENBLAS_SUPPORTED
 807 #endif
 808
 809
 810 #ifndef OPENBLAS_SUPPORTED
 811 #error "This arch/CPU is not supported by OpenBLAS."
 812 #endif
 813
 814 #else
 815
 816 #endif
 817
 818 static int get_num_cores(void) {
 819
 820 #ifdef OS_WINDOWS
 821   SYSTEM_INFO sysinfo;
 822 #elif defined(__FreeBSD__) || defined(__APPLE__)
 823   int m[2], count;
 824   size_t len;
 825 #endif
 826
 827 #ifdef linux
 828   //returns the number of processors which are currently online
 829   return sysconf(_SC_NPROCESSORS_ONLN);
 830
 831 #elif defined(OS_WINDOWS)
 832
 833   GetSystemInfo(&sysinfo);
 834   return sysinfo.dwNumberOfProcessors;
 835
 836 #elif defined(__FreeBSD__) || defined(__APPLE__)
 837   m[0] = CTL_HW;
 838   m[1] = HW_NCPU;
 839   len = sizeof(int);
 840   sysctl(m, 2, &count, &len, NULL, 0);
 841
 842   return count;
 843 #else
 844   return 2;
 845 #endif
 846 }
 847
 848 int main(int argc, char *argv[]){
 849
 850 #ifdef FORCE
 851   char buffer[8192], *p, *q;
 852   int length;
 853 #endif
 854
 855   if (argc == 1) return 0;
 856
 857   switch (argv[1][0]) {
 858
 859   case '0' : /* for Makefile */
 860
 861 #ifdef FORCE
 862     printf("CORE=%s\n", CORENAME);
 863 #else
 864 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 865     printf("CORE=%s\n", get_corename());
 866 #endif
 867 #endif
 868
 869 #ifdef FORCE
 870     printf("LIBCORE=%s\n", LIBNAME);
 871 #else
 872     printf("LIBCORE=");
 873     get_libname();
 874     printf("\n");
 875 #endif
 876
 877     printf("NUM_CORES=%d\n", get_num_cores());
 878
 879 #if defined(__arm__) && !defined(FORCE)
 880         get_features();
 881 #endif
 882
 883
 884 #if defined(__i386__) || defined(__x86_64__)
 885 #ifndef FORCE
 886     get_sse();
 887 #else
 888
 889     sprintf(buffer, "%s", ARCHCONFIG);
 890
 891     p = &buffer[0];
 892
 893     while (*p) {
 894       if ((*p == '-') && (*(p + 1) == 'D')) {
 895         p += 2;
 896
 897         while ((*p != ' ') && (*p != '\0')) {
 898
 899           if (*p == '=') {
 900             printf("=");
 901             p ++;
 902             while ((*p != ' ') && (*p != '\0')) {
 903               printf("%c", *p);
 904               p ++;
 905             }
 906           } else {
 907             printf("%c", *p);
 908             p ++;
 909             if ((*p == ' ') || (*p =='\0')) printf("=1");
 910           }
 911         }
 912
 913         printf("\n");
 914       } else p ++;
 915     }
 916 #endif
 917 #endif
 918
 919 #if NO_PARALLEL_MAKE==1
 920     printf("MAKE += -j 1\n");
 921 #else
 922 #ifndef OS_WINDOWS
 923     printf("MAKE += -j %d\n", get_num_cores());
 924 #endif
 925 #endif
 926
 927     break;
 928
 929   case '1' : /* For config.h */
 930 #ifdef FORCE
 931     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 932
 933     p = &buffer[0];
 934     while (*p) {
 935       if ((*p == '-') && (*(p + 1) == 'D')) {
 936         p += 2;
 937         printf("#define ");
 938
 939         while ((*p != ' ') && (*p != '\0')) {
 940
 941           if (*p == '=') {
 942             printf(" ");
 943             p ++;
 944             while ((*p != ' ') && (*p != '\0')) {
 945               printf("%c", *p);
 946               p ++;
 947             }
 948           } else {
 949             printf("%c", *p);
 950             p ++;
 951           }
 952         }
 953
 954         printf("\n");
 955       } else p ++;
 956     }
 957 #else
 958     get_cpuconfig();
 959 #endif
 960
 961 #ifdef FORCE
 962     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
 963 #else
 964 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 965     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
 966 #endif
 967 #endif
 968
 969  break;
 970
 971   case '2' : /* SMP */
 972     if (get_num_cores() > 1) printf("SMP=1\n");
 973     break;
 974   }
 975
 976   fflush(stdout);
 977
 978   return 0;
 979 }
 980