getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P5600          */
 136 /* #define FORCE_ITANIUM2       */
 137 /* #define FORCE_SPARC          */
 138 /* #define FORCE_SPARCV7        */
 139 /* #define FORCE_GENERIC        */
 140
 141 #ifdef FORCE_P2
 142 #define FORCE
 143 #define FORCE_INTEL
 144 #define ARCHITECTURE    "X86"
 145 #define SUBARCHITECTURE "PENTIUM2"
 146 #define ARCHCONFIG   "-DPENTIUM2 " \
 147                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 148                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 149                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 150                      "-DHAVE_CMOV -DHAVE_MMX"
 151 #define LIBNAME   "p2"
 152 #define CORENAME  "P5"
 153 #endif
 154
 155 #ifdef FORCE_KATMAI
 156 #define FORCE
 157 #define FORCE_INTEL
 158 #define ARCHITECTURE    "X86"
 159 #define SUBARCHITECTURE "PENTIUM3"
 160 #define ARCHCONFIG   "-DPENTIUM3 " \
 161                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 162                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 163                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 164                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 165 #define LIBNAME   "katmai"
 166 #define CORENAME  "KATMAI"
 167 #endif
 168
 169 #ifdef FORCE_COPPERMINE
 170 #define FORCE
 171 #define FORCE_INTEL
 172 #define ARCHITECTURE    "X86"
 173 #define SUBARCHITECTURE "PENTIUM3"
 174 #define ARCHCONFIG   "-DPENTIUM3 " \
 175                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 176                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 177                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 178                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 179 #define LIBNAME   "coppermine"
 180 #define CORENAME  "COPPERMINE"
 181 #endif
 182
 183 #ifdef FORCE_NORTHWOOD
 184 #define FORCE
 185 #define FORCE_INTEL
 186 #define ARCHITECTURE    "X86"
 187 #define SUBARCHITECTURE "PENTIUM4"
 188 #define ARCHCONFIG   "-DPENTIUM4 " \
 189                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 190                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 191                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 192                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 193 #define LIBNAME   "northwood"
 194 #define CORENAME  "NORTHWOOD"
 195 #endif
 196
 197 #ifdef FORCE_PRESCOTT
 198 #define FORCE
 199 #define FORCE_INTEL
 200 #define ARCHITECTURE    "X86"
 201 #define SUBARCHITECTURE "PENTIUM4"
 202 #define ARCHCONFIG   "-DPENTIUM4 " \
 203                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 204                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 205                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 206                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 207 #define LIBNAME   "prescott"
 208 #define CORENAME  "PRESCOTT"
 209 #endif
 210
 211 #ifdef FORCE_BANIAS
 212 #define FORCE
 213 #define FORCE_INTEL
 214 #define ARCHITECTURE    "X86"
 215 #define SUBARCHITECTURE "BANIAS"
 216 #define ARCHCONFIG   "-DPENTIUMM " \
 217                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 218                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 219                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 220                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 221 #define LIBNAME   "banias"
 222 #define CORENAME  "BANIAS"
 223 #endif
 224
 225 #ifdef FORCE_YONAH
 226 #define FORCE
 227 #define FORCE_INTEL
 228 #define ARCHITECTURE    "X86"
 229 #define SUBARCHITECTURE "YONAH"
 230 #define ARCHCONFIG   "-DPENTIUMM " \
 231                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 232                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 233                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 234                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 235 #define LIBNAME   "yonah"
 236 #define CORENAME  "YONAH"
 237 #endif
 238
 239 #ifdef FORCE_CORE2
 240 #define FORCE
 241 #define FORCE_INTEL
 242 #define ARCHITECTURE    "X86"
 243 #define SUBARCHITECTURE "CONRORE"
 244 #define ARCHCONFIG   "-DCORE2 " \
 245                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 246                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 247                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 248                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 249 #define LIBNAME   "core2"
 250 #define CORENAME  "CORE2"
 251 #endif
 252
 253 #ifdef FORCE_PENRYN
 254 #define FORCE
 255 #define FORCE_INTEL
 256 #define ARCHITECTURE    "X86"
 257 #define SUBARCHITECTURE "PENRYN"
 258 #define ARCHCONFIG   "-DPENRYN " \
 259                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 260                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 261                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 262                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 263 #define LIBNAME   "penryn"
 264 #define CORENAME  "PENRYN"
 265 #endif
 266
 267 #ifdef FORCE_DUNNINGTON
 268 #define FORCE
 269 #define FORCE_INTEL
 270 #define ARCHITECTURE    "X86"
 271 #define SUBARCHITECTURE "DUNNINGTON"
 272 #define ARCHCONFIG   "-DDUNNINGTON " \
 273                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 274                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 275                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 276                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 277                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 278 #define LIBNAME   "dunnington"
 279 #define CORENAME  "DUNNINGTON"
 280 #endif
 281
 282 #ifdef FORCE_NEHALEM
 283 #define FORCE
 284 #define FORCE_INTEL
 285 #define ARCHITECTURE    "X86"
 286 #define SUBARCHITECTURE "NEHALEM"
 287 #define ARCHCONFIG   "-DNEHALEM " \
 288                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 289                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 290                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 291                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 292 #define LIBNAME   "nehalem"
 293 #define CORENAME  "NEHALEM"
 294 #endif
 295
 296 #ifdef FORCE_SANDYBRIDGE
 297 #define FORCE
 298 #define FORCE_INTEL
 299 #define ARCHITECTURE    "X86"
 300 #define SUBARCHITECTURE "SANDYBRIDGE"
 301 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 302                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 303                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 304                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 305                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 306 #define LIBNAME   "sandybridge"
 307 #define CORENAME  "SANDYBRIDGE"
 308 #endif
 309
 310 #ifdef FORCE_HASWELL
 311 #define FORCE
 312 #define FORCE_INTEL
 313 #define ARCHITECTURE    "X86"
 314 #define SUBARCHITECTURE "HASWELL"
 315 #define ARCHCONFIG   "-DHASWELL " \
 316                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 317                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 318                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 319                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 320                      "-DFMA3"
 321 #define LIBNAME   "haswell"
 322 #define CORENAME  "HASWELL"
 323 #endif
 324
 325 #ifdef FORCE_ATOM
 326 #define FORCE
 327 #define FORCE_INTEL
 328 #define ARCHITECTURE    "X86"
 329 #define SUBARCHITECTURE "ATOM"
 330 #define ARCHCONFIG   "-DATOM " \
 331                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 332                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 333                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 334                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 335 #define LIBNAME   "atom"
 336 #define CORENAME  "ATOM"
 337 #endif
 338
 339 #ifdef FORCE_ATHLON
 340 #define FORCE
 341 #define FORCE_INTEL
 342 #define ARCHITECTURE    "X86"
 343 #define SUBARCHITECTURE "ATHLON"
 344 #define ARCHCONFIG   "-DATHLON " \
 345                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 346                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 347                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 348                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 349 #define LIBNAME   "athlon"
 350 #define CORENAME  "ATHLON"
 351 #endif
 352
 353 #ifdef FORCE_OPTERON
 354 #define FORCE
 355 #define FORCE_INTEL
 356 #define ARCHITECTURE    "X86"
 357 #define SUBARCHITECTURE "OPTERON"
 358 #define ARCHCONFIG   "-DOPTERON " \
 359                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 360                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 361                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 362                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 363 #define LIBNAME   "opteron"
 364 #define CORENAME  "OPTERON"
 365 #endif
 366
 367 #ifdef FORCE_OPTERON_SSE3
 368 #define FORCE
 369 #define FORCE_INTEL
 370 #define ARCHITECTURE    "X86"
 371 #define SUBARCHITECTURE "OPTERON"
 372 #define ARCHCONFIG   "-DOPTERON " \
 373                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 374                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 375                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 376                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 377 #define LIBNAME   "opteron"
 378 #define CORENAME  "OPTERON"
 379 #endif
 380
 381 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 382 #define FORCE
 383 #define FORCE_INTEL
 384 #define ARCHITECTURE    "X86"
 385 #define SUBARCHITECTURE "BARCELONA"
 386 #define ARCHCONFIG   "-DBARCELONA " \
 387                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 388                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 389                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 390                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 391                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 392 #define LIBNAME   "barcelona"
 393 #define CORENAME  "BARCELONA"
 394 #endif
 395
 396 #if defined(FORCE_BOBCAT)
 397 #define FORCE
 398 #define FORCE_INTEL
 399 #define ARCHITECTURE    "X86"
 400 #define SUBARCHITECTURE "BOBCAT"
 401 #define ARCHCONFIG   "-DBOBCAT " \
 402                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 403                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 404                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 405                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 406                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 407 #define LIBNAME   "bobcat"
 408 #define CORENAME  "BOBCAT"
 409 #endif
 410
 411 #if defined (FORCE_BULLDOZER)
 412 #define FORCE
 413 #define FORCE_INTEL
 414 #define ARCHITECTURE    "X86"
 415 #define SUBARCHITECTURE "BULLDOZER"
 416 #define ARCHCONFIG   "-DBULLDOZER " \
 417                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 418                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 419                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 420                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 421                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 422                      "-DHAVE_AVX -DHAVE_FMA4"
 423 #define LIBNAME   "bulldozer"
 424 #define CORENAME  "BULLDOZER"
 425 #endif
 426
 427 #if defined (FORCE_PILEDRIVER)
 428 #define FORCE
 429 #define FORCE_INTEL
 430 #define ARCHITECTURE    "X86"
 431 #define SUBARCHITECTURE "PILEDRIVER"
 432 #define ARCHCONFIG   "-DPILEDRIVER " \
 433                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 434                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 435                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 436                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 437                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 438                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 439 #define LIBNAME   "piledriver"
 440 #define CORENAME  "PILEDRIVER"
 441 #endif
 442
 443 #if defined (FORCE_STEAMROLLER)
 444 #define FORCE
 445 #define FORCE_INTEL
 446 #define ARCHITECTURE    "X86"
 447 #define SUBARCHITECTURE "STEAMROLLER"
 448 #define ARCHCONFIG   "-DSTEAMROLLER " \
 449                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 450                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 451                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 452                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 453                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 454                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 455 #define LIBNAME   "steamroller"
 456 #define CORENAME  "STEAMROLLER"
 457 #endif
 458
 459 #if defined (FORCE_EXCAVATOR)
 460 #define FORCE
 461 #define FORCE_INTEL
 462 #define ARCHITECTURE    "X86"
 463 #define SUBARCHITECTURE "EXCAVATOR"
 464 #define ARCHCONFIG   "-DEXCAVATOR " \
 465                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 466                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 467                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 468                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 469                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 470                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 471 #define LIBNAME   "excavator"
 472 #define CORENAME  "EXCAVATOR"
 473 #endif
 474
 475
 476 #ifdef FORCE_SSE_GENERIC
 477 #define FORCE
 478 #define FORCE_INTEL
 479 #define ARCHITECTURE    "X86"
 480 #define SUBARCHITECTURE "GENERIC"
 481 #define ARCHCONFIG   "-DGENERIC " \
 482                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 483                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 484                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 485                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 486 #define LIBNAME   "generic"
 487 #define CORENAME  "GENERIC"
 488 #endif
 489
 490 #ifdef FORCE_VIAC3
 491 #define FORCE
 492 #define FORCE_INTEL
 493 #define ARCHITECTURE    "X86"
 494 #define SUBARCHITECTURE "VIAC3"
 495 #define ARCHCONFIG   "-DVIAC3 " \
 496                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 497                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 498                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 499                      "-DHAVE_MMX -DHAVE_SSE "
 500 #define LIBNAME   "viac3"
 501 #define CORENAME  "VIAC3"
 502 #endif
 503
 504 #ifdef FORCE_NANO
 505 #define FORCE
 506 #define FORCE_INTEL
 507 #define ARCHITECTURE    "X86"
 508 #define SUBARCHITECTURE "NANO"
 509 #define ARCHCONFIG   "-DNANO " \
 510                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 511                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 512                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 513                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 514 #define LIBNAME   "nano"
 515 #define CORENAME  "NANO"
 516 #endif
 517
 518 #ifdef FORCE_POWER3
 519 #define FORCE
 520 #define ARCHITECTURE    "POWER"
 521 #define SUBARCHITECTURE "POWER3"
 522 #define SUBDIRNAME      "power"
 523 #define ARCHCONFIG   "-DPOWER3 " \
 524                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 525                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 526                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 527 #define LIBNAME   "power3"
 528 #define CORENAME  "POWER3"
 529 #endif
 530
 531 #ifdef FORCE_POWER4
 532 #define FORCE
 533 #define ARCHITECTURE    "POWER"
 534 #define SUBARCHITECTURE "POWER4"
 535 #define SUBDIRNAME      "power"
 536 #define ARCHCONFIG   "-DPOWER4 " \
 537                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 538                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 539                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 540 #define LIBNAME   "power4"
 541 #define CORENAME  "POWER4"
 542 #endif
 543
 544 #ifdef FORCE_POWER5
 545 #define FORCE
 546 #define ARCHITECTURE    "POWER"
 547 #define SUBARCHITECTURE "POWER5"
 548 #define SUBDIRNAME      "power"
 549 #define ARCHCONFIG   "-DPOWER5 " \
 550                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 551                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 552                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 553 #define LIBNAME   "power5"
 554 #define CORENAME  "POWER5"
 555 #endif
 556
 557 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 558 #define FORCE
 559 #define ARCHITECTURE    "POWER"
 560 #define SUBARCHITECTURE "POWER6"
 561 #define SUBDIRNAME      "power"
 562 #define ARCHCONFIG   "-DPOWER6 " \
 563                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 564                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 565                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 566 #define LIBNAME   "power6"
 567 #define CORENAME  "POWER6"
 568 #endif
 569
 570 #if defined(FORCE_POWER8)
 571 #define FORCE
 572 #define ARCHITECTURE    "POWER"
 573 #define SUBARCHITECTURE "POWER8"
 574 #define SUBDIRNAME      "power"
 575 #define ARCHCONFIG   "-DPOWER8 " \
 576                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 577                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 578                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 579 #define LIBNAME   "power8"
 580 #define CORENAME  "POWER8"
 581 #endif
 582
 583
 584 #ifdef FORCE_PPCG4
 585 #define FORCE
 586 #define ARCHITECTURE    "POWER"
 587 #define SUBARCHITECTURE "PPCG4"
 588 #define SUBDIRNAME      "power"
 589 #define ARCHCONFIG   "-DPPCG4 " \
 590                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 591                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 592                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 593 #define LIBNAME   "ppcg4"
 594 #define CORENAME  "PPCG4"
 595 #endif
 596
 597 #ifdef FORCE_PPC970
 598 #define FORCE
 599 #define ARCHITECTURE    "POWER"
 600 #define SUBARCHITECTURE "PPC970"
 601 #define SUBDIRNAME      "power"
 602 #define ARCHCONFIG   "-DPPC970 " \
 603                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 604                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 605                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 606 #define LIBNAME   "ppc970"
 607 #define CORENAME  "PPC970"
 608 #endif
 609
 610 #ifdef FORCE_PPC970MP
 611 #define FORCE
 612 #define ARCHITECTURE    "POWER"
 613 #define SUBARCHITECTURE "PPC970"
 614 #define SUBDIRNAME      "power"
 615 #define ARCHCONFIG   "-DPPC970 " \
 616                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 617                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 618                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 619 #define LIBNAME   "ppc970mp"
 620 #define CORENAME  "PPC970"
 621 #endif
 622
 623 #ifdef FORCE_PPC440
 624 #define FORCE
 625 #define ARCHITECTURE    "POWER"
 626 #define SUBARCHITECTURE "PPC440"
 627 #define SUBDIRNAME      "power"
 628 #define ARCHCONFIG   "-DPPC440 " \
 629                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 630                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 631                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 632 #define LIBNAME   "ppc440"
 633 #define CORENAME  "PPC440"
 634 #endif
 635
 636 #ifdef FORCE_PPC440FP2
 637 #define FORCE
 638 #define ARCHITECTURE    "POWER"
 639 #define SUBARCHITECTURE "PPC440FP2"
 640 #define SUBDIRNAME      "power"
 641 #define ARCHCONFIG   "-DPPC440FP2 " \
 642                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 643                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 644                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 645 #define LIBNAME   "ppc440FP2"
 646 #define CORENAME  "PPC440FP2"
 647 #endif
 648
 649 #ifdef FORCE_CELL
 650 #define FORCE
 651 #define ARCHITECTURE    "POWER"
 652 #define SUBARCHITECTURE "CELL"
 653 #define SUBDIRNAME      "power"
 654 #define ARCHCONFIG   "-DCELL " \
 655                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 656                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 657                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 658 #define LIBNAME   "cell"
 659 #define CORENAME  "CELL"
 660 #endif
 661
 662 #ifdef FORCE_SICORTEX
 663 #define FORCE
 664 #define ARCHITECTURE    "MIPS"
 665 #define SUBARCHITECTURE "SICORTEX"
 666 #define SUBDIRNAME      "mips"
 667 #define ARCHCONFIG   "-DSICORTEX " \
 668                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 669                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 670                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 671 #define LIBNAME   "mips"
 672 #define CORENAME  "sicortex"
 673 #endif
 674
 675
 676 #ifdef FORCE_LOONGSON3A
 677 #define FORCE
 678 #define ARCHITECTURE    "MIPS"
 679 #define SUBARCHITECTURE "LOONGSON3A"
 680 #define SUBDIRNAME      "mips64"
 681 #define ARCHCONFIG   "-DLOONGSON3A " \
 682        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 683        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 684        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 685 #define LIBNAME   "loongson3a"
 686 #define CORENAME  "LOONGSON3A"
 687 #else
 688 #endif
 689
 690 #ifdef FORCE_LOONGSON3B
 691 #define FORCE
 692 #define ARCHITECTURE    "MIPS"
 693 #define SUBARCHITECTURE "LOONGSON3B"
 694 #define SUBDIRNAME      "mips64"
 695 #define ARCHCONFIG   "-DLOONGSON3B " \
 696        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 697        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 698        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 699 #define LIBNAME   "loongson3b"
 700 #define CORENAME  "LOONGSON3B"
 701 #else
 702 #endif
 703
 704 #ifdef FORCE_I6400
 705 #define FORCE
 706 #define ARCHITECTURE    "MIPS"
 707 #define SUBARCHITECTURE "I6400"
 708 #define SUBDIRNAME      "mips64"
 709 #define ARCHCONFIG   "-DI6400 " \
 710        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 711        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 712        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 713 #define LIBNAME   "i6400"
 714 #define CORENAME  "I6400"
 715 #else
 716 #endif
 717
 718 #ifdef FORCE_P5600
 719 #define FORCE
 720 #define ARCHITECTURE    "MIPS"
 721 #define SUBARCHITECTURE "P5600"
 722 #define SUBDIRNAME      "mips"
 723 #define ARCHCONFIG   "-DP5600 " \
 724        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 725        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 726        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 727 #define LIBNAME   "p5600"
 728 #define CORENAME  "P5600"
 729 #else
 730 #endif
 731
 732 #ifdef FORCE_ITANIUM2
 733 #define FORCE
 734 #define ARCHITECTURE    "IA64"
 735 #define SUBARCHITECTURE "ITANIUM2"
 736 #define SUBDIRNAME      "ia64"
 737 #define ARCHCONFIG   "-DITANIUM2 " \
 738                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 739                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 740 #define LIBNAME   "itanium2"
 741 #define CORENAME  "itanium2"
 742 #endif
 743
 744 #ifdef FORCE_SPARC
 745 #define FORCE
 746 #define ARCHITECTURE    "SPARC"
 747 #define SUBARCHITECTURE "SPARC"
 748 #define SUBDIRNAME      "sparc"
 749 #define ARCHCONFIG   "-DSPARC -DV9 " \
 750                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 751                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 752 #define LIBNAME   "sparc"
 753 #define CORENAME  "sparc"
 754 #endif
 755
 756 #ifdef FORCE_SPARCV7
 757 #define FORCE
 758 #define ARCHITECTURE    "SPARC"
 759 #define SUBARCHITECTURE "SPARC"
 760 #define SUBDIRNAME      "sparc"
 761 #define ARCHCONFIG   "-DSPARC -DV7 " \
 762                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 763                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 764 #define LIBNAME   "sparcv7"
 765 #define CORENAME  "sparcv7"
 766 #endif
 767
 768 #ifdef FORCE_GENERIC
 769 #define FORCE
 770 #define ARCHITECTURE    "GENERIC"
 771 #define SUBARCHITECTURE "GENERIC"
 772 #define SUBDIRNAME      "generic"
 773 #define ARCHCONFIG   "-DGENERIC " \
 774                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 775                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 776                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 777 #define LIBNAME   "generic"
 778 #define CORENAME  "generic"
 779 #endif
 780
 781 #ifdef FORCE_ARMV7
 782 #define FORCE
 783 #define ARCHITECTURE    "ARM"
 784 #define SUBARCHITECTURE "ARMV7"
 785 #define SUBDIRNAME      "arm"
 786 #define ARCHCONFIG   "-DARMV7 " \
 787        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 788        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 789        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 790        "-DHAVE_VFPV3 -DHAVE_VFP"
 791 #define LIBNAME   "armv7"
 792 #define CORENAME  "ARMV7"
 793 #else
 794 #endif
 795
 796 #ifdef FORCE_CORTEXA9
 797 #define FORCE
 798 #define ARCHITECTURE    "ARM"
 799 #define SUBARCHITECTURE "CORTEXA9"
 800 #define SUBDIRNAME      "arm"
 801 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 802        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 803        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 804        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 805        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 806 #define LIBNAME   "cortexa9"
 807 #define CORENAME  "CORTEXA9"
 808 #else
 809 #endif
 810
 811 #ifdef FORCE_CORTEXA15
 812 #define FORCE
 813 #define ARCHITECTURE    "ARM"
 814 #define SUBARCHITECTURE "CORTEXA15"
 815 #define SUBDIRNAME      "arm"
 816 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 817        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 818        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 819        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 820        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 821 #define LIBNAME   "cortexa15"
 822 #define CORENAME  "CORTEXA15"
 823 #else
 824 #endif
 825
 826 #ifdef FORCE_ARMV6
 827 #define FORCE
 828 #define ARCHITECTURE    "ARM"
 829 #define SUBARCHITECTURE "ARMV6"
 830 #define SUBDIRNAME      "arm"
 831 #define ARCHCONFIG   "-DARMV6 " \
 832        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 833        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 834        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 835        "-DHAVE_VFP"
 836 #define LIBNAME   "armv6"
 837 #define CORENAME  "ARMV6"
 838 #else
 839 #endif
 840
 841 #ifdef FORCE_ARMV5
 842 #define FORCE
 843 #define ARCHITECTURE    "ARM"
 844 #define SUBARCHITECTURE "ARMV5"
 845 #define SUBDIRNAME      "arm"
 846 #define ARCHCONFIG   "-DARMV5 " \
 847        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 848        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 849        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 850 #define LIBNAME   "armv5"
 851 #define CORENAME  "ARMV5"
 852 #else
 853 #endif
 854
 855
 856 #ifdef FORCE_ARMV8
 857 #define FORCE
 858 #define ARCHITECTURE    "ARM64"
 859 #define SUBARCHITECTURE "ARMV8"
 860 #define SUBDIRNAME      "arm64"
 861 #define ARCHCONFIG   "-DARMV8 " \
 862        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 863        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 864        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 865 #define LIBNAME   "armv8"
 866 #define CORENAME  "ARMV8"
 867 #endif
 868
 869 #ifdef FORCE_CORTEXA57
 870 #define FORCE
 871 #define ARCHITECTURE    "ARM64"
 872 #define SUBARCHITECTURE "ARMV8"
 873 #define SUBDIRNAME      "arm64"
 874 #define ARCHCONFIG   "-DCORTEXA57 " \
 875        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 876        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 877        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 878        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 879        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 880 #define LIBNAME   "cortexa57"
 881 #define CORENAME  "CORTEXA57"
 882 #else
 883 #endif
 884
 885 #ifndef FORCE
 886
 887 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 888     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 889 #ifndef POWER
 890 #define POWER
 891 #endif
 892 #define OPENBLAS_SUPPORTED
 893 #endif
 894
 895 #ifdef INTEL_AMD
 896 #include "cpuid_x86.c"
 897 #define OPENBLAS_SUPPORTED
 898 #endif
 899
 900 #ifdef __ia64__
 901 #include "cpuid_ia64.c"
 902 #define OPENBLAS_SUPPORTED
 903 #endif
 904
 905 #ifdef __alpha
 906 #include "cpuid_alpha.c"
 907 #define OPENBLAS_SUPPORTED
 908 #endif
 909
 910 #ifdef POWER
 911 #include "cpuid_power.c"
 912 #define OPENBLAS_SUPPORTED
 913 #endif
 914
 915 #ifdef sparc
 916 #include "cpuid_sparc.c"
 917 #define OPENBLAS_SUPPORTED
 918 #endif
 919
 920 #ifdef __mips__
 921 #ifdef __mips64
 922 #include "cpuid_mips64.c"
 923 #else
 924 #include "cpuid_mips.c"
 925 #endif
 926 #define OPENBLAS_SUPPORTED
 927 #endif
 928
 929 #ifdef __arm__
 930 #include "cpuid_arm.c"
 931 #define OPENBLAS_SUPPORTED
 932 #endif
 933
 934 #ifdef __aarch64__
 935 #include "cpuid_arm64.c"
 936 #define OPENBLAS_SUPPORTED
 937 #endif
 938
 939
 940 #ifndef OPENBLAS_SUPPORTED
 941 #error "This arch/CPU is not supported by OpenBLAS."
 942 #endif
 943
 944 #else
 945
 946 #endif
 947
 948 static int get_num_cores(void) {
 949
 950 #ifdef OS_WINDOWS
 951   SYSTEM_INFO sysinfo;
 952 #elif defined(__FreeBSD__) || defined(__APPLE__)
 953   int m[2], count;
 954   size_t len;
 955 #endif
 956
 957 #if defined(linux) || defined(__sun__)
 958   //returns the number of processors which are currently online
 959   return sysconf(_SC_NPROCESSORS_ONLN);
 960
 961 #elif defined(OS_WINDOWS)
 962
 963   GetSystemInfo(&sysinfo);
 964   return sysinfo.dwNumberOfProcessors;
 965
 966 #elif defined(__FreeBSD__) || defined(__APPLE__)
 967   m[0] = CTL_HW;
 968   m[1] = HW_NCPU;
 969   len = sizeof(int);
 970   sysctl(m, 2, &count, &len, NULL, 0);
 971
 972   return count;
 973 #else
 974   return 2;
 975 #endif
 976 }
 977
 978 int main(int argc, char *argv[]){
 979
 980 #ifdef FORCE
 981   char buffer[8192], *p, *q;
 982   int length;
 983 #endif
 984
 985   if (argc == 1) return 0;
 986
 987   switch (argv[1][0]) {
 988
 989   case '0' : /* for Makefile */
 990
 991 #ifdef FORCE
 992     printf("CORE=%s\n", CORENAME);
 993 #else
 994 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 995     printf("CORE=%s\n", get_corename());
 996 #endif
 997 #endif
 998
 999 #ifdef FORCE
1000     printf("LIBCORE=%s\n", LIBNAME);
1001 #else
1002     printf("LIBCORE=");
1003     get_libname();
1004     printf("\n");
1005 #endif
1006
1007     printf("NUM_CORES=%d\n", get_num_cores());
1008
1009 #if defined(__arm__) && !defined(FORCE)
1010         get_features();
1011 #endif
1012
1013
1014 #ifdef INTEL_AMD
1015 #ifndef FORCE
1016     get_sse();
1017 #else
1018
1019     sprintf(buffer, "%s", ARCHCONFIG);
1020
1021     p = &buffer[0];
1022
1023     while (*p) {
1024       if ((*p == '-') && (*(p + 1) == 'D')) {
1025         p += 2;
1026
1027         while ((*p != ' ') && (*p != '\0')) {
1028
1029           if (*p == '=') {
1030             printf("=");
1031             p ++;
1032             while ((*p != ' ') && (*p != '\0')) {
1033               printf("%c", *p);
1034               p ++;
1035             }
1036           } else {
1037             printf("%c", *p);
1038             p ++;
1039             if ((*p == ' ') || (*p =='\0')) printf("=1");
1040           }
1041         }
1042
1043         printf("\n");
1044       } else p ++;
1045     }
1046 #endif
1047 #endif
1048
1049 #ifdef MAKE_NB_JOBS
1050   #if MAKE_NB_JOBS > 0
1051     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1052   #else
1053     // Let make use parent -j argument or -j1 if there
1054     // is no make parent
1055   #endif
1056 #elif NO_PARALLEL_MAKE==1
1057     printf("MAKE += -j 1\n");
1058 #else
1059 #ifndef OS_WINDOWS
1060     printf("MAKE += -j %d\n", get_num_cores());
1061 #endif
1062 #endif
1063
1064     break;
1065
1066   case '1' : /* For config.h */
1067 #ifdef FORCE
1068     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1069
1070     p = &buffer[0];
1071     while (*p) {
1072       if ((*p == '-') && (*(p + 1) == 'D')) {
1073         p += 2;
1074         printf("#define ");
1075
1076         while ((*p != ' ') && (*p != '\0')) {
1077
1078           if (*p == '=') {
1079             printf(" ");
1080             p ++;
1081             while ((*p != ' ') && (*p != '\0')) {
1082               printf("%c", *p);
1083               p ++;
1084             }
1085           } else {
1086             printf("%c", *p);
1087             p ++;
1088           }
1089         }
1090
1091         printf("\n");
1092       } else p ++;
1093     }
1094 #else
1095     get_cpuconfig();
1096 #endif
1097
1098 #ifdef FORCE
1099     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1100 #else
1101 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1102     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1103 #endif
1104 #endif
1105
1106  break;
1107
1108   case '2' : /* SMP */
1109     if (get_num_cores() > 1) printf("SMP=1\n");
1110     break;
1111   }
1112
1113   fflush(stdout);
1114
1115   return 0;
1116 }
1117