getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93 #if defined(AIX)
  94 #include <sys/sysinfo.h>
  95 #endif
  96
  97 #if defined(__x86_64__) || defined(_M_X64)
  98 #if (( defined(__GNUC__)  && __GNUC__   > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
  99 #else
 100 #ifndef NO_AVX512
 101 #define NO_AVX512
 102 #endif
 103 #endif
 104 #endif
 105 /* #define FORCE_P2             */
 106 /* #define FORCE_KATMAI         */
 107 /* #define FORCE_COPPERMINE     */
 108 /* #define FORCE_NORTHWOOD      */
 109 /* #define FORCE_PRESCOTT       */
 110 /* #define FORCE_BANIAS         */
 111 /* #define FORCE_YONAH          */
 112 /* #define FORCE_CORE2          */
 113 /* #define FORCE_PENRYN         */
 114 /* #define FORCE_DUNNINGTON     */
 115 /* #define FORCE_NEHALEM        */
 116 /* #define FORCE_SANDYBRIDGE    */
 117 /* #define FORCE_ATOM           */
 118 /* #define FORCE_ATHLON         */
 119 /* #define FORCE_OPTERON        */
 120 /* #define FORCE_OPTERON_SSE3   */
 121 /* #define FORCE_BARCELONA      */
 122 /* #define FORCE_SHANGHAI       */
 123 /* #define FORCE_ISTANBUL       */
 124 /* #define FORCE_BOBCAT         */
 125 /* #define FORCE_BULLDOZER      */
 126 /* #define FORCE_PILEDRIVER     */
 127 /* #define FORCE_SSE_GENERIC    */
 128 /* #define FORCE_VIAC3          */
 129 /* #define FORCE_NANO           */
 130 /* #define FORCE_POWER3         */
 131 /* #define FORCE_POWER4         */
 132 /* #define FORCE_POWER5         */
 133 /* #define FORCE_POWER6         */
 134 /* #define FORCE_POWER7         */
 135 /* #define FORCE_POWER8         */
 136 /* #define FORCE_PPCG4          */
 137 /* #define FORCE_PPC970         */
 138 /* #define FORCE_PPC970MP       */
 139 /* #define FORCE_PPC440         */
 140 /* #define FORCE_PPC440FP2      */
 141 /* #define FORCE_CELL           */
 142 /* #define FORCE_SICORTEX       */
 143 /* #define FORCE_LOONGSON3R3    */
 144 /* #define FORCE_LOONGSON3R4    */
 145 /* #define FORCE_I6400          */
 146 /* #define FORCE_P6600          */
 147 /* #define FORCE_P5600          */
 148 /* #define FORCE_I6500          */
 149 /* #define FORCE_ITANIUM2       */
 150 /* #define FORCE_SPARC          */
 151 /* #define FORCE_SPARCV7        */
 152 /* #define FORCE_ZARCH_GENERIC  */
 153 /* #define FORCE_Z13            */
 154 /* #define FORCE_GENERIC        */
 155
 156 #ifdef FORCE_P2
 157 #define FORCE
 158 #define FORCE_INTEL
 159 #define ARCHITECTURE    "X86"
 160 #define SUBARCHITECTURE "PENTIUM2"
 161 #define ARCHCONFIG   "-DPENTIUM2 " \
 162                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 163                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 164                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 165                      "-DHAVE_CMOV -DHAVE_MMX"
 166 #define LIBNAME   "p2"
 167 #define CORENAME  "P5"
 168 #endif
 169
 170 #ifdef FORCE_KATMAI
 171 #define FORCE
 172 #define FORCE_INTEL
 173 #define ARCHITECTURE    "X86"
 174 #define SUBARCHITECTURE "PENTIUM3"
 175 #define ARCHCONFIG   "-DPENTIUM3 " \
 176                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 177                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 178                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 179                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 180 #define LIBNAME   "katmai"
 181 #define CORENAME  "KATMAI"
 182 #endif
 183
 184 #ifdef FORCE_COPPERMINE
 185 #define FORCE
 186 #define FORCE_INTEL
 187 #define ARCHITECTURE    "X86"
 188 #define SUBARCHITECTURE "PENTIUM3"
 189 #define ARCHCONFIG   "-DPENTIUM3 " \
 190                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 191                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 192                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 193                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 194 #define LIBNAME   "coppermine"
 195 #define CORENAME  "COPPERMINE"
 196 #endif
 197
 198 #ifdef FORCE_NORTHWOOD
 199 #define FORCE
 200 #define FORCE_INTEL
 201 #define ARCHITECTURE    "X86"
 202 #define SUBARCHITECTURE "PENTIUM4"
 203 #define ARCHCONFIG   "-DPENTIUM4 " \
 204                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 205                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 206                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 207                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 208 #define LIBNAME   "northwood"
 209 #define CORENAME  "NORTHWOOD"
 210 #endif
 211
 212 #ifdef FORCE_PRESCOTT
 213 #define FORCE
 214 #define FORCE_INTEL
 215 #define ARCHITECTURE    "X86"
 216 #define SUBARCHITECTURE "PENTIUM4"
 217 #define ARCHCONFIG   "-DPENTIUM4 " \
 218                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 219                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 220                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 221                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 222 #define LIBNAME   "prescott"
 223 #define CORENAME  "PRESCOTT"
 224 #endif
 225
 226 #ifdef FORCE_BANIAS
 227 #define FORCE
 228 #define FORCE_INTEL
 229 #define ARCHITECTURE    "X86"
 230 #define SUBARCHITECTURE "BANIAS"
 231 #define ARCHCONFIG   "-DPENTIUMM " \
 232                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 233                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 234                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 235                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 236 #define LIBNAME   "banias"
 237 #define CORENAME  "BANIAS"
 238 #endif
 239
 240 #ifdef FORCE_YONAH
 241 #define FORCE
 242 #define FORCE_INTEL
 243 #define ARCHITECTURE    "X86"
 244 #define SUBARCHITECTURE "YONAH"
 245 #define ARCHCONFIG   "-DPENTIUMM " \
 246                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 247                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 248                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 249                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 250 #define LIBNAME   "yonah"
 251 #define CORENAME  "YONAH"
 252 #endif
 253
 254 #ifdef FORCE_CORE2
 255 #define FORCE
 256 #define FORCE_INTEL
 257 #define ARCHITECTURE    "X86"
 258 #define SUBARCHITECTURE "CONRORE"
 259 #define ARCHCONFIG   "-DCORE2 " \
 260                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 261                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 262                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 263                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 264 #define LIBNAME   "core2"
 265 #define CORENAME  "CORE2"
 266 #endif
 267
 268 #ifdef FORCE_PENRYN
 269 #define FORCE
 270 #define FORCE_INTEL
 271 #define ARCHITECTURE    "X86"
 272 #define SUBARCHITECTURE "PENRYN"
 273 #define ARCHCONFIG   "-DPENRYN " \
 274                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 275                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 276                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 277                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 278 #define LIBNAME   "penryn"
 279 #define CORENAME  "PENRYN"
 280 #endif
 281
 282 #ifdef FORCE_DUNNINGTON
 283 #define FORCE
 284 #define FORCE_INTEL
 285 #define ARCHITECTURE    "X86"
 286 #define SUBARCHITECTURE "DUNNINGTON"
 287 #define ARCHCONFIG   "-DDUNNINGTON " \
 288                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 289                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 290                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 291                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 292                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 293 #define LIBNAME   "dunnington"
 294 #define CORENAME  "DUNNINGTON"
 295 #endif
 296
 297 #ifdef FORCE_NEHALEM
 298 #define FORCE
 299 #define FORCE_INTEL
 300 #define ARCHITECTURE    "X86"
 301 #define SUBARCHITECTURE "NEHALEM"
 302 #define ARCHCONFIG   "-DNEHALEM " \
 303                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 304                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 305                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 306                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 307 #define LIBNAME   "nehalem"
 308 #define CORENAME  "NEHALEM"
 309 #endif
 310
 311 #ifdef FORCE_SANDYBRIDGE
 312 #define FORCE
 313 #define FORCE_INTEL
 314 #define ARCHITECTURE    "X86"
 315 #define SUBARCHITECTURE "SANDYBRIDGE"
 316 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 317                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 318                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 319                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 320                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 321 #define LIBNAME   "sandybridge"
 322 #define CORENAME  "SANDYBRIDGE"
 323 #endif
 324
 325 #ifdef FORCE_HASWELL
 326 #define FORCE
 327 #define FORCE_INTEL
 328 #define ARCHITECTURE    "X86"
 329 #ifdef NO_AVX2
 330 #define SUBARCHITECTURE "SANDYBRIDGE"
 331 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 332                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 333                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 334                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 335                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 336 #define LIBNAME   "sandybridge"
 337 #define CORENAME  "SANDYBRIDGE"
 338 #else
 339 #define SUBARCHITECTURE "HASWELL"
 340 #define ARCHCONFIG   "-DHASWELL " \
 341                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 342                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 343                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 344                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 345                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 346 #define LIBNAME   "haswell"
 347 #define CORENAME  "HASWELL"
 348 #endif
 349 #endif
 350
 351 #ifdef FORCE_SKYLAKEX
 352 #ifdef NO_AVX512
 353 #define FORCE
 354 #define FORCE_INTEL
 355 #define ARCHITECTURE    "X86"
 356 #define SUBARCHITECTURE "HASWELL"
 357 #define ARCHCONFIG   "-DHASWELL " \
 358                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 359                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 360                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 361                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 362                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 363 #define LIBNAME   "haswell"
 364 #define CORENAME  "HASWELL"
 365 #else
 366 #define FORCE
 367 #define FORCE_INTEL
 368 #define ARCHITECTURE    "X86"
 369 #define SUBARCHITECTURE "SKYLAKEX"
 370 #define ARCHCONFIG   "-DSKYLAKEX " \
 371                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 372                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 373                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 374                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 375                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 376 #define LIBNAME   "skylakex"
 377 #define CORENAME  "SKYLAKEX"
 378 #endif
 379 #endif
 380
 381 #ifdef FORCE_COOPERLAKE
 382 #ifdef NO_AVX512
 383 #define FORCE
 384 #define FORCE_INTEL
 385 #define ARCHITECTURE    "X86"
 386 #define SUBARCHITECTURE "HASWELL"
 387 #define ARCHCONFIG   "-DHASWELL " \
 388                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 389                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 390                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 391                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 392                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 393 #define LIBNAME   "haswell"
 394 #define CORENAME  "HASWELL"
 395 #else
 396 #define FORCE
 397 #define FORCE_INTEL
 398 #define ARCHITECTURE    "X86"
 399 #define SUBARCHITECTURE "COOPERLAKE"
 400 #define ARCHCONFIG   "-DCOOPERLAKE " \
 401                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 402                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 403                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 404                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 405                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
 406 #define LIBNAME   "cooperlake"
 407 #define CORENAME  "COOPERLAKE"
 408 #endif
 409 #endif
 410
 411 #ifdef FORCE_ATOM
 412 #define FORCE
 413 #define FORCE_INTEL
 414 #define ARCHITECTURE    "X86"
 415 #define SUBARCHITECTURE "ATOM"
 416 #define ARCHCONFIG   "-DATOM " \
 417                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 418                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 419                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 420                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 421 #define LIBNAME   "atom"
 422 #define CORENAME  "ATOM"
 423 #endif
 424
 425 #ifdef FORCE_ATHLON
 426 #define FORCE
 427 #define FORCE_INTEL
 428 #define ARCHITECTURE    "X86"
 429 #define SUBARCHITECTURE "ATHLON"
 430 #define ARCHCONFIG   "-DATHLON " \
 431                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 432                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 433                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 434                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 435 #define LIBNAME   "athlon"
 436 #define CORENAME  "ATHLON"
 437 #endif
 438
 439 #ifdef FORCE_OPTERON
 440 #define FORCE
 441 #define FORCE_INTEL
 442 #define ARCHITECTURE    "X86"
 443 #define SUBARCHITECTURE "OPTERON"
 444 #define ARCHCONFIG   "-DOPTERON " \
 445                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 446                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 447                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 448                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 449 #define LIBNAME   "opteron"
 450 #define CORENAME  "OPTERON"
 451 #endif
 452
 453 #ifdef FORCE_OPTERON_SSE3
 454 #define FORCE
 455 #define FORCE_INTEL
 456 #define ARCHITECTURE    "X86"
 457 #define SUBARCHITECTURE "OPTERON"
 458 #define ARCHCONFIG   "-DOPTERON " \
 459                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 460                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 461                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 462                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 463 #define LIBNAME   "opteron"
 464 #define CORENAME  "OPTERON"
 465 #endif
 466
 467 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 468 #define FORCE
 469 #define FORCE_INTEL
 470 #define ARCHITECTURE    "X86"
 471 #define SUBARCHITECTURE "BARCELONA"
 472 #define ARCHCONFIG   "-DBARCELONA " \
 473                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 474                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 475                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 476                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 477                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 478 #define LIBNAME   "barcelona"
 479 #define CORENAME  "BARCELONA"
 480 #endif
 481
 482 #if defined(FORCE_BOBCAT)
 483 #define FORCE
 484 #define FORCE_INTEL
 485 #define ARCHITECTURE    "X86"
 486 #define SUBARCHITECTURE "BOBCAT"
 487 #define ARCHCONFIG   "-DBOBCAT " \
 488                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 489                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 490                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 491                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 492                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 493 #define LIBNAME   "bobcat"
 494 #define CORENAME  "BOBCAT"
 495 #endif
 496
 497 #if defined (FORCE_BULLDOZER)
 498 #define FORCE
 499 #define FORCE_INTEL
 500 #define ARCHITECTURE    "X86"
 501 #define SUBARCHITECTURE "BULLDOZER"
 502 #define ARCHCONFIG   "-DBULLDOZER " \
 503                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 504                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 505                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 506                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 507                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 508                      "-DHAVE_AVX"
 509 #define LIBNAME   "bulldozer"
 510 #define CORENAME  "BULLDOZER"
 511 #endif
 512
 513 #if defined (FORCE_PILEDRIVER)
 514 #define FORCE
 515 #define FORCE_INTEL
 516 #define ARCHITECTURE    "X86"
 517 #define SUBARCHITECTURE "PILEDRIVER"
 518 #define ARCHCONFIG   "-DPILEDRIVER " \
 519                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 520                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 521                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 522                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 523                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 524                      "-DHAVE_AVX -DHAVE_FMA3"
 525 #define LIBNAME   "piledriver"
 526 #define CORENAME  "PILEDRIVER"
 527 #endif
 528
 529 #if defined (FORCE_STEAMROLLER)
 530 #define FORCE
 531 #define FORCE_INTEL
 532 #define ARCHITECTURE    "X86"
 533 #define SUBARCHITECTURE "STEAMROLLER"
 534 #define ARCHCONFIG   "-DSTEAMROLLER " \
 535                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 536                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 537                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 538                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 539                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 540                      "-DHAVE_AVX -DHAVE_FMA3"
 541 #define LIBNAME   "steamroller"
 542 #define CORENAME  "STEAMROLLER"
 543 #endif
 544
 545 #if defined (FORCE_EXCAVATOR)
 546 #define FORCE
 547 #define FORCE_INTEL
 548 #define ARCHITECTURE    "X86"
 549 #define SUBARCHITECTURE "EXCAVATOR"
 550 #define ARCHCONFIG   "-DEXCAVATOR " \
 551                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 552                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 553                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 554                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 555                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 556                      "-DHAVE_AVX -DHAVE_FMA3"
 557 #define LIBNAME   "excavator"
 558 #define CORENAME  "EXCAVATOR"
 559 #endif
 560
 561 #if defined (FORCE_ZEN)
 562 #define FORCE
 563 #define FORCE_INTEL
 564 #define ARCHITECTURE    "X86"
 565 #ifdef NO_AVX2
 566 #define SUBARCHITECTURE "SANDYBRIDGE"
 567 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 568                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 569                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 570                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 571                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 572 #define LIBNAME   "sandybridge"
 573 #define CORENAME  "SANDYBRIDGE"
 574 #else
 575 #define SUBARCHITECTURE "ZEN"
 576 #define ARCHCONFIG   "-DZEN " \
 577                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 578                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 579                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 580                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 581                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 582                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 583                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 584                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 585                      "-DHAVE_AVX -DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 586 #define LIBNAME   "zen"
 587 #define CORENAME  "ZEN"
 588 #endif
 589 #endif
 590
 591
 592 #ifdef FORCE_SSE_GENERIC
 593 #define FORCE
 594 #define FORCE_INTEL
 595 #define ARCHITECTURE    "X86"
 596 #define SUBARCHITECTURE "GENERIC"
 597 #define ARCHCONFIG   "-DGENERIC " \
 598                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 599                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 600                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 601                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 602 #define LIBNAME   "generic"
 603 #define CORENAME  "GENERIC"
 604 #endif
 605
 606 #ifdef FORCE_VIAC3
 607 #define FORCE
 608 #define FORCE_INTEL
 609 #define ARCHITECTURE    "X86"
 610 #define SUBARCHITECTURE "VIAC3"
 611 #define ARCHCONFIG   "-DVIAC3 " \
 612                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 613                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 614                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 615                      "-DHAVE_MMX -DHAVE_SSE "
 616 #define LIBNAME   "viac3"
 617 #define CORENAME  "VIAC3"
 618 #endif
 619
 620 #ifdef FORCE_NANO
 621 #define FORCE
 622 #define FORCE_INTEL
 623 #define ARCHITECTURE    "X86"
 624 #define SUBARCHITECTURE "NANO"
 625 #define ARCHCONFIG   "-DNANO " \
 626                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 627                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 628                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 629                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 630 #define LIBNAME   "nano"
 631 #define CORENAME  "NANO"
 632 #endif
 633
 634 #ifdef FORCE_POWER3
 635 #define FORCE
 636 #define ARCHITECTURE    "POWER"
 637 #define SUBARCHITECTURE "POWER3"
 638 #define SUBDIRNAME      "power"
 639 #define ARCHCONFIG   "-DPOWER3 " \
 640                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 641                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 642                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 643 #define LIBNAME   "power3"
 644 #define CORENAME  "POWER3"
 645 #endif
 646
 647 #ifdef FORCE_POWER4
 648 #define FORCE
 649 #define ARCHITECTURE    "POWER"
 650 #define SUBARCHITECTURE "POWER4"
 651 #define SUBDIRNAME      "power"
 652 #define ARCHCONFIG   "-DPOWER4 " \
 653                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 654                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 655                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 656 #define LIBNAME   "power4"
 657 #define CORENAME  "POWER4"
 658 #endif
 659
 660 #ifdef FORCE_POWER5
 661 #define FORCE
 662 #define ARCHITECTURE    "POWER"
 663 #define SUBARCHITECTURE "POWER5"
 664 #define SUBDIRNAME      "power"
 665 #define ARCHCONFIG   "-DPOWER5 " \
 666                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 667                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 668                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 669 #define LIBNAME   "power5"
 670 #define CORENAME  "POWER5"
 671 #endif
 672
 673 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 674 #define FORCE
 675 #define ARCHITECTURE    "POWER"
 676 #define SUBARCHITECTURE "POWER6"
 677 #define SUBDIRNAME      "power"
 678 #define ARCHCONFIG   "-DPOWER6 " \
 679                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 680                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 681                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 682 #define LIBNAME   "power6"
 683 #define CORENAME  "POWER6"
 684 #endif
 685
 686 #if defined(FORCE_POWER8)
 687 #define FORCE
 688 #define ARCHITECTURE    "POWER"
 689 #define SUBARCHITECTURE "POWER8"
 690 #define SUBDIRNAME      "power"
 691 #define ARCHCONFIG   "-DPOWER8 " \
 692                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 693                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 694                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 695 #define LIBNAME   "power8"
 696 #define CORENAME  "POWER8"
 697 #endif
 698
 699 #if defined(FORCE_POWER9)
 700 #define FORCE
 701 #define ARCHITECTURE    "POWER"
 702 #define SUBARCHITECTURE "POWER9"
 703 #define SUBDIRNAME      "power"
 704 #define ARCHCONFIG   "-DPOWER9 " \
 705                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 706                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 707                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 708 #define LIBNAME   "power9"
 709 #define CORENAME  "POWER9"
 710 #endif
 711
 712 #if defined(FORCE_POWER10)
 713 #define FORCE
 714 #define ARCHITECTURE    "POWER"
 715 #define SUBARCHITECTURE "POWER10"
 716 #define SUBDIRNAME      "power"
 717 #define ARCHCONFIG   "-DPOWER10 " \
 718                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 719                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 720                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 721 #define LIBNAME   "power10"
 722 #define CORENAME  "POWER10"
 723 #endif
 724
 725 #ifdef FORCE_PPCG4
 726 #define FORCE
 727 #define ARCHITECTURE    "POWER"
 728 #define SUBARCHITECTURE "PPCG4"
 729 #define SUBDIRNAME      "power"
 730 #define ARCHCONFIG   "-DPPCG4 " \
 731                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 732                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 733                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 734 #define LIBNAME   "ppcg4"
 735 #define CORENAME  "PPCG4"
 736 #endif
 737
 738 #ifdef FORCE_PPC970
 739 #define FORCE
 740 #define ARCHITECTURE    "POWER"
 741 #define SUBARCHITECTURE "PPC970"
 742 #define SUBDIRNAME      "power"
 743 #define ARCHCONFIG   "-DPPC970 " \
 744                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 745                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 746                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 747 #define LIBNAME   "ppc970"
 748 #define CORENAME  "PPC970"
 749 #endif
 750
 751 #ifdef FORCE_PPC970MP
 752 #define FORCE
 753 #define ARCHITECTURE    "POWER"
 754 #define SUBARCHITECTURE "PPC970"
 755 #define SUBDIRNAME      "power"
 756 #define ARCHCONFIG   "-DPPC970 " \
 757                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 758                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 759                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 760 #define LIBNAME   "ppc970mp"
 761 #define CORENAME  "PPC970"
 762 #endif
 763
 764 #ifdef FORCE_PPC440
 765 #define FORCE
 766 #define ARCHITECTURE    "POWER"
 767 #define SUBARCHITECTURE "PPC440"
 768 #define SUBDIRNAME      "power"
 769 #define ARCHCONFIG   "-DPPC440 " \
 770                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 771                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 772                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 773 #define LIBNAME   "ppc440"
 774 #define CORENAME  "PPC440"
 775 #endif
 776
 777 #ifdef FORCE_PPC440FP2
 778 #define FORCE
 779 #define ARCHITECTURE    "POWER"
 780 #define SUBARCHITECTURE "PPC440FP2"
 781 #define SUBDIRNAME      "power"
 782 #define ARCHCONFIG   "-DPPC440FP2 " \
 783                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 784                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 785                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 786 #define LIBNAME   "ppc440FP2"
 787 #define CORENAME  "PPC440FP2"
 788 #endif
 789
 790 #ifdef FORCE_CELL
 791 #define FORCE
 792 #define ARCHITECTURE    "POWER"
 793 #define SUBARCHITECTURE "CELL"
 794 #define SUBDIRNAME      "power"
 795 #define ARCHCONFIG   "-DCELL " \
 796                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 797                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 798                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 799 #define LIBNAME   "cell"
 800 #define CORENAME  "CELL"
 801 #endif
 802
 803 #ifdef FORCE_SICORTEX
 804 #define FORCE
 805 #define ARCHITECTURE    "MIPS"
 806 #define SUBARCHITECTURE "SICORTEX"
 807 #define SUBDIRNAME      "mips"
 808 #define ARCHCONFIG   "-DSICORTEX " \
 809                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 810                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 811                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 812 #define LIBNAME   "mips"
 813 #define CORENAME  "sicortex"
 814 #endif
 815
 816
 817 #if defined FORCE_LOONGSON3R3 || defined FORCE_LOONGSON3A || defined FORCE_LOONGSON3B
 818 #define FORCE
 819 #define ARCHITECTURE    "MIPS"
 820 #define SUBARCHITECTURE "LOONGSON3R3"
 821 #define SUBDIRNAME      "mips64"
 822 #define ARCHCONFIG   "-DLOONGSON3R3 " \
 823        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 824        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 825        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 826 #define LIBNAME   "loongson3r3"
 827 #define CORENAME  "LOONGSON3R3"
 828 #else
 829 #endif
 830
 831 #ifdef FORCE_LOONGSON3R4
 832 #define FORCE
 833 #define ARCHITECTURE    "MIPS"
 834 #define SUBARCHITECTURE "LOONGSON3R4"
 835 #define SUBDIRNAME      "mips64"
 836 #define ARCHCONFIG   "-DLOONGSON3R4 " \
 837        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 838        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 839        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 840 #define LIBNAME   "loongson3r4"
 841 #define CORENAME  "LOONGSON3R4"
 842 #else
 843 #endif
 844
 845 #ifdef FORCE_I6400
 846 #define FORCE
 847 #define ARCHITECTURE    "MIPS"
 848 #define SUBARCHITECTURE "I6400"
 849 #define SUBDIRNAME      "mips64"
 850 #define ARCHCONFIG   "-DI6400 " \
 851        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 852        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 853        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 854 #define LIBNAME   "i6400"
 855 #define CORENAME  "I6400"
 856 #else
 857 #endif
 858
 859 #ifdef FORCE_P6600
 860 #define FORCE
 861 #define ARCHITECTURE    "MIPS"
 862 #define SUBARCHITECTURE "P6600"
 863 #define SUBDIRNAME      "mips64"
 864 #define ARCHCONFIG   "-DP6600 " \
 865        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 866        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 867        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 868 #define LIBNAME   "p6600"
 869 #define CORENAME  "P6600"
 870 #else
 871 #endif
 872
 873 #ifdef FORCE_P5600
 874 #define FORCE
 875 #define ARCHITECTURE    "MIPS"
 876 #define SUBARCHITECTURE "P5600"
 877 #define SUBDIRNAME      "mips"
 878 #define ARCHCONFIG   "-DP5600 " \
 879        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 880        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 881        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 882 #define LIBNAME   "p5600"
 883 #define CORENAME  "P5600"
 884 #else
 885 #endif
 886
 887 #ifdef FORCE_MIPS1004K
 888 #define FORCE
 889 #define ARCHITECTURE    "MIPS"
 890 #define SUBARCHITECTURE "MIPS1004K"
 891 #define SUBDIRNAME      "mips"
 892 #define ARCHCONFIG   "-DMIPS1004K " \
 893        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 894        "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 895        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 896 #define LIBNAME   "mips1004K"
 897 #define CORENAME  "MIPS1004K"
 898 #else
 899 #endif
 900
 901 #ifdef FORCE_MIPS24K
 902 #define FORCE
 903 #define ARCHITECTURE    "MIPS"
 904 #define SUBARCHITECTURE "MIPS24K"
 905 #define SUBDIRNAME      "mips"
 906 #define ARCHCONFIG   "-DMIPS24K " \
 907        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 908        "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
 909        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 910 #define LIBNAME   "mips24K"
 911 #define CORENAME  "MIPS24K"
 912 #else
 913 #endif
 914
 915 #ifdef FORCE_I6500
 916 #define FORCE
 917 #define ARCHITECTURE    "MIPS"
 918 #define SUBARCHITECTURE "I6500"
 919 #define SUBDIRNAME      "mips64"
 920 #define ARCHCONFIG   "-DI6500 " \
 921        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 922        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 923        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 924 #define LIBNAME   "i6500"
 925 #define CORENAME  "I6500"
 926 #else
 927 #endif
 928
 929 #ifdef FORCE_ITANIUM2
 930 #define FORCE
 931 #define ARCHITECTURE    "IA64"
 932 #define SUBARCHITECTURE "ITANIUM2"
 933 #define SUBDIRNAME      "ia64"
 934 #define ARCHCONFIG   "-DITANIUM2 " \
 935                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 936                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 937 #define LIBNAME   "itanium2"
 938 #define CORENAME  "itanium2"
 939 #endif
 940
 941 #ifdef FORCE_SPARC
 942 #define FORCE
 943 #define ARCHITECTURE    "SPARC"
 944 #define SUBARCHITECTURE "SPARC"
 945 #define SUBDIRNAME      "sparc"
 946 #define ARCHCONFIG   "-DSPARC -DV9 " \
 947                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 948                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 949 #define LIBNAME   "sparc"
 950 #define CORENAME  "sparc"
 951 #endif
 952
 953 #ifdef FORCE_SPARCV7
 954 #define FORCE
 955 #define ARCHITECTURE    "SPARC"
 956 #define SUBARCHITECTURE "SPARC"
 957 #define SUBDIRNAME      "sparc"
 958 #define ARCHCONFIG   "-DSPARC -DV7 " \
 959                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 960                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 961 #define LIBNAME   "sparcv7"
 962 #define CORENAME  "sparcv7"
 963 #endif
 964
 965 #ifdef FORCE_GENERIC
 966 #define FORCE
 967 #define ARCHITECTURE    "GENERIC"
 968 #define SUBARCHITECTURE "GENERIC"
 969 #define SUBDIRNAME      "generic"
 970 #define ARCHCONFIG   "-DGENERIC " \
 971                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 972                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 973                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 974 #define LIBNAME   "generic"
 975 #define CORENAME  "generic"
 976 #endif
 977
 978 #ifdef FORCE_ARMV7
 979 #define FORCE
 980 #define ARCHITECTURE    "ARM"
 981 #define SUBARCHITECTURE "ARMV7"
 982 #define SUBDIRNAME      "arm"
 983 #define ARCHCONFIG   "-DARMV7 " \
 984        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 985        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 986        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 987        "-DHAVE_VFPV3 -DHAVE_VFP"
 988 #define LIBNAME   "armv7"
 989 #define CORENAME  "ARMV7"
 990 #else
 991 #endif
 992
 993 #ifdef FORCE_CORTEXA9
 994 #define FORCE
 995 #define ARCHITECTURE    "ARM"
 996 #define SUBARCHITECTURE "CORTEXA9"
 997 #define SUBDIRNAME      "arm"
 998 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 999        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1000        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1001        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1002        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1003 #define LIBNAME   "cortexa9"
1004 #define CORENAME  "CORTEXA9"
1005 #else
1006 #endif
1007
1008 #ifdef FORCE_RISCV64_GENERIC
1009 #define FORCE
1010 #define ARCHITECTURE    "RISCV64"
1011 #define SUBARCHITECTURE "RISCV64_GENERIC"
1012 #define SUBDIRNAME      "riscv64"
1013 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
1014        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1015        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1016        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1017 #define LIBNAME   "riscv64_generic"
1018 #define CORENAME  "RISCV64_GENERIC"
1019 #else
1020 #endif
1021
1022 #ifdef FORCE_CORTEXA15
1023 #define FORCE
1024 #define ARCHITECTURE    "ARM"
1025 #define SUBARCHITECTURE "CORTEXA15"
1026 #define SUBDIRNAME      "arm"
1027 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
1028        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1029        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1030        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1031        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1032 #define LIBNAME   "cortexa15"
1033 #define CORENAME  "CORTEXA15"
1034 #else
1035 #endif
1036
1037 #ifdef FORCE_ARMV6
1038 #define FORCE
1039 #define ARCHITECTURE    "ARM"
1040 #define SUBARCHITECTURE "ARMV6"
1041 #define SUBDIRNAME      "arm"
1042 #define ARCHCONFIG   "-DARMV6 " \
1043        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1044        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1045        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1046        "-DHAVE_VFP"
1047 #define LIBNAME   "armv6"
1048 #define CORENAME  "ARMV6"
1049 #else
1050 #endif
1051
1052 #ifdef FORCE_ARMV5
1053 #define FORCE
1054 #define ARCHITECTURE    "ARM"
1055 #define SUBARCHITECTURE "ARMV5"
1056 #define SUBDIRNAME      "arm"
1057 #define ARCHCONFIG   "-DARMV5 " \
1058        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1059        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1060        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1061 #define LIBNAME   "armv5"
1062 #define CORENAME  "ARMV5"
1063 #else
1064 #endif
1065
1066
1067 #ifdef FORCE_ARMV8
1068 #define FORCE
1069 #define ARCHITECTURE    "ARM64"
1070 #define SUBARCHITECTURE "ARMV8"
1071 #define SUBDIRNAME      "arm64"
1072 #define ARCHCONFIG   "-DARMV8 " \
1073        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1074        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1075        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1076        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1077 #define LIBNAME   "armv8"
1078 #define CORENAME  "ARMV8"
1079 #endif
1080
1081 #ifdef FORCE_CORTEXA53
1082 #define FORCE
1083 #define ARCHITECTURE    "ARM64"
1084 #define SUBARCHITECTURE "CORTEXA53"
1085 #define SUBDIRNAME      "arm64"
1086 #define ARCHCONFIG   "-DCORTEXA53 " \
1087        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1088        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1089        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1090        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1091        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1092 #define LIBNAME   "cortexa53"
1093 #define CORENAME  "CORTEXA53"
1094 #else
1095 #endif
1096
1097 #ifdef FORCE_CORTEXA57
1098 #define FORCE
1099 #define ARCHITECTURE    "ARM64"
1100 #define SUBARCHITECTURE "CORTEXA57"
1101 #define SUBDIRNAME      "arm64"
1102 #define ARCHCONFIG   "-DCORTEXA57 " \
1103        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1104        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1105        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1106        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1107        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1108 #define LIBNAME   "cortexa57"
1109 #define CORENAME  "CORTEXA57"
1110 #else
1111 #endif
1112
1113 #ifdef FORCE_CORTEXA72
1114 #define FORCE
1115 #define ARCHITECTURE    "ARM64"
1116 #define SUBARCHITECTURE "CORTEXA72"
1117 #define SUBDIRNAME      "arm64"
1118 #define ARCHCONFIG   "-DCORTEXA72 " \
1119        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1120        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1121        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1122        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1123        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1124 #define LIBNAME   "cortexa72"
1125 #define CORENAME  "CORTEXA72"
1126 #else
1127 #endif
1128
1129 #ifdef FORCE_CORTEXA73
1130 #define FORCE
1131 #define ARCHITECTURE    "ARM64"
1132 #define SUBARCHITECTURE "CORTEXA73"
1133 #define SUBDIRNAME      "arm64"
1134 #define ARCHCONFIG   "-DCORTEXA73 " \
1135        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1136        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1137        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1138        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1139        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1140 #define LIBNAME   "cortexa73"
1141 #define CORENAME  "CORTEXA73"
1142 #else
1143 #endif
1144
1145 #ifdef FORCE_NEOVERSEN1
1146 #define FORCE
1147 #define ARCHITECTURE    "ARM64"
1148 #define SUBARCHITECTURE "NEOVERSEN1"
1149 #define SUBDIRNAME      "arm64"
1150 #define ARCHCONFIG   "-DNEOVERSEN1 " \
1151        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1152        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1153        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1154        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1155        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1156        "-march=armv8.2-a -mtune=cortex-a72"
1157 #define LIBNAME   "neoversen1"
1158 #define CORENAME  "NEOVERSEN1"
1159 #else
1160 #endif
1161
1162
1163 #ifdef FORCE_FALKOR
1164 #define FORCE
1165 #define ARCHITECTURE    "ARM64"
1166 #define SUBARCHITECTURE "FALKOR"
1167 #define SUBDIRNAME      "arm64"
1168 #define ARCHCONFIG   "-DFALKOR " \
1169        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1170        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1171        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1172        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1173        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1174 #define LIBNAME   "falkor"
1175 #define CORENAME  "FALKOR"
1176 #else
1177 #endif
1178
1179 #ifdef FORCE_THUNDERX
1180 #define FORCE
1181 #define ARCHITECTURE    "ARM64"
1182 #define SUBARCHITECTURE "THUNDERX"
1183 #define SUBDIRNAME      "arm64"
1184 #define ARCHCONFIG   "-DTHUNDERX " \
1185        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1186        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1187        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1188        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1189 #define LIBNAME   "thunderx"
1190 #define CORENAME  "THUNDERX"
1191 #else
1192 #endif
1193
1194 #ifdef FORCE_THUNDERX2T99
1195 #define ARMV8
1196 #define FORCE
1197 #define ARCHITECTURE    "ARM64"
1198 #define SUBARCHITECTURE "THUNDERX2T99"
1199 #define SUBDIRNAME      "arm64"
1200 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1201        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1202        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1203        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1204        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1205        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1206        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1207 #define LIBNAME   "thunderx2t99"
1208 #define CORENAME  "THUNDERX2T99"
1209 #else
1210 #endif
1211
1212 #ifdef FORCE_TSV110
1213 #define FORCE
1214 #define ARCHITECTURE    "ARM64"
1215 #define SUBARCHITECTURE "TSV110"
1216 #define SUBDIRNAME      "arm64"
1217 #define ARCHCONFIG   "-DTSV110 " \
1218        "-DL1_CODE_SIZE=65536  -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1219        "-DL1_DATA_SIZE=65536  -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1220        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1221        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1222        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1223 #define LIBNAME   "tsv110"
1224 #define CORENAME  "TSV110"
1225 #else
1226 #endif
1227
1228 #ifdef FORCE_EMAG8180
1229 #define ARMV8
1230 #define FORCE
1231 #define ARCHITECTURE    "ARM64"
1232 #define SUBARCHITECTURE "EMAG8180"
1233 #define SUBDIRNAME      "arm64"
1234 #define ARCHCONFIG   "-DEMAG8180 " \
1235        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1236        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1237        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1238        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1239        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1240        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1241 #define LIBNAME   "emag8180"
1242 #define CORENAME  "EMAG8180"
1243 #endif
1244
1245 #ifdef FORCE_THUNDERX3T110
1246 #define ARMV8
1247 #define FORCE
1248 #define ARCHITECTURE    "ARM64"
1249 #define SUBARCHITECTURE "THUNDERX3T110"
1250 #define SUBDIRNAME      "arm64"
1251 #define ARCHCONFIG   "-DTHUNDERX3T110 " \
1252        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1253        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1254        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1255        "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1256        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1257        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1258 #define LIBNAME   "thunderx3t110"
1259 #define CORENAME  "THUNDERX3T110"
1260 #else
1261 #endif
1262
1263 #ifdef FORCE_VORTEX
1264 #define FORCE
1265 #define ARCHITECTURE    "ARM64"
1266 #define SUBARCHITECTURE "VORTEX"
1267 #define SUBDIRNAME      "arm64"
1268 #define ARCHCONFIG   "-DVORTEX " \
1269        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1270        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1271        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1272        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1273 #define LIBNAME   "vortex"
1274 #define CORENAME  "VORTEX"
1275 #endif
1276
1277 #ifdef FORCE_ZARCH_GENERIC
1278 #define FORCE
1279 #define ARCHITECTURE    "ZARCH"
1280 #define SUBARCHITECTURE "ZARCH_GENERIC"
1281 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1282        "-DDTB_DEFAULT_ENTRIES=64"
1283 #define LIBNAME   "zarch_generic"
1284 #define CORENAME  "ZARCH_GENERIC"
1285 #endif
1286
1287 #ifdef FORCE_Z13
1288 #define FORCE
1289 #define ARCHITECTURE    "ZARCH"
1290 #define SUBARCHITECTURE "Z13"
1291 #define ARCHCONFIG   "-DZ13 " \
1292        "-DDTB_DEFAULT_ENTRIES=64"
1293 #define LIBNAME   "z13"
1294 #define CORENAME  "Z13"
1295 #endif
1296
1297 #ifdef FORCE_Z14
1298 #define FORCE
1299 #define ARCHITECTURE    "ZARCH"
1300 #define SUBARCHITECTURE "Z14"
1301 #define ARCHCONFIG   "-DZ14 " \
1302        "-DDTB_DEFAULT_ENTRIES=64"
1303 #define LIBNAME   "z14"
1304 #define CORENAME  "Z14"
1305 #endif
1306
1307 #ifdef FORCE_C910V
1308 #define FORCE
1309 #define ARCHITECTURE    "RISCV64"
1310 #define SUBARCHITECTURE "C910V"
1311 #define SUBDIRNAME      "riscv64"
1312 #define ARCHCONFIG   "-DC910V " \
1313        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1314        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1315        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1316 #define LIBNAME   "c910v"
1317 #define CORENAME  "C910V"
1318 #else
1319 #endif
1320
1321
1322 #ifndef FORCE
1323
1324 #ifdef USER_TARGET
1325 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1326 #endif
1327
1328 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1329     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1330 #ifndef POWER
1331 #define POWER
1332 #endif
1333 #define OPENBLAS_SUPPORTED
1334 #endif
1335
1336 #if defined(__zarch__) || defined(__s390x__)
1337 #define ZARCH
1338 #include "cpuid_zarch.c"
1339 #define OPENBLAS_SUPPORTED
1340 #endif
1341
1342 #ifdef INTEL_AMD
1343 #include "cpuid_x86.c"
1344 #define OPENBLAS_SUPPORTED
1345 #endif
1346
1347 #ifdef __ia64__
1348 #include "cpuid_ia64.c"
1349 #define OPENBLAS_SUPPORTED
1350 #endif
1351
1352 #ifdef __alpha
1353 #include "cpuid_alpha.c"
1354 #define OPENBLAS_SUPPORTED
1355 #endif
1356
1357 #ifdef POWER
1358 #include "cpuid_power.c"
1359 #define OPENBLAS_SUPPORTED
1360 #endif
1361
1362 #ifdef sparc
1363 #include "cpuid_sparc.c"
1364 #define OPENBLAS_SUPPORTED
1365 #endif
1366
1367 #ifdef __mips__
1368 #ifdef __mips64
1369 #include "cpuid_mips64.c"
1370 #else
1371 #include "cpuid_mips.c"
1372 #endif
1373 #define OPENBLAS_SUPPORTED
1374 #endif
1375
1376 #ifdef __riscv
1377 #include "cpuid_riscv64.c"
1378 #define OPENBLAS_SUPPORTED
1379 #endif
1380
1381 #ifdef __arm__
1382 #include "cpuid_arm.c"
1383 #define OPENBLAS_SUPPORTED
1384 #endif
1385
1386 #ifdef __aarch64__
1387 #include "cpuid_arm64.c"
1388 #define OPENBLAS_SUPPORTED
1389 #endif
1390
1391
1392 #ifndef OPENBLAS_SUPPORTED
1393 #error "This arch/CPU is not supported by OpenBLAS."
1394 #endif
1395
1396 #else
1397
1398 #endif
1399
1400 static int get_num_cores(void) {
1401
1402 #ifdef OS_WINDOWS
1403   SYSTEM_INFO sysinfo;
1404 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1405   int m[2], count;
1406   size_t len;
1407 #endif
1408
1409 #if defined(linux) || defined(__sun__)
1410   //returns the number of processors which are currently online
1411   return sysconf(_SC_NPROCESSORS_CONF);
1412
1413 #elif defined(OS_WINDOWS)
1414
1415   GetSystemInfo(&sysinfo);
1416   return sysinfo.dwNumberOfProcessors;
1417
1418 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1419   m[0] = CTL_HW;
1420   m[1] = HW_NCPU;
1421   len = sizeof(int);
1422   sysctl(m, 2, &count, &len, NULL, 0);
1423
1424   return count;
1425
1426 #elif defined(AIX)
1427   //returns the number of processors which are currently online
1428   return sysconf(_SC_NPROCESSORS_ONLN);
1429
1430 #else
1431   return 2;
1432 #endif
1433 }
1434
1435 int main(int argc, char *argv[]){
1436
1437 #ifdef FORCE
1438   char buffer[8192], *p, *q;
1439   int length;
1440 #endif
1441
1442   if (argc == 1) return 0;
1443
1444   switch (argv[1][0]) {
1445
1446   case '0' : /* for Makefile */
1447
1448 #ifdef FORCE
1449     printf("CORE=%s\n", CORENAME);
1450 #else
1451 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1452     printf("CORE=%s\n", get_corename());
1453 #endif
1454 #endif
1455
1456 #ifdef FORCE
1457     printf("LIBCORE=%s\n", LIBNAME);
1458 #else
1459     printf("LIBCORE=");
1460     get_libname();
1461     printf("\n");
1462 #endif
1463
1464     printf("NUM_CORES=%d\n", get_num_cores());
1465
1466 #if defined(__arm__)
1467 #if !defined(FORCE)
1468     fprintf(stderr,"get features!\n");
1469         get_features();
1470 #else
1471     fprintf(stderr,"split archconfig!\n");
1472     sprintf(buffer, "%s", ARCHCONFIG);
1473
1474     p = &buffer[0];
1475
1476     while (*p) {
1477       if ((*p == '-') && (*(p + 1) == 'D')) {
1478         p += 2;
1479         if (*p != 'H') {
1480                 while( (*p != ' ') && (*p != '-') && (*p != '\0') && (*p != '\n')) {p++; }
1481                 if (*p == '-') continue;
1482         }
1483         while ((*p != ' ') && (*p != '\0')) {
1484
1485           if (*p == '=') {
1486             printf("=");
1487             p ++;
1488             while ((*p != ' ') && (*p != '\0')) {
1489               printf("%c", *p);
1490               p ++;
1491             }
1492           } else {
1493             printf("%c", *p);
1494             p ++;
1495             if ((*p == ' ') || (*p =='\0')) printf("=1\n");
1496           }
1497         }
1498       } else p ++;
1499     }
1500 #endif
1501 #endif
1502
1503
1504 #ifdef INTEL_AMD
1505 #ifndef FORCE
1506     get_sse();
1507 #else
1508
1509     sprintf(buffer, "%s", ARCHCONFIG);
1510
1511     p = &buffer[0];
1512
1513     while (*p) {
1514       if ((*p == '-') && (*(p + 1) == 'D')) {
1515         p += 2;
1516
1517         while ((*p != ' ') && (*p != '\0')) {
1518
1519           if (*p == '=') {
1520             printf("=");
1521             p ++;
1522             while ((*p != ' ') && (*p != '\0')) {
1523               printf("%c", *p);
1524               p ++;
1525             }
1526           } else {
1527             printf("%c", *p);
1528             p ++;
1529             if ((*p == ' ') || (*p =='\0')) printf("=1");
1530           }
1531         }
1532
1533         printf("\n");
1534       } else p ++;
1535     }
1536 #endif
1537 #endif
1538
1539 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1540 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1541 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1542 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1543 #endif
1544 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1545 printf("ELF_VERSION=2\n");
1546 #endif
1547
1548 #ifdef MAKE_NB_JOBS
1549   #if MAKE_NB_JOBS > 0
1550     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1551   #else
1552     // Let make use parent -j argument or -j1 if there
1553     // is no make parent
1554   #endif
1555 #elif NO_PARALLEL_MAKE==1
1556     printf("MAKE += -j 1\n");
1557 #else
1558     printf("MAKE += -j %d\n", get_num_cores());
1559 #endif
1560
1561     break;
1562
1563   case '1' : /* For config.h */
1564 #ifdef FORCE
1565     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1566
1567     p = &buffer[0];
1568     while (*p) {
1569       if ((*p == '-') && (*(p + 1) == 'D')) {
1570         p += 2;
1571         printf("#define ");
1572
1573         while ((*p != ' ') && (*p != '\0')) {
1574
1575           if (*p == '=') {
1576             printf(" ");
1577             p ++;
1578             while ((*p != ' ') && (*p != '\0')) {
1579               printf("%c", *p);
1580               p ++;
1581             }
1582           } else {
1583             if (*p != '\n')
1584             printf("%c", *p);
1585             p ++;
1586           }
1587         }
1588
1589         printf("\n");
1590       } else p ++;
1591     }
1592 #else
1593     get_cpuconfig();
1594 #endif
1595
1596 #ifdef FORCE
1597     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1598 #else
1599 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1600     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1601 #endif
1602 #endif
1603
1604  break;
1605
1606   case '2' : /* SMP */
1607     if (get_num_cores() > 1) printf("SMP=1\n");
1608     break;
1609   }
1610
1611   fflush(stdout);
1612
1613   return 0;
1614 }
1615