getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P6600          */
 136 /* #define FORCE_P5600          */
 137 /* #define FORCE_I6500          */
 138 /* #define FORCE_ITANIUM2       */
 139 /* #define FORCE_SPARC          */
 140 /* #define FORCE_SPARCV7        */
 141 /* #define FORCE_ZARCH_GENERIC  */
 142 /* #define FORCE_Z13            */
 143 /* #define FORCE_GENERIC        */
 144
 145 #ifdef FORCE_P2
 146 #define FORCE
 147 #define FORCE_INTEL
 148 #define ARCHITECTURE    "X86"
 149 #define SUBARCHITECTURE "PENTIUM2"
 150 #define ARCHCONFIG   "-DPENTIUM2 " \
 151                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 152                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 153                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 154                      "-DHAVE_CMOV -DHAVE_MMX"
 155 #define LIBNAME   "p2"
 156 #define CORENAME  "P5"
 157 #endif
 158
 159 #ifdef FORCE_KATMAI
 160 #define FORCE
 161 #define FORCE_INTEL
 162 #define ARCHITECTURE    "X86"
 163 #define SUBARCHITECTURE "PENTIUM3"
 164 #define ARCHCONFIG   "-DPENTIUM3 " \
 165                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 166                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 167                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 168                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 169 #define LIBNAME   "katmai"
 170 #define CORENAME  "KATMAI"
 171 #endif
 172
 173 #ifdef FORCE_COPPERMINE
 174 #define FORCE
 175 #define FORCE_INTEL
 176 #define ARCHITECTURE    "X86"
 177 #define SUBARCHITECTURE "PENTIUM3"
 178 #define ARCHCONFIG   "-DPENTIUM3 " \
 179                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 180                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 181                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 182                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 183 #define LIBNAME   "coppermine"
 184 #define CORENAME  "COPPERMINE"
 185 #endif
 186
 187 #ifdef FORCE_NORTHWOOD
 188 #define FORCE
 189 #define FORCE_INTEL
 190 #define ARCHITECTURE    "X86"
 191 #define SUBARCHITECTURE "PENTIUM4"
 192 #define ARCHCONFIG   "-DPENTIUM4 " \
 193                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 194                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 195                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 196                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 197 #define LIBNAME   "northwood"
 198 #define CORENAME  "NORTHWOOD"
 199 #endif
 200
 201 #ifdef FORCE_PRESCOTT
 202 #define FORCE
 203 #define FORCE_INTEL
 204 #define ARCHITECTURE    "X86"
 205 #define SUBARCHITECTURE "PENTIUM4"
 206 #define ARCHCONFIG   "-DPENTIUM4 " \
 207                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 208                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 209                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 210                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 211 #define LIBNAME   "prescott"
 212 #define CORENAME  "PRESCOTT"
 213 #endif
 214
 215 #ifdef FORCE_BANIAS
 216 #define FORCE
 217 #define FORCE_INTEL
 218 #define ARCHITECTURE    "X86"
 219 #define SUBARCHITECTURE "BANIAS"
 220 #define ARCHCONFIG   "-DPENTIUMM " \
 221                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 222                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 223                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 224                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 225 #define LIBNAME   "banias"
 226 #define CORENAME  "BANIAS"
 227 #endif
 228
 229 #ifdef FORCE_YONAH
 230 #define FORCE
 231 #define FORCE_INTEL
 232 #define ARCHITECTURE    "X86"
 233 #define SUBARCHITECTURE "YONAH"
 234 #define ARCHCONFIG   "-DPENTIUMM " \
 235                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 236                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 237                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 238                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 239 #define LIBNAME   "yonah"
 240 #define CORENAME  "YONAH"
 241 #endif
 242
 243 #ifdef FORCE_CORE2
 244 #define FORCE
 245 #define FORCE_INTEL
 246 #define ARCHITECTURE    "X86"
 247 #define SUBARCHITECTURE "CONRORE"
 248 #define ARCHCONFIG   "-DCORE2 " \
 249                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 250                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 251                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 252                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 253 #define LIBNAME   "core2"
 254 #define CORENAME  "CORE2"
 255 #endif
 256
 257 #ifdef FORCE_PENRYN
 258 #define FORCE
 259 #define FORCE_INTEL
 260 #define ARCHITECTURE    "X86"
 261 #define SUBARCHITECTURE "PENRYN"
 262 #define ARCHCONFIG   "-DPENRYN " \
 263                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 264                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 265                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 266                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 267 #define LIBNAME   "penryn"
 268 #define CORENAME  "PENRYN"
 269 #endif
 270
 271 #ifdef FORCE_DUNNINGTON
 272 #define FORCE
 273 #define FORCE_INTEL
 274 #define ARCHITECTURE    "X86"
 275 #define SUBARCHITECTURE "DUNNINGTON"
 276 #define ARCHCONFIG   "-DDUNNINGTON " \
 277                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 278                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 279                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 280                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 281                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 282 #define LIBNAME   "dunnington"
 283 #define CORENAME  "DUNNINGTON"
 284 #endif
 285
 286 #ifdef FORCE_NEHALEM
 287 #define FORCE
 288 #define FORCE_INTEL
 289 #define ARCHITECTURE    "X86"
 290 #define SUBARCHITECTURE "NEHALEM"
 291 #define ARCHCONFIG   "-DNEHALEM " \
 292                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 293                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 294                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 295                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 296 #define LIBNAME   "nehalem"
 297 #define CORENAME  "NEHALEM"
 298 #endif
 299
 300 #ifdef FORCE_SANDYBRIDGE
 301 #define FORCE
 302 #define FORCE_INTEL
 303 #define ARCHITECTURE    "X86"
 304 #define SUBARCHITECTURE "SANDYBRIDGE"
 305 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 306                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 307                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 308                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 309                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 310 #define LIBNAME   "sandybridge"
 311 #define CORENAME  "SANDYBRIDGE"
 312 #endif
 313
 314 #ifdef FORCE_HASWELL
 315 #define FORCE
 316 #define FORCE_INTEL
 317 #define ARCHITECTURE    "X86"
 318 #define SUBARCHITECTURE "HASWELL"
 319 #define ARCHCONFIG   "-DHASWELL " \
 320                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 321                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 322                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 323                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 324                      "-DFMA3"
 325 #define LIBNAME   "haswell"
 326 #define CORENAME  "HASWELL"
 327 #endif
 328
 329 #ifdef FORCE_ATOM
 330 #define FORCE
 331 #define FORCE_INTEL
 332 #define ARCHITECTURE    "X86"
 333 #define SUBARCHITECTURE "ATOM"
 334 #define ARCHCONFIG   "-DATOM " \
 335                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 336                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 337                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 338                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 339 #define LIBNAME   "atom"
 340 #define CORENAME  "ATOM"
 341 #endif
 342
 343 #ifdef FORCE_ATHLON
 344 #define FORCE
 345 #define FORCE_INTEL
 346 #define ARCHITECTURE    "X86"
 347 #define SUBARCHITECTURE "ATHLON"
 348 #define ARCHCONFIG   "-DATHLON " \
 349                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 350                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 351                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 352                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 353 #define LIBNAME   "athlon"
 354 #define CORENAME  "ATHLON"
 355 #endif
 356
 357 #ifdef FORCE_OPTERON
 358 #define FORCE
 359 #define FORCE_INTEL
 360 #define ARCHITECTURE    "X86"
 361 #define SUBARCHITECTURE "OPTERON"
 362 #define ARCHCONFIG   "-DOPTERON " \
 363                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 364                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 365                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 366                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 367 #define LIBNAME   "opteron"
 368 #define CORENAME  "OPTERON"
 369 #endif
 370
 371 #ifdef FORCE_OPTERON_SSE3
 372 #define FORCE
 373 #define FORCE_INTEL
 374 #define ARCHITECTURE    "X86"
 375 #define SUBARCHITECTURE "OPTERON"
 376 #define ARCHCONFIG   "-DOPTERON " \
 377                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 378                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 379                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 380                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 381 #define LIBNAME   "opteron"
 382 #define CORENAME  "OPTERON"
 383 #endif
 384
 385 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 386 #define FORCE
 387 #define FORCE_INTEL
 388 #define ARCHITECTURE    "X86"
 389 #define SUBARCHITECTURE "BARCELONA"
 390 #define ARCHCONFIG   "-DBARCELONA " \
 391                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 392                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 393                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 394                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 395                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 396 #define LIBNAME   "barcelona"
 397 #define CORENAME  "BARCELONA"
 398 #endif
 399
 400 #if defined(FORCE_BOBCAT)
 401 #define FORCE
 402 #define FORCE_INTEL
 403 #define ARCHITECTURE    "X86"
 404 #define SUBARCHITECTURE "BOBCAT"
 405 #define ARCHCONFIG   "-DBOBCAT " \
 406                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 407                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 408                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 409                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 410                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 411 #define LIBNAME   "bobcat"
 412 #define CORENAME  "BOBCAT"
 413 #endif
 414
 415 #if defined (FORCE_BULLDOZER)
 416 #define FORCE
 417 #define FORCE_INTEL
 418 #define ARCHITECTURE    "X86"
 419 #define SUBARCHITECTURE "BULLDOZER"
 420 #define ARCHCONFIG   "-DBULLDOZER " \
 421                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 422                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 423                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 424                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 425                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 426                      "-DHAVE_AVX -DHAVE_FMA4"
 427 #define LIBNAME   "bulldozer"
 428 #define CORENAME  "BULLDOZER"
 429 #endif
 430
 431 #if defined (FORCE_PILEDRIVER)
 432 #define FORCE
 433 #define FORCE_INTEL
 434 #define ARCHITECTURE    "X86"
 435 #define SUBARCHITECTURE "PILEDRIVER"
 436 #define ARCHCONFIG   "-DPILEDRIVER " \
 437                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 438                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 439                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 440                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 441                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 442                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 443 #define LIBNAME   "piledriver"
 444 #define CORENAME  "PILEDRIVER"
 445 #endif
 446
 447 #if defined (FORCE_STEAMROLLER)
 448 #define FORCE
 449 #define FORCE_INTEL
 450 #define ARCHITECTURE    "X86"
 451 #define SUBARCHITECTURE "STEAMROLLER"
 452 #define ARCHCONFIG   "-DSTEAMROLLER " \
 453                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 454                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 455                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 456                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 457                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 458                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 459 #define LIBNAME   "steamroller"
 460 #define CORENAME  "STEAMROLLER"
 461 #endif
 462
 463 #if defined (FORCE_EXCAVATOR)
 464 #define FORCE
 465 #define FORCE_INTEL
 466 #define ARCHITECTURE    "X86"
 467 #define SUBARCHITECTURE "EXCAVATOR"
 468 #define ARCHCONFIG   "-DEXCAVATOR " \
 469                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 470                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 471                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 472                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 473                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 474                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 475 #define LIBNAME   "excavator"
 476 #define CORENAME  "EXCAVATOR"
 477 #endif
 478
 479 #if defined (FORCE_ZEN)
 480 #define FORCE
 481 #define FORCE_INTEL
 482 #define ARCHITECTURE    "X86"
 483 #define SUBARCHITECTURE "ZEN"
 484 #define ARCHCONFIG   "-DZEN " \
 485                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 486                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 487                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 488                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 489                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 490                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 491                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 492                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 493                      "-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
 494 #define LIBNAME   "zen"
 495 #define CORENAME  "ZEN"
 496 #endif
 497
 498
 499 #ifdef FORCE_SSE_GENERIC
 500 #define FORCE
 501 #define FORCE_INTEL
 502 #define ARCHITECTURE    "X86"
 503 #define SUBARCHITECTURE "GENERIC"
 504 #define ARCHCONFIG   "-DGENERIC " \
 505                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 506                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 507                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 508                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 509 #define LIBNAME   "generic"
 510 #define CORENAME  "GENERIC"
 511 #endif
 512
 513 #ifdef FORCE_VIAC3
 514 #define FORCE
 515 #define FORCE_INTEL
 516 #define ARCHITECTURE    "X86"
 517 #define SUBARCHITECTURE "VIAC3"
 518 #define ARCHCONFIG   "-DVIAC3 " \
 519                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 520                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 521                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 522                      "-DHAVE_MMX -DHAVE_SSE "
 523 #define LIBNAME   "viac3"
 524 #define CORENAME  "VIAC3"
 525 #endif
 526
 527 #ifdef FORCE_NANO
 528 #define FORCE
 529 #define FORCE_INTEL
 530 #define ARCHITECTURE    "X86"
 531 #define SUBARCHITECTURE "NANO"
 532 #define ARCHCONFIG   "-DNANO " \
 533                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 534                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 535                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 536                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 537 #define LIBNAME   "nano"
 538 #define CORENAME  "NANO"
 539 #endif
 540
 541 #ifdef FORCE_POWER3
 542 #define FORCE
 543 #define ARCHITECTURE    "POWER"
 544 #define SUBARCHITECTURE "POWER3"
 545 #define SUBDIRNAME      "power"
 546 #define ARCHCONFIG   "-DPOWER3 " \
 547                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 548                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 549                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 550 #define LIBNAME   "power3"
 551 #define CORENAME  "POWER3"
 552 #endif
 553
 554 #ifdef FORCE_POWER4
 555 #define FORCE
 556 #define ARCHITECTURE    "POWER"
 557 #define SUBARCHITECTURE "POWER4"
 558 #define SUBDIRNAME      "power"
 559 #define ARCHCONFIG   "-DPOWER4 " \
 560                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 561                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 562                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 563 #define LIBNAME   "power4"
 564 #define CORENAME  "POWER4"
 565 #endif
 566
 567 #ifdef FORCE_POWER5
 568 #define FORCE
 569 #define ARCHITECTURE    "POWER"
 570 #define SUBARCHITECTURE "POWER5"
 571 #define SUBDIRNAME      "power"
 572 #define ARCHCONFIG   "-DPOWER5 " \
 573                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 574                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 575                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 576 #define LIBNAME   "power5"
 577 #define CORENAME  "POWER5"
 578 #endif
 579
 580 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 581 #define FORCE
 582 #define ARCHITECTURE    "POWER"
 583 #define SUBARCHITECTURE "POWER6"
 584 #define SUBDIRNAME      "power"
 585 #define ARCHCONFIG   "-DPOWER6 " \
 586                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 587                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 588                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 589 #define LIBNAME   "power6"
 590 #define CORENAME  "POWER6"
 591 #endif
 592
 593 #if defined(FORCE_POWER8)
 594 #define FORCE
 595 #define ARCHITECTURE    "POWER"
 596 #define SUBARCHITECTURE "POWER8"
 597 #define SUBDIRNAME      "power"
 598 #define ARCHCONFIG   "-DPOWER8 " \
 599                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 600                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 601                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 602 #define LIBNAME   "power8"
 603 #define CORENAME  "POWER8"
 604 #endif
 605
 606
 607 #ifdef FORCE_PPCG4
 608 #define FORCE
 609 #define ARCHITECTURE    "POWER"
 610 #define SUBARCHITECTURE "PPCG4"
 611 #define SUBDIRNAME      "power"
 612 #define ARCHCONFIG   "-DPPCG4 " \
 613                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 614                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 615                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 616 #define LIBNAME   "ppcg4"
 617 #define CORENAME  "PPCG4"
 618 #endif
 619
 620 #ifdef FORCE_PPC970
 621 #define FORCE
 622 #define ARCHITECTURE    "POWER"
 623 #define SUBARCHITECTURE "PPC970"
 624 #define SUBDIRNAME      "power"
 625 #define ARCHCONFIG   "-DPPC970 " \
 626                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 627                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 628                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 629 #define LIBNAME   "ppc970"
 630 #define CORENAME  "PPC970"
 631 #endif
 632
 633 #ifdef FORCE_PPC970MP
 634 #define FORCE
 635 #define ARCHITECTURE    "POWER"
 636 #define SUBARCHITECTURE "PPC970"
 637 #define SUBDIRNAME      "power"
 638 #define ARCHCONFIG   "-DPPC970 " \
 639                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 640                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 641                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 642 #define LIBNAME   "ppc970mp"
 643 #define CORENAME  "PPC970"
 644 #endif
 645
 646 #ifdef FORCE_PPC440
 647 #define FORCE
 648 #define ARCHITECTURE    "POWER"
 649 #define SUBARCHITECTURE "PPC440"
 650 #define SUBDIRNAME      "power"
 651 #define ARCHCONFIG   "-DPPC440 " \
 652                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 653                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 654                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 655 #define LIBNAME   "ppc440"
 656 #define CORENAME  "PPC440"
 657 #endif
 658
 659 #ifdef FORCE_PPC440FP2
 660 #define FORCE
 661 #define ARCHITECTURE    "POWER"
 662 #define SUBARCHITECTURE "PPC440FP2"
 663 #define SUBDIRNAME      "power"
 664 #define ARCHCONFIG   "-DPPC440FP2 " \
 665                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 666                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 667                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 668 #define LIBNAME   "ppc440FP2"
 669 #define CORENAME  "PPC440FP2"
 670 #endif
 671
 672 #ifdef FORCE_CELL
 673 #define FORCE
 674 #define ARCHITECTURE    "POWER"
 675 #define SUBARCHITECTURE "CELL"
 676 #define SUBDIRNAME      "power"
 677 #define ARCHCONFIG   "-DCELL " \
 678                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 679                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 680                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 681 #define LIBNAME   "cell"
 682 #define CORENAME  "CELL"
 683 #endif
 684
 685 #ifdef FORCE_SICORTEX
 686 #define FORCE
 687 #define ARCHITECTURE    "MIPS"
 688 #define SUBARCHITECTURE "SICORTEX"
 689 #define SUBDIRNAME      "mips"
 690 #define ARCHCONFIG   "-DSICORTEX " \
 691                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 692                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 693                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 694 #define LIBNAME   "mips"
 695 #define CORENAME  "sicortex"
 696 #endif
 697
 698
 699 #ifdef FORCE_LOONGSON3A
 700 #define FORCE
 701 #define ARCHITECTURE    "MIPS"
 702 #define SUBARCHITECTURE "LOONGSON3A"
 703 #define SUBDIRNAME      "mips64"
 704 #define ARCHCONFIG   "-DLOONGSON3A " \
 705        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 706        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 707        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 708 #define LIBNAME   "loongson3a"
 709 #define CORENAME  "LOONGSON3A"
 710 #else
 711 #endif
 712
 713 #ifdef FORCE_LOONGSON3B
 714 #define FORCE
 715 #define ARCHITECTURE    "MIPS"
 716 #define SUBARCHITECTURE "LOONGSON3B"
 717 #define SUBDIRNAME      "mips64"
 718 #define ARCHCONFIG   "-DLOONGSON3B " \
 719        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 720        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 721        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 722 #define LIBNAME   "loongson3b"
 723 #define CORENAME  "LOONGSON3B"
 724 #else
 725 #endif
 726
 727 #ifdef FORCE_I6400
 728 #define FORCE
 729 #define ARCHITECTURE    "MIPS"
 730 #define SUBARCHITECTURE "I6400"
 731 #define SUBDIRNAME      "mips64"
 732 #define ARCHCONFIG   "-DI6400 " \
 733        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 734        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 735        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 736 #define LIBNAME   "i6400"
 737 #define CORENAME  "I6400"
 738 #else
 739 #endif
 740
 741 #ifdef FORCE_P6600
 742 #define FORCE
 743 #define ARCHITECTURE    "MIPS"
 744 #define SUBARCHITECTURE "P6600"
 745 #define SUBDIRNAME      "mips64"
 746 #define ARCHCONFIG   "-DP6600 " \
 747        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 748        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 749        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 750 #define LIBNAME   "p6600"
 751 #define CORENAME  "P6600"
 752 #else
 753 #endif
 754
 755 #ifdef FORCE_P5600
 756 #define FORCE
 757 #define ARCHITECTURE    "MIPS"
 758 #define SUBARCHITECTURE "P5600"
 759 #define SUBDIRNAME      "mips"
 760 #define ARCHCONFIG   "-DP5600 " \
 761        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 762        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 763        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 764 #define LIBNAME   "p5600"
 765 #define CORENAME  "P5600"
 766 #else
 767 #endif
 768
 769 #ifdef FORCE_I6500
 770 #define FORCE
 771 #define ARCHITECTURE    "MIPS"
 772 #define SUBARCHITECTURE "I6500"
 773 #define SUBDIRNAME      "mips64"
 774 #define ARCHCONFIG   "-DI6500 " \
 775        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 776        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 777        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 778 #define LIBNAME   "i6500"
 779 #define CORENAME  "I6500"
 780 #else
 781 #endif
 782
 783 #ifdef FORCE_ITANIUM2
 784 #define FORCE
 785 #define ARCHITECTURE    "IA64"
 786 #define SUBARCHITECTURE "ITANIUM2"
 787 #define SUBDIRNAME      "ia64"
 788 #define ARCHCONFIG   "-DITANIUM2 " \
 789                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 790                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 791 #define LIBNAME   "itanium2"
 792 #define CORENAME  "itanium2"
 793 #endif
 794
 795 #ifdef FORCE_SPARC
 796 #define FORCE
 797 #define ARCHITECTURE    "SPARC"
 798 #define SUBARCHITECTURE "SPARC"
 799 #define SUBDIRNAME      "sparc"
 800 #define ARCHCONFIG   "-DSPARC -DV9 " \
 801                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 802                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 803 #define LIBNAME   "sparc"
 804 #define CORENAME  "sparc"
 805 #endif
 806
 807 #ifdef FORCE_SPARCV7
 808 #define FORCE
 809 #define ARCHITECTURE    "SPARC"
 810 #define SUBARCHITECTURE "SPARC"
 811 #define SUBDIRNAME      "sparc"
 812 #define ARCHCONFIG   "-DSPARC -DV7 " \
 813                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 814                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 815 #define LIBNAME   "sparcv7"
 816 #define CORENAME  "sparcv7"
 817 #endif
 818
 819 #ifdef FORCE_GENERIC
 820 #define FORCE
 821 #define ARCHITECTURE    "GENERIC"
 822 #define SUBARCHITECTURE "GENERIC"
 823 #define SUBDIRNAME      "generic"
 824 #define ARCHCONFIG   "-DGENERIC " \
 825                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 826                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 827                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 828 #define LIBNAME   "generic"
 829 #define CORENAME  "generic"
 830 #endif
 831
 832 #ifdef FORCE_ARMV7
 833 #define FORCE
 834 #define ARCHITECTURE    "ARM"
 835 #define SUBARCHITECTURE "ARMV7"
 836 #define SUBDIRNAME      "arm"
 837 #define ARCHCONFIG   "-DARMV7 " \
 838        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 839        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 840        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 841        "-DHAVE_VFPV3 -DHAVE_VFP"
 842 #define LIBNAME   "armv7"
 843 #define CORENAME  "ARMV7"
 844 #else
 845 #endif
 846
 847 #ifdef FORCE_CORTEXA9
 848 #define FORCE
 849 #define ARCHITECTURE    "ARM"
 850 #define SUBARCHITECTURE "CORTEXA9"
 851 #define SUBDIRNAME      "arm"
 852 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 853        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 854        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 855        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 856        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 857 #define LIBNAME   "cortexa9"
 858 #define CORENAME  "CORTEXA9"
 859 #else
 860 #endif
 861
 862 #ifdef FORCE_CORTEXA15
 863 #define FORCE
 864 #define ARCHITECTURE    "ARM"
 865 #define SUBARCHITECTURE "CORTEXA15"
 866 #define SUBDIRNAME      "arm"
 867 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 868        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 869        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 870        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 871        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 872 #define LIBNAME   "cortexa15"
 873 #define CORENAME  "CORTEXA15"
 874 #else
 875 #endif
 876
 877 #ifdef FORCE_ARMV6
 878 #define FORCE
 879 #define ARCHITECTURE    "ARM"
 880 #define SUBARCHITECTURE "ARMV6"
 881 #define SUBDIRNAME      "arm"
 882 #define ARCHCONFIG   "-DARMV6 " \
 883        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 884        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 885        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 886        "-DHAVE_VFP"
 887 #define LIBNAME   "armv6"
 888 #define CORENAME  "ARMV6"
 889 #else
 890 #endif
 891
 892 #ifdef FORCE_ARMV5
 893 #define FORCE
 894 #define ARCHITECTURE    "ARM"
 895 #define SUBARCHITECTURE "ARMV5"
 896 #define SUBDIRNAME      "arm"
 897 #define ARCHCONFIG   "-DARMV5 " \
 898        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 899        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 900        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 901 #define LIBNAME   "armv5"
 902 #define CORENAME  "ARMV5"
 903 #else
 904 #endif
 905
 906
 907 #ifdef FORCE_ARMV8
 908 #define FORCE
 909 #define ARCHITECTURE    "ARM64"
 910 #define SUBARCHITECTURE "ARMV8"
 911 #define SUBDIRNAME      "arm64"
 912 #define ARCHCONFIG   "-DARMV8 " \
 913        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 914        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 915        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 916 #define LIBNAME   "armv8"
 917 #define CORENAME  "ARMV8"
 918 #endif
 919
 920 #ifdef FORCE_CORTEXA57
 921 #define FORCE
 922 #define ARCHITECTURE    "ARM64"
 923 #define SUBARCHITECTURE "CORTEXA57"
 924 #define SUBDIRNAME      "arm64"
 925 #define ARCHCONFIG   "-DCORTEXA57 " \
 926        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 927        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 928        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 929        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 930        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 931 #define LIBNAME   "cortexa57"
 932 #define CORENAME  "CORTEXA57"
 933 #else
 934 #endif
 935
 936 #ifdef FORCE_VULCAN
 937 #define FORCE
 938 #define ARCHITECTURE    "ARM64"
 939 #define SUBARCHITECTURE "VULCAN"
 940 #define SUBDIRNAME      "arm64"
 941 #define ARCHCONFIG   "-DVULCAN " \
 942        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 943        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 944        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 945        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 946        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 947        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 948 #define LIBNAME   "vulcan"
 949 #define CORENAME  "VULCAN"
 950 #else
 951 #endif
 952
 953 #ifdef FORCE_THUNDERX
 954 #define FORCE
 955 #define ARCHITECTURE    "ARM64"
 956 #define SUBARCHITECTURE "THUNDERX"
 957 #define SUBDIRNAME      "arm64"
 958 #define ARCHCONFIG   "-DTHUNDERX " \
 959        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 960        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
 961        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 "
 962 #define LIBNAME   "thunderx"
 963 #define CORENAME  "THUNDERX"
 964 #else
 965 #endif
 966
 967 #ifdef FORCE_THUNDERX2T99
 968 #define FORCE
 969 #define ARCHITECTURE    "ARM64"
 970 #define SUBARCHITECTURE "THUNDERX2T99"
 971 #define SUBDIRNAME      "arm64"
 972 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
 973        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 974        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 975        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 976        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 977        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 978        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 979 #define LIBNAME   "thunderx2t99"
 980 #define CORENAME  "THUNDERX2T99"
 981 #else
 982 #endif
 983
 984 #ifdef FORCE_ZARCH_GENERIC
 985 #define FORCE
 986 #define ARCHITECTURE    "ZARCH"
 987 #define SUBARCHITECTURE "ZARCH_GENERIC"
 988 #define ARCHCONFIG   "-DZARCH_GENERIC " \
 989        "-DDTB_DEFAULT_ENTRIES=64"
 990 #define LIBNAME   "zarch_generic"
 991 #define CORENAME  "ZARCH_GENERIC"
 992 #endif
 993
 994 #ifdef FORCE_Z13
 995 #define FORCE
 996 #define ARCHITECTURE    "ZARCH"
 997 #define SUBARCHITECTURE "Z13"
 998 #define ARCHCONFIG   "-DZ13 " \
 999        "-DDTB_DEFAULT_ENTRIES=64"
1000 #define LIBNAME   "z13"
1001 #define CORENAME  "Z13"
1002 #endif
1003
1004 #ifndef FORCE
1005
1006 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1007     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1008 #ifndef POWER
1009 #define POWER
1010 #endif
1011 #define OPENBLAS_SUPPORTED
1012 #endif
1013
1014 #if defined(__zarch__) || defined(__s390x__)
1015 #define ZARCH
1016 #include "cpuid_zarch.c"
1017 #define OPENBLAS_SUPPORTED
1018 #endif
1019
1020 #ifdef INTEL_AMD
1021 #include "cpuid_x86.c"
1022 #define OPENBLAS_SUPPORTED
1023 #endif
1024
1025 #ifdef __ia64__
1026 #include "cpuid_ia64.c"
1027 #define OPENBLAS_SUPPORTED
1028 #endif
1029
1030 #ifdef __alpha
1031 #include "cpuid_alpha.c"
1032 #define OPENBLAS_SUPPORTED
1033 #endif
1034
1035 #ifdef POWER
1036 #include "cpuid_power.c"
1037 #define OPENBLAS_SUPPORTED
1038 #endif
1039
1040 #ifdef sparc
1041 #include "cpuid_sparc.c"
1042 #define OPENBLAS_SUPPORTED
1043 #endif
1044
1045 #ifdef __mips__
1046 #ifdef __mips64
1047 #include "cpuid_mips64.c"
1048 #else
1049 #include "cpuid_mips.c"
1050 #endif
1051 #define OPENBLAS_SUPPORTED
1052 #endif
1053
1054 #ifdef __arm__
1055 #include "cpuid_arm.c"
1056 #define OPENBLAS_SUPPORTED
1057 #endif
1058
1059 #ifdef __aarch64__
1060 #include "cpuid_arm64.c"
1061 #define OPENBLAS_SUPPORTED
1062 #endif
1063
1064
1065 #ifndef OPENBLAS_SUPPORTED
1066 #error "This arch/CPU is not supported by OpenBLAS."
1067 #endif
1068
1069 #else
1070
1071 #endif
1072
1073 static int get_num_cores(void) {
1074
1075 #ifdef OS_WINDOWS
1076   SYSTEM_INFO sysinfo;
1077 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1078   int m[2], count;
1079   size_t len;
1080 #endif
1081
1082 #if defined(linux) || defined(__sun__)
1083   //returns the number of processors which are currently online
1084   return sysconf(_SC_NPROCESSORS_CONF);
1085
1086 #elif defined(OS_WINDOWS)
1087
1088   GetSystemInfo(&sysinfo);
1089   return sysinfo.dwNumberOfProcessors;
1090
1091 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1092   m[0] = CTL_HW;
1093   m[1] = HW_NCPU;
1094   len = sizeof(int);
1095   sysctl(m, 2, &count, &len, NULL, 0);
1096
1097   return count;
1098 #else
1099   return 2;
1100 #endif
1101 }
1102
1103 int main(int argc, char *argv[]){
1104
1105 #ifdef FORCE
1106   char buffer[8192], *p, *q;
1107   int length;
1108 #endif
1109
1110   if (argc == 1) return 0;
1111
1112   switch (argv[1][0]) {
1113
1114   case '0' : /* for Makefile */
1115
1116 #ifdef FORCE
1117     printf("CORE=%s\n", CORENAME);
1118 #else
1119 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1120     printf("CORE=%s\n", get_corename());
1121 #endif
1122 #endif
1123
1124 #ifdef FORCE
1125     printf("LIBCORE=%s\n", LIBNAME);
1126 #else
1127     printf("LIBCORE=");
1128     get_libname();
1129     printf("\n");
1130 #endif
1131
1132     printf("NUM_CORES=%d\n", get_num_cores());
1133
1134 #if defined(__arm__) && !defined(FORCE)
1135         get_features();
1136 #endif
1137
1138
1139 #ifdef INTEL_AMD
1140 #ifndef FORCE
1141     get_sse();
1142 #else
1143
1144     sprintf(buffer, "%s", ARCHCONFIG);
1145
1146     p = &buffer[0];
1147
1148     while (*p) {
1149       if ((*p == '-') && (*(p + 1) == 'D')) {
1150         p += 2;
1151
1152         while ((*p != ' ') && (*p != '\0')) {
1153
1154           if (*p == '=') {
1155             printf("=");
1156             p ++;
1157             while ((*p != ' ') && (*p != '\0')) {
1158               printf("%c", *p);
1159               p ++;
1160             }
1161           } else {
1162             printf("%c", *p);
1163             p ++;
1164             if ((*p == ' ') || (*p =='\0')) printf("=1");
1165           }
1166         }
1167
1168         printf("\n");
1169       } else p ++;
1170     }
1171 #endif
1172 #endif
1173
1174 #ifdef MAKE_NB_JOBS
1175   #if MAKE_NB_JOBS > 0
1176     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1177   #else
1178     // Let make use parent -j argument or -j1 if there
1179     // is no make parent
1180   #endif
1181 #elif NO_PARALLEL_MAKE==1
1182     printf("MAKE += -j 1\n");
1183 #else
1184 #ifndef OS_WINDOWS
1185     printf("MAKE += -j %d\n", get_num_cores());
1186 #endif
1187 #endif
1188
1189     break;
1190
1191   case '1' : /* For config.h */
1192 #ifdef FORCE
1193     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1194
1195     p = &buffer[0];
1196     while (*p) {
1197       if ((*p == '-') && (*(p + 1) == 'D')) {
1198         p += 2;
1199         printf("#define ");
1200
1201         while ((*p != ' ') && (*p != '\0')) {
1202
1203           if (*p == '=') {
1204             printf(" ");
1205             p ++;
1206             while ((*p != ' ') && (*p != '\0')) {
1207               printf("%c", *p);
1208               p ++;
1209             }
1210           } else {
1211             if (*p != '\n')
1212             printf("%c", *p);
1213             p ++;
1214           }
1215         }
1216
1217         printf("\n");
1218       } else p ++;
1219     }
1220 #else
1221     get_cpuconfig();
1222 #endif
1223
1224 #ifdef FORCE
1225     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1226 #else
1227 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1228     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1229 #endif
1230 #endif
1231
1232  break;
1233
1234   case '2' : /* SMP */
1235     if (get_num_cores() > 1) printf("SMP=1\n");
1236     break;
1237   }
1238
1239   fflush(stdout);
1240
1241   return 0;
1242 }
1243