getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93 #if defined(AIX)
  94 #include <sys/sysinfo.h>
  95 #endif
  96
  97 #if defined(__x86_64__) || defined(_M_X64)
  98 #if (( defined(__GNUC__)  && __GNUC__   > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
  99 #else
 100 #define NO_AVX512
 101 #endif
 102 #endif
 103 /* #define FORCE_P2             */
 104 /* #define FORCE_KATMAI         */
 105 /* #define FORCE_COPPERMINE     */
 106 /* #define FORCE_NORTHWOOD      */
 107 /* #define FORCE_PRESCOTT       */
 108 /* #define FORCE_BANIAS         */
 109 /* #define FORCE_YONAH          */
 110 /* #define FORCE_CORE2          */
 111 /* #define FORCE_PENRYN         */
 112 /* #define FORCE_DUNNINGTON     */
 113 /* #define FORCE_NEHALEM        */
 114 /* #define FORCE_SANDYBRIDGE    */
 115 /* #define FORCE_ATOM           */
 116 /* #define FORCE_ATHLON         */
 117 /* #define FORCE_OPTERON        */
 118 /* #define FORCE_OPTERON_SSE3   */
 119 /* #define FORCE_BARCELONA      */
 120 /* #define FORCE_SHANGHAI       */
 121 /* #define FORCE_ISTANBUL       */
 122 /* #define FORCE_BOBCAT         */
 123 /* #define FORCE_BULLDOZER      */
 124 /* #define FORCE_PILEDRIVER     */
 125 /* #define FORCE_SSE_GENERIC    */
 126 /* #define FORCE_VIAC3          */
 127 /* #define FORCE_NANO           */
 128 /* #define FORCE_POWER3         */
 129 /* #define FORCE_POWER4         */
 130 /* #define FORCE_POWER5         */
 131 /* #define FORCE_POWER6         */
 132 /* #define FORCE_POWER7         */
 133 /* #define FORCE_POWER8         */
 134 /* #define FORCE_PPCG4          */
 135 /* #define FORCE_PPC970         */
 136 /* #define FORCE_PPC970MP       */
 137 /* #define FORCE_PPC440         */
 138 /* #define FORCE_PPC440FP2      */
 139 /* #define FORCE_CELL           */
 140 /* #define FORCE_SICORTEX       */
 141 /* #define FORCE_LOONGSON3A     */
 142 /* #define FORCE_LOONGSON3B     */
 143 /* #define FORCE_I6400          */
 144 /* #define FORCE_P6600          */
 145 /* #define FORCE_P5600          */
 146 /* #define FORCE_I6500          */
 147 /* #define FORCE_ITANIUM2       */
 148 /* #define FORCE_SPARC          */
 149 /* #define FORCE_SPARCV7        */
 150 /* #define FORCE_ZARCH_GENERIC  */
 151 /* #define FORCE_Z13            */
 152 /* #define FORCE_GENERIC        */
 153
 154 #ifdef FORCE_P2
 155 #define FORCE
 156 #define FORCE_INTEL
 157 #define ARCHITECTURE    "X86"
 158 #define SUBARCHITECTURE "PENTIUM2"
 159 #define ARCHCONFIG   "-DPENTIUM2 " \
 160                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 161                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 162                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 163                      "-DHAVE_CMOV -DHAVE_MMX"
 164 #define LIBNAME   "p2"
 165 #define CORENAME  "P5"
 166 #endif
 167
 168 #ifdef FORCE_KATMAI
 169 #define FORCE
 170 #define FORCE_INTEL
 171 #define ARCHITECTURE    "X86"
 172 #define SUBARCHITECTURE "PENTIUM3"
 173 #define ARCHCONFIG   "-DPENTIUM3 " \
 174                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 175                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 176                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 177                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 178 #define LIBNAME   "katmai"
 179 #define CORENAME  "KATMAI"
 180 #endif
 181
 182 #ifdef FORCE_COPPERMINE
 183 #define FORCE
 184 #define FORCE_INTEL
 185 #define ARCHITECTURE    "X86"
 186 #define SUBARCHITECTURE "PENTIUM3"
 187 #define ARCHCONFIG   "-DPENTIUM3 " \
 188                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 189                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 190                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 191                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 192 #define LIBNAME   "coppermine"
 193 #define CORENAME  "COPPERMINE"
 194 #endif
 195
 196 #ifdef FORCE_NORTHWOOD
 197 #define FORCE
 198 #define FORCE_INTEL
 199 #define ARCHITECTURE    "X86"
 200 #define SUBARCHITECTURE "PENTIUM4"
 201 #define ARCHCONFIG   "-DPENTIUM4 " \
 202                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 203                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 204                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 205                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 206 #define LIBNAME   "northwood"
 207 #define CORENAME  "NORTHWOOD"
 208 #endif
 209
 210 #ifdef FORCE_PRESCOTT
 211 #define FORCE
 212 #define FORCE_INTEL
 213 #define ARCHITECTURE    "X86"
 214 #define SUBARCHITECTURE "PENTIUM4"
 215 #define ARCHCONFIG   "-DPENTIUM4 " \
 216                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 217                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 218                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 219                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 220 #define LIBNAME   "prescott"
 221 #define CORENAME  "PRESCOTT"
 222 #endif
 223
 224 #ifdef FORCE_BANIAS
 225 #define FORCE
 226 #define FORCE_INTEL
 227 #define ARCHITECTURE    "X86"
 228 #define SUBARCHITECTURE "BANIAS"
 229 #define ARCHCONFIG   "-DPENTIUMM " \
 230                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 231                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 232                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 233                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 234 #define LIBNAME   "banias"
 235 #define CORENAME  "BANIAS"
 236 #endif
 237
 238 #ifdef FORCE_YONAH
 239 #define FORCE
 240 #define FORCE_INTEL
 241 #define ARCHITECTURE    "X86"
 242 #define SUBARCHITECTURE "YONAH"
 243 #define ARCHCONFIG   "-DPENTIUMM " \
 244                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 245                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 246                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 247                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 248 #define LIBNAME   "yonah"
 249 #define CORENAME  "YONAH"
 250 #endif
 251
 252 #ifdef FORCE_CORE2
 253 #define FORCE
 254 #define FORCE_INTEL
 255 #define ARCHITECTURE    "X86"
 256 #define SUBARCHITECTURE "CONRORE"
 257 #define ARCHCONFIG   "-DCORE2 " \
 258                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 259                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 260                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 261                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 262 #define LIBNAME   "core2"
 263 #define CORENAME  "CORE2"
 264 #endif
 265
 266 #ifdef FORCE_PENRYN
 267 #define FORCE
 268 #define FORCE_INTEL
 269 #define ARCHITECTURE    "X86"
 270 #define SUBARCHITECTURE "PENRYN"
 271 #define ARCHCONFIG   "-DPENRYN " \
 272                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 273                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 274                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 275                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 276 #define LIBNAME   "penryn"
 277 #define CORENAME  "PENRYN"
 278 #endif
 279
 280 #ifdef FORCE_DUNNINGTON
 281 #define FORCE
 282 #define FORCE_INTEL
 283 #define ARCHITECTURE    "X86"
 284 #define SUBARCHITECTURE "DUNNINGTON"
 285 #define ARCHCONFIG   "-DDUNNINGTON " \
 286                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 287                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 288                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 289                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 290                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 291 #define LIBNAME   "dunnington"
 292 #define CORENAME  "DUNNINGTON"
 293 #endif
 294
 295 #ifdef FORCE_NEHALEM
 296 #define FORCE
 297 #define FORCE_INTEL
 298 #define ARCHITECTURE    "X86"
 299 #define SUBARCHITECTURE "NEHALEM"
 300 #define ARCHCONFIG   "-DNEHALEM " \
 301                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 302                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 303                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 304                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 305 #define LIBNAME   "nehalem"
 306 #define CORENAME  "NEHALEM"
 307 #endif
 308
 309 #ifdef FORCE_SANDYBRIDGE
 310 #define FORCE
 311 #define FORCE_INTEL
 312 #define ARCHITECTURE    "X86"
 313 #define SUBARCHITECTURE "SANDYBRIDGE"
 314 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 315                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 316                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 317                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 318                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 319 #define LIBNAME   "sandybridge"
 320 #define CORENAME  "SANDYBRIDGE"
 321 #endif
 322
 323 #ifdef FORCE_HASWELL
 324 #define FORCE
 325 #define FORCE_INTEL
 326 #define ARCHITECTURE    "X86"
 327 #define SUBARCHITECTURE "HASWELL"
 328 #define ARCHCONFIG   "-DHASWELL " \
 329                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 330                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 331                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 332                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 333                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 334 #define LIBNAME   "haswell"
 335 #define CORENAME  "HASWELL"
 336 #endif
 337
 338 #ifdef FORCE_SKYLAKEX
 339 #ifdef NO_AVX512
 340 #define FORCE
 341 #define FORCE_INTEL
 342 #define ARCHITECTURE    "X86"
 343 #define SUBARCHITECTURE "HASWELL"
 344 #define ARCHCONFIG   "-DHASWELL " \
 345                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 346                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 347                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 348                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 349                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 350 #define LIBNAME   "haswell"
 351 #define CORENAME  "HASWELL"
 352 #else
 353 #define FORCE
 354 #define FORCE_INTEL
 355 #define ARCHITECTURE    "X86"
 356 #define SUBARCHITECTURE "SKYLAKEX"
 357 #define ARCHCONFIG   "-DSKYLAKEX " \
 358                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 359                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 360                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 361                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 362                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 363 #define LIBNAME   "skylakex"
 364 #define CORENAME  "SKYLAKEX"
 365 #endif
 366 #endif
 367
 368 #ifdef FORCE_COOPERLAKE
 369 #ifdef NO_AVX512
 370 #define FORCE
 371 #define FORCE_INTEL
 372 #define ARCHITECTURE    "X86"
 373 #define SUBARCHITECTURE "HASWELL"
 374 #define ARCHCONFIG   "-DHASWELL " \
 375                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 376                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 377                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 378                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 379                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 380 #define LIBNAME   "haswell"
 381 #define CORENAME  "HASWELL"
 382 #else
 383 #define FORCE
 384 #define FORCE_INTEL
 385 #define ARCHITECTURE    "X86"
 386 #define SUBARCHITECTURE "COOPERLAKE"
 387 #define ARCHCONFIG   "-DCOOPERLAKE " \
 388                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 389                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 390                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 391                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 392                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
 393 #define LIBNAME   "cooperlake"
 394 #define CORENAME  "COOPERLAKE"
 395 #endif
 396 #endif
 397
 398 #ifdef FORCE_ATOM
 399 #define FORCE
 400 #define FORCE_INTEL
 401 #define ARCHITECTURE    "X86"
 402 #define SUBARCHITECTURE "ATOM"
 403 #define ARCHCONFIG   "-DATOM " \
 404                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 405                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 406                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 407                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 408 #define LIBNAME   "atom"
 409 #define CORENAME  "ATOM"
 410 #endif
 411
 412 #ifdef FORCE_ATHLON
 413 #define FORCE
 414 #define FORCE_INTEL
 415 #define ARCHITECTURE    "X86"
 416 #define SUBARCHITECTURE "ATHLON"
 417 #define ARCHCONFIG   "-DATHLON " \
 418                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 419                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 420                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 421                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 422 #define LIBNAME   "athlon"
 423 #define CORENAME  "ATHLON"
 424 #endif
 425
 426 #ifdef FORCE_OPTERON
 427 #define FORCE
 428 #define FORCE_INTEL
 429 #define ARCHITECTURE    "X86"
 430 #define SUBARCHITECTURE "OPTERON"
 431 #define ARCHCONFIG   "-DOPTERON " \
 432                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 433                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 434                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 435                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 436 #define LIBNAME   "opteron"
 437 #define CORENAME  "OPTERON"
 438 #endif
 439
 440 #ifdef FORCE_OPTERON_SSE3
 441 #define FORCE
 442 #define FORCE_INTEL
 443 #define ARCHITECTURE    "X86"
 444 #define SUBARCHITECTURE "OPTERON"
 445 #define ARCHCONFIG   "-DOPTERON " \
 446                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 447                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 448                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 449                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 450 #define LIBNAME   "opteron"
 451 #define CORENAME  "OPTERON"
 452 #endif
 453
 454 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 455 #define FORCE
 456 #define FORCE_INTEL
 457 #define ARCHITECTURE    "X86"
 458 #define SUBARCHITECTURE "BARCELONA"
 459 #define ARCHCONFIG   "-DBARCELONA " \
 460                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 461                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 462                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 463                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 464                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 465 #define LIBNAME   "barcelona"
 466 #define CORENAME  "BARCELONA"
 467 #endif
 468
 469 #if defined(FORCE_BOBCAT)
 470 #define FORCE
 471 #define FORCE_INTEL
 472 #define ARCHITECTURE    "X86"
 473 #define SUBARCHITECTURE "BOBCAT"
 474 #define ARCHCONFIG   "-DBOBCAT " \
 475                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 476                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 477                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 478                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 479                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 480 #define LIBNAME   "bobcat"
 481 #define CORENAME  "BOBCAT"
 482 #endif
 483
 484 #if defined (FORCE_BULLDOZER)
 485 #define FORCE
 486 #define FORCE_INTEL
 487 #define ARCHITECTURE    "X86"
 488 #define SUBARCHITECTURE "BULLDOZER"
 489 #define ARCHCONFIG   "-DBULLDOZER " \
 490                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 491                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 492                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 493                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 494                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 495                      "-DHAVE_AVX"
 496 #define LIBNAME   "bulldozer"
 497 #define CORENAME  "BULLDOZER"
 498 #endif
 499
 500 #if defined (FORCE_PILEDRIVER)
 501 #define FORCE
 502 #define FORCE_INTEL
 503 #define ARCHITECTURE    "X86"
 504 #define SUBARCHITECTURE "PILEDRIVER"
 505 #define ARCHCONFIG   "-DPILEDRIVER " \
 506                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 507                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 508                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 509                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 510                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 511                      "-DHAVE_AVX -DHAVE_FMA3"
 512 #define LIBNAME   "piledriver"
 513 #define CORENAME  "PILEDRIVER"
 514 #endif
 515
 516 #if defined (FORCE_STEAMROLLER)
 517 #define FORCE
 518 #define FORCE_INTEL
 519 #define ARCHITECTURE    "X86"
 520 #define SUBARCHITECTURE "STEAMROLLER"
 521 #define ARCHCONFIG   "-DSTEAMROLLER " \
 522                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 523                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 524                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 525                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 526                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 527                      "-DHAVE_AVX -DHAVE_FMA3"
 528 #define LIBNAME   "steamroller"
 529 #define CORENAME  "STEAMROLLER"
 530 #endif
 531
 532 #if defined (FORCE_EXCAVATOR)
 533 #define FORCE
 534 #define FORCE_INTEL
 535 #define ARCHITECTURE    "X86"
 536 #define SUBARCHITECTURE "EXCAVATOR"
 537 #define ARCHCONFIG   "-DEXCAVATOR " \
 538                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 539                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 540                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 541                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 542                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 543                      "-DHAVE_AVX -DHAVE_FMA3"
 544 #define LIBNAME   "excavator"
 545 #define CORENAME  "EXCAVATOR"
 546 #endif
 547
 548 #if defined (FORCE_ZEN)
 549 #define FORCE
 550 #define FORCE_INTEL
 551 #define ARCHITECTURE    "X86"
 552 #define SUBARCHITECTURE "ZEN"
 553 #define ARCHCONFIG   "-DZEN " \
 554                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 555                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 556                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 557                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 558                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 559                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 560                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 561                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 562                      "-DHAVE_AVX -DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 563 #define LIBNAME   "zen"
 564 #define CORENAME  "ZEN"
 565 #endif
 566
 567
 568 #ifdef FORCE_SSE_GENERIC
 569 #define FORCE
 570 #define FORCE_INTEL
 571 #define ARCHITECTURE    "X86"
 572 #define SUBARCHITECTURE "GENERIC"
 573 #define ARCHCONFIG   "-DGENERIC " \
 574                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 575                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 576                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 577                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 578 #define LIBNAME   "generic"
 579 #define CORENAME  "GENERIC"
 580 #endif
 581
 582 #ifdef FORCE_VIAC3
 583 #define FORCE
 584 #define FORCE_INTEL
 585 #define ARCHITECTURE    "X86"
 586 #define SUBARCHITECTURE "VIAC3"
 587 #define ARCHCONFIG   "-DVIAC3 " \
 588                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 589                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 590                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 591                      "-DHAVE_MMX -DHAVE_SSE "
 592 #define LIBNAME   "viac3"
 593 #define CORENAME  "VIAC3"
 594 #endif
 595
 596 #ifdef FORCE_NANO
 597 #define FORCE
 598 #define FORCE_INTEL
 599 #define ARCHITECTURE    "X86"
 600 #define SUBARCHITECTURE "NANO"
 601 #define ARCHCONFIG   "-DNANO " \
 602                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 603                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 604                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 605                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 606 #define LIBNAME   "nano"
 607 #define CORENAME  "NANO"
 608 #endif
 609
 610 #ifdef FORCE_POWER3
 611 #define FORCE
 612 #define ARCHITECTURE    "POWER"
 613 #define SUBARCHITECTURE "POWER3"
 614 #define SUBDIRNAME      "power"
 615 #define ARCHCONFIG   "-DPOWER3 " \
 616                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 617                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 618                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 619 #define LIBNAME   "power3"
 620 #define CORENAME  "POWER3"
 621 #endif
 622
 623 #ifdef FORCE_POWER4
 624 #define FORCE
 625 #define ARCHITECTURE    "POWER"
 626 #define SUBARCHITECTURE "POWER4"
 627 #define SUBDIRNAME      "power"
 628 #define ARCHCONFIG   "-DPOWER4 " \
 629                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 630                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 631                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 632 #define LIBNAME   "power4"
 633 #define CORENAME  "POWER4"
 634 #endif
 635
 636 #ifdef FORCE_POWER5
 637 #define FORCE
 638 #define ARCHITECTURE    "POWER"
 639 #define SUBARCHITECTURE "POWER5"
 640 #define SUBDIRNAME      "power"
 641 #define ARCHCONFIG   "-DPOWER5 " \
 642                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 643                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 644                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 645 #define LIBNAME   "power5"
 646 #define CORENAME  "POWER5"
 647 #endif
 648
 649 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 650 #define FORCE
 651 #define ARCHITECTURE    "POWER"
 652 #define SUBARCHITECTURE "POWER6"
 653 #define SUBDIRNAME      "power"
 654 #define ARCHCONFIG   "-DPOWER6 " \
 655                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 656                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 657                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 658 #define LIBNAME   "power6"
 659 #define CORENAME  "POWER6"
 660 #endif
 661
 662 #if defined(FORCE_POWER8)
 663 #define FORCE
 664 #define ARCHITECTURE    "POWER"
 665 #define SUBARCHITECTURE "POWER8"
 666 #define SUBDIRNAME      "power"
 667 #define ARCHCONFIG   "-DPOWER8 " \
 668                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 669                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 670                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 671 #define LIBNAME   "power8"
 672 #define CORENAME  "POWER8"
 673 #endif
 674
 675 #if defined(FORCE_POWER9)
 676 #define FORCE
 677 #define ARCHITECTURE    "POWER"
 678 #define SUBARCHITECTURE "POWER9"
 679 #define SUBDIRNAME      "power"
 680 #define ARCHCONFIG   "-DPOWER9 " \
 681                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 682                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 683                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 684 #define LIBNAME   "power9"
 685 #define CORENAME  "POWER9"
 686 #endif
 687
 688 #if defined(FORCE_POWER10)
 689 #define FORCE
 690 #define ARCHITECTURE    "POWER"
 691 #define SUBARCHITECTURE "POWER10"
 692 #define SUBDIRNAME      "power"
 693 #define ARCHCONFIG   "-DPOWER10 " \
 694                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 695                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 696                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 697 #define LIBNAME   "power10"
 698 #define CORENAME  "POWER10"
 699 #endif
 700
 701 #ifdef FORCE_PPCG4
 702 #define FORCE
 703 #define ARCHITECTURE    "POWER"
 704 #define SUBARCHITECTURE "PPCG4"
 705 #define SUBDIRNAME      "power"
 706 #define ARCHCONFIG   "-DPPCG4 " \
 707                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 708                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 709                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 710 #define LIBNAME   "ppcg4"
 711 #define CORENAME  "PPCG4"
 712 #endif
 713
 714 #ifdef FORCE_PPC970
 715 #define FORCE
 716 #define ARCHITECTURE    "POWER"
 717 #define SUBARCHITECTURE "PPC970"
 718 #define SUBDIRNAME      "power"
 719 #define ARCHCONFIG   "-DPPC970 " \
 720                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 721                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 722                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 723 #define LIBNAME   "ppc970"
 724 #define CORENAME  "PPC970"
 725 #endif
 726
 727 #ifdef FORCE_PPC970MP
 728 #define FORCE
 729 #define ARCHITECTURE    "POWER"
 730 #define SUBARCHITECTURE "PPC970"
 731 #define SUBDIRNAME      "power"
 732 #define ARCHCONFIG   "-DPPC970 " \
 733                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 734                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 735                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 736 #define LIBNAME   "ppc970mp"
 737 #define CORENAME  "PPC970"
 738 #endif
 739
 740 #ifdef FORCE_PPC440
 741 #define FORCE
 742 #define ARCHITECTURE    "POWER"
 743 #define SUBARCHITECTURE "PPC440"
 744 #define SUBDIRNAME      "power"
 745 #define ARCHCONFIG   "-DPPC440 " \
 746                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 747                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 748                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 749 #define LIBNAME   "ppc440"
 750 #define CORENAME  "PPC440"
 751 #endif
 752
 753 #ifdef FORCE_PPC440FP2
 754 #define FORCE
 755 #define ARCHITECTURE    "POWER"
 756 #define SUBARCHITECTURE "PPC440FP2"
 757 #define SUBDIRNAME      "power"
 758 #define ARCHCONFIG   "-DPPC440FP2 " \
 759                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 760                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 761                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 762 #define LIBNAME   "ppc440FP2"
 763 #define CORENAME  "PPC440FP2"
 764 #endif
 765
 766 #ifdef FORCE_CELL
 767 #define FORCE
 768 #define ARCHITECTURE    "POWER"
 769 #define SUBARCHITECTURE "CELL"
 770 #define SUBDIRNAME      "power"
 771 #define ARCHCONFIG   "-DCELL " \
 772                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 773                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 774                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 775 #define LIBNAME   "cell"
 776 #define CORENAME  "CELL"
 777 #endif
 778
 779 #ifdef FORCE_SICORTEX
 780 #define FORCE
 781 #define ARCHITECTURE    "MIPS"
 782 #define SUBARCHITECTURE "SICORTEX"
 783 #define SUBDIRNAME      "mips"
 784 #define ARCHCONFIG   "-DSICORTEX " \
 785                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 786                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 787                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 788 #define LIBNAME   "mips"
 789 #define CORENAME  "sicortex"
 790 #endif
 791
 792
 793 #ifdef FORCE_LOONGSON3A
 794 #define FORCE
 795 #define ARCHITECTURE    "MIPS"
 796 #define SUBARCHITECTURE "LOONGSON3A"
 797 #define SUBDIRNAME      "mips64"
 798 #define ARCHCONFIG   "-DLOONGSON3A " \
 799        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 800        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 801        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 802 #define LIBNAME   "loongson3a"
 803 #define CORENAME  "LOONGSON3A"
 804 #else
 805 #endif
 806
 807 #ifdef FORCE_LOONGSON3B
 808 #define FORCE
 809 #define ARCHITECTURE    "MIPS"
 810 #define SUBARCHITECTURE "LOONGSON3B"
 811 #define SUBDIRNAME      "mips64"
 812 #define ARCHCONFIG   "-DLOONGSON3B " \
 813        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 814        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 815        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 816 #define LIBNAME   "loongson3b"
 817 #define CORENAME  "LOONGSON3B"
 818 #else
 819 #endif
 820
 821 #ifdef FORCE_I6400
 822 #define FORCE
 823 #define ARCHITECTURE    "MIPS"
 824 #define SUBARCHITECTURE "I6400"
 825 #define SUBDIRNAME      "mips64"
 826 #define ARCHCONFIG   "-DI6400 " \
 827        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 828        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 829        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 830 #define LIBNAME   "i6400"
 831 #define CORENAME  "I6400"
 832 #else
 833 #endif
 834
 835 #ifdef FORCE_P6600
 836 #define FORCE
 837 #define ARCHITECTURE    "MIPS"
 838 #define SUBARCHITECTURE "P6600"
 839 #define SUBDIRNAME      "mips64"
 840 #define ARCHCONFIG   "-DP6600 " \
 841        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 842        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 843        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 844 #define LIBNAME   "p6600"
 845 #define CORENAME  "P6600"
 846 #else
 847 #endif
 848
 849 #ifdef FORCE_P5600
 850 #define FORCE
 851 #define ARCHITECTURE    "MIPS"
 852 #define SUBARCHITECTURE "P5600"
 853 #define SUBDIRNAME      "mips"
 854 #define ARCHCONFIG   "-DP5600 " \
 855        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 856        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 857        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 858 #define LIBNAME   "p5600"
 859 #define CORENAME  "P5600"
 860 #else
 861 #endif
 862
 863 #ifdef FORCE_MIPS1004K
 864 #define FORCE
 865 #define ARCHITECTURE    "MIPS"
 866 #define SUBARCHITECTURE "MIPS1004K"
 867 #define SUBDIRNAME      "mips"
 868 #define ARCHCONFIG   "-DMIPS1004K " \
 869        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 870        "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 871        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 872 #define LIBNAME   "mips1004K"
 873 #define CORENAME  "MIPS1004K"
 874 #else
 875 #endif
 876
 877 #ifdef FORCE_MIPS24K
 878 #define FORCE
 879 #define ARCHITECTURE    "MIPS"
 880 #define SUBARCHITECTURE "MIPS24K"
 881 #define SUBDIRNAME      "mips"
 882 #define ARCHCONFIG   "-DMIPS24K " \
 883        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 884        "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
 885        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 886 #define LIBNAME   "mips24K"
 887 #define CORENAME  "MIPS24K"
 888 #else
 889 #endif
 890
 891 #ifdef FORCE_I6500
 892 #define FORCE
 893 #define ARCHITECTURE    "MIPS"
 894 #define SUBARCHITECTURE "I6500"
 895 #define SUBDIRNAME      "mips64"
 896 #define ARCHCONFIG   "-DI6500 " \
 897        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 898        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 899        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 900 #define LIBNAME   "i6500"
 901 #define CORENAME  "I6500"
 902 #else
 903 #endif
 904
 905 #ifdef FORCE_ITANIUM2
 906 #define FORCE
 907 #define ARCHITECTURE    "IA64"
 908 #define SUBARCHITECTURE "ITANIUM2"
 909 #define SUBDIRNAME      "ia64"
 910 #define ARCHCONFIG   "-DITANIUM2 " \
 911                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 912                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 913 #define LIBNAME   "itanium2"
 914 #define CORENAME  "itanium2"
 915 #endif
 916
 917 #ifdef FORCE_SPARC
 918 #define FORCE
 919 #define ARCHITECTURE    "SPARC"
 920 #define SUBARCHITECTURE "SPARC"
 921 #define SUBDIRNAME      "sparc"
 922 #define ARCHCONFIG   "-DSPARC -DV9 " \
 923                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 924                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 925 #define LIBNAME   "sparc"
 926 #define CORENAME  "sparc"
 927 #endif
 928
 929 #ifdef FORCE_SPARCV7
 930 #define FORCE
 931 #define ARCHITECTURE    "SPARC"
 932 #define SUBARCHITECTURE "SPARC"
 933 #define SUBDIRNAME      "sparc"
 934 #define ARCHCONFIG   "-DSPARC -DV7 " \
 935                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 936                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 937 #define LIBNAME   "sparcv7"
 938 #define CORENAME  "sparcv7"
 939 #endif
 940
 941 #ifdef FORCE_GENERIC
 942 #define FORCE
 943 #define ARCHITECTURE    "GENERIC"
 944 #define SUBARCHITECTURE "GENERIC"
 945 #define SUBDIRNAME      "generic"
 946 #define ARCHCONFIG   "-DGENERIC " \
 947                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 948                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 949                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 950 #define LIBNAME   "generic"
 951 #define CORENAME  "generic"
 952 #endif
 953
 954 #ifdef FORCE_ARMV7
 955 #define FORCE
 956 #define ARCHITECTURE    "ARM"
 957 #define SUBARCHITECTURE "ARMV7"
 958 #define SUBDIRNAME      "arm"
 959 #define ARCHCONFIG   "-DARMV7 " \
 960        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 961        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 962        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 963        "-DHAVE_VFPV3 -DHAVE_VFP"
 964 #define LIBNAME   "armv7"
 965 #define CORENAME  "ARMV7"
 966 #else
 967 #endif
 968
 969 #ifdef FORCE_CORTEXA9
 970 #define FORCE
 971 #define ARCHITECTURE    "ARM"
 972 #define SUBARCHITECTURE "CORTEXA9"
 973 #define SUBDIRNAME      "arm"
 974 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 975        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 976        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 977        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 978        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 979 #define LIBNAME   "cortexa9"
 980 #define CORENAME  "CORTEXA9"
 981 #else
 982 #endif
 983
 984 #ifdef FORCE_RISCV64_GENERIC
 985 #define FORCE
 986 #define ARCHITECTURE    "RISCV64"
 987 #define SUBARCHITECTURE "RISCV64_GENERIC"
 988 #define SUBDIRNAME      "riscv64"
 989 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
 990        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 991        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 992        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 993 #define LIBNAME   "riscv64_generic"
 994 #define CORENAME  "RISCV64_GENERIC"
 995 #else
 996 #endif
 997
 998 #ifdef FORCE_CORTEXA15
 999 #define FORCE
1000 #define ARCHITECTURE    "ARM"
1001 #define SUBARCHITECTURE "CORTEXA15"
1002 #define SUBDIRNAME      "arm"
1003 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
1004        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1005        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1006        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1007        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1008 #define LIBNAME   "cortexa15"
1009 #define CORENAME  "CORTEXA15"
1010 #else
1011 #endif
1012
1013 #ifdef FORCE_ARMV6
1014 #define FORCE
1015 #define ARCHITECTURE    "ARM"
1016 #define SUBARCHITECTURE "ARMV6"
1017 #define SUBDIRNAME      "arm"
1018 #define ARCHCONFIG   "-DARMV6 " \
1019        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1020        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1021        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1022        "-DHAVE_VFP"
1023 #define LIBNAME   "armv6"
1024 #define CORENAME  "ARMV6"
1025 #else
1026 #endif
1027
1028 #ifdef FORCE_ARMV5
1029 #define FORCE
1030 #define ARCHITECTURE    "ARM"
1031 #define SUBARCHITECTURE "ARMV5"
1032 #define SUBDIRNAME      "arm"
1033 #define ARCHCONFIG   "-DARMV5 " \
1034        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1035        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1036        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1037 #define LIBNAME   "armv5"
1038 #define CORENAME  "ARMV5"
1039 #else
1040 #endif
1041
1042
1043 #ifdef FORCE_ARMV8
1044 #define FORCE
1045 #define ARCHITECTURE    "ARM64"
1046 #define SUBARCHITECTURE "ARMV8"
1047 #define SUBDIRNAME      "arm64"
1048 #define ARCHCONFIG   "-DARMV8 " \
1049        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1050        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1051        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1052        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1053 #define LIBNAME   "armv8"
1054 #define CORENAME  "ARMV8"
1055 #endif
1056
1057 #ifdef FORCE_CORTEXA53
1058 #define FORCE
1059 #define ARCHITECTURE    "ARM64"
1060 #define SUBARCHITECTURE "CORTEXA53"
1061 #define SUBDIRNAME      "arm64"
1062 #define ARCHCONFIG   "-DCORTEXA53 " \
1063        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1064        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1065        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1066        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1067        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1068 #define LIBNAME   "cortexa53"
1069 #define CORENAME  "CORTEXA53"
1070 #else
1071 #endif
1072
1073 #ifdef FORCE_CORTEXA57
1074 #define FORCE
1075 #define ARCHITECTURE    "ARM64"
1076 #define SUBARCHITECTURE "CORTEXA57"
1077 #define SUBDIRNAME      "arm64"
1078 #define ARCHCONFIG   "-DCORTEXA57 " \
1079        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1080        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1081        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1082        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1083        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1084 #define LIBNAME   "cortexa57"
1085 #define CORENAME  "CORTEXA57"
1086 #else
1087 #endif
1088
1089 #ifdef FORCE_CORTEXA72
1090 #define FORCE
1091 #define ARCHITECTURE    "ARM64"
1092 #define SUBARCHITECTURE "CORTEXA72"
1093 #define SUBDIRNAME      "arm64"
1094 #define ARCHCONFIG   "-DCORTEXA72 " \
1095        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1096        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1097        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1098        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1099        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1100 #define LIBNAME   "cortexa72"
1101 #define CORENAME  "CORTEXA72"
1102 #else
1103 #endif
1104
1105 #ifdef FORCE_CORTEXA73
1106 #define FORCE
1107 #define ARCHITECTURE    "ARM64"
1108 #define SUBARCHITECTURE "CORTEXA73"
1109 #define SUBDIRNAME      "arm64"
1110 #define ARCHCONFIG   "-DCORTEXA73 " \
1111        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1112        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1113        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1114        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1115        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1116 #define LIBNAME   "cortexa73"
1117 #define CORENAME  "CORTEXA73"
1118 #else
1119 #endif
1120
1121 #ifdef FORCE_NEOVERSEN1
1122 #define FORCE
1123 #define ARCHITECTURE    "ARM64"
1124 #define SUBARCHITECTURE "NEOVERSEN1"
1125 #define SUBDIRNAME      "arm64"
1126 #define ARCHCONFIG   "-DNEOVERSEN1 " \
1127        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1128        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1129        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1130        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1131        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1132        "-march=armv8.2-a -mtune=cortex-a72"
1133 #define LIBNAME   "neoversen1"
1134 #define CORENAME  "NEOVERSEN1"
1135 #else
1136 #endif
1137
1138
1139 #ifdef FORCE_FALKOR
1140 #define FORCE
1141 #define ARCHITECTURE    "ARM64"
1142 #define SUBARCHITECTURE "FALKOR"
1143 #define SUBDIRNAME      "arm64"
1144 #define ARCHCONFIG   "-DFALKOR " \
1145        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1146        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1147        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1148        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1149        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1150 #define LIBNAME   "falkor"
1151 #define CORENAME  "FALKOR"
1152 #else
1153 #endif
1154
1155 #ifdef FORCE_THUNDERX
1156 #define FORCE
1157 #define ARCHITECTURE    "ARM64"
1158 #define SUBARCHITECTURE "THUNDERX"
1159 #define SUBDIRNAME      "arm64"
1160 #define ARCHCONFIG   "-DTHUNDERX " \
1161        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1162        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1163        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1164        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1165 #define LIBNAME   "thunderx"
1166 #define CORENAME  "THUNDERX"
1167 #else
1168 #endif
1169
1170 #ifdef FORCE_THUNDERX2T99
1171 #define ARMV8
1172 #define FORCE
1173 #define ARCHITECTURE    "ARM64"
1174 #define SUBARCHITECTURE "THUNDERX2T99"
1175 #define SUBDIRNAME      "arm64"
1176 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1177        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1178        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1179        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1180        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1181        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1182        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1183 #define LIBNAME   "thunderx2t99"
1184 #define CORENAME  "THUNDERX2T99"
1185 #else
1186 #endif
1187
1188 #ifdef FORCE_TSV110
1189 #define FORCE
1190 #define ARCHITECTURE    "ARM64"
1191 #define SUBARCHITECTURE "TSV110"
1192 #define SUBDIRNAME      "arm64"
1193 #define ARCHCONFIG   "-DTSV110 " \
1194        "-DL1_CODE_SIZE=65536  -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1195        "-DL1_DATA_SIZE=65536  -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1196        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1197        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1198        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1199 #define LIBNAME   "tsv110"
1200 #define CORENAME  "TSV110"
1201 #else
1202 #endif
1203
1204 #ifdef FORCE_EMAG8180
1205 #define ARMV8
1206 #define FORCE
1207 #define ARCHITECTURE    "ARM64"
1208 #define SUBARCHITECTURE "EMAG8180"
1209 #define SUBDIRNAME      "arm64"
1210 #define ARCHCONFIG   "-DEMAG8180 " \
1211        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1212        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1213        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1214        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1215        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1216        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1217 #define LIBNAME   "emag8180"
1218 #define CORENAME  "EMAG8180"
1219 #endif
1220
1221 #ifdef FORCE_THUNDERX3T110
1222 #define ARMV8
1223 #define FORCE
1224 #define ARCHITECTURE    "ARM64"
1225 #define SUBARCHITECTURE "THUNDERX3T110"
1226 #define SUBDIRNAME      "arm64"
1227 #define ARCHCONFIG   "-DTHUNDERX3T110 " \
1228        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1229        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1230        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1231        "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1232        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1233        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1234 #define LIBNAME   "thunderx3t110"
1235 #define CORENAME  "THUNDERX3T110"
1236 #else
1237 #endif
1238
1239 #ifdef FORCE_VORTEX
1240 #define FORCE
1241 #define ARCHITECTURE    "ARM64"
1242 #define SUBARCHITECTURE "VORTEX"
1243 #define SUBDIRNAME      "arm64"
1244 #define ARCHCONFIG   "-DVORTEX " \
1245        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1246        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1247        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1248        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1249 #define LIBNAME   "vortex"
1250 #define CORENAME  "VORTEX"
1251 #endif
1252
1253 #ifdef FORCE_ZARCH_GENERIC
1254 #define FORCE
1255 #define ARCHITECTURE    "ZARCH"
1256 #define SUBARCHITECTURE "ZARCH_GENERIC"
1257 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1258        "-DDTB_DEFAULT_ENTRIES=64"
1259 #define LIBNAME   "zarch_generic"
1260 #define CORENAME  "ZARCH_GENERIC"
1261 #endif
1262
1263 #ifdef FORCE_Z13
1264 #define FORCE
1265 #define ARCHITECTURE    "ZARCH"
1266 #define SUBARCHITECTURE "Z13"
1267 #define ARCHCONFIG   "-DZ13 " \
1268        "-DDTB_DEFAULT_ENTRIES=64"
1269 #define LIBNAME   "z13"
1270 #define CORENAME  "Z13"
1271 #endif
1272
1273 #ifdef FORCE_Z14
1274 #define FORCE
1275 #define ARCHITECTURE    "ZARCH"
1276 #define SUBARCHITECTURE "Z14"
1277 #define ARCHCONFIG   "-DZ14 " \
1278        "-DDTB_DEFAULT_ENTRIES=64"
1279 #define LIBNAME   "z14"
1280 #define CORENAME  "Z14"
1281 #endif
1282
1283 #ifdef FORCE_C910V
1284 #define FORCE
1285 #define ARCHITECTURE    "RISCV64"
1286 #define SUBARCHITECTURE "C910V"
1287 #define SUBDIRNAME      "riscv64"
1288 #define ARCHCONFIG   "-DC910V " \
1289        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1290        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1291        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1292 #define LIBNAME   "c910v"
1293 #define CORENAME  "C910V"
1294 #else
1295 #endif
1296
1297
1298 #ifndef FORCE
1299
1300 #ifdef USER_TARGET
1301 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1302 #endif
1303
1304 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1305     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1306 #ifndef POWER
1307 #define POWER
1308 #endif
1309 #define OPENBLAS_SUPPORTED
1310 #endif
1311
1312 #if defined(__zarch__) || defined(__s390x__)
1313 #define ZARCH
1314 #include "cpuid_zarch.c"
1315 #define OPENBLAS_SUPPORTED
1316 #endif
1317
1318 #ifdef INTEL_AMD
1319 #include "cpuid_x86.c"
1320 #define OPENBLAS_SUPPORTED
1321 #endif
1322
1323 #ifdef __ia64__
1324 #include "cpuid_ia64.c"
1325 #define OPENBLAS_SUPPORTED
1326 #endif
1327
1328 #ifdef __alpha
1329 #include "cpuid_alpha.c"
1330 #define OPENBLAS_SUPPORTED
1331 #endif
1332
1333 #ifdef POWER
1334 #include "cpuid_power.c"
1335 #define OPENBLAS_SUPPORTED
1336 #endif
1337
1338 #ifdef sparc
1339 #include "cpuid_sparc.c"
1340 #define OPENBLAS_SUPPORTED
1341 #endif
1342
1343 #ifdef __mips__
1344 #ifdef __mips64
1345 #include "cpuid_mips64.c"
1346 #else
1347 #include "cpuid_mips.c"
1348 #endif
1349 #define OPENBLAS_SUPPORTED
1350 #endif
1351
1352 #ifdef __riscv
1353 #include "cpuid_riscv64.c"
1354 #endif
1355
1356 #ifdef __arm__
1357 #include "cpuid_arm.c"
1358 #define OPENBLAS_SUPPORTED
1359 #endif
1360
1361 #ifdef __aarch64__
1362 #include "cpuid_arm64.c"
1363 #define OPENBLAS_SUPPORTED
1364 #endif
1365
1366
1367 #ifndef OPENBLAS_SUPPORTED
1368 #error "This arch/CPU is not supported by OpenBLAS."
1369 #endif
1370
1371 #else
1372
1373 #endif
1374
1375 static int get_num_cores(void) {
1376
1377 #ifdef OS_WINDOWS
1378   SYSTEM_INFO sysinfo;
1379 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1380   int m[2], count;
1381   size_t len;
1382 #endif
1383
1384 #if defined(linux) || defined(__sun__)
1385   //returns the number of processors which are currently online
1386   return sysconf(_SC_NPROCESSORS_CONF);
1387
1388 #elif defined(OS_WINDOWS)
1389
1390   GetSystemInfo(&sysinfo);
1391   return sysinfo.dwNumberOfProcessors;
1392
1393 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1394   m[0] = CTL_HW;
1395   m[1] = HW_NCPU;
1396   len = sizeof(int);
1397   sysctl(m, 2, &count, &len, NULL, 0);
1398
1399   return count;
1400
1401 #elif defined(AIX)
1402   //returns the number of processors which are currently online
1403   return sysconf(_SC_NPROCESSORS_ONLN);
1404
1405 #else
1406   return 2;
1407 #endif
1408 }
1409
1410 int main(int argc, char *argv[]){
1411
1412 #ifdef FORCE
1413   char buffer[8192], *p, *q;
1414   int length;
1415 #endif
1416
1417   if (argc == 1) return 0;
1418
1419   switch (argv[1][0]) {
1420
1421   case '0' : /* for Makefile */
1422
1423 #ifdef FORCE
1424     printf("CORE=%s\n", CORENAME);
1425 #else
1426 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1427     printf("CORE=%s\n", get_corename());
1428 #endif
1429 #endif
1430
1431 #ifdef FORCE
1432     printf("LIBCORE=%s\n", LIBNAME);
1433 #else
1434     printf("LIBCORE=");
1435     get_libname();
1436     printf("\n");
1437 #endif
1438
1439     printf("NUM_CORES=%d\n", get_num_cores());
1440
1441 #if defined(__arm__)
1442 #if !defined(FORCE)
1443     fprintf(stderr,"get features!\n");
1444         get_features();
1445 #else
1446     fprintf(stderr,"split archconfig!\n");
1447     sprintf(buffer, "%s", ARCHCONFIG);
1448
1449     p = &buffer[0];
1450
1451     while (*p) {
1452       if ((*p == '-') && (*(p + 1) == 'D')) {
1453         p += 2;
1454         if (*p != 'H') {
1455                 while( (*p != ' ') && (*p != '-') && (*p != '\0') && (*p != '\n')) {p++; }
1456                 if (*p == '-') continue;
1457         }
1458         while ((*p != ' ') && (*p != '\0')) {
1459
1460           if (*p == '=') {
1461             printf("=");
1462             p ++;
1463             while ((*p != ' ') && (*p != '\0')) {
1464               printf("%c", *p);
1465               p ++;
1466             }
1467           } else {
1468             printf("%c", *p);
1469             p ++;
1470             if ((*p == ' ') || (*p =='\0')) printf("=1\n");
1471           }
1472         }
1473       } else p ++;
1474     }
1475 #endif
1476 #endif
1477
1478
1479 #ifdef INTEL_AMD
1480 #ifndef FORCE
1481     get_sse();
1482 #else
1483
1484     sprintf(buffer, "%s", ARCHCONFIG);
1485
1486     p = &buffer[0];
1487
1488     while (*p) {
1489       if ((*p == '-') && (*(p + 1) == 'D')) {
1490         p += 2;
1491
1492         while ((*p != ' ') && (*p != '\0')) {
1493
1494           if (*p == '=') {
1495             printf("=");
1496             p ++;
1497             while ((*p != ' ') && (*p != '\0')) {
1498               printf("%c", *p);
1499               p ++;
1500             }
1501           } else {
1502             printf("%c", *p);
1503             p ++;
1504             if ((*p == ' ') || (*p =='\0')) printf("=1");
1505           }
1506         }
1507
1508         printf("\n");
1509       } else p ++;
1510     }
1511 #endif
1512 #endif
1513
1514 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1515 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1516 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1517 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1518 #endif
1519 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1520 printf("ELF_VERSION=2\n");
1521 #endif
1522
1523 #ifdef MAKE_NB_JOBS
1524   #if MAKE_NB_JOBS > 0
1525     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1526   #else
1527     // Let make use parent -j argument or -j1 if there
1528     // is no make parent
1529   #endif
1530 #elif NO_PARALLEL_MAKE==1
1531     printf("MAKE += -j 1\n");
1532 #else
1533     printf("MAKE += -j %d\n", get_num_cores());
1534 #endif
1535
1536     break;
1537
1538   case '1' : /* For config.h */
1539 #ifdef FORCE
1540     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1541
1542     p = &buffer[0];
1543     while (*p) {
1544       if ((*p == '-') && (*(p + 1) == 'D')) {
1545         p += 2;
1546         printf("#define ");
1547
1548         while ((*p != ' ') && (*p != '\0')) {
1549
1550           if (*p == '=') {
1551             printf(" ");
1552             p ++;
1553             while ((*p != ' ') && (*p != '\0')) {
1554               printf("%c", *p);
1555               p ++;
1556             }
1557           } else {
1558             if (*p != '\n')
1559             printf("%c", *p);
1560             p ++;
1561           }
1562         }
1563
1564         printf("\n");
1565       } else p ++;
1566     }
1567 #else
1568     get_cpuconfig();
1569 #endif
1570
1571 #ifdef FORCE
1572     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1573 #else
1574 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1575     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1576 #endif
1577 #endif
1578
1579  break;
1580
1581   case '2' : /* SMP */
1582     if (get_num_cores() > 1) printf("SMP=1\n");
1583     break;
1584   }
1585
1586   fflush(stdout);
1587
1588   return 0;
1589 }
1590