1 /*****************************************************************************
2 Copyright (c) 2011-2014, The OpenBLAS Project
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are
9 1. Redistributions of source code must retain the above copyright
10 notice, this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in
14 the documentation and/or other materials provided with the
16 3. Neither the name of the OpenBLAS project nor the names of
17 its contributors may be used to endorse or promote products
18 derived from this software without specific prior written
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 **********************************************************************************/
34 /*********************************************************************/
35 /* Copyright 2009, 2010 The University of Texas at Austin. */
36 /* All rights reserved. */
38 /* Redistribution and use in source and binary forms, with or */
39 /* without modification, are permitted provided that the following */
40 /* conditions are met: */
42 /* 1. Redistributions of source code must retain the above */
43 /* copyright notice, this list of conditions and the following */
46 /* 2. Redistributions in binary form must reproduce the above */
47 /* copyright notice, this list of conditions and the following */
48 /* disclaimer in the documentation and/or other materials */
49 /* provided with the distribution. */
51 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
52 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
53 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
54 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
55 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
56 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
57 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
58 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
59 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
60 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
61 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
62 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
63 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
64 /* POSSIBILITY OF SUCH DAMAGE. */
66 /* The views and conclusions contained in the software and */
67 /* documentation are those of the authors and should not be */
68 /* interpreted as representing official policies, either expressed */
69 /* or implied, of The University of Texas at Austin. */
70 /*********************************************************************/
72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
86 #include <sys/types.h>
87 #include <sys/sysctl.h>
89 #if defined(linux) || defined(__sun__)
90 #include <sys/sysinfo.h>
94 #include <sys/sysinfo.h>
97 #if defined(__x86_64__) || defined(_M_X64)
98 #if (( defined(__GNUC__) && __GNUC__ > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
103 /* #define FORCE_P2 */
104 /* #define FORCE_KATMAI */
105 /* #define FORCE_COPPERMINE */
106 /* #define FORCE_NORTHWOOD */
107 /* #define FORCE_PRESCOTT */
108 /* #define FORCE_BANIAS */
109 /* #define FORCE_YONAH */
110 /* #define FORCE_CORE2 */
111 /* #define FORCE_PENRYN */
112 /* #define FORCE_DUNNINGTON */
113 /* #define FORCE_NEHALEM */
114 /* #define FORCE_SANDYBRIDGE */
115 /* #define FORCE_ATOM */
116 /* #define FORCE_ATHLON */
117 /* #define FORCE_OPTERON */
118 /* #define FORCE_OPTERON_SSE3 */
119 /* #define FORCE_BARCELONA */
120 /* #define FORCE_SHANGHAI */
121 /* #define FORCE_ISTANBUL */
122 /* #define FORCE_BOBCAT */
123 /* #define FORCE_BULLDOZER */
124 /* #define FORCE_PILEDRIVER */
125 /* #define FORCE_SSE_GENERIC */
126 /* #define FORCE_VIAC3 */
127 /* #define FORCE_NANO */
128 /* #define FORCE_POWER3 */
129 /* #define FORCE_POWER4 */
130 /* #define FORCE_POWER5 */
131 /* #define FORCE_POWER6 */
132 /* #define FORCE_POWER7 */
133 /* #define FORCE_POWER8 */
134 /* #define FORCE_PPCG4 */
135 /* #define FORCE_PPC970 */
136 /* #define FORCE_PPC970MP */
137 /* #define FORCE_PPC440 */
138 /* #define FORCE_PPC440FP2 */
139 /* #define FORCE_CELL */
140 /* #define FORCE_SICORTEX */
141 /* #define FORCE_LOONGSON3A */
142 /* #define FORCE_LOONGSON3B */
143 /* #define FORCE_I6400 */
144 /* #define FORCE_P6600 */
145 /* #define FORCE_P5600 */
146 /* #define FORCE_I6500 */
147 /* #define FORCE_ITANIUM2 */
148 /* #define FORCE_SPARC */
149 /* #define FORCE_SPARCV7 */
150 /* #define FORCE_ZARCH_GENERIC */
151 /* #define FORCE_Z13 */
152 /* #define FORCE_GENERIC */
157 #define ARCHITECTURE "X86"
158 #define SUBARCHITECTURE "PENTIUM2"
159 #define ARCHCONFIG "-DPENTIUM2 " \
160 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
161 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
162 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
163 "-DHAVE_CMOV -DHAVE_MMX"
165 #define CORENAME "P5"
171 #define ARCHITECTURE "X86"
172 #define SUBARCHITECTURE "PENTIUM3"
173 #define ARCHCONFIG "-DPENTIUM3 " \
174 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
175 "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
176 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
177 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
178 #define LIBNAME "katmai"
179 #define CORENAME "KATMAI"
182 #ifdef FORCE_COPPERMINE
185 #define ARCHITECTURE "X86"
186 #define SUBARCHITECTURE "PENTIUM3"
187 #define ARCHCONFIG "-DPENTIUM3 " \
188 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
189 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
190 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
191 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
192 #define LIBNAME "coppermine"
193 #define CORENAME "COPPERMINE"
196 #ifdef FORCE_NORTHWOOD
199 #define ARCHITECTURE "X86"
200 #define SUBARCHITECTURE "PENTIUM4"
201 #define ARCHCONFIG "-DPENTIUM4 " \
202 "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
203 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
204 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
205 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
206 #define LIBNAME "northwood"
207 #define CORENAME "NORTHWOOD"
210 #ifdef FORCE_PRESCOTT
213 #define ARCHITECTURE "X86"
214 #define SUBARCHITECTURE "PENTIUM4"
215 #define ARCHCONFIG "-DPENTIUM4 " \
216 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
217 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
218 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
219 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
220 #define LIBNAME "prescott"
221 #define CORENAME "PRESCOTT"
227 #define ARCHITECTURE "X86"
228 #define SUBARCHITECTURE "BANIAS"
229 #define ARCHCONFIG "-DPENTIUMM " \
230 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
231 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
232 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
233 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
234 #define LIBNAME "banias"
235 #define CORENAME "BANIAS"
241 #define ARCHITECTURE "X86"
242 #define SUBARCHITECTURE "YONAH"
243 #define ARCHCONFIG "-DPENTIUMM " \
244 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
245 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
246 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
247 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
248 #define LIBNAME "yonah"
249 #define CORENAME "YONAH"
255 #define ARCHITECTURE "X86"
256 #define SUBARCHITECTURE "CONRORE"
257 #define ARCHCONFIG "-DCORE2 " \
258 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
259 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
260 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
261 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
262 #define LIBNAME "core2"
263 #define CORENAME "CORE2"
269 #define ARCHITECTURE "X86"
270 #define SUBARCHITECTURE "PENRYN"
271 #define ARCHCONFIG "-DPENRYN " \
272 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
273 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
274 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
275 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
276 #define LIBNAME "penryn"
277 #define CORENAME "PENRYN"
280 #ifdef FORCE_DUNNINGTON
283 #define ARCHITECTURE "X86"
284 #define SUBARCHITECTURE "DUNNINGTON"
285 #define ARCHCONFIG "-DDUNNINGTON " \
286 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
287 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
288 "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
289 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
290 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
291 #define LIBNAME "dunnington"
292 #define CORENAME "DUNNINGTON"
298 #define ARCHITECTURE "X86"
299 #define SUBARCHITECTURE "NEHALEM"
300 #define ARCHCONFIG "-DNEHALEM " \
301 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
302 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
303 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
304 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
305 #define LIBNAME "nehalem"
306 #define CORENAME "NEHALEM"
309 #ifdef FORCE_SANDYBRIDGE
312 #define ARCHITECTURE "X86"
313 #define SUBARCHITECTURE "SANDYBRIDGE"
314 #define ARCHCONFIG "-DSANDYBRIDGE " \
315 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
316 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
317 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
318 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
319 #define LIBNAME "sandybridge"
320 #define CORENAME "SANDYBRIDGE"
326 #define ARCHITECTURE "X86"
327 #define SUBARCHITECTURE "HASWELL"
328 #define ARCHCONFIG "-DHASWELL " \
329 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
330 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
331 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
332 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
334 #define LIBNAME "haswell"
335 #define CORENAME "HASWELL"
338 #ifdef FORCE_SKYLAKEX
342 #define ARCHITECTURE "X86"
343 #define SUBARCHITECTURE "HASWELL"
344 #define ARCHCONFIG "-DHASWELL " \
345 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
346 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
347 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
348 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
350 #define LIBNAME "haswell"
351 #define CORENAME "HASWELL"
355 #define ARCHITECTURE "X86"
356 #define SUBARCHITECTURE "SKYLAKEX"
357 #define ARCHCONFIG "-DSKYLAKEX " \
358 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
359 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
360 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
361 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
362 "-DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
363 #define LIBNAME "skylakex"
364 #define CORENAME "SKYLAKEX"
368 #ifdef FORCE_COOPERLAKE
372 #define ARCHITECTURE "X86"
373 #define SUBARCHITECTURE "HASWELL"
374 #define ARCHCONFIG "-DHASWELL " \
375 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
376 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
377 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
378 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
380 #define LIBNAME "haswell"
381 #define CORENAME "HASWELL"
385 #define ARCHITECTURE "X86"
386 #define SUBARCHITECTURE "COOPERLAKE"
387 #define ARCHCONFIG "-DCOOPERLAKE " \
388 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
389 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
390 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
391 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
392 "-DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
393 #define LIBNAME "cooperlake"
394 #define CORENAME "COOPERLAKE"
401 #define ARCHITECTURE "X86"
402 #define SUBARCHITECTURE "ATOM"
403 #define ARCHCONFIG "-DATOM " \
404 "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
405 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
406 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
407 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
408 #define LIBNAME "atom"
409 #define CORENAME "ATOM"
415 #define ARCHITECTURE "X86"
416 #define SUBARCHITECTURE "ATHLON"
417 #define ARCHCONFIG "-DATHLON " \
418 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
419 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
420 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
421 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
422 #define LIBNAME "athlon"
423 #define CORENAME "ATHLON"
429 #define ARCHITECTURE "X86"
430 #define SUBARCHITECTURE "OPTERON"
431 #define ARCHCONFIG "-DOPTERON " \
432 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
433 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
434 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
435 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
436 #define LIBNAME "opteron"
437 #define CORENAME "OPTERON"
440 #ifdef FORCE_OPTERON_SSE3
443 #define ARCHITECTURE "X86"
444 #define SUBARCHITECTURE "OPTERON"
445 #define ARCHCONFIG "-DOPTERON " \
446 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
447 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
448 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
449 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
450 #define LIBNAME "opteron"
451 #define CORENAME "OPTERON"
454 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
457 #define ARCHITECTURE "X86"
458 #define SUBARCHITECTURE "BARCELONA"
459 #define ARCHCONFIG "-DBARCELONA " \
460 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
461 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL3_SIZE=2097152 " \
462 "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
463 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
464 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
465 #define LIBNAME "barcelona"
466 #define CORENAME "BARCELONA"
469 #if defined(FORCE_BOBCAT)
472 #define ARCHITECTURE "X86"
473 #define SUBARCHITECTURE "BOBCAT"
474 #define ARCHCONFIG "-DBOBCAT " \
475 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
476 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
477 "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
478 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
479 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
480 #define LIBNAME "bobcat"
481 #define CORENAME "BOBCAT"
484 #if defined (FORCE_BULLDOZER)
487 #define ARCHITECTURE "X86"
488 #define SUBARCHITECTURE "BULLDOZER"
489 #define ARCHCONFIG "-DBULLDOZER " \
490 "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
491 "-DL2_SIZE=1024000 -DL2_LINESIZE=64 -DL3_SIZE=16777216 " \
492 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
493 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
494 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
495 "-DHAVE_AVX -DHAVE_FMA4"
496 #define LIBNAME "bulldozer"
497 #define CORENAME "BULLDOZER"
500 #if defined (FORCE_PILEDRIVER)
503 #define ARCHITECTURE "X86"
504 #define SUBARCHITECTURE "PILEDRIVER"
505 #define ARCHCONFIG "-DPILEDRIVER " \
506 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
507 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
508 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
509 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
510 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
511 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
512 #define LIBNAME "piledriver"
513 #define CORENAME "PILEDRIVER"
516 #if defined (FORCE_STEAMROLLER)
519 #define ARCHITECTURE "X86"
520 #define SUBARCHITECTURE "STEAMROLLER"
521 #define ARCHCONFIG "-DSTEAMROLLER " \
522 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
523 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
524 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
525 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
526 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
527 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
528 #define LIBNAME "steamroller"
529 #define CORENAME "STEAMROLLER"
532 #if defined (FORCE_EXCAVATOR)
535 #define ARCHITECTURE "X86"
536 #define SUBARCHITECTURE "EXCAVATOR"
537 #define ARCHCONFIG "-DEXCAVATOR " \
538 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
539 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
540 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
541 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
542 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
543 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
544 #define LIBNAME "excavator"
545 #define CORENAME "EXCAVATOR"
548 #if defined (FORCE_ZEN)
551 #define ARCHITECTURE "X86"
552 #define SUBARCHITECTURE "ZEN"
553 #define ARCHCONFIG "-DZEN " \
554 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
555 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
556 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
557 "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
558 "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
559 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
560 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
561 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
562 "-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
563 #define LIBNAME "zen"
564 #define CORENAME "ZEN"
568 #ifdef FORCE_SSE_GENERIC
571 #define ARCHITECTURE "X86"
572 #define SUBARCHITECTURE "GENERIC"
573 #define ARCHCONFIG "-DGENERIC " \
574 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
575 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
576 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
577 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
578 #define LIBNAME "generic"
579 #define CORENAME "GENERIC"
585 #define ARCHITECTURE "X86"
586 #define SUBARCHITECTURE "VIAC3"
587 #define ARCHCONFIG "-DVIAC3 " \
588 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
589 "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
590 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
591 "-DHAVE_MMX -DHAVE_SSE "
592 #define LIBNAME "viac3"
593 #define CORENAME "VIAC3"
599 #define ARCHITECTURE "X86"
600 #define SUBARCHITECTURE "NANO"
601 #define ARCHCONFIG "-DNANO " \
602 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
603 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
604 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
605 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
606 #define LIBNAME "nano"
607 #define CORENAME "NANO"
612 #define ARCHITECTURE "POWER"
613 #define SUBARCHITECTURE "POWER3"
614 #define SUBDIRNAME "power"
615 #define ARCHCONFIG "-DPOWER3 " \
616 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
617 "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
618 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
619 #define LIBNAME "power3"
620 #define CORENAME "POWER3"
625 #define ARCHITECTURE "POWER"
626 #define SUBARCHITECTURE "POWER4"
627 #define SUBDIRNAME "power"
628 #define ARCHCONFIG "-DPOWER4 " \
629 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
630 "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
631 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
632 #define LIBNAME "power4"
633 #define CORENAME "POWER4"
638 #define ARCHITECTURE "POWER"
639 #define SUBARCHITECTURE "POWER5"
640 #define SUBDIRNAME "power"
641 #define ARCHCONFIG "-DPOWER5 " \
642 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
643 "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
644 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
645 #define LIBNAME "power5"
646 #define CORENAME "POWER5"
649 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
651 #define ARCHITECTURE "POWER"
652 #define SUBARCHITECTURE "POWER6"
653 #define SUBDIRNAME "power"
654 #define ARCHCONFIG "-DPOWER6 " \
655 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
656 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
657 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
658 #define LIBNAME "power6"
659 #define CORENAME "POWER6"
662 #if defined(FORCE_POWER8)
664 #define ARCHITECTURE "POWER"
665 #define SUBARCHITECTURE "POWER8"
666 #define SUBDIRNAME "power"
667 #define ARCHCONFIG "-DPOWER8 " \
668 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
669 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
670 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
671 #define LIBNAME "power8"
672 #define CORENAME "POWER8"
675 #if defined(FORCE_POWER9)
677 #define ARCHITECTURE "POWER"
678 #define SUBARCHITECTURE "POWER9"
679 #define SUBDIRNAME "power"
680 #define ARCHCONFIG "-DPOWER9 " \
681 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
682 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
683 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
684 #define LIBNAME "power9"
685 #define CORENAME "POWER9"
688 #if defined(FORCE_POWER10)
690 #define ARCHITECTURE "POWER"
691 #define SUBARCHITECTURE "POWER10"
692 #define SUBDIRNAME "power"
693 #define ARCHCONFIG "-DPOWER10 " \
694 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
695 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
696 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
697 #define LIBNAME "power10"
698 #define CORENAME "POWER10"
703 #define ARCHITECTURE "POWER"
704 #define SUBARCHITECTURE "PPCG4"
705 #define SUBDIRNAME "power"
706 #define ARCHCONFIG "-DPPCG4 " \
707 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
708 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
709 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
710 #define LIBNAME "ppcg4"
711 #define CORENAME "PPCG4"
716 #define ARCHITECTURE "POWER"
717 #define SUBARCHITECTURE "PPC970"
718 #define SUBDIRNAME "power"
719 #define ARCHCONFIG "-DPPC970 " \
720 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
721 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
722 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
723 #define LIBNAME "ppc970"
724 #define CORENAME "PPC970"
727 #ifdef FORCE_PPC970MP
729 #define ARCHITECTURE "POWER"
730 #define SUBARCHITECTURE "PPC970"
731 #define SUBDIRNAME "power"
732 #define ARCHCONFIG "-DPPC970 " \
733 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
734 "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
735 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
736 #define LIBNAME "ppc970mp"
737 #define CORENAME "PPC970"
742 #define ARCHITECTURE "POWER"
743 #define SUBARCHITECTURE "PPC440"
744 #define SUBDIRNAME "power"
745 #define ARCHCONFIG "-DPPC440 " \
746 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
747 "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
748 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
749 #define LIBNAME "ppc440"
750 #define CORENAME "PPC440"
753 #ifdef FORCE_PPC440FP2
755 #define ARCHITECTURE "POWER"
756 #define SUBARCHITECTURE "PPC440FP2"
757 #define SUBDIRNAME "power"
758 #define ARCHCONFIG "-DPPC440FP2 " \
759 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
760 "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
761 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
762 #define LIBNAME "ppc440FP2"
763 #define CORENAME "PPC440FP2"
768 #define ARCHITECTURE "POWER"
769 #define SUBARCHITECTURE "CELL"
770 #define SUBDIRNAME "power"
771 #define ARCHCONFIG "-DCELL " \
772 "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
773 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
774 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
775 #define LIBNAME "cell"
776 #define CORENAME "CELL"
779 #ifdef FORCE_SICORTEX
781 #define ARCHITECTURE "MIPS"
782 #define SUBARCHITECTURE "SICORTEX"
783 #define SUBDIRNAME "mips"
784 #define ARCHCONFIG "-DSICORTEX " \
785 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
786 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
787 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
788 #define LIBNAME "mips"
789 #define CORENAME "sicortex"
793 #ifdef FORCE_LOONGSON3A
795 #define ARCHITECTURE "MIPS"
796 #define SUBARCHITECTURE "LOONGSON3A"
797 #define SUBDIRNAME "mips64"
798 #define ARCHCONFIG "-DLOONGSON3A " \
799 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
800 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
801 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
802 #define LIBNAME "loongson3a"
803 #define CORENAME "LOONGSON3A"
807 #ifdef FORCE_LOONGSON3B
809 #define ARCHITECTURE "MIPS"
810 #define SUBARCHITECTURE "LOONGSON3B"
811 #define SUBDIRNAME "mips64"
812 #define ARCHCONFIG "-DLOONGSON3B " \
813 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
814 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
815 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
816 #define LIBNAME "loongson3b"
817 #define CORENAME "LOONGSON3B"
823 #define ARCHITECTURE "MIPS"
824 #define SUBARCHITECTURE "I6400"
825 #define SUBDIRNAME "mips64"
826 #define ARCHCONFIG "-DI6400 " \
827 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
828 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
829 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
830 #define LIBNAME "i6400"
831 #define CORENAME "I6400"
837 #define ARCHITECTURE "MIPS"
838 #define SUBARCHITECTURE "P6600"
839 #define SUBDIRNAME "mips64"
840 #define ARCHCONFIG "-DP6600 " \
841 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
842 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
843 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
844 #define LIBNAME "p6600"
845 #define CORENAME "P6600"
851 #define ARCHITECTURE "MIPS"
852 #define SUBARCHITECTURE "P5600"
853 #define SUBDIRNAME "mips"
854 #define ARCHCONFIG "-DP5600 " \
855 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
856 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
857 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
858 #define LIBNAME "p5600"
859 #define CORENAME "P5600"
863 #ifdef FORCE_MIPS1004K
865 #define ARCHITECTURE "MIPS"
866 #define SUBARCHITECTURE "MIPS1004K"
867 #define SUBDIRNAME "mips"
868 #define ARCHCONFIG "-DMIPS1004K " \
869 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
870 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
871 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
872 #define LIBNAME "mips1004K"
873 #define CORENAME "MIPS1004K"
879 #define ARCHITECTURE "MIPS"
880 #define SUBARCHITECTURE "MIPS24K"
881 #define SUBDIRNAME "mips"
882 #define ARCHCONFIG "-DMIPS24K " \
883 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
884 "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
885 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
886 #define LIBNAME "mips24K"
887 #define CORENAME "MIPS24K"
893 #define ARCHITECTURE "MIPS"
894 #define SUBARCHITECTURE "I6500"
895 #define SUBDIRNAME "mips64"
896 #define ARCHCONFIG "-DI6500 " \
897 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
898 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
899 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
900 #define LIBNAME "i6500"
901 #define CORENAME "I6500"
905 #ifdef FORCE_ITANIUM2
907 #define ARCHITECTURE "IA64"
908 #define SUBARCHITECTURE "ITANIUM2"
909 #define SUBDIRNAME "ia64"
910 #define ARCHCONFIG "-DITANIUM2 " \
911 "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
912 "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
913 #define LIBNAME "itanium2"
914 #define CORENAME "itanium2"
919 #define ARCHITECTURE "SPARC"
920 #define SUBARCHITECTURE "SPARC"
921 #define SUBDIRNAME "sparc"
922 #define ARCHCONFIG "-DSPARC -DV9 " \
923 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
924 "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
925 #define LIBNAME "sparc"
926 #define CORENAME "sparc"
931 #define ARCHITECTURE "SPARC"
932 #define SUBARCHITECTURE "SPARC"
933 #define SUBDIRNAME "sparc"
934 #define ARCHCONFIG "-DSPARC -DV7 " \
935 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
936 "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
937 #define LIBNAME "sparcv7"
938 #define CORENAME "sparcv7"
943 #define ARCHITECTURE "GENERIC"
944 #define SUBARCHITECTURE "GENERIC"
945 #define SUBDIRNAME "generic"
946 #define ARCHCONFIG "-DGENERIC " \
947 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
948 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
949 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
950 #define LIBNAME "generic"
951 #define CORENAME "generic"
956 #define ARCHITECTURE "ARM"
957 #define SUBARCHITECTURE "ARMV7"
958 #define SUBDIRNAME "arm"
959 #define ARCHCONFIG "-DARMV7 " \
960 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
961 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
962 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
963 "-DHAVE_VFPV3 -DHAVE_VFP"
964 #define LIBNAME "armv7"
965 #define CORENAME "ARMV7"
969 #ifdef FORCE_CORTEXA9
971 #define ARCHITECTURE "ARM"
972 #define SUBARCHITECTURE "CORTEXA9"
973 #define SUBDIRNAME "arm"
974 #define ARCHCONFIG "-DCORTEXA9 -DARMV7 " \
975 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
976 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
977 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
978 "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
979 #define LIBNAME "cortexa9"
980 #define CORENAME "CORTEXA9"
984 #ifdef FORCE_CORTEXA15
986 #define ARCHITECTURE "ARM"
987 #define SUBARCHITECTURE "CORTEXA15"
988 #define SUBDIRNAME "arm"
989 #define ARCHCONFIG "-DCORTEXA15 -DARMV7 " \
990 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
991 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
992 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
993 "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
994 #define LIBNAME "cortexa15"
995 #define CORENAME "CORTEXA15"
1001 #define ARCHITECTURE "ARM"
1002 #define SUBARCHITECTURE "ARMV6"
1003 #define SUBDIRNAME "arm"
1004 #define ARCHCONFIG "-DARMV6 " \
1005 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1006 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1007 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1009 #define LIBNAME "armv6"
1010 #define CORENAME "ARMV6"
1016 #define ARCHITECTURE "ARM"
1017 #define SUBARCHITECTURE "ARMV5"
1018 #define SUBDIRNAME "arm"
1019 #define ARCHCONFIG "-DARMV5 " \
1020 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1021 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1022 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1023 #define LIBNAME "armv5"
1024 #define CORENAME "ARMV5"
1031 #define ARCHITECTURE "ARM64"
1032 #define SUBARCHITECTURE "ARMV8"
1033 #define SUBDIRNAME "arm64"
1034 #define ARCHCONFIG "-DARMV8 " \
1035 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1036 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1037 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1038 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1039 #define LIBNAME "armv8"
1040 #define CORENAME "ARMV8"
1043 #ifdef FORCE_CORTEXA53
1045 #define ARCHITECTURE "ARM64"
1046 #define SUBARCHITECTURE "CORTEXA53"
1047 #define SUBDIRNAME "arm64"
1048 #define ARCHCONFIG "-DCORTEXA53 " \
1049 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1050 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1051 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1052 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1053 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1054 #define LIBNAME "cortexa53"
1055 #define CORENAME "CORTEXA53"
1059 #ifdef FORCE_CORTEXA57
1061 #define ARCHITECTURE "ARM64"
1062 #define SUBARCHITECTURE "CORTEXA57"
1063 #define SUBDIRNAME "arm64"
1064 #define ARCHCONFIG "-DCORTEXA57 " \
1065 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1066 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1067 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1068 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1069 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1070 #define LIBNAME "cortexa57"
1071 #define CORENAME "CORTEXA57"
1075 #ifdef FORCE_CORTEXA72
1077 #define ARCHITECTURE "ARM64"
1078 #define SUBARCHITECTURE "CORTEXA72"
1079 #define SUBDIRNAME "arm64"
1080 #define ARCHCONFIG "-DCORTEXA72 " \
1081 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1082 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1083 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1084 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1085 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1086 #define LIBNAME "cortexa72"
1087 #define CORENAME "CORTEXA72"
1091 #ifdef FORCE_CORTEXA73
1093 #define ARCHITECTURE "ARM64"
1094 #define SUBARCHITECTURE "CORTEXA73"
1095 #define SUBDIRNAME "arm64"
1096 #define ARCHCONFIG "-DCORTEXA73 " \
1097 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1098 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1099 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1100 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1101 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1102 #define LIBNAME "cortexa73"
1103 #define CORENAME "CORTEXA73"
1107 #ifdef FORCE_NEOVERSEN1
1109 #define ARCHITECTURE "ARM64"
1110 #define SUBARCHITECTURE "NEOVERSEN1"
1111 #define SUBDIRNAME "arm64"
1112 #define ARCHCONFIG "-DNEOVERSEN1 " \
1113 "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1114 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1115 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1116 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1117 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1118 "-march=armv8.2-a -mtune=cortex-a72"
1119 #define LIBNAME "neoversen1"
1120 #define CORENAME "NEOVERSEN1"
1127 #define ARCHITECTURE "ARM64"
1128 #define SUBARCHITECTURE "FALKOR"
1129 #define SUBDIRNAME "arm64"
1130 #define ARCHCONFIG "-DFALKOR " \
1131 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1132 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1133 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1134 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1135 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1136 #define LIBNAME "falkor"
1137 #define CORENAME "FALKOR"
1141 #ifdef FORCE_THUNDERX
1143 #define ARCHITECTURE "ARM64"
1144 #define SUBARCHITECTURE "THUNDERX"
1145 #define SUBDIRNAME "arm64"
1146 #define ARCHCONFIG "-DTHUNDERX " \
1147 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1148 "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1149 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1150 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1151 #define LIBNAME "thunderx"
1152 #define CORENAME "THUNDERX"
1156 #ifdef FORCE_THUNDERX2T99
1159 #define ARCHITECTURE "ARM64"
1160 #define SUBARCHITECTURE "THUNDERX2T99"
1161 #define SUBDIRNAME "arm64"
1162 #define ARCHCONFIG "-DTHUNDERX2T99 " \
1163 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1164 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1165 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1166 "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1167 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1168 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1169 #define LIBNAME "thunderx2t99"
1170 #define CORENAME "THUNDERX2T99"
1176 #define ARCHITECTURE "ARM64"
1177 #define SUBARCHITECTURE "TSV110"
1178 #define SUBDIRNAME "arm64"
1179 #define ARCHCONFIG "-DTSV110 " \
1180 "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1181 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1182 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1183 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1184 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1185 #define LIBNAME "tsv110"
1186 #define CORENAME "TSV110"
1190 #ifdef FORCE_EMAG8180
1193 #define ARCHITECTURE "ARM64"
1194 #define SUBARCHITECTURE "EMAG8180"
1195 #define SUBDIRNAME "arm64"
1196 #define ARCHCONFIG "-DEMAG8180 " \
1197 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1198 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1199 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1200 "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1201 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1202 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1203 #define LIBNAME "emag8180"
1204 #define CORENAME "EMAG8180"
1207 #ifdef FORCE_THUNDERX3T110
1210 #define ARCHITECTURE "ARM64"
1211 #define SUBARCHITECTURE "THUNDERX3T110"
1212 #define SUBDIRNAME "arm64"
1213 #define ARCHCONFIG "-DTHUNDERX3T110 " \
1214 "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1215 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1216 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1217 "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1218 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1219 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1220 #define LIBNAME "thunderx3t110"
1221 #define CORENAME "THUNDERX3T110"
1225 #ifdef FORCE_ZARCH_GENERIC
1227 #define ARCHITECTURE "ZARCH"
1228 #define SUBARCHITECTURE "ZARCH_GENERIC"
1229 #define ARCHCONFIG "-DZARCH_GENERIC " \
1230 "-DDTB_DEFAULT_ENTRIES=64"
1231 #define LIBNAME "zarch_generic"
1232 #define CORENAME "ZARCH_GENERIC"
1237 #define ARCHITECTURE "ZARCH"
1238 #define SUBARCHITECTURE "Z13"
1239 #define ARCHCONFIG "-DZ13 " \
1240 "-DDTB_DEFAULT_ENTRIES=64"
1241 #define LIBNAME "z13"
1242 #define CORENAME "Z13"
1247 #define ARCHITECTURE "ZARCH"
1248 #define SUBARCHITECTURE "Z14"
1249 #define ARCHCONFIG "-DZ14 " \
1250 "-DDTB_DEFAULT_ENTRIES=64"
1251 #define LIBNAME "z14"
1252 #define CORENAME "Z14"
1258 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1261 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1262 defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1266 #define OPENBLAS_SUPPORTED
1269 #if defined(__zarch__) || defined(__s390x__)
1271 #include "cpuid_zarch.c"
1272 #define OPENBLAS_SUPPORTED
1276 #include "cpuid_x86.c"
1277 #define OPENBLAS_SUPPORTED
1281 #include "cpuid_ia64.c"
1282 #define OPENBLAS_SUPPORTED
1286 #include "cpuid_alpha.c"
1287 #define OPENBLAS_SUPPORTED
1291 #include "cpuid_power.c"
1292 #define OPENBLAS_SUPPORTED
1296 #include "cpuid_sparc.c"
1297 #define OPENBLAS_SUPPORTED
1302 #include "cpuid_mips64.c"
1304 #include "cpuid_mips.c"
1306 #define OPENBLAS_SUPPORTED
1310 #include "cpuid_arm.c"
1311 #define OPENBLAS_SUPPORTED
1315 #include "cpuid_arm64.c"
1316 #define OPENBLAS_SUPPORTED
1320 #ifndef OPENBLAS_SUPPORTED
1321 #error "This arch/CPU is not supported by OpenBLAS."
1328 static int get_num_cores(void) {
1331 SYSTEM_INFO sysinfo;
1332 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1337 #if defined(linux) || defined(__sun__)
1338 //returns the number of processors which are currently online
1339 return sysconf(_SC_NPROCESSORS_CONF);
1341 #elif defined(OS_WINDOWS)
1343 GetSystemInfo(&sysinfo);
1344 return sysinfo.dwNumberOfProcessors;
1346 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1350 sysctl(m, 2, &count, &len, NULL, 0);
1355 //returns the number of processors which are currently online
1356 return sysconf(_SC_NPROCESSORS_ONLN);
1363 int main(int argc, char *argv[]){
1366 char buffer[8192], *p, *q;
1370 if (argc == 1) return 0;
1372 switch (argv[1][0]) {
1374 case '0' : /* for Makefile */
1377 printf("CORE=%s\n", CORENAME);
1379 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1380 printf("CORE=%s\n", get_corename());
1385 printf("LIBCORE=%s\n", LIBNAME);
1392 printf("NUM_CORES=%d\n", get_num_cores());
1394 #if defined(__arm__) && !defined(FORCE)
1404 sprintf(buffer, "%s", ARCHCONFIG);
1409 if ((*p == '-') && (*(p + 1) == 'D')) {
1412 while ((*p != ' ') && (*p != '\0')) {
1417 while ((*p != ' ') && (*p != '\0')) {
1424 if ((*p == ' ') || (*p =='\0')) printf("=1");
1434 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1435 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1436 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1437 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1439 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1440 printf("ELF_VERSION=2\n");
1444 #if MAKE_NB_JOBS > 0
1445 printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1447 // Let make use parent -j argument or -j1 if there
1448 // is no make parent
1450 #elif NO_PARALLEL_MAKE==1
1451 printf("MAKE += -j 1\n");
1453 printf("MAKE += -j %d\n", get_num_cores());
1458 case '1' : /* For config.h */
1460 sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1464 if ((*p == '-') && (*(p + 1) == 'D')) {
1468 while ((*p != ' ') && (*p != '\0')) {
1473 while ((*p != ' ') && (*p != '\0')) {
1492 printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1494 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1495 printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1501 case '2' : /* SMP */
1502 if (get_num_cores() > 1) printf("SMP=1\n");