getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93 #if defined(AIX)
  94 #include <sys/sysinfo.h>
  95 #endif
  96
  97 /* #define FORCE_P2             */
  98 /* #define FORCE_KATMAI         */
  99 /* #define FORCE_COPPERMINE     */
 100 /* #define FORCE_NORTHWOOD      */
 101 /* #define FORCE_PRESCOTT       */
 102 /* #define FORCE_BANIAS         */
 103 /* #define FORCE_YONAH          */
 104 /* #define FORCE_CORE2          */
 105 /* #define FORCE_PENRYN         */
 106 /* #define FORCE_DUNNINGTON     */
 107 /* #define FORCE_NEHALEM        */
 108 /* #define FORCE_SANDYBRIDGE    */
 109 /* #define FORCE_ATOM           */
 110 /* #define FORCE_ATHLON         */
 111 /* #define FORCE_OPTERON        */
 112 /* #define FORCE_OPTERON_SSE3   */
 113 /* #define FORCE_BARCELONA      */
 114 /* #define FORCE_SHANGHAI       */
 115 /* #define FORCE_ISTANBUL       */
 116 /* #define FORCE_BOBCAT         */
 117 /* #define FORCE_BULLDOZER      */
 118 /* #define FORCE_PILEDRIVER     */
 119 /* #define FORCE_SSE_GENERIC    */
 120 /* #define FORCE_VIAC3          */
 121 /* #define FORCE_NANO           */
 122 /* #define FORCE_POWER3         */
 123 /* #define FORCE_POWER4         */
 124 /* #define FORCE_POWER5         */
 125 /* #define FORCE_POWER6         */
 126 /* #define FORCE_POWER7         */
 127 /* #define FORCE_POWER8         */
 128 /* #define FORCE_PPCG4          */
 129 /* #define FORCE_PPC970         */
 130 /* #define FORCE_PPC970MP       */
 131 /* #define FORCE_PPC440         */
 132 /* #define FORCE_PPC440FP2      */
 133 /* #define FORCE_CELL           */
 134 /* #define FORCE_SICORTEX       */
 135 /* #define FORCE_LOONGSON3R3     */
 136 /* #define FORCE_LOONGSON3R4     */
 137 /* #define FORCE_LOONGSON3R5     */
 138 /* #define FORCE_LOONGSON2K1000  */
 139 /* #define FORCE_LOONGSONGENERIC */
 140 /* #define FORCE_I6400          */
 141 /* #define FORCE_P6600          */
 142 /* #define FORCE_P5600          */
 143 /* #define FORCE_I6500          */
 144 /* #define FORCE_ITANIUM2       */
 145 /* #define FORCE_SPARC          */
 146 /* #define FORCE_SPARCV7        */
 147 /* #define FORCE_ZARCH_GENERIC  */
 148 /* #define FORCE_Z13            */
 149 /* #define FORCE_GENERIC        */
 150
 151 #ifdef FORCE_P2
 152 #define FORCE
 153 #define FORCE_INTEL
 154 #define ARCHITECTURE    "X86"
 155 #define SUBARCHITECTURE "PENTIUM2"
 156 #define ARCHCONFIG   "-DPENTIUM2 " \
 157                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 158                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 159                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 160                      "-DHAVE_CMOV -DHAVE_MMX"
 161 #define LIBNAME   "p2"
 162 #define CORENAME  "P5"
 163 #endif
 164
 165 #ifdef FORCE_KATMAI
 166 #define FORCE
 167 #define FORCE_INTEL
 168 #define ARCHITECTURE    "X86"
 169 #define SUBARCHITECTURE "PENTIUM3"
 170 #define ARCHCONFIG   "-DPENTIUM3 " \
 171                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 172                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 173                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 174                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 175 #define LIBNAME   "katmai"
 176 #define CORENAME  "KATMAI"
 177 #endif
 178
 179 #ifdef FORCE_COPPERMINE
 180 #define FORCE
 181 #define FORCE_INTEL
 182 #define ARCHITECTURE    "X86"
 183 #define SUBARCHITECTURE "PENTIUM3"
 184 #define ARCHCONFIG   "-DPENTIUM3 " \
 185                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 186                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 187                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 188                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 189 #define LIBNAME   "coppermine"
 190 #define CORENAME  "COPPERMINE"
 191 #endif
 192
 193 #ifdef FORCE_NORTHWOOD
 194 #define FORCE
 195 #define FORCE_INTEL
 196 #define ARCHITECTURE    "X86"
 197 #define SUBARCHITECTURE "PENTIUM4"
 198 #define ARCHCONFIG   "-DPENTIUM4 " \
 199                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 200                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 201                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 202                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 203 #define LIBNAME   "northwood"
 204 #define CORENAME  "NORTHWOOD"
 205 #endif
 206
 207 #ifdef FORCE_PRESCOTT
 208 #define FORCE
 209 #define FORCE_INTEL
 210 #define ARCHITECTURE    "X86"
 211 #define SUBARCHITECTURE "PENTIUM4"
 212 #define ARCHCONFIG   "-DPENTIUM4 " \
 213                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 214                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 215                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 216                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 217 #define LIBNAME   "prescott"
 218 #define CORENAME  "PRESCOTT"
 219 #endif
 220
 221 #ifdef FORCE_BANIAS
 222 #define FORCE
 223 #define FORCE_INTEL
 224 #define ARCHITECTURE    "X86"
 225 #define SUBARCHITECTURE "BANIAS"
 226 #define ARCHCONFIG   "-DPENTIUMM " \
 227                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 228                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 229                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 230                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 231 #define LIBNAME   "banias"
 232 #define CORENAME  "BANIAS"
 233 #endif
 234
 235 #ifdef FORCE_YONAH
 236 #define FORCE
 237 #define FORCE_INTEL
 238 #define ARCHITECTURE    "X86"
 239 #define SUBARCHITECTURE "YONAH"
 240 #define ARCHCONFIG   "-DPENTIUMM " \
 241                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 242                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 243                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 244                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 245 #define LIBNAME   "yonah"
 246 #define CORENAME  "YONAH"
 247 #endif
 248
 249 #ifdef FORCE_CORE2
 250 #define FORCE
 251 #define FORCE_INTEL
 252 #define ARCHITECTURE    "X86"
 253 #define SUBARCHITECTURE "CONRORE"
 254 #define ARCHCONFIG   "-DCORE2 " \
 255                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 256                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 257                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 258                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 259 #define LIBNAME   "core2"
 260 #define CORENAME  "CORE2"
 261 #endif
 262
 263 #ifdef FORCE_PENRYN
 264 #define FORCE
 265 #define FORCE_INTEL
 266 #define ARCHITECTURE    "X86"
 267 #define SUBARCHITECTURE "PENRYN"
 268 #define ARCHCONFIG   "-DPENRYN " \
 269                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 270                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 271                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 272                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 273 #define LIBNAME   "penryn"
 274 #define CORENAME  "PENRYN"
 275 #endif
 276
 277 #ifdef FORCE_DUNNINGTON
 278 #define FORCE
 279 #define FORCE_INTEL
 280 #define ARCHITECTURE    "X86"
 281 #define SUBARCHITECTURE "DUNNINGTON"
 282 #define ARCHCONFIG   "-DDUNNINGTON " \
 283                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 284                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 285                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 286                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 287                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 288 #define LIBNAME   "dunnington"
 289 #define CORENAME  "DUNNINGTON"
 290 #endif
 291
 292 #ifdef FORCE_NEHALEM
 293 #define FORCE
 294 #define FORCE_INTEL
 295 #define ARCHITECTURE    "X86"
 296 #define SUBARCHITECTURE "NEHALEM"
 297 #define ARCHCONFIG   "-DNEHALEM " \
 298                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 299                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 300                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 301                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 302 #define LIBNAME   "nehalem"
 303 #define CORENAME  "NEHALEM"
 304 #endif
 305
 306 #ifdef FORCE_SANDYBRIDGE
 307 #define FORCE
 308 #define FORCE_INTEL
 309 #define ARCHITECTURE    "X86"
 310 #ifdef NO_AVX
 311 #define SUBARCHITECTURE "NEHALEM"
 312 #define ARCHCONFIG   "-DNEHALEM " \
 313                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 314                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 315                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 316                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 317 #define LIBNAME   "nehalem"
 318 #define CORENAME  "NEHALEM"
 319 #else
 320 #define SUBARCHITECTURE "SANDYBRIDGE"
 321 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 322                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 323                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 324                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 325                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 326 #define LIBNAME   "sandybridge"
 327 #define CORENAME  "SANDYBRIDGE"
 328 #endif
 329 #endif
 330
 331 #ifdef FORCE_HASWELL
 332 #define FORCE
 333 #define FORCE_INTEL
 334 #define ARCHITECTURE    "X86"
 335 #ifdef NO_AVX2
 336 #ifdef NO_AVX
 337 #define SUBARCHITECTURE "NEHALEM"
 338 #define ARCHCONFIG   "-DNEHALEM " \
 339                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 340                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 341                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 342                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 343 #define LIBNAME   "nehalem"
 344 #define CORENAME  "NEHALEM"
 345 #else
 346 #define SUBARCHITECTURE "SANDYBRIDGE"
 347 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 348                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 349                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 350                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 351                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 352 #define LIBNAME   "sandybridge"
 353 #define CORENAME  "SANDYBRIDGE"
 354 #endif
 355 #else
 356 #define SUBARCHITECTURE "HASWELL"
 357 #define ARCHCONFIG   "-DHASWELL " \
 358                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 359                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 360                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 361                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 362                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 363 #define LIBNAME   "haswell"
 364 #define CORENAME  "HASWELL"
 365 #endif
 366 #endif
 367
 368 #ifdef FORCE_SKYLAKEX
 369 #define FORCE
 370 #define FORCE_INTEL
 371 #define ARCHITECTURE    "X86"
 372 #ifdef NO_AVX512
 373 #ifdef NO_AVX2
 374 #ifdef NO_AVX
 375 #define SUBARCHITECTURE "NEHALEM"
 376 #define ARCHCONFIG   "-DNEHALEM " \
 377                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 378                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 379                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 380                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 381 #define LIBNAME   "nehalem"
 382 #define CORENAME  "NEHALEM"
 383 #else
 384 #define SUBARCHITECTURE "SANDYBRIDGE"
 385 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 386                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 387                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 388                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 389                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 390 #define LIBNAME   "sandybridge"
 391 #define CORENAME  "SANDYBRIDGE"
 392 #endif
 393 #else
 394 #define SUBARCHITECTURE "HASWELL"
 395 #define ARCHCONFIG   "-DHASWELL " \
 396                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 397                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 398                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 399                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 400                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 401 #define LIBNAME   "haswell"
 402 #define CORENAME  "HASWELL"
 403 #endif
 404 #else
 405 #define SUBARCHITECTURE "SKYLAKEX"
 406 #define ARCHCONFIG   "-DSKYLAKEX " \
 407                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 408                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 409                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 410                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 411                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 412 #define LIBNAME   "skylakex"
 413 #define CORENAME  "SKYLAKEX"
 414 #endif
 415 #endif
 416
 417 #ifdef FORCE_COOPERLAKE
 418 #define FORCE
 419 #define FORCE_INTEL
 420 #define ARCHITECTURE    "X86"
 421 #ifdef NO_AVX512
 422 #ifdef NO_AVX2
 423 #ifdef NO_AVX
 424 #define SUBARCHITECTURE "NEHALEM"
 425 #define ARCHCONFIG   "-DNEHALEM " \
 426                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 427                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 428                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 429                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 430 #define LIBNAME   "nehalem"
 431 #define CORENAME  "NEHALEM"
 432 #else
 433 #define SUBARCHITECTURE "SANDYBRIDGE"
 434 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 435                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 436                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 437                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 438                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 439 #define LIBNAME   "sandybridge"
 440 #define CORENAME  "SANDYBRIDGE"
 441 #endif
 442 #else
 443 #define SUBARCHITECTURE "HASWELL"
 444 #define ARCHCONFIG   "-DHASWELL " \
 445                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 446                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 447                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 448                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 449                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 450 #define LIBNAME   "haswell"
 451 #define CORENAME  "HASWELL"
 452 #endif
 453 #else
 454 #define SUBARCHITECTURE "COOPERLAKE"
 455 #define ARCHCONFIG   "-DCOOPERLAKE " \
 456                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 457                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 458                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 459                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 460                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
 461 #define LIBNAME   "cooperlake"
 462 #define CORENAME  "COOPERLAKE"
 463 #endif
 464 #endif
 465
 466 #ifdef FORCE_SAPPHIRERAPIDS
 467 #define FORCE
 468 #define FORCE_INTEL
 469 #define ARCHITECTURE    "X86"
 470 #ifdef NO_AVX512
 471 #ifdef NO_AVX2
 472 #ifdef NO_AVX
 473 #define SUBARCHITECTURE "NEHALEM"
 474 #define ARCHCONFIG   "-DNEHALEM " \
 475                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 476                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 477                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 478                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 479 #define LIBNAME   "nehalem"
 480 #define CORENAME  "NEHALEM"
 481 #else
 482 #define SUBARCHITECTURE "SANDYBRIDGE"
 483 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 484                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 485                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 486                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 487                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 488 #define LIBNAME   "sandybridge"
 489 #define CORENAME  "SANDYBRIDGE"
 490 #endif
 491 #else
 492 #define SUBARCHITECTURE "HASWELL"
 493 #define ARCHCONFIG   "-DHASWELL " \
 494                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 495                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 496                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 497                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 498                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 499 #define LIBNAME   "haswell"
 500 #define CORENAME  "HASWELL"
 501 #endif
 502 #else
 503 #define SUBARCHITECTURE "SAPPHIRERAPIDS"
 504 #define ARCHCONFIG   "-DSAPPHIRERAPIDS " \
 505                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 506                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 507                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 508                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 509                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=sapphirerapids"
 510 #define LIBNAME   "sapphirerapids"
 511 #define CORENAME  "SAPPHIRERAPIDS"
 512 #endif
 513 #endif
 514
 515 #ifdef FORCE_ATOM
 516 #define FORCE
 517 #define FORCE_INTEL
 518 #define ARCHITECTURE    "X86"
 519 #define SUBARCHITECTURE "ATOM"
 520 #define ARCHCONFIG   "-DATOM " \
 521                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 522                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 523                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 524                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 525 #define LIBNAME   "atom"
 526 #define CORENAME  "ATOM"
 527 #endif
 528
 529 #ifdef FORCE_ATHLON
 530 #define FORCE
 531 #define FORCE_INTEL
 532 #define ARCHITECTURE    "X86"
 533 #define SUBARCHITECTURE "ATHLON"
 534 #define ARCHCONFIG   "-DATHLON " \
 535                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 536                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 537                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 538                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 539 #define LIBNAME   "athlon"
 540 #define CORENAME  "ATHLON"
 541 #endif
 542
 543 #ifdef FORCE_OPTERON
 544 #define FORCE
 545 #define FORCE_INTEL
 546 #define ARCHITECTURE    "X86"
 547 #define SUBARCHITECTURE "OPTERON"
 548 #define ARCHCONFIG   "-DOPTERON " \
 549                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 550                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 551                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 552                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 553 #define LIBNAME   "opteron"
 554 #define CORENAME  "OPTERON"
 555 #endif
 556
 557 #ifdef FORCE_OPTERON_SSE3
 558 #define FORCE
 559 #define FORCE_INTEL
 560 #define ARCHITECTURE    "X86"
 561 #define SUBARCHITECTURE "OPTERON"
 562 #define ARCHCONFIG   "-DOPTERON " \
 563                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 564                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 565                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 566                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 567 #define LIBNAME   "opteron"
 568 #define CORENAME  "OPTERON"
 569 #endif
 570
 571 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 572 #define FORCE
 573 #define FORCE_INTEL
 574 #define ARCHITECTURE    "X86"
 575 #define SUBARCHITECTURE "BARCELONA"
 576 #define ARCHCONFIG   "-DBARCELONA " \
 577                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 578                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 579                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 580                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 581                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 582 #define LIBNAME   "barcelona"
 583 #define CORENAME  "BARCELONA"
 584 #endif
 585
 586 #if defined(FORCE_BOBCAT)
 587 #define FORCE
 588 #define FORCE_INTEL
 589 #define ARCHITECTURE    "X86"
 590 #define SUBARCHITECTURE "BOBCAT"
 591 #define ARCHCONFIG   "-DBOBCAT " \
 592                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 593                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 594                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 595                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 596                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 597 #define LIBNAME   "bobcat"
 598 #define CORENAME  "BOBCAT"
 599 #endif
 600
 601 #if defined (FORCE_BULLDOZER)
 602 #define FORCE
 603 #define FORCE_INTEL
 604 #define ARCHITECTURE    "X86"
 605 #define SUBARCHITECTURE "BULLDOZER"
 606 #define ARCHCONFIG   "-DBULLDOZER " \
 607                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 608                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 609                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 610                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 611                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 612                      "-DHAVE_AVX"
 613 #define LIBNAME   "bulldozer"
 614 #define CORENAME  "BULLDOZER"
 615 #endif
 616
 617 #if defined (FORCE_PILEDRIVER)
 618 #define FORCE
 619 #define FORCE_INTEL
 620 #define ARCHITECTURE    "X86"
 621 #define SUBARCHITECTURE "PILEDRIVER"
 622 #define ARCHCONFIG   "-DPILEDRIVER " \
 623                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 624                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 625                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 626                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 627                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 628                      "-DHAVE_AVX -DHAVE_FMA3"
 629 #define LIBNAME   "piledriver"
 630 #define CORENAME  "PILEDRIVER"
 631 #endif
 632
 633 #if defined (FORCE_STEAMROLLER)
 634 #define FORCE
 635 #define FORCE_INTEL
 636 #define ARCHITECTURE    "X86"
 637 #define SUBARCHITECTURE "STEAMROLLER"
 638 #define ARCHCONFIG   "-DSTEAMROLLER " \
 639                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 640                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 641                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 642                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 643                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 644                      "-DHAVE_AVX -DHAVE_FMA3"
 645 #define LIBNAME   "steamroller"
 646 #define CORENAME  "STEAMROLLER"
 647 #endif
 648
 649 #if defined (FORCE_EXCAVATOR)
 650 #define FORCE
 651 #define FORCE_INTEL
 652 #define ARCHITECTURE    "X86"
 653 #define SUBARCHITECTURE "EXCAVATOR"
 654 #define ARCHCONFIG   "-DEXCAVATOR " \
 655                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 656                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 657                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 658                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 659                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 660                      "-DHAVE_AVX -DHAVE_FMA3"
 661 #define LIBNAME   "excavator"
 662 #define CORENAME  "EXCAVATOR"
 663 #endif
 664
 665 #if defined (FORCE_ZEN)
 666 #define FORCE
 667 #define FORCE_INTEL
 668 #define ARCHITECTURE    "X86"
 669 #ifdef NO_AVX2
 670 #ifdef NO_AVX
 671 #define SUBARCHITECTURE "NEHALEM"
 672 #define ARCHCONFIG   "-DNEHALEM " \
 673                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 674                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 675                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 676                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 677 #define LIBNAME   "nehalem"
 678 #define CORENAME  "NEHALEM"
 679 #else
 680 #define SUBARCHITECTURE "SANDYBRIDGE"
 681 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 682                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 683                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 684                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 685                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 686 #define LIBNAME   "sandybridge"
 687 #define CORENAME  "SANDYBRIDGE"
 688 #endif
 689 #else
 690 #define SUBARCHITECTURE "ZEN"
 691 #define ARCHCONFIG   "-DZEN " \
 692                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 693                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 694                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 695                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 696                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 697                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 698                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 699                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 700                      "-DHAVE_AVX -DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 701 #define LIBNAME   "zen"
 702 #define CORENAME  "ZEN"
 703 #endif
 704 #endif
 705
 706
 707 #ifdef FORCE_SSE_GENERIC
 708 #define FORCE
 709 #define FORCE_INTEL
 710 #define ARCHITECTURE    "X86"
 711 #define SUBARCHITECTURE "GENERIC"
 712 #define ARCHCONFIG   "-DGENERIC " \
 713                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 714                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 715                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 716                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 717 #define LIBNAME   "generic"
 718 #define CORENAME  "GENERIC"
 719 #endif
 720
 721 #ifdef FORCE_VIAC3
 722 #define FORCE
 723 #define FORCE_INTEL
 724 #define ARCHITECTURE    "X86"
 725 #define SUBARCHITECTURE "VIAC3"
 726 #define ARCHCONFIG   "-DVIAC3 " \
 727                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 728                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 729                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 730                      "-DHAVE_MMX -DHAVE_SSE "
 731 #define LIBNAME   "viac3"
 732 #define CORENAME  "VIAC3"
 733 #endif
 734
 735 #ifdef FORCE_NANO
 736 #define FORCE
 737 #define FORCE_INTEL
 738 #define ARCHITECTURE    "X86"
 739 #define SUBARCHITECTURE "NANO"
 740 #define ARCHCONFIG   "-DNANO " \
 741                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 742                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 743                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 744                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 745 #define LIBNAME   "nano"
 746 #define CORENAME  "NANO"
 747 #endif
 748
 749 #ifdef FORCE_POWER3
 750 #define FORCE
 751 #define ARCHITECTURE    "POWER"
 752 #define SUBARCHITECTURE "POWER3"
 753 #define SUBDIRNAME      "power"
 754 #define ARCHCONFIG   "-DPOWER3 " \
 755                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 756                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 757                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 758 #define LIBNAME   "power3"
 759 #define CORENAME  "POWER3"
 760 #endif
 761
 762 #ifdef FORCE_POWER4
 763 #define FORCE
 764 #define ARCHITECTURE    "POWER"
 765 #define SUBARCHITECTURE "POWER4"
 766 #define SUBDIRNAME      "power"
 767 #define ARCHCONFIG   "-DPOWER4 " \
 768                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 769                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 770                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 771 #define LIBNAME   "power4"
 772 #define CORENAME  "POWER4"
 773 #endif
 774
 775 #ifdef FORCE_POWER5
 776 #define FORCE
 777 #define ARCHITECTURE    "POWER"
 778 #define SUBARCHITECTURE "POWER5"
 779 #define SUBDIRNAME      "power"
 780 #define ARCHCONFIG   "-DPOWER5 " \
 781                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 782                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 783                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 784 #define LIBNAME   "power5"
 785 #define CORENAME  "POWER5"
 786 #endif
 787
 788 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 789 #define FORCE
 790 #define ARCHITECTURE    "POWER"
 791 #define SUBARCHITECTURE "POWER6"
 792 #define SUBDIRNAME      "power"
 793 #define ARCHCONFIG   "-DPOWER6 " \
 794                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 795                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 796                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 797 #define LIBNAME   "power6"
 798 #define CORENAME  "POWER6"
 799 #endif
 800
 801 #if defined(FORCE_POWER8)
 802 #define FORCE
 803 #define ARCHITECTURE    "POWER"
 804 #define SUBARCHITECTURE "POWER8"
 805 #define SUBDIRNAME      "power"
 806 #define ARCHCONFIG   "-DPOWER8 " \
 807                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 808                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 809                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 810 #define LIBNAME   "power8"
 811 #define CORENAME  "POWER8"
 812 #endif
 813
 814 #if defined(FORCE_POWER9)
 815 #define FORCE
 816 #define ARCHITECTURE    "POWER"
 817 #define SUBARCHITECTURE "POWER9"
 818 #define SUBDIRNAME      "power"
 819 #define ARCHCONFIG   "-DPOWER9 " \
 820                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 821                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 822                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 823 #define LIBNAME   "power9"
 824 #define CORENAME  "POWER9"
 825 #endif
 826
 827 #if defined(FORCE_POWER10)
 828 #define FORCE
 829 #define ARCHITECTURE    "POWER"
 830 #define SUBARCHITECTURE "POWER10"
 831 #define SUBDIRNAME      "power"
 832 #define ARCHCONFIG   "-DPOWER10 " \
 833                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 834                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 835                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 836 #define LIBNAME   "power10"
 837 #define CORENAME  "POWER10"
 838 #endif
 839
 840 #ifdef FORCE_PPCG4
 841 #define FORCE
 842 #define ARCHITECTURE    "POWER"
 843 #define SUBARCHITECTURE "PPCG4"
 844 #define SUBDIRNAME      "power"
 845 #define ARCHCONFIG   "-DPPCG4 " \
 846                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 847                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 848                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 849 #define LIBNAME   "ppcg4"
 850 #define CORENAME  "PPCG4"
 851 #endif
 852
 853 #ifdef FORCE_PPC970
 854 #define FORCE
 855 #define ARCHITECTURE    "POWER"
 856 #define SUBARCHITECTURE "PPC970"
 857 #define SUBDIRNAME      "power"
 858 #define ARCHCONFIG   "-DPPC970 " \
 859                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 860                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 861                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 862 #define LIBNAME   "ppc970"
 863 #define CORENAME  "PPC970"
 864 #endif
 865
 866 #ifdef FORCE_PPC970MP
 867 #define FORCE
 868 #define ARCHITECTURE    "POWER"
 869 #define SUBARCHITECTURE "PPC970"
 870 #define SUBDIRNAME      "power"
 871 #define ARCHCONFIG   "-DPPC970 " \
 872                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 873                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 874                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 875 #define LIBNAME   "ppc970mp"
 876 #define CORENAME  "PPC970"
 877 #endif
 878
 879 #ifdef FORCE_PPC440
 880 #define FORCE
 881 #define ARCHITECTURE    "POWER"
 882 #define SUBARCHITECTURE "PPC440"
 883 #define SUBDIRNAME      "power"
 884 #define ARCHCONFIG   "-DPPC440 " \
 885                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 886                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 887                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 888 #define LIBNAME   "ppc440"
 889 #define CORENAME  "PPC440"
 890 #endif
 891
 892 #ifdef FORCE_PPC440FP2
 893 #define FORCE
 894 #define ARCHITECTURE    "POWER"
 895 #define SUBARCHITECTURE "PPC440FP2"
 896 #define SUBDIRNAME      "power"
 897 #define ARCHCONFIG   "-DPPC440FP2 " \
 898                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 899                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 900                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 901 #define LIBNAME   "ppc440FP2"
 902 #define CORENAME  "PPC440FP2"
 903 #endif
 904
 905 #ifdef FORCE_CELL
 906 #define FORCE
 907 #define ARCHITECTURE    "POWER"
 908 #define SUBARCHITECTURE "CELL"
 909 #define SUBDIRNAME      "power"
 910 #define ARCHCONFIG   "-DCELL " \
 911                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 912                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 913                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 914 #define LIBNAME   "cell"
 915 #define CORENAME  "CELL"
 916 #endif
 917
 918 #ifdef FORCE_SICORTEX
 919 #define FORCE
 920 #define ARCHITECTURE    "MIPS"
 921 #define SUBARCHITECTURE "SICORTEX"
 922 #define SUBDIRNAME      "mips"
 923 #define ARCHCONFIG   "-DSICORTEX " \
 924                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 925                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 926                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 927 #define LIBNAME   "mips"
 928 #define CORENAME  "sicortex"
 929 #endif
 930
 931
 932 #if defined FORCE_LOONGSON3R3 || defined FORCE_LOONGSON3A || defined FORCE_LOONGSON3B
 933 #define FORCE
 934 #define ARCHITECTURE    "MIPS"
 935 #define SUBARCHITECTURE "LOONGSON3R3"
 936 #define SUBDIRNAME      "mips64"
 937 #define ARCHCONFIG   "-DLOONGSON3R3 " \
 938        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 939        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 940        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 941 #define LIBNAME   "loongson3r3"
 942 #define CORENAME  "LOONGSON3R3"
 943 #else
 944 #endif
 945
 946 #ifdef FORCE_LOONGSON3R4
 947 #define FORCE
 948 #define ARCHITECTURE    "MIPS"
 949 #define SUBARCHITECTURE "LOONGSON3R4"
 950 #define SUBDIRNAME      "mips64"
 951 #define ARCHCONFIG   "-DLOONGSON3R4 " \
 952        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 953        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 954        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 955 #define LIBNAME   "loongson3r4"
 956 #define CORENAME  "LOONGSON3R4"
 957 #else
 958 #endif
 959
 960 #ifdef FORCE_LOONGSON3R5
 961 #define FORCE
 962 #define ARCHITECTURE    "LOONGARCH"
 963 #define SUBARCHITECTURE "LOONGSON3R5"
 964 #define SUBDIRNAME      "loongarch64"
 965 #define ARCHCONFIG   "-DLOONGSON3R5 " \
 966        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 967        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 968        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 969 #define LIBNAME   "loongson3r5"
 970 #define CORENAME  "LOONGSON3R5"
 971 #else
 972 #endif
 973
 974 #ifdef FORCE_LOONGSON2K1000
 975 #define FORCE
 976 #define ARCHITECTURE    "LOONGARCH"
 977 #define SUBARCHITECTURE "LOONGSON2K1000"
 978 #define SUBDIRNAME      "loongarch64"
 979 #define ARCHCONFIG   "-DLOONGSON2K1000 " \
 980        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 981        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 982        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 983 #define LIBNAME   "loongson2k1000"
 984 #define CORENAME  "LOONGSON2K1000"
 985 #else
 986 #endif
 987
 988 #ifdef FORCE_LOONGSONGENERIC
 989 #define FORCE
 990 #define ARCHITECTURE    "LOONGARCH"
 991 #define SUBARCHITECTURE "LOONGSONGENERIC"
 992 #define SUBDIRNAME      "loongarch64"
 993 #define ARCHCONFIG   "-DLOONGSONGENERIC " \
 994        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 995        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 996        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 997 #define LIBNAME   "loongsongeneric"
 998 #define CORENAME  "LOONGSONGENERIC"
 999 #else
1000 #endif
1001
1002 #ifdef FORCE_I6400
1003 #define FORCE
1004 #define ARCHITECTURE    "MIPS"
1005 #define SUBARCHITECTURE "I6400"
1006 #define SUBDIRNAME      "mips64"
1007 #define ARCHCONFIG   "-DI6400 " \
1008        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1009        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1010        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1011 #define LIBNAME   "i6400"
1012 #define CORENAME  "I6400"
1013 #else
1014 #endif
1015
1016 #ifdef FORCE_P6600
1017 #define FORCE
1018 #define ARCHITECTURE    "MIPS"
1019 #define SUBARCHITECTURE "P6600"
1020 #define SUBDIRNAME      "mips64"
1021 #define ARCHCONFIG   "-DP6600 " \
1022        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1023        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1024        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1025 #define LIBNAME   "p6600"
1026 #define CORENAME  "P6600"
1027 #else
1028 #endif
1029
1030 #ifdef FORCE_P5600
1031 #define FORCE
1032 #define ARCHITECTURE    "MIPS"
1033 #define SUBARCHITECTURE "P5600"
1034 #define SUBDIRNAME      "mips"
1035 #define ARCHCONFIG   "-DP5600 " \
1036        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1037        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1038        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1039 #define LIBNAME   "p5600"
1040 #define CORENAME  "P5600"
1041 #else
1042 #endif
1043
1044 #ifdef FORCE_MIPS1004K
1045 #define FORCE
1046 #define ARCHITECTURE    "MIPS"
1047 #define SUBARCHITECTURE "MIPS1004K"
1048 #define SUBDIRNAME      "mips"
1049 #define ARCHCONFIG   "-DMIPS1004K " \
1050        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1051        "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
1052        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1053 #define LIBNAME   "mips1004K"
1054 #define CORENAME  "MIPS1004K"
1055 #else
1056 #endif
1057
1058 #ifdef FORCE_MIPS24K
1059 #define FORCE
1060 #define ARCHITECTURE    "MIPS"
1061 #define SUBARCHITECTURE "MIPS24K"
1062 #define SUBDIRNAME      "mips"
1063 #define ARCHCONFIG   "-DMIPS24K " \
1064        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1065        "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
1066        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1067 #define LIBNAME   "mips24K"
1068 #define CORENAME  "MIPS24K"
1069 #else
1070 #endif
1071
1072 #ifdef FORCE_I6500
1073 #define FORCE
1074 #define ARCHITECTURE    "MIPS"
1075 #define SUBARCHITECTURE "I6500"
1076 #define SUBDIRNAME      "mips64"
1077 #define ARCHCONFIG   "-DI6500 " \
1078        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1079        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1080        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1081 #define LIBNAME   "i6500"
1082 #define CORENAME  "I6500"
1083 #else
1084 #endif
1085
1086 #ifdef FORCE_ITANIUM2
1087 #define FORCE
1088 #define ARCHITECTURE    "IA64"
1089 #define SUBARCHITECTURE "ITANIUM2"
1090 #define SUBDIRNAME      "ia64"
1091 #define ARCHCONFIG   "-DITANIUM2 " \
1092                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
1093                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
1094 #define LIBNAME   "itanium2"
1095 #define CORENAME  "itanium2"
1096 #endif
1097
1098 #ifdef FORCE_SPARC
1099 #define FORCE
1100 #define ARCHITECTURE    "SPARC"
1101 #define SUBARCHITECTURE "SPARC"
1102 #define SUBDIRNAME      "sparc"
1103 #define ARCHCONFIG   "-DSPARC -DV9 " \
1104                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1105                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1106 #define LIBNAME   "sparc"
1107 #define CORENAME  "sparc"
1108 #endif
1109
1110 #ifdef FORCE_SPARCV7
1111 #define FORCE
1112 #define ARCHITECTURE    "SPARC"
1113 #define SUBARCHITECTURE "SPARC"
1114 #define SUBDIRNAME      "sparc"
1115 #define ARCHCONFIG   "-DSPARC -DV7 " \
1116                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1117                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1118 #define LIBNAME   "sparcv7"
1119 #define CORENAME  "sparcv7"
1120 #endif
1121
1122 #ifdef FORCE_GENERIC
1123 #define FORCE
1124 #define ARCHITECTURE    "GENERIC"
1125 #define SUBARCHITECTURE "GENERIC"
1126 #define SUBDIRNAME      "generic"
1127 #define ARCHCONFIG   "-DGENERIC " \
1128                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1129                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
1130                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1131 #define LIBNAME   "generic"
1132 #define CORENAME  "generic"
1133 #endif
1134
1135 #ifdef FORCE_ARMV7
1136 #define FORCE
1137 #define ARCHITECTURE    "ARM"
1138 #define SUBARCHITECTURE "ARMV7"
1139 #define SUBDIRNAME      "arm"
1140 #define ARCHCONFIG   "-DARMV7 " \
1141        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1142        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1143        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1144        "-DHAVE_VFPV3 -DHAVE_VFP"
1145 #define LIBNAME   "armv7"
1146 #define CORENAME  "ARMV7"
1147 #else
1148 #endif
1149
1150 #ifdef FORCE_CORTEXA9
1151 #define FORCE
1152 #define ARCHITECTURE    "ARM"
1153 #define SUBARCHITECTURE "CORTEXA9"
1154 #define SUBDIRNAME      "arm"
1155 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
1156        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1157        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1158        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1159        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1160 #define LIBNAME   "cortexa9"
1161 #define CORENAME  "CORTEXA9"
1162 #else
1163 #endif
1164
1165 #ifdef FORCE_RISCV64_GENERIC
1166 #define FORCE
1167 #define ARCHITECTURE    "RISCV64"
1168 #define SUBARCHITECTURE "RISCV64_GENERIC"
1169 #define SUBDIRNAME      "riscv64"
1170 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
1171        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1172        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1173        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1174 #define LIBNAME   "riscv64_generic"
1175 #define CORENAME  "RISCV64_GENERIC"
1176 #else
1177 #endif
1178
1179 #ifdef FORCE_CORTEXA15
1180 #define FORCE
1181 #define ARCHITECTURE    "ARM"
1182 #define SUBARCHITECTURE "CORTEXA15"
1183 #define SUBDIRNAME      "arm"
1184 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
1185        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1186        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1187        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1188        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1189 #define LIBNAME   "cortexa15"
1190 #define CORENAME  "CORTEXA15"
1191 #else
1192 #endif
1193
1194 #ifdef FORCE_ARMV6
1195 #define FORCE
1196 #define ARCHITECTURE    "ARM"
1197 #define SUBARCHITECTURE "ARMV6"
1198 #define SUBDIRNAME      "arm"
1199 #define ARCHCONFIG   "-DARMV6 " \
1200        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1201        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1202        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1203        "-DHAVE_VFP"
1204 #define LIBNAME   "armv6"
1205 #define CORENAME  "ARMV6"
1206 #else
1207 #endif
1208
1209 #ifdef FORCE_ARMV5
1210 #define FORCE
1211 #define ARCHITECTURE    "ARM"
1212 #define SUBARCHITECTURE "ARMV5"
1213 #define SUBDIRNAME      "arm"
1214 #define ARCHCONFIG   "-DARMV5 " \
1215        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1216        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1217        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1218 #define LIBNAME   "armv5"
1219 #define CORENAME  "ARMV5"
1220 #else
1221 #endif
1222
1223 #ifdef FORCE_ARMV8SVE
1224 #define FORCE
1225 #define ARCHITECTURE    "ARM64"
1226 #define SUBARCHITECTURE "ARMV8SVE"
1227 #define SUBDIRNAME      "arm64"
1228 #define ARCHCONFIG   "-DARMV8SVE " \
1229        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1230        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1231        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1232        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8"
1233 #define LIBNAME   "armv8sve"
1234 #define CORENAME  "ARMV8SVE"
1235 #endif
1236
1237
1238 #ifdef FORCE_ARMV8
1239 #define FORCE
1240 #define ARCHITECTURE    "ARM64"
1241 #define SUBARCHITECTURE "ARMV8"
1242 #define SUBDIRNAME      "arm64"
1243 #define ARCHCONFIG   "-DARMV8 " \
1244        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1245        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1246        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1247        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1248 #define LIBNAME   "armv8"
1249 #define CORENAME  "ARMV8"
1250 #endif
1251
1252 #ifdef FORCE_CORTEXA53
1253 #define FORCE
1254 #define ARCHITECTURE    "ARM64"
1255 #define SUBARCHITECTURE "CORTEXA53"
1256 #define SUBDIRNAME      "arm64"
1257 #define ARCHCONFIG   "-DCORTEXA53 " \
1258        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1259        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1260        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1261        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1262        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1263 #define LIBNAME   "cortexa53"
1264 #define CORENAME  "CORTEXA53"
1265 #endif
1266
1267 #ifdef FORCE_CORTEXA57
1268 #define FORCE
1269 #define ARCHITECTURE    "ARM64"
1270 #define SUBARCHITECTURE "CORTEXA57"
1271 #define SUBDIRNAME      "arm64"
1272 #define ARCHCONFIG   "-DCORTEXA57 " \
1273        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1274        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1275        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1276        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1277        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1278 #define LIBNAME   "cortexa57"
1279 #define CORENAME  "CORTEXA57"
1280 #endif
1281
1282 #ifdef FORCE_CORTEXA72
1283 #define FORCE
1284 #define ARCHITECTURE    "ARM64"
1285 #define SUBARCHITECTURE "CORTEXA72"
1286 #define SUBDIRNAME      "arm64"
1287 #define ARCHCONFIG   "-DCORTEXA72 " \
1288        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1289        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1290        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1291        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1292        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1293 #define LIBNAME   "cortexa72"
1294 #define CORENAME  "CORTEXA72"
1295 #endif
1296
1297 #ifdef FORCE_CORTEXA73
1298 #define FORCE
1299 #define ARCHITECTURE    "ARM64"
1300 #define SUBARCHITECTURE "CORTEXA73"
1301 #define SUBDIRNAME      "arm64"
1302 #define ARCHCONFIG   "-DCORTEXA73 " \
1303        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1304        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1305        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1306        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1307        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1308 #define LIBNAME   "cortexa73"
1309 #define CORENAME  "CORTEXA73"
1310 #endif
1311
1312 #ifdef FORCE_CORTEXX1
1313 #define FORCE
1314 #define ARCHITECTURE    "ARM64"
1315 #define SUBARCHITECTURE "CORTEXX1"
1316 #define SUBDIRNAME      "arm64"
1317 #define ARCHCONFIG   "-DCORTEXX1 " \
1318        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1319        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1320        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1321        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1322 #define LIBNAME   "cortexx1"
1323 #define CORENAME  "CORTEXX1"
1324 #endif
1325
1326 #ifdef FORCE_CORTEXX2
1327 #define FORCE
1328 #define ARCHITECTURE    "ARM64"
1329 #define SUBARCHITECTURE "CORTEXX2"
1330 #define SUBDIRNAME      "arm64"
1331 #define ARCHCONFIG   "-DCORTEXX2 " \
1332        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1333        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1334        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1335        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1336 #define LIBNAME   "cortexx2"
1337 #define CORENAME  "CORTEXX2"
1338 #endif
1339
1340 #ifdef FORCE_CORTEXA510
1341 #define FORCE
1342 #define ARCHITECTURE    "ARM64"
1343 #define SUBARCHITECTURE "CORTEXA510"
1344 #define SUBDIRNAME      "arm64"
1345 #define ARCHCONFIG   "-DCORTEXA510 " \
1346        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1347        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1348        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1349        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1350 #define LIBNAME   "cortexa510"
1351 #define CORENAME  "CORTEXA510"
1352 #endif
1353
1354 #ifdef FORCE_CORTEXA710
1355 #define FORCE
1356 #define ARCHITECTURE    "ARM64"
1357 #define SUBARCHITECTURE "CORTEXA710"
1358 #define SUBDIRNAME      "arm64"
1359 #define ARCHCONFIG   "-DCORTEXA710 " \
1360        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1361        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1362        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1363        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1364 #define LIBNAME   "cortexa710"
1365 #define CORENAME  "CORTEXA710"
1366 #endif
1367
1368 #ifdef FORCE_NEOVERSEN1
1369 #define FORCE
1370 #define ARCHITECTURE    "ARM64"
1371 #define SUBARCHITECTURE "NEOVERSEN1"
1372 #define SUBDIRNAME      "arm64"
1373 #define ARCHCONFIG   "-DNEOVERSEN1 " \
1374        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1375        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1376        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1377        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1378        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1379        "-march=armv8.2-a -mtune=neoverse-n1"
1380 #define LIBNAME   "neoversen1"
1381 #define CORENAME  "NEOVERSEN1"
1382 #endif
1383
1384 #ifdef FORCE_NEOVERSEV1
1385 #define FORCE
1386 #define ARCHITECTURE    "ARM64"
1387 #define SUBARCHITECTURE "NEOVERSEV1"
1388 #define SUBDIRNAME      "arm64"
1389 #define ARCHCONFIG   "-DNEOVERSEV1 " \
1390        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1391        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1392        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1393        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1394        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 " \
1395        "-march=armv8.4-a -mtune=neoverse-v1"
1396 #define LIBNAME   "neoversev1"
1397 #define CORENAME  "NEOVERSEV1"
1398 #endif
1399
1400
1401 #ifdef FORCE_NEOVERSEN2
1402 #define FORCE
1403 #define ARCHITECTURE    "ARM64"
1404 #define SUBARCHITECTURE "NEOVERSEN2"
1405 #define SUBDIRNAME      "arm64"
1406 #define ARCHCONFIG   "-DNEOVERSEN2 " \
1407        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1408        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1409        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1410        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1411        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 " \
1412        "-march=armv8.5-a -mtune=neoverse-n2"
1413 #define LIBNAME   "neoversen2"
1414 #define CORENAME  "NEOVERSEN2"
1415 #endif
1416
1417 #ifdef FORCE_CORTEXA55
1418 #define FORCE
1419 #define ARCHITECTURE    "ARM64"
1420 #define SUBARCHITECTURE "CORTEXA55"
1421 #define SUBDIRNAME      "arm64"
1422 #define ARCHCONFIG   "-DCORTEXA55 " \
1423        "-DL1_CODE_SIZE=16384 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1424        "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1425        "-DL2_SIZE=65536 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1426        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1427        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1428 #define LIBNAME   "cortexa55"
1429 #define CORENAME  "CORTEXA55"
1430 #endif
1431
1432 #ifdef FORCE_FALKOR
1433 #define FORCE
1434 #define ARCHITECTURE    "ARM64"
1435 #define SUBARCHITECTURE "FALKOR"
1436 #define SUBDIRNAME      "arm64"
1437 #define ARCHCONFIG   "-DFALKOR " \
1438        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1439        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1440        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1441        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1442        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1443 #define LIBNAME   "falkor"
1444 #define CORENAME  "FALKOR"
1445 #endif
1446
1447 #ifdef FORCE_THUNDERX
1448 #define FORCE
1449 #define ARCHITECTURE    "ARM64"
1450 #define SUBARCHITECTURE "THUNDERX"
1451 #define SUBDIRNAME      "arm64"
1452 #define ARCHCONFIG   "-DTHUNDERX " \
1453        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1454        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1455        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1456        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1457 #define LIBNAME   "thunderx"
1458 #define CORENAME  "THUNDERX"
1459 #endif
1460
1461 #ifdef FORCE_THUNDERX2T99
1462 #define ARMV8
1463 #define FORCE
1464 #define ARCHITECTURE    "ARM64"
1465 #define SUBARCHITECTURE "THUNDERX2T99"
1466 #define SUBDIRNAME      "arm64"
1467 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1468        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1469        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1470        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1471        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1472        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1473        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1474 #define LIBNAME   "thunderx2t99"
1475 #define CORENAME  "THUNDERX2T99"
1476 #endif
1477
1478 #ifdef FORCE_TSV110
1479 #define FORCE
1480 #define ARCHITECTURE    "ARM64"
1481 #define SUBARCHITECTURE "TSV110"
1482 #define SUBDIRNAME      "arm64"
1483 #define ARCHCONFIG   "-DTSV110 " \
1484        "-DL1_CODE_SIZE=65536  -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1485        "-DL1_DATA_SIZE=65536  -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1486        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1487        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1488        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1489 #define LIBNAME   "tsv110"
1490 #define CORENAME  "TSV110"
1491 #endif
1492
1493 #ifdef FORCE_EMAG8180
1494 #define ARMV8
1495 #define FORCE
1496 #define ARCHITECTURE    "ARM64"
1497 #define SUBARCHITECTURE "EMAG8180"
1498 #define SUBDIRNAME      "arm64"
1499 #define ARCHCONFIG   "-DEMAG8180 " \
1500        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1501        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1502        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1503        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1504        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1505        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1506 #define LIBNAME   "emag8180"
1507 #define CORENAME  "EMAG8180"
1508 #endif
1509
1510 #ifdef FORCE_THUNDERX3T110
1511 #define ARMV8
1512 #define FORCE
1513 #define ARCHITECTURE    "ARM64"
1514 #define SUBARCHITECTURE "THUNDERX3T110"
1515 #define SUBDIRNAME      "arm64"
1516 #define ARCHCONFIG   "-DTHUNDERX3T110 " \
1517        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1518        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1519        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1520        "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1521        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1522        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1523 #define LIBNAME   "thunderx3t110"
1524 #define CORENAME  "THUNDERX3T110"
1525 #endif
1526
1527 #ifdef FORCE_VORTEX
1528 #define FORCE
1529 #define ARCHITECTURE    "ARM64"
1530 #define SUBARCHITECTURE "VORTEX"
1531 #define SUBDIRNAME      "arm64"
1532 #define ARCHCONFIG   "-DVORTEX " \
1533        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1534        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1535        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1536        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1537 #define LIBNAME   "vortex"
1538 #define CORENAME  "VORTEX"
1539 #endif
1540
1541 #ifdef FORCE_A64FX
1542 #define ARMV8
1543 #define FORCE
1544 #define ARCHITECTURE    "ARM64"
1545 #define SUBARCHITECTURE "A64FX"
1546 #define SUBDIRNAME      "arm64"
1547 #define ARCHCONFIG   "-DA64FX " \
1548        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=256 -DL1_CODE_ASSOCIATIVE=8 " \
1549        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=256 -DL1_DATA_ASSOCIATIVE=8 " \
1550        "-DL2_SIZE=8388608 -DL2_LINESIZE=256 -DL2_ASSOCIATIVE=8 " \
1551        "-DL3_SIZE=0 -DL3_LINESIZE=0 -DL3_ASSOCIATIVE=0 " \
1552        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1553        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8"
1554 #define LIBNAME   "a64fx"
1555 #define CORENAME  "A64FX"
1556 #endif
1557
1558 #ifdef FORCE_FT2000
1559 #define ARMV8
1560 #define FORCE
1561 #define ARCHITECTURE    "ARM64"
1562 #define SUBARCHITECTURE "FT2000"
1563 #define SUBDIRNAME      "arm64"
1564 #define ARCHCONFIG   "-DFT2000 " \
1565        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1566        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1567        "-DL2_SIZE=33554426-DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1568        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1569        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1570 #define LIBNAME   "ft2000"
1571 #define CORENAME  "FT2000"
1572 #endif
1573
1574 #ifdef FORCE_ZARCH_GENERIC
1575 #define FORCE
1576 #define ARCHITECTURE    "ZARCH"
1577 #define SUBARCHITECTURE "ZARCH_GENERIC"
1578 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1579        "-DDTB_DEFAULT_ENTRIES=64"
1580 #define LIBNAME   "zarch_generic"
1581 #define CORENAME  "ZARCH_GENERIC"
1582 #endif
1583
1584 #ifdef FORCE_Z13
1585 #define FORCE
1586 #define ARCHITECTURE    "ZARCH"
1587 #define SUBARCHITECTURE "Z13"
1588 #define ARCHCONFIG   "-DZ13 " \
1589        "-DDTB_DEFAULT_ENTRIES=64"
1590 #define LIBNAME   "z13"
1591 #define CORENAME  "Z13"
1592 #endif
1593
1594 #ifdef FORCE_Z14
1595 #define FORCE
1596 #define ARCHITECTURE    "ZARCH"
1597 #define SUBARCHITECTURE "Z14"
1598 #define ARCHCONFIG   "-DZ14 " \
1599        "-DDTB_DEFAULT_ENTRIES=64"
1600 #define LIBNAME   "z14"
1601 #define CORENAME  "Z14"
1602 #endif
1603
1604 #ifdef FORCE_C910V
1605 #define FORCE
1606 #define ARCHITECTURE    "RISCV64"
1607 #ifdef NO_RV64GV
1608 #define SUBARCHITECTURE "RISCV64_GENERIC"
1609 #define SUBDIRNAME      "riscv64"
1610 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
1611        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1612        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1613        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1614 #define LIBNAME   "riscv64_generic"
1615 #define CORENAME  "RISCV64_GENERIC"
1616 #else
1617 #define SUBARCHITECTURE "C910V"
1618 #define SUBDIRNAME      "riscv64"
1619 #define ARCHCONFIG   "-DC910V " \
1620        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1621        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1622        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1623 #define LIBNAME   "c910v"
1624 #define CORENAME  "C910V"
1625 #endif
1626 #else
1627 #endif
1628
1629
1630 #if defined(FORCE_E2K) || defined(__e2k__)
1631 #define FORCE
1632 #define ARCHITECTURE "E2K"
1633 #define ARCHCONFIG   "-DGENERIC " \
1634                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
1635                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
1636                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1637 #define LIBNAME   "generic"
1638 #define CORENAME  "generic"
1639 #endif
1640
1641 #ifndef FORCE
1642
1643 #ifdef USER_TARGET
1644 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1645 #endif
1646
1647 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1648     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1649 #ifndef POWER
1650 #define POWER
1651 #endif
1652 #define OPENBLAS_SUPPORTED
1653 #endif
1654
1655 #if defined(__zarch__) || defined(__s390x__)
1656 #define ZARCH
1657 #include "cpuid_zarch.c"
1658 #define OPENBLAS_SUPPORTED
1659 #endif
1660
1661 #ifdef INTEL_AMD
1662 #include "cpuid_x86.c"
1663 #define OPENBLAS_SUPPORTED
1664 #endif
1665
1666 #ifdef __ia64__
1667 #include "cpuid_ia64.c"
1668 #define OPENBLAS_SUPPORTED
1669 #endif
1670
1671 #ifdef __alpha
1672 #include "cpuid_alpha.c"
1673 #define OPENBLAS_SUPPORTED
1674 #endif
1675
1676 #ifdef POWER
1677 #include "cpuid_power.c"
1678 #define OPENBLAS_SUPPORTED
1679 #endif
1680
1681 #ifdef sparc
1682 #include "cpuid_sparc.c"
1683 #define OPENBLAS_SUPPORTED
1684 #endif
1685
1686 #ifdef __mips__
1687 #ifdef __mips64
1688 #include "cpuid_mips64.c"
1689 #else
1690 #include "cpuid_mips.c"
1691 #endif
1692 #define OPENBLAS_SUPPORTED
1693 #endif
1694
1695 #ifdef __loongarch64
1696 #include "cpuid_loongarch64.c"
1697 #define OPENBLAS_SUPPORTED
1698 #endif
1699
1700 #ifdef __riscv
1701 #include "cpuid_riscv64.c"
1702 #define OPENBLAS_SUPPORTED
1703 #endif
1704
1705 #ifdef __arm__
1706 #include "cpuid_arm.c"
1707 #define OPENBLAS_SUPPORTED
1708 #endif
1709
1710 #ifdef __aarch64__
1711 #include "cpuid_arm64.c"
1712 #define OPENBLAS_SUPPORTED
1713 #endif
1714
1715
1716 #ifndef OPENBLAS_SUPPORTED
1717 #error "This arch/CPU is not supported by OpenBLAS."
1718 #endif
1719
1720 #else
1721
1722 #endif
1723
1724 static int get_num_cores(void) {
1725
1726   int count;
1727 #ifdef OS_WINDOWS
1728   SYSTEM_INFO sysinfo;
1729 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1730   int m[2];
1731   size_t len;
1732 #endif
1733
1734 #if defined(linux) || defined(__sun__)
1735   //returns the number of processors which are currently online
1736   count = sysconf(_SC_NPROCESSORS_CONF);
1737   if (count <= 0) count = 2;
1738   return count;
1739
1740 #elif defined(OS_WINDOWS)
1741
1742   GetSystemInfo(&sysinfo);
1743   return sysinfo.dwNumberOfProcessors;
1744
1745 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1746   m[0] = CTL_HW;
1747   m[1] = HW_NCPU;
1748   len = sizeof(int);
1749   sysctl(m, 2, &count, &len, NULL, 0);
1750   if (count <= 0) count = 2;
1751
1752   return count;
1753
1754 #elif defined(AIX)
1755   //returns the number of processors which are currently online
1756   count = sysconf(_SC_NPROCESSORS_ONLN);
1757   if (count <= 0) count = 2;
1758
1759 #else
1760   return 2;
1761 #endif
1762 }
1763
1764 int main(int argc, char *argv[]){
1765
1766 #ifdef FORCE
1767   char buffer[8192], *p, *q;
1768   int length;
1769 #endif
1770
1771   if (argc == 1) return 0;
1772
1773   switch (argv[1][0]) {
1774
1775   case '0' : /* for Makefile */
1776
1777 #ifdef FORCE
1778     printf("CORE=%s\n", CORENAME);
1779 #else
1780 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) || defined(__riscv)
1781     printf("CORE=%s\n", get_corename());
1782 #endif
1783 #endif
1784
1785 #ifdef FORCE
1786     printf("LIBCORE=%s\n", LIBNAME);
1787 #else
1788     printf("LIBCORE=");
1789     get_libname();
1790     printf("\n");
1791 #endif
1792
1793     printf("NUM_CORES=%d\n", get_num_cores());
1794
1795 #if defined(__arm__)
1796 #if !defined(FORCE)
1797     fprintf(stderr,"get features!\n");
1798         get_features();
1799 #else
1800     fprintf(stderr,"split archconfig!\n");
1801     sprintf(buffer, "%s", ARCHCONFIG);
1802
1803     p = &buffer[0];
1804
1805     while (*p) {
1806       if ((*p == '-') && (*(p + 1) == 'D')) {
1807         p += 2;
1808         if (*p != 'H') {
1809                 while( (*p != ' ') && (*p != '-') && (*p != '\0') && (*p != '\n')) {p++; }
1810                 if (*p == '-') continue;
1811         }
1812         while ((*p != ' ') && (*p != '\0')) {
1813
1814           if (*p == '=') {
1815             printf("=");
1816             p ++;
1817             while ((*p != ' ') && (*p != '\0')) {
1818               printf("%c", *p);
1819               p ++;
1820             }
1821           } else {
1822             printf("%c", *p);
1823             p ++;
1824             if ((*p == ' ') || (*p =='\0')) printf("=1\n");
1825           }
1826         }
1827       } else p ++;
1828     }
1829 #endif
1830 #endif
1831
1832
1833 #ifdef INTEL_AMD
1834 #ifndef FORCE
1835     get_sse();
1836 #else
1837
1838     sprintf(buffer, "%s", ARCHCONFIG);
1839
1840     p = &buffer[0];
1841
1842     while (*p) {
1843       if ((*p == '-') && (*(p + 1) == 'D')) {
1844         p += 2;
1845
1846         while ((*p != ' ') && (*p != '\0')) {
1847
1848           if (*p == '=') {
1849             printf("=");
1850             p ++;
1851             while ((*p != ' ') && (*p != '\0')) {
1852               printf("%c", *p);
1853               p ++;
1854             }
1855           } else {
1856             printf("%c", *p);
1857             p ++;
1858             if ((*p == ' ') || (*p =='\0')) printf("=1");
1859           }
1860         }
1861
1862         printf("\n");
1863       } else p ++;
1864     }
1865 #endif
1866 #endif
1867
1868 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1869 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1870 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1871 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1872 #endif
1873 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1874 printf("ELF_VERSION=2\n");
1875 #endif
1876
1877 #ifdef MAKE_NB_JOBS
1878   #if MAKE_NB_JOBS > 0
1879     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1880   #else
1881     // Let make use parent -j argument or -j1 if there
1882     // is no make parent
1883   #endif
1884 #elif NO_PARALLEL_MAKE==1
1885     printf("MAKE += -j 1\n");
1886 #else
1887     printf("MAKE += -j %d\n", get_num_cores());
1888 #endif
1889
1890     break;
1891
1892   case '1' : /* For config.h */
1893 #ifdef FORCE
1894     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1895
1896     p = &buffer[0];
1897     while (*p) {
1898       if ((*p == '-') && (*(p + 1) == 'D')) {
1899         p += 2;
1900         printf("#define ");
1901
1902         while ((*p != ' ') && (*p != '\0')) {
1903
1904           if (*p == '=') {
1905             printf(" ");
1906             p ++;
1907             while ((*p != ' ') && (*p != '\0')) {
1908               printf("%c", *p);
1909               p ++;
1910             }
1911           } else {
1912             if (*p != '\n')
1913             printf("%c", *p);
1914             p ++;
1915           }
1916         }
1917
1918         printf("\n");
1919       } else p ++;
1920     }
1921 #else
1922     get_cpuconfig();
1923 #endif
1924
1925 #ifdef FORCE
1926     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1927 #else
1928 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) || defined(__riscv)
1929     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1930 #endif
1931 #endif
1932
1933  break;
1934
1935   case '2' : /* SMP */
1936     if (get_num_cores() > 1) printf("SMP=1\n");
1937     break;
1938   }
1939
1940   fflush(stdout);
1941
1942   return 0;
1943 }
1944