getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011,2012 Lab of Parallel Software and Computational Science,ISCAS
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the ISCAS nor the names of its contributors may
  17       be used to endorse or promote products derived from this software
  18       without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  26 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  27 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  28 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  29 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30
  31 **********************************************************************************/
  32
  33 /*********************************************************************/
  34 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  35 /* All rights reserved.                                              */
  36 /*                                                                   */
  37 /* Redistribution and use in source and binary forms, with or        */
  38 /* without modification, are permitted provided that the following   */
  39 /* conditions are met:                                               */
  40 /*                                                                   */
  41 /*   1. Redistributions of source code must retain the above         */
  42 /*      copyright notice, this list of conditions and the following  */
  43 /*      disclaimer.                                                  */
  44 /*                                                                   */
  45 /*   2. Redistributions in binary form must reproduce the above      */
  46 /*      copyright notice, this list of conditions and the following  */
  47 /*      disclaimer in the documentation and/or other materials       */
  48 /*      provided with the distribution.                              */
  49 /*                                                                   */
  50 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  51 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  52 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  53 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  54 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  55 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  56 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  57 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  58 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  59 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  60 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  61 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  62 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  63 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  64 /*                                                                   */
  65 /* The views and conclusions contained in the software and           */
  66 /* documentation are those of the authors and should not be          */
  67 /* interpreted as representing official policies, either expressed   */
  68 /* or implied, of The University of Texas at Austin.                 */
  69 /*********************************************************************/
  70
  71 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__)
  72 #define OS_WINDOWS
  73 #endif
  74
  75 #include <stdio.h>
  76 #include <string.h>
  77 #ifdef OS_WINDOWS
  78 #include <windows.h>
  79 #endif
  80 #if defined(__FreeBSD__) || defined(__APPLE__)
  81 #include <sys/types.h>
  82 #include <sys/sysctl.h>
  83 #endif
  84 #ifdef linux
  85 #include <sys/sysinfo.h>
  86 #endif
  87
  88 /* #define FORCE_P2             */
  89 /* #define FORCE_KATMAI         */
  90 /* #define FORCE_COPPERMINE     */
  91 /* #define FORCE_NORTHWOOD      */
  92 /* #define FORCE_PRESCOTT       */
  93 /* #define FORCE_BANIAS         */
  94 /* #define FORCE_YONAH          */
  95 /* #define FORCE_CORE2          */
  96 /* #define FORCE_PENRYN         */
  97 /* #define FORCE_DUNNINGTON     */
  98 /* #define FORCE_NEHALEM        */
  99 /* #define FORCE_ATHLON         */
 100 /* #define FORCE_OPTERON        */
 101 /* #define FORCE_OPTERON_SSE3   */
 102 /* #define FORCE_BARCELONA      */
 103 /* #define FORCE_SHANGHAI       */
 104 /* #define FORCE_ISTANBUL       */
 105 /* #define FORCE_BULLDOZER      */
 106 /* #define FORCE_BOBCAT */
 107 /* #define FORCE_SSE_GENERIC    */
 108 /* #define FORCE_VIAC3          */
 109 /* #define FORCE_NANO           */
 110 /* #define FORCE_POWER3         */
 111 /* #define FORCE_POWER4         */
 112 /* #define FORCE_POWER5         */
 113 /* #define FORCE_POWER6         */
 114 /* #define FORCE_PPCG4          */
 115 /* #define FORCE_PPC970         */
 116 /* #define FORCE_PPC970MP       */
 117 /* #define FORCE_PPC440         */
 118 /* #define FORCE_PPC440FP2      */
 119 /* #define FORCE_CELL           */
 120 /* #define FORCE_SICORTEX       */
 121 /* #define FORCE_LOONGSON3A      */
 122 /* #define FORCE_LOONGSON3B      */
 123 /* #define FORCE_ITANIUM2       */
 124 /* #define FORCE_GENERIC        */
 125 /* #define FORCE_SPARC          */
 126 /* #define FORCE_SPARCV7        */
 127
 128 #ifdef FORCE_P2
 129 #define FORCE
 130 #define FORCE_INTEL
 131 #define ARCHITECTURE    "X86"
 132 #define SUBARCHITECTURE "PENTIUM2"
 133 #define ARCHCONFIG   "-DPENTIUM2 " \
 134                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 135                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 136                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 137                      "-DHAVE_CMOV -DHAVE_MMX"
 138 #define LIBNAME   "p2"
 139 #define CORENAME  "P5"
 140 #endif
 141
 142 #ifdef FORCE_COPPERMINE
 143 #define FORCE
 144 #define FORCE_INTEL
 145 #define ARCHITECTURE    "X86"
 146 #define SUBARCHITECTURE "PENTIUM3"
 147 #define ARCHCONFIG   "-DPENTIUM3 " \
 148                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 149                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 150                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 151                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 152 #define LIBNAME   "coppermine"
 153 #define CORENAME  "COPPERMINE"
 154 #endif
 155
 156 #ifdef FORCE_KATMAI
 157 #define FORCE
 158 #define FORCE_INTEL
 159 #define ARCHITECTURE    "X86"
 160 #define SUBARCHITECTURE "PENTIUM3"
 161 #define ARCHCONFIG   "-DPENTIUM3 " \
 162                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 163                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 164                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 165                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 166 #define LIBNAME   "katmai"
 167 #define CORENAME  "KATMAI"
 168 #endif
 169
 170 #ifdef FORCE_NORTHWOOD
 171 #define FORCE
 172 #define FORCE_INTEL
 173 #define ARCHITECTURE    "X86"
 174 #define SUBARCHITECTURE "PENTIUM4"
 175 #define ARCHCONFIG   "-DPENTIUM4 " \
 176                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 177                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 178                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 179                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 180 #define LIBNAME   "northwood"
 181 #define CORENAME  "NORTHWOOD"
 182 #endif
 183
 184 #ifdef FORCE_PRESCOTT
 185 #define FORCE
 186 #define FORCE_INTEL
 187 #define ARCHITECTURE    "X86"
 188 #define SUBARCHITECTURE "PENTIUM4"
 189 #define ARCHCONFIG   "-DPENTIUM4 " \
 190                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 191                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 192                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 193                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 194 #define LIBNAME   "prescott"
 195 #define CORENAME  "PRESCOTT"
 196 #endif
 197
 198 #ifdef FORCE_BANIAS
 199 #define FORCE
 200 #define FORCE_INTEL
 201 #define ARCHITECTURE    "X86"
 202 #define SUBARCHITECTURE "BANIAS"
 203 #define ARCHCONFIG   "-DPENTIUMM " \
 204                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 205                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 206                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 207                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 208 #define LIBNAME   "banias"
 209 #define CORENAME  "BANIAS"
 210 #endif
 211
 212 #ifdef FORCE_YONAH
 213 #define FORCE
 214 #define FORCE_INTEL
 215 #define ARCHITECTURE    "X86"
 216 #define SUBARCHITECTURE "YONAH"
 217 #define ARCHCONFIG   "-DPENTIUMM " \
 218                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 219                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 220                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 221                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 222 #define LIBNAME   "yonah"
 223 #define CORENAME  "YONAH"
 224 #endif
 225
 226 #ifdef FORCE_CORE2
 227 #define FORCE
 228 #define FORCE_INTEL
 229 #define ARCHITECTURE    "X86"
 230 #define SUBARCHITECTURE "CONRORE"
 231 #define ARCHCONFIG   "-DCORE2 " \
 232                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 233                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 234                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 235                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 236 #define LIBNAME   "core2"
 237 #define CORENAME  "CORE2"
 238 #endif
 239
 240 #ifdef FORCE_PENRYN
 241 #define FORCE
 242 #define FORCE_INTEL
 243 #define ARCHITECTURE    "X86"
 244 #define SUBARCHITECTURE "PENRYN"
 245 #define ARCHCONFIG   "-DPENRYN " \
 246                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 247                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 248                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 249                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 250 #define LIBNAME   "penryn"
 251 #define CORENAME  "PENRYN"
 252 #endif
 253
 254 #ifdef FORCE_DUNNINGTON
 255 #define FORCE
 256 #define FORCE_INTEL
 257 #define ARCHITECTURE    "X86"
 258 #define SUBARCHITECTURE "DUNNINGTON"
 259 #define ARCHCONFIG   "-DDUNNINGTON " \
 260                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 261                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 262                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 263                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 264                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 265 #define LIBNAME   "dunnington"
 266 #define CORENAME  "DUNNINGTON"
 267 #endif
 268
 269 #ifdef FORCE_NEHALEM
 270 #define FORCE
 271 #define FORCE_INTEL
 272 #define ARCHITECTURE    "X86"
 273 #define SUBARCHITECTURE "NEHALEM"
 274 #define ARCHCONFIG   "-DNEHALEM " \
 275                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 276                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 277                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 278                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 279 #define LIBNAME   "nehalem"
 280 #define CORENAME  "NEHALEM"
 281 #endif
 282
 283 #ifdef FORCE_SANDYBRIDGE
 284 #define FORCE
 285 #define FORCE_INTEL
 286 #define ARCHITECTURE    "X86"
 287 #define SUBARCHITECTURE "SANDYBRIDGE"
 288 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 289                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 290                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 291                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 292                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 293 #define LIBNAME   "sandybridge"
 294 #define CORENAME  "SANDYBRIDGE"
 295 #endif
 296
 297 #ifdef FORCE_ATOM
 298 #define FORCE
 299 #define FORCE_INTEL
 300 #define ARCHITECTURE    "X86"
 301 #define SUBARCHITECTURE "ATOM"
 302 #define ARCHCONFIG   "-DATOM " \
 303                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 304                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 305                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 306                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 307 #define LIBNAME   "atom"
 308 #define CORENAME  "ATOM"
 309 #endif
 310
 311 #ifdef FORCE_ATHLON
 312 #define FORCE
 313 #define FORCE_INTEL
 314 #define ARCHITECTURE    "X86"
 315 #define SUBARCHITECTURE "ATHLON"
 316 #define ARCHCONFIG   "-DATHLON " \
 317                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 318                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 319                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 320                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 321 #define LIBNAME   "athlon"
 322 #define CORENAME  "ATHLON"
 323 #endif
 324
 325 #ifdef FORCE_OPTERON
 326 #define FORCE
 327 #define FORCE_INTEL
 328 #define ARCHITECTURE    "X86"
 329 #define SUBARCHITECTURE "OPTERON"
 330 #define ARCHCONFIG   "-DOPTERON " \
 331                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 332                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 333                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 334                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 335 #define LIBNAME   "opteron"
 336 #define CORENAME  "OPTERON"
 337 #endif
 338
 339 #ifdef FORCE_OPTERON_SSE3
 340 #define FORCE
 341 #define FORCE_INTEL
 342 #define ARCHITECTURE    "X86"
 343 #define SUBARCHITECTURE "OPTERON"
 344 #define ARCHCONFIG   "-DOPTERON " \
 345                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 346                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 347                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 348                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 349 #define LIBNAME   "opteron"
 350 #define CORENAME  "OPTERON"
 351 #endif
 352
 353 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL) || defined (FORCE_BULLDOZER)
 354 #define FORCE
 355 #define FORCE_INTEL
 356 #define ARCHITECTURE    "X86"
 357 #define SUBARCHITECTURE "BARCELONA"
 358 #define ARCHCONFIG   "-DBARCELONA " \
 359                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 360                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 361                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 362                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 363                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 364 #define LIBNAME   "barcelona"
 365 #define CORENAME  "BARCELONA"
 366 #endif
 367
 368 #if defined(FORCE_BOBCAT)
 369 #define FORCE
 370 #define FORCE_INTEL
 371 #define ARCHITECTURE    "X86"
 372 #define SUBARCHITECTURE "BOBCAT"
 373 #define ARCHCONFIG   "-DBOBCAT " \
 374                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 375                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 376                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 377                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 378                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 379 #define LIBNAME   "bobcat"
 380 #define CORENAME  "BOBCAT"
 381 #endif
 382
 383 #ifdef FORCE_SSE_GENERIC
 384 #define FORCE
 385 #define FORCE_INTEL
 386 #define ARCHITECTURE    "X86"
 387 #define SUBARCHITECTURE "GENERIC"
 388 #define ARCHCONFIG   "-DGENERIC " \
 389                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 390                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 391                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 392                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 393 #define LIBNAME   "generic"
 394 #define CORENAME  "GENERIC"
 395 #endif
 396
 397 #ifdef FORCE_VIAC3
 398 #define FORCE
 399 #define FORCE_INTEL
 400 #define ARCHITECTURE    "X86"
 401 #define SUBARCHITECTURE "VIAC3"
 402 #define ARCHCONFIG   "-DVIAC3 " \
 403                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 404                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 405                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 406                      "-DHAVE_MMX -DHAVE_SSE "
 407 #define LIBNAME   "viac3"
 408 #define CORENAME  "VIAC3"
 409 #endif
 410
 411 #ifdef FORCE_NANO
 412 #define FORCE
 413 #define FORCE_INTEL
 414 #define ARCHITECTURE    "X86"
 415 #define SUBARCHITECTURE "NANO"
 416 #define ARCHCONFIG   "-DNANO " \
 417                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 418                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 419                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 420                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 421 #define LIBNAME   "nano"
 422 #define CORENAME  "NANO"
 423 #endif
 424
 425 #ifdef FORCE_POWER3
 426 #define FORCE
 427 #define ARCHITECTURE    "POWER"
 428 #define SUBARCHITECTURE "POWER3"
 429 #define SUBDIRNAME      "power"
 430 #define ARCHCONFIG   "-DPOWER3 " \
 431                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 432                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 433                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 434 #define LIBNAME   "power3"
 435 #define CORENAME  "POWER3"
 436 #endif
 437
 438 #ifdef FORCE_POWER4
 439 #define FORCE
 440 #define ARCHITECTURE    "POWER"
 441 #define SUBARCHITECTURE "POWER4"
 442 #define SUBDIRNAME      "power"
 443 #define ARCHCONFIG   "-DPOWER4 " \
 444                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 445                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 446                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 447 #define LIBNAME   "power4"
 448 #define CORENAME  "POWER4"
 449 #endif
 450
 451 #ifdef FORCE_POWER5
 452 #define FORCE
 453 #define ARCHITECTURE    "POWER"
 454 #define SUBARCHITECTURE "POWER5"
 455 #define SUBDIRNAME      "power"
 456 #define ARCHCONFIG   "-DPOWER5 " \
 457                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 458                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 459                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 460 #define LIBNAME   "power5"
 461 #define CORENAME  "POWER5"
 462 #endif
 463
 464 #ifdef FORCE_POWER6
 465 #define FORCE
 466 #define ARCHITECTURE    "POWER"
 467 #define SUBARCHITECTURE "POWER6"
 468 #define SUBDIRNAME      "power"
 469 #define ARCHCONFIG   "-DPOWER6 " \
 470                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 471                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 472                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 473 #define LIBNAME   "power6"
 474 #define CORENAME  "POWER6"
 475 #endif
 476
 477 #ifdef FORCE_PPCG4
 478 #define FORCE
 479 #define ARCHITECTURE    "POWER"
 480 #define SUBARCHITECTURE "PPCG4"
 481 #define SUBDIRNAME      "power"
 482 #define ARCHCONFIG   "-DPPCG4 " \
 483                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 484                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 485                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 486 #define LIBNAME   "ppcg4"
 487 #define CORENAME  "PPCG4"
 488 #endif
 489
 490 #ifdef FORCE_PPC970
 491 #define FORCE
 492 #define ARCHITECTURE    "POWER"
 493 #define SUBARCHITECTURE "PPC970"
 494 #define SUBDIRNAME      "power"
 495 #define ARCHCONFIG   "-DPPC970 " \
 496                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 497                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 498                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 499 #define LIBNAME   "ppc970"
 500 #define CORENAME  "PPC970"
 501 #endif
 502
 503 #ifdef FORCE_PPC970MP
 504 #define FORCE
 505 #define ARCHITECTURE    "POWER"
 506 #define SUBARCHITECTURE "PPC970"
 507 #define SUBDIRNAME      "power"
 508 #define ARCHCONFIG   "-DPPC970 " \
 509                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 510                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 511                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 512 #define LIBNAME   "ppc970mp"
 513 #define CORENAME  "PPC970"
 514 #endif
 515
 516 #ifdef FORCE_PPC440
 517 #define FORCE
 518 #define ARCHITECTURE    "POWER"
 519 #define SUBARCHITECTURE "PPC440"
 520 #define SUBDIRNAME      "power"
 521 #define ARCHCONFIG   "-DPPC440 " \
 522                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 523                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 524                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 525 #define LIBNAME   "ppc440"
 526 #define CORENAME  "PPC440"
 527 #endif
 528
 529 #ifdef FORCE_PPC440FP2
 530 #define FORCE
 531 #define ARCHITECTURE    "POWER"
 532 #define SUBARCHITECTURE "PPC440FP2"
 533 #define SUBDIRNAME      "power"
 534 #define ARCHCONFIG   "-DPPC440FP2 " \
 535                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 536                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 537                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 538 #define LIBNAME   "ppc440FP2"
 539 #define CORENAME  "PPC440FP2"
 540 #endif
 541
 542 #ifdef FORCE_CELL
 543 #define FORCE
 544 #define ARCHITECTURE    "POWER"
 545 #define SUBARCHITECTURE "CELL"
 546 #define SUBDIRNAME      "power"
 547 #define ARCHCONFIG   "-DCELL " \
 548                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 549                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 550                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 551 #define LIBNAME   "cell"
 552 #define CORENAME  "CELL"
 553 #endif
 554
 555 #ifdef FORCE_SICORTEX
 556 #define FORCE
 557 #define ARCHITECTURE    "MIPS"
 558 #define SUBARCHITECTURE "SICORTEX"
 559 #define SUBDIRNAME      "mips"
 560 #define ARCHCONFIG   "-DSICORTEX " \
 561                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 562                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 563                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 564 #define LIBNAME   "mips"
 565 #define CORENAME  "sicortex"
 566 #endif
 567
 568
 569 #ifdef FORCE_LOONGSON3A
 570 #define FORCE
 571 #define ARCHITECTURE    "MIPS"
 572 #define SUBARCHITECTURE "LOONGSON3A"
 573 #define SUBDIRNAME      "mips64"
 574 #define ARCHCONFIG   "-DLOONGSON3A " \
 575        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 576        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 577        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 578 #define LIBNAME   "loongson3a"
 579 #define CORENAME  "LOONGSON3A"
 580 #else
 581 #endif
 582
 583 #ifdef FORCE_LOONGSON3B
 584 #define FORCE
 585 #define ARCHITECTURE    "MIPS"
 586 #define SUBARCHITECTURE "LOONGSON3B"
 587 #define SUBDIRNAME      "mips64"
 588 #define ARCHCONFIG   "-DLOONGSON3B " \
 589        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 590        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 591        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 592 #define LIBNAME   "loongson3b"
 593 #define CORENAME  "LOONGSON3B"
 594 #else
 595 #endif
 596
 597 #ifdef FORCE_ITANIUM2
 598 #define FORCE
 599 #define ARCHITECTURE    "IA64"
 600 #define SUBARCHITECTURE "ITANIUM2"
 601 #define SUBDIRNAME      "ia64"
 602 #define ARCHCONFIG   "-DITANIUM2 " \
 603                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 604                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 605 #define LIBNAME   "itanium2"
 606 #define CORENAME  "itanium2"
 607 #endif
 608
 609 #ifdef FORCE_SPARC
 610 #define FORCE
 611 #define ARCHITECTURE    "SPARC"
 612 #define SUBARCHITECTURE "SPARC"
 613 #define SUBDIRNAME      "sparc"
 614 #define ARCHCONFIG   "-DSPARC -DV9 " \
 615                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 616                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 617 #define LIBNAME   "sparc"
 618 #define CORENAME  "sparc"
 619 #endif
 620
 621 #ifdef FORCE_SPARCV7
 622 #define FORCE
 623 #define ARCHITECTURE    "SPARC"
 624 #define SUBARCHITECTURE "SPARC"
 625 #define SUBDIRNAME      "sparc"
 626 #define ARCHCONFIG   "-DSPARC -DV7 " \
 627                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 628                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 629 #define LIBNAME   "sparcv7"
 630 #define CORENAME  "sparcv7"
 631 #endif
 632
 633 #ifdef FORCE_GENERIC
 634 #define FORCE
 635 #define ARCHITECTURE    "GENERIC"
 636 #define SUBARCHITECTURE "GENERIC"
 637 #define SUBDIRNAME      "generic"
 638 #define ARCHCONFIG   "-DGENERIC " \
 639                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 640                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 641                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 642 #define LIBNAME   "generic"
 643 #define CORENAME  "generic"
 644 #endif
 645
 646 #ifndef FORCE
 647
 648 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 649     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 650 #ifndef POWER
 651 #define POWER
 652 #endif
 653 #define OPENBLAS_SUPPORTED
 654 #endif
 655
 656 #if defined(__i386__) || (__x86_64__)
 657 #include "cpuid_x86.c"
 658 #define OPENBLAS_SUPPORTED
 659 #endif
 660
 661 #ifdef __ia64__
 662 #include "cpuid_ia64.c"
 663 #define OPENBLAS_SUPPORTED
 664 #endif
 665
 666 #ifdef __alpha
 667 #include "cpuid_alpha.c"
 668 #define OPENBLAS_SUPPORTED
 669 #endif
 670
 671 #ifdef POWER
 672 #include "cpuid_power.c"
 673 #define OPENBLAS_SUPPORTED
 674 #endif
 675
 676 #ifdef sparc
 677 #include "cpuid_sparc.c"
 678 #define OPENBLAS_SUPPORTED
 679 #endif
 680
 681 #ifdef __mips__
 682 #include "cpuid_mips.c"
 683 #define OPENBLAS_SUPPORTED
 684 #endif
 685
 686 #ifndef OPENBLAS_SUPPORTED
 687 #error "This arch/CPU is not supported by OpenBLAS."
 688 #endif
 689
 690 #else
 691
 692 #endif
 693
 694 static int get_num_cores(void) {
 695
 696 #ifdef OS_WINDOWS
 697   SYSTEM_INFO sysinfo;
 698 #elif defined(__FreeBSD__) || defined(__APPLE__)
 699   int m[2], count;
 700   size_t len;
 701 #endif
 702
 703 #ifdef linux
 704   return get_nprocs();
 705
 706 #elif defined(OS_WINDOWS)
 707
 708   GetSystemInfo(&sysinfo);
 709   return sysinfo.dwNumberOfProcessors;
 710
 711 #elif defined(__FreeBSD__) || defined(__APPLE__)
 712   m[0] = CTL_HW;
 713   m[1] = HW_NCPU;
 714   len = sizeof(int);
 715   sysctl(m, 2, &count, &len, NULL, 0);
 716
 717   return count;
 718 #else
 719   return 2;
 720 #endif
 721 }
 722
 723 int main(int argc, char *argv[]){
 724
 725 #ifdef FORCE
 726   char buffer[8192], *p, *q;
 727   int length;
 728 #endif
 729
 730   if (argc == 1) return 0;
 731
 732   switch (argv[1][0]) {
 733
 734   case '0' : /* for Makefile */
 735
 736 #ifdef FORCE
 737     printf("CORE=%s\n", CORENAME);
 738 #else
 739 #if defined(__i386__) || defined(__x86_64__) || defined(POWER) || defined(__mips__)
 740     printf("CORE=%s\n", get_corename());
 741 #endif
 742 #endif
 743
 744 #ifdef FORCE
 745     printf("LIBCORE=%s\n", LIBNAME);
 746 #else
 747     printf("LIBCORE=");
 748     get_libname();
 749     printf("\n");
 750 #endif
 751
 752     printf("NUM_CORES=%d\n", get_num_cores());
 753
 754 #if defined(__i386__) || defined(__x86_64__)
 755 #ifndef FORCE
 756     get_sse();
 757 #else
 758
 759     sprintf(buffer, "%s", ARCHCONFIG);
 760
 761     p = &buffer[0];
 762
 763     while (*p) {
 764       if ((*p == '-') && (*(p + 1) == 'D')) {
 765         p += 2;
 766
 767         while ((*p != ' ') && (*p != '\0')) {
 768
 769           if (*p == '=') {
 770             printf("=");
 771             p ++;
 772             while ((*p != ' ') && (*p != '\0')) {
 773               printf("%c", *p);
 774               p ++;
 775             }
 776           } else {
 777             printf("%c", *p);
 778             p ++;
 779             if ((*p == ' ') || (*p =='\0')) printf("=1");
 780           }
 781         }
 782
 783         printf("\n");
 784       } else p ++;
 785     }
 786 #endif
 787 #endif
 788
 789 #ifndef OS_WINDOWS
 790     printf("MAKE += -j %d\n", get_num_cores());
 791 #endif
 792
 793     break;
 794
 795   case '1' : /* For config.h */
 796 #ifdef FORCE
 797     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 798
 799     p = &buffer[0];
 800     while (*p) {
 801       if ((*p == '-') && (*(p + 1) == 'D')) {
 802         p += 2;
 803         printf("#define ");
 804
 805         while ((*p != ' ') && (*p != '\0')) {
 806
 807           if (*p == '=') {
 808             printf(" ");
 809             p ++;
 810             while ((*p != ' ') && (*p != '\0')) {
 811               printf("%c", *p);
 812               p ++;
 813             }
 814           } else {
 815             printf("%c", *p);
 816             p ++;
 817           }
 818         }
 819
 820         printf("\n");
 821       } else p ++;
 822     }
 823 #else
 824     get_cpuconfig();
 825 #endif
 826  break;
 827
 828   case '2' : /* SMP */
 829     if (get_num_cores() > 1) printf("SMP=1\n");
 830     break;
 831   }
 832
 833   fflush(stdout);
 834
 835   return 0;
 836 }
 837