1 /*****************************************************************************
2 Copyright (c) 2011-2014, The OpenBLAS Project
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are
9 1. Redistributions of source code must retain the above copyright
10 notice, this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in
14 the documentation and/or other materials provided with the
16 3. Neither the name of the OpenBLAS project nor the names of
17 its contributors may be used to endorse or promote products
18 derived from this software without specific prior written
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 **********************************************************************************/
34 /*********************************************************************/
35 /* Copyright 2009, 2010 The University of Texas at Austin. */
36 /* All rights reserved. */
38 /* Redistribution and use in source and binary forms, with or */
39 /* without modification, are permitted provided that the following */
40 /* conditions are met: */
42 /* 1. Redistributions of source code must retain the above */
43 /* copyright notice, this list of conditions and the following */
46 /* 2. Redistributions in binary form must reproduce the above */
47 /* copyright notice, this list of conditions and the following */
48 /* disclaimer in the documentation and/or other materials */
49 /* provided with the distribution. */
51 /* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
52 /* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
53 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
54 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
55 /* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
56 /* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
57 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
58 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
59 /* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
60 /* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
61 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
62 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
63 /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
64 /* POSSIBILITY OF SUCH DAMAGE. */
66 /* The views and conclusions contained in the software and */
67 /* documentation are those of the authors and should not be */
68 /* interpreted as representing official policies, either expressed */
69 /* or implied, of The University of Texas at Austin. */
70 /*********************************************************************/
72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
86 #include <sys/types.h>
87 #include <sys/sysctl.h>
89 #if defined(linux) || defined(__sun__)
90 #include <sys/sysinfo.h>
94 #if (( defined(__GNUC__) && __GNUC__ > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
98 /* #define FORCE_P2 */
99 /* #define FORCE_KATMAI */
100 /* #define FORCE_COPPERMINE */
101 /* #define FORCE_NORTHWOOD */
102 /* #define FORCE_PRESCOTT */
103 /* #define FORCE_BANIAS */
104 /* #define FORCE_YONAH */
105 /* #define FORCE_CORE2 */
106 /* #define FORCE_PENRYN */
107 /* #define FORCE_DUNNINGTON */
108 /* #define FORCE_NEHALEM */
109 /* #define FORCE_SANDYBRIDGE */
110 /* #define FORCE_ATOM */
111 /* #define FORCE_ATHLON */
112 /* #define FORCE_OPTERON */
113 /* #define FORCE_OPTERON_SSE3 */
114 /* #define FORCE_BARCELONA */
115 /* #define FORCE_SHANGHAI */
116 /* #define FORCE_ISTANBUL */
117 /* #define FORCE_BOBCAT */
118 /* #define FORCE_BULLDOZER */
119 /* #define FORCE_PILEDRIVER */
120 /* #define FORCE_SSE_GENERIC */
121 /* #define FORCE_VIAC3 */
122 /* #define FORCE_NANO */
123 /* #define FORCE_POWER3 */
124 /* #define FORCE_POWER4 */
125 /* #define FORCE_POWER5 */
126 /* #define FORCE_POWER6 */
127 /* #define FORCE_POWER7 */
128 /* #define FORCE_POWER8 */
129 /* #define FORCE_PPCG4 */
130 /* #define FORCE_PPC970 */
131 /* #define FORCE_PPC970MP */
132 /* #define FORCE_PPC440 */
133 /* #define FORCE_PPC440FP2 */
134 /* #define FORCE_CELL */
135 /* #define FORCE_SICORTEX */
136 /* #define FORCE_LOONGSON3A */
137 /* #define FORCE_LOONGSON3B */
138 /* #define FORCE_I6400 */
139 /* #define FORCE_P6600 */
140 /* #define FORCE_P5600 */
141 /* #define FORCE_I6500 */
142 /* #define FORCE_ITANIUM2 */
143 /* #define FORCE_SPARC */
144 /* #define FORCE_SPARCV7 */
145 /* #define FORCE_ZARCH_GENERIC */
146 /* #define FORCE_Z13 */
147 /* #define FORCE_GENERIC */
152 #define ARCHITECTURE "X86"
153 #define SUBARCHITECTURE "PENTIUM2"
154 #define ARCHCONFIG "-DPENTIUM2 " \
155 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
156 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
157 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
158 "-DHAVE_CMOV -DHAVE_MMX"
160 #define CORENAME "P5"
166 #define ARCHITECTURE "X86"
167 #define SUBARCHITECTURE "PENTIUM3"
168 #define ARCHCONFIG "-DPENTIUM3 " \
169 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
170 "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
171 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
172 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
173 #define LIBNAME "katmai"
174 #define CORENAME "KATMAI"
177 #ifdef FORCE_COPPERMINE
180 #define ARCHITECTURE "X86"
181 #define SUBARCHITECTURE "PENTIUM3"
182 #define ARCHCONFIG "-DPENTIUM3 " \
183 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
184 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
185 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
186 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
187 #define LIBNAME "coppermine"
188 #define CORENAME "COPPERMINE"
191 #ifdef FORCE_NORTHWOOD
194 #define ARCHITECTURE "X86"
195 #define SUBARCHITECTURE "PENTIUM4"
196 #define ARCHCONFIG "-DPENTIUM4 " \
197 "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
198 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
199 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
200 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
201 #define LIBNAME "northwood"
202 #define CORENAME "NORTHWOOD"
205 #ifdef FORCE_PRESCOTT
208 #define ARCHITECTURE "X86"
209 #define SUBARCHITECTURE "PENTIUM4"
210 #define ARCHCONFIG "-DPENTIUM4 " \
211 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
212 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
213 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
214 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
215 #define LIBNAME "prescott"
216 #define CORENAME "PRESCOTT"
222 #define ARCHITECTURE "X86"
223 #define SUBARCHITECTURE "BANIAS"
224 #define ARCHCONFIG "-DPENTIUMM " \
225 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
226 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
227 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
228 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
229 #define LIBNAME "banias"
230 #define CORENAME "BANIAS"
236 #define ARCHITECTURE "X86"
237 #define SUBARCHITECTURE "YONAH"
238 #define ARCHCONFIG "-DPENTIUMM " \
239 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
240 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
241 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
242 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
243 #define LIBNAME "yonah"
244 #define CORENAME "YONAH"
250 #define ARCHITECTURE "X86"
251 #define SUBARCHITECTURE "CONRORE"
252 #define ARCHCONFIG "-DCORE2 " \
253 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
254 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
255 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
256 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
257 #define LIBNAME "core2"
258 #define CORENAME "CORE2"
264 #define ARCHITECTURE "X86"
265 #define SUBARCHITECTURE "PENRYN"
266 #define ARCHCONFIG "-DPENRYN " \
267 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
268 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
269 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
270 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
271 #define LIBNAME "penryn"
272 #define CORENAME "PENRYN"
275 #ifdef FORCE_DUNNINGTON
278 #define ARCHITECTURE "X86"
279 #define SUBARCHITECTURE "DUNNINGTON"
280 #define ARCHCONFIG "-DDUNNINGTON " \
281 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
282 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
283 "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
284 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
285 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
286 #define LIBNAME "dunnington"
287 #define CORENAME "DUNNINGTON"
293 #define ARCHITECTURE "X86"
294 #define SUBARCHITECTURE "NEHALEM"
295 #define ARCHCONFIG "-DNEHALEM " \
296 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
297 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
298 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
299 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
300 #define LIBNAME "nehalem"
301 #define CORENAME "NEHALEM"
304 #ifdef FORCE_SANDYBRIDGE
307 #define ARCHITECTURE "X86"
308 #define SUBARCHITECTURE "SANDYBRIDGE"
309 #define ARCHCONFIG "-DSANDYBRIDGE " \
310 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
311 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
312 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
313 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
314 #define LIBNAME "sandybridge"
315 #define CORENAME "SANDYBRIDGE"
321 #define ARCHITECTURE "X86"
322 #define SUBARCHITECTURE "HASWELL"
323 #define ARCHCONFIG "-DHASWELL " \
324 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
325 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
326 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
327 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
329 #define LIBNAME "haswell"
330 #define CORENAME "HASWELL"
333 #ifdef FORCE_SKYLAKEX
337 #define ARCHITECTURE "X86"
338 #define SUBARCHITECTURE "HASWELL"
339 #define ARCHCONFIG "-DHASWELL " \
340 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
341 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
342 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
343 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
345 #define LIBNAME "haswell"
346 #define CORENAME "HASWELL"
350 #define ARCHITECTURE "X86"
351 #define SUBARCHITECTURE "SKYLAKEX"
352 #define ARCHCONFIG "-DSKYLAKEX " \
353 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
354 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
355 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
356 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
357 "-DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
358 #define LIBNAME "skylakex"
359 #define CORENAME "SKYLAKEX"
366 #define ARCHITECTURE "X86"
367 #define SUBARCHITECTURE "ATOM"
368 #define ARCHCONFIG "-DATOM " \
369 "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
370 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
371 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
372 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
373 #define LIBNAME "atom"
374 #define CORENAME "ATOM"
380 #define ARCHITECTURE "X86"
381 #define SUBARCHITECTURE "ATHLON"
382 #define ARCHCONFIG "-DATHLON " \
383 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
384 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
385 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
386 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
387 #define LIBNAME "athlon"
388 #define CORENAME "ATHLON"
394 #define ARCHITECTURE "X86"
395 #define SUBARCHITECTURE "OPTERON"
396 #define ARCHCONFIG "-DOPTERON " \
397 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
398 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
399 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
400 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
401 #define LIBNAME "opteron"
402 #define CORENAME "OPTERON"
405 #ifdef FORCE_OPTERON_SSE3
408 #define ARCHITECTURE "X86"
409 #define SUBARCHITECTURE "OPTERON"
410 #define ARCHCONFIG "-DOPTERON " \
411 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
412 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
413 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
414 "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
415 #define LIBNAME "opteron"
416 #define CORENAME "OPTERON"
419 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
422 #define ARCHITECTURE "X86"
423 #define SUBARCHITECTURE "BARCELONA"
424 #define ARCHCONFIG "-DBARCELONA " \
425 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
426 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL3_SIZE=2097152 " \
427 "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
428 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
429 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
430 #define LIBNAME "barcelona"
431 #define CORENAME "BARCELONA"
434 #if defined(FORCE_BOBCAT)
437 #define ARCHITECTURE "X86"
438 #define SUBARCHITECTURE "BOBCAT"
439 #define ARCHCONFIG "-DBOBCAT " \
440 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
441 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
442 "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
443 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
444 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
445 #define LIBNAME "bobcat"
446 #define CORENAME "BOBCAT"
449 #if defined (FORCE_BULLDOZER)
452 #define ARCHITECTURE "X86"
453 #define SUBARCHITECTURE "BULLDOZER"
454 #define ARCHCONFIG "-DBULLDOZER " \
455 "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
456 "-DL2_SIZE=1024000 -DL2_LINESIZE=64 -DL3_SIZE=16777216 " \
457 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
458 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
459 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
460 "-DHAVE_AVX -DHAVE_FMA4"
461 #define LIBNAME "bulldozer"
462 #define CORENAME "BULLDOZER"
465 #if defined (FORCE_PILEDRIVER)
468 #define ARCHITECTURE "X86"
469 #define SUBARCHITECTURE "PILEDRIVER"
470 #define ARCHCONFIG "-DPILEDRIVER " \
471 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
472 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
473 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
474 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
475 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
476 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
477 #define LIBNAME "piledriver"
478 #define CORENAME "PILEDRIVER"
481 #if defined (FORCE_STEAMROLLER)
484 #define ARCHITECTURE "X86"
485 #define SUBARCHITECTURE "STEAMROLLER"
486 #define ARCHCONFIG "-DSTEAMROLLER " \
487 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
488 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
489 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
490 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
491 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
492 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
493 #define LIBNAME "steamroller"
494 #define CORENAME "STEAMROLLER"
497 #if defined (FORCE_EXCAVATOR)
500 #define ARCHITECTURE "X86"
501 #define SUBARCHITECTURE "EXCAVATOR"
502 #define ARCHCONFIG "-DEXCAVATOR " \
503 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
504 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
505 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
506 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
507 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
508 "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
509 #define LIBNAME "excavator"
510 #define CORENAME "EXCAVATOR"
513 #if defined (FORCE_ZEN)
516 #define ARCHITECTURE "X86"
517 #define SUBARCHITECTURE "ZEN"
518 #define ARCHCONFIG "-DZEN " \
519 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
520 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
521 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
522 "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
523 "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
524 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
525 "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
526 "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
527 "-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
528 #define LIBNAME "zen"
529 #define CORENAME "ZEN"
533 #ifdef FORCE_SSE_GENERIC
536 #define ARCHITECTURE "X86"
537 #define SUBARCHITECTURE "GENERIC"
538 #define ARCHCONFIG "-DGENERIC " \
539 "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
540 "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
541 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
542 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
543 #define LIBNAME "generic"
544 #define CORENAME "GENERIC"
550 #define ARCHITECTURE "X86"
551 #define SUBARCHITECTURE "VIAC3"
552 #define ARCHCONFIG "-DVIAC3 " \
553 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
554 "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
555 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
556 "-DHAVE_MMX -DHAVE_SSE "
557 #define LIBNAME "viac3"
558 #define CORENAME "VIAC3"
564 #define ARCHITECTURE "X86"
565 #define SUBARCHITECTURE "NANO"
566 #define ARCHCONFIG "-DNANO " \
567 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
568 "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
569 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
570 "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
571 #define LIBNAME "nano"
572 #define CORENAME "NANO"
577 #define ARCHITECTURE "POWER"
578 #define SUBARCHITECTURE "POWER3"
579 #define SUBDIRNAME "power"
580 #define ARCHCONFIG "-DPOWER3 " \
581 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
582 "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
583 "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
584 #define LIBNAME "power3"
585 #define CORENAME "POWER3"
590 #define ARCHITECTURE "POWER"
591 #define SUBARCHITECTURE "POWER4"
592 #define SUBDIRNAME "power"
593 #define ARCHCONFIG "-DPOWER4 " \
594 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
595 "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
596 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
597 #define LIBNAME "power4"
598 #define CORENAME "POWER4"
603 #define ARCHITECTURE "POWER"
604 #define SUBARCHITECTURE "POWER5"
605 #define SUBDIRNAME "power"
606 #define ARCHCONFIG "-DPOWER5 " \
607 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
608 "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
609 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
610 #define LIBNAME "power5"
611 #define CORENAME "POWER5"
614 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
616 #define ARCHITECTURE "POWER"
617 #define SUBARCHITECTURE "POWER6"
618 #define SUBDIRNAME "power"
619 #define ARCHCONFIG "-DPOWER6 " \
620 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
621 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
622 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
623 #define LIBNAME "power6"
624 #define CORENAME "POWER6"
627 #if defined(FORCE_POWER8)
629 #define ARCHITECTURE "POWER"
630 #define SUBARCHITECTURE "POWER8"
631 #define SUBDIRNAME "power"
632 #define ARCHCONFIG "-DPOWER8 " \
633 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
634 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
635 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
636 #define LIBNAME "power8"
637 #define CORENAME "POWER8"
640 #if defined(FORCE_POWER9)
642 #define ARCHITECTURE "POWER"
643 #define SUBARCHITECTURE "POWER9"
644 #define SUBDIRNAME "power"
645 #define ARCHCONFIG "-DPOWER9 " \
646 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
647 "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
648 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
649 #define LIBNAME "power9"
650 #define CORENAME "POWER9"
655 #define ARCHITECTURE "POWER"
656 #define SUBARCHITECTURE "PPCG4"
657 #define SUBDIRNAME "power"
658 #define ARCHCONFIG "-DPPCG4 " \
659 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
660 "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
661 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
662 #define LIBNAME "ppcg4"
663 #define CORENAME "PPCG4"
668 #define ARCHITECTURE "POWER"
669 #define SUBARCHITECTURE "PPC970"
670 #define SUBDIRNAME "power"
671 #define ARCHCONFIG "-DPPC970 " \
672 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
673 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
674 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
675 #define LIBNAME "ppc970"
676 #define CORENAME "PPC970"
679 #ifdef FORCE_PPC970MP
681 #define ARCHITECTURE "POWER"
682 #define SUBARCHITECTURE "PPC970"
683 #define SUBDIRNAME "power"
684 #define ARCHCONFIG "-DPPC970 " \
685 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
686 "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
687 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
688 #define LIBNAME "ppc970mp"
689 #define CORENAME "PPC970"
694 #define ARCHITECTURE "POWER"
695 #define SUBARCHITECTURE "PPC440"
696 #define SUBDIRNAME "power"
697 #define ARCHCONFIG "-DPPC440 " \
698 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
699 "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
700 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
701 #define LIBNAME "ppc440"
702 #define CORENAME "PPC440"
705 #ifdef FORCE_PPC440FP2
707 #define ARCHITECTURE "POWER"
708 #define SUBARCHITECTURE "PPC440FP2"
709 #define SUBDIRNAME "power"
710 #define ARCHCONFIG "-DPPC440FP2 " \
711 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
712 "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
713 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
714 #define LIBNAME "ppc440FP2"
715 #define CORENAME "PPC440FP2"
720 #define ARCHITECTURE "POWER"
721 #define SUBARCHITECTURE "CELL"
722 #define SUBDIRNAME "power"
723 #define ARCHCONFIG "-DCELL " \
724 "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
725 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
726 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
727 #define LIBNAME "cell"
728 #define CORENAME "CELL"
731 #ifdef FORCE_SICORTEX
733 #define ARCHITECTURE "MIPS"
734 #define SUBARCHITECTURE "SICORTEX"
735 #define SUBDIRNAME "mips"
736 #define ARCHCONFIG "-DSICORTEX " \
737 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
738 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
739 "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
740 #define LIBNAME "mips"
741 #define CORENAME "sicortex"
745 #ifdef FORCE_LOONGSON3A
747 #define ARCHITECTURE "MIPS"
748 #define SUBARCHITECTURE "LOONGSON3A"
749 #define SUBDIRNAME "mips64"
750 #define ARCHCONFIG "-DLOONGSON3A " \
751 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
752 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
753 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
754 #define LIBNAME "loongson3a"
755 #define CORENAME "LOONGSON3A"
759 #ifdef FORCE_LOONGSON3B
761 #define ARCHITECTURE "MIPS"
762 #define SUBARCHITECTURE "LOONGSON3B"
763 #define SUBDIRNAME "mips64"
764 #define ARCHCONFIG "-DLOONGSON3B " \
765 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
766 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
767 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
768 #define LIBNAME "loongson3b"
769 #define CORENAME "LOONGSON3B"
775 #define ARCHITECTURE "MIPS"
776 #define SUBARCHITECTURE "I6400"
777 #define SUBDIRNAME "mips64"
778 #define ARCHCONFIG "-DI6400 " \
779 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
780 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
781 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
782 #define LIBNAME "i6400"
783 #define CORENAME "I6400"
789 #define ARCHITECTURE "MIPS"
790 #define SUBARCHITECTURE "P6600"
791 #define SUBDIRNAME "mips64"
792 #define ARCHCONFIG "-DP6600 " \
793 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
794 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
795 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
796 #define LIBNAME "p6600"
797 #define CORENAME "P6600"
803 #define ARCHITECTURE "MIPS"
804 #define SUBARCHITECTURE "P5600"
805 #define SUBDIRNAME "mips"
806 #define ARCHCONFIG "-DP5600 " \
807 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
808 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
809 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
810 #define LIBNAME "p5600"
811 #define CORENAME "P5600"
817 #define ARCHITECTURE "MIPS"
818 #define SUBARCHITECTURE "I6500"
819 #define SUBDIRNAME "mips64"
820 #define ARCHCONFIG "-DI6500 " \
821 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
822 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
823 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
824 #define LIBNAME "i6500"
825 #define CORENAME "I6500"
829 #ifdef FORCE_ITANIUM2
831 #define ARCHITECTURE "IA64"
832 #define SUBARCHITECTURE "ITANIUM2"
833 #define SUBDIRNAME "ia64"
834 #define ARCHCONFIG "-DITANIUM2 " \
835 "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
836 "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
837 #define LIBNAME "itanium2"
838 #define CORENAME "itanium2"
843 #define ARCHITECTURE "SPARC"
844 #define SUBARCHITECTURE "SPARC"
845 #define SUBDIRNAME "sparc"
846 #define ARCHCONFIG "-DSPARC -DV9 " \
847 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
848 "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
849 #define LIBNAME "sparc"
850 #define CORENAME "sparc"
855 #define ARCHITECTURE "SPARC"
856 #define SUBARCHITECTURE "SPARC"
857 #define SUBDIRNAME "sparc"
858 #define ARCHCONFIG "-DSPARC -DV7 " \
859 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
860 "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
861 #define LIBNAME "sparcv7"
862 #define CORENAME "sparcv7"
867 #define ARCHITECTURE "GENERIC"
868 #define SUBARCHITECTURE "GENERIC"
869 #define SUBDIRNAME "generic"
870 #define ARCHCONFIG "-DGENERIC " \
871 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
872 "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
873 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
874 #define LIBNAME "generic"
875 #define CORENAME "generic"
880 #define ARCHITECTURE "ARM"
881 #define SUBARCHITECTURE "ARMV7"
882 #define SUBDIRNAME "arm"
883 #define ARCHCONFIG "-DARMV7 " \
884 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
885 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
886 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
887 "-DHAVE_VFPV3 -DHAVE_VFP"
888 #define LIBNAME "armv7"
889 #define CORENAME "ARMV7"
893 #ifdef FORCE_CORTEXA9
895 #define ARCHITECTURE "ARM"
896 #define SUBARCHITECTURE "CORTEXA9"
897 #define SUBDIRNAME "arm"
898 #define ARCHCONFIG "-DCORTEXA9 -DARMV7 " \
899 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
900 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
901 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
902 "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
903 #define LIBNAME "cortexa9"
904 #define CORENAME "CORTEXA9"
908 #ifdef FORCE_CORTEXA15
910 #define ARCHITECTURE "ARM"
911 #define SUBARCHITECTURE "CORTEXA15"
912 #define SUBDIRNAME "arm"
913 #define ARCHCONFIG "-DCORTEXA15 -DARMV7 " \
914 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
915 "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
916 "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
917 "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
918 #define LIBNAME "cortexa15"
919 #define CORENAME "CORTEXA15"
925 #define ARCHITECTURE "ARM"
926 #define SUBARCHITECTURE "ARMV6"
927 #define SUBDIRNAME "arm"
928 #define ARCHCONFIG "-DARMV6 " \
929 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
930 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
931 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
933 #define LIBNAME "armv6"
934 #define CORENAME "ARMV6"
940 #define ARCHITECTURE "ARM"
941 #define SUBARCHITECTURE "ARMV5"
942 #define SUBDIRNAME "arm"
943 #define ARCHCONFIG "-DARMV5 " \
944 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
945 "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
946 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
947 #define LIBNAME "armv5"
948 #define CORENAME "ARMV5"
955 #define ARCHITECTURE "ARM64"
956 #define SUBARCHITECTURE "ARMV8"
957 #define SUBDIRNAME "arm64"
958 #define ARCHCONFIG "-DARMV8 " \
959 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
960 "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
961 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
962 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
963 #define LIBNAME "armv8"
964 #define CORENAME "ARMV8"
967 #ifdef FORCE_CORTEXA53
969 #define ARCHITECTURE "ARM64"
970 #define SUBARCHITECTURE "CORTEXA53"
971 #define SUBDIRNAME "arm64"
972 #define ARCHCONFIG "-DCORTEXA53 " \
973 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
974 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
975 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
976 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
977 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
978 #define LIBNAME "cortexa53"
979 #define CORENAME "CORTEXA53"
983 #ifdef FORCE_CORTEXA57
985 #define ARCHITECTURE "ARM64"
986 #define SUBARCHITECTURE "CORTEXA57"
987 #define SUBDIRNAME "arm64"
988 #define ARCHCONFIG "-DCORTEXA57 " \
989 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
990 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
991 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
992 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
993 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
994 #define LIBNAME "cortexa57"
995 #define CORENAME "CORTEXA57"
999 #ifdef FORCE_CORTEXA72
1001 #define ARCHITECTURE "ARM64"
1002 #define SUBARCHITECTURE "CORTEXA72"
1003 #define SUBDIRNAME "arm64"
1004 #define ARCHCONFIG "-DCORTEXA72 " \
1005 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1006 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1007 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1008 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1009 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1010 #define LIBNAME "cortexa72"
1011 #define CORENAME "CORTEXA72"
1015 #ifdef FORCE_CORTEXA73
1017 #define ARCHITECTURE "ARM64"
1018 #define SUBARCHITECTURE "CORTEXA73"
1019 #define SUBDIRNAME "arm64"
1020 #define ARCHCONFIG "-DCORTEXA73 " \
1021 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1022 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1023 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1024 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1025 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1026 #define LIBNAME "cortexa73"
1027 #define CORENAME "CORTEXA73"
1033 #define ARCHITECTURE "ARM64"
1034 #define SUBARCHITECTURE "FALKOR"
1035 #define SUBDIRNAME "arm64"
1036 #define ARCHCONFIG "-DFALKOR " \
1037 "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1038 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1039 "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1040 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1041 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1042 #define LIBNAME "falkor"
1043 #define CORENAME "FALKOR"
1047 #ifdef FORCE_THUNDERX
1049 #define ARCHITECTURE "ARM64"
1050 #define SUBARCHITECTURE "THUNDERX"
1051 #define SUBDIRNAME "arm64"
1052 #define ARCHCONFIG "-DTHUNDERX " \
1053 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1054 "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1055 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1056 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1057 #define LIBNAME "thunderx"
1058 #define CORENAME "THUNDERX"
1062 #ifdef FORCE_THUNDERX2T99
1065 #define ARCHITECTURE "ARM64"
1066 #define SUBARCHITECTURE "THUNDERX2T99"
1067 #define SUBDIRNAME "arm64"
1068 #define ARCHCONFIG "-DTHUNDERX2T99 " \
1069 "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1070 "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1071 "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1072 "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1073 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1074 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1075 #define LIBNAME "thunderx2t99"
1076 #define CORENAME "THUNDERX2T99"
1082 #define ARCHITECTURE "ARM64"
1083 #define SUBARCHITECTURE "TSV110"
1084 #define SUBDIRNAME "arm64"
1085 #define ARCHCONFIG "-DTSV110 " \
1086 "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1087 "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1088 "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1089 "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1090 "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1091 #define LIBNAME "tsv110"
1092 #define CORENAME "TSV110"
1097 #ifdef FORCE_ZARCH_GENERIC
1099 #define ARCHITECTURE "ZARCH"
1100 #define SUBARCHITECTURE "ZARCH_GENERIC"
1101 #define ARCHCONFIG "-DZARCH_GENERIC " \
1102 "-DDTB_DEFAULT_ENTRIES=64"
1103 #define LIBNAME "zarch_generic"
1104 #define CORENAME "ZARCH_GENERIC"
1109 #define ARCHITECTURE "ZARCH"
1110 #define SUBARCHITECTURE "Z13"
1111 #define ARCHCONFIG "-DZ13 " \
1112 "-DDTB_DEFAULT_ENTRIES=64"
1113 #define LIBNAME "z13"
1114 #define CORENAME "Z13"
1119 #define ARCHITECTURE "ZARCH"
1120 #define SUBARCHITECTURE "Z14"
1121 #define ARCHCONFIG "-DZ14 " \
1122 "-DDTB_DEFAULT_ENTRIES=64"
1123 #define LIBNAME "z14"
1124 #define CORENAME "Z14"
1130 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1133 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1134 defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1138 #define OPENBLAS_SUPPORTED
1141 #if defined(__zarch__) || defined(__s390x__)
1143 #include "cpuid_zarch.c"
1144 #define OPENBLAS_SUPPORTED
1148 #include "cpuid_x86.c"
1149 #define OPENBLAS_SUPPORTED
1153 #include "cpuid_ia64.c"
1154 #define OPENBLAS_SUPPORTED
1158 #include "cpuid_alpha.c"
1159 #define OPENBLAS_SUPPORTED
1163 #include "cpuid_power.c"
1164 #define OPENBLAS_SUPPORTED
1168 #include "cpuid_sparc.c"
1169 #define OPENBLAS_SUPPORTED
1174 #include "cpuid_mips64.c"
1176 #include "cpuid_mips.c"
1178 #define OPENBLAS_SUPPORTED
1182 #include "cpuid_arm.c"
1183 #define OPENBLAS_SUPPORTED
1187 #include "cpuid_arm64.c"
1188 #define OPENBLAS_SUPPORTED
1192 #ifndef OPENBLAS_SUPPORTED
1193 #error "This arch/CPU is not supported by OpenBLAS."
1200 static int get_num_cores(void) {
1203 SYSTEM_INFO sysinfo;
1204 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1209 #if defined(linux) || defined(__sun__)
1210 //returns the number of processors which are currently online
1211 return sysconf(_SC_NPROCESSORS_CONF);
1213 #elif defined(OS_WINDOWS)
1215 GetSystemInfo(&sysinfo);
1216 return sysinfo.dwNumberOfProcessors;
1218 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1222 sysctl(m, 2, &count, &len, NULL, 0);
1230 int main(int argc, char *argv[]){
1233 char buffer[8192], *p, *q;
1237 if (argc == 1) return 0;
1239 switch (argv[1][0]) {
1241 case '0' : /* for Makefile */
1244 printf("CORE=%s\n", CORENAME);
1246 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1247 printf("CORE=%s\n", get_corename());
1252 printf("LIBCORE=%s\n", LIBNAME);
1259 printf("NUM_CORES=%d\n", get_num_cores());
1261 #if defined(__arm__) && !defined(FORCE)
1271 sprintf(buffer, "%s", ARCHCONFIG);
1276 if ((*p == '-') && (*(p + 1) == 'D')) {
1279 while ((*p != ' ') && (*p != '\0')) {
1284 while ((*p != ' ') && (*p != '\0')) {
1291 if ((*p == ' ') || (*p =='\0')) printf("=1");
1302 #if MAKE_NB_JOBS > 0
1303 printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1305 // Let make use parent -j argument or -j1 if there
1306 // is no make parent
1308 #elif NO_PARALLEL_MAKE==1
1309 printf("MAKE += -j 1\n");
1311 printf("MAKE += -j %d\n", get_num_cores());
1316 case '1' : /* For config.h */
1318 sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1322 if ((*p == '-') && (*(p + 1) == 'D')) {
1326 while ((*p != ' ') && (*p != '\0')) {
1331 while ((*p != ' ') && (*p != '\0')) {
1350 printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1352 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1353 printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1359 case '2' : /* SMP */
1360 if (get_num_cores() > 1) printf("SMP=1\n");