getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P6600          */
 136 /* #define FORCE_P5600          */
 137 /* #define FORCE_I6500          */
 138 /* #define FORCE_ITANIUM2       */
 139 /* #define FORCE_SPARC          */
 140 /* #define FORCE_SPARCV7        */
 141 /* #define FORCE_ZARCH_GENERIC  */
 142 /* #define FORCE_Z13            */
 143 /* #define FORCE_GENERIC        */
 144
 145 #ifdef FORCE_P2
 146 #define FORCE
 147 #define FORCE_INTEL
 148 #define ARCHITECTURE    "X86"
 149 #define SUBARCHITECTURE "PENTIUM2"
 150 #define ARCHCONFIG   "-DPENTIUM2 " \
 151                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 152                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 153                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 154                      "-DHAVE_CMOV -DHAVE_MMX"
 155 #define LIBNAME   "p2"
 156 #define CORENAME  "P5"
 157 #endif
 158
 159 #ifdef FORCE_KATMAI
 160 #define FORCE
 161 #define FORCE_INTEL
 162 #define ARCHITECTURE    "X86"
 163 #define SUBARCHITECTURE "PENTIUM3"
 164 #define ARCHCONFIG   "-DPENTIUM3 " \
 165                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 166                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 167                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 168                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 169 #define LIBNAME   "katmai"
 170 #define CORENAME  "KATMAI"
 171 #endif
 172
 173 #ifdef FORCE_COPPERMINE
 174 #define FORCE
 175 #define FORCE_INTEL
 176 #define ARCHITECTURE    "X86"
 177 #define SUBARCHITECTURE "PENTIUM3"
 178 #define ARCHCONFIG   "-DPENTIUM3 " \
 179                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 180                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 181                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 182                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 183 #define LIBNAME   "coppermine"
 184 #define CORENAME  "COPPERMINE"
 185 #endif
 186
 187 #ifdef FORCE_NORTHWOOD
 188 #define FORCE
 189 #define FORCE_INTEL
 190 #define ARCHITECTURE    "X86"
 191 #define SUBARCHITECTURE "PENTIUM4"
 192 #define ARCHCONFIG   "-DPENTIUM4 " \
 193                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 194                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 195                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 196                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 197 #define LIBNAME   "northwood"
 198 #define CORENAME  "NORTHWOOD"
 199 #endif
 200
 201 #ifdef FORCE_PRESCOTT
 202 #define FORCE
 203 #define FORCE_INTEL
 204 #define ARCHITECTURE    "X86"
 205 #define SUBARCHITECTURE "PENTIUM4"
 206 #define ARCHCONFIG   "-DPENTIUM4 " \
 207                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 208                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 209                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 210                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 211 #define LIBNAME   "prescott"
 212 #define CORENAME  "PRESCOTT"
 213 #endif
 214
 215 #ifdef FORCE_BANIAS
 216 #define FORCE
 217 #define FORCE_INTEL
 218 #define ARCHITECTURE    "X86"
 219 #define SUBARCHITECTURE "BANIAS"
 220 #define ARCHCONFIG   "-DPENTIUMM " \
 221                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 222                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 223                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 224                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 225 #define LIBNAME   "banias"
 226 #define CORENAME  "BANIAS"
 227 #endif
 228
 229 #ifdef FORCE_YONAH
 230 #define FORCE
 231 #define FORCE_INTEL
 232 #define ARCHITECTURE    "X86"
 233 #define SUBARCHITECTURE "YONAH"
 234 #define ARCHCONFIG   "-DPENTIUMM " \
 235                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 236                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 237                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 238                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 239 #define LIBNAME   "yonah"
 240 #define CORENAME  "YONAH"
 241 #endif
 242
 243 #ifdef FORCE_CORE2
 244 #define FORCE
 245 #define FORCE_INTEL
 246 #define ARCHITECTURE    "X86"
 247 #define SUBARCHITECTURE "CONRORE"
 248 #define ARCHCONFIG   "-DCORE2 " \
 249                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 250                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 251                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 252                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 253 #define LIBNAME   "core2"
 254 #define CORENAME  "CORE2"
 255 #endif
 256
 257 #ifdef FORCE_PENRYN
 258 #define FORCE
 259 #define FORCE_INTEL
 260 #define ARCHITECTURE    "X86"
 261 #define SUBARCHITECTURE "PENRYN"
 262 #define ARCHCONFIG   "-DPENRYN " \
 263                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 264                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 265                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 266                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 267 #define LIBNAME   "penryn"
 268 #define CORENAME  "PENRYN"
 269 #endif
 270
 271 #ifdef FORCE_DUNNINGTON
 272 #define FORCE
 273 #define FORCE_INTEL
 274 #define ARCHITECTURE    "X86"
 275 #define SUBARCHITECTURE "DUNNINGTON"
 276 #define ARCHCONFIG   "-DDUNNINGTON " \
 277                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 278                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 279                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 280                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 281                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 282 #define LIBNAME   "dunnington"
 283 #define CORENAME  "DUNNINGTON"
 284 #endif
 285
 286 #ifdef FORCE_NEHALEM
 287 #define FORCE
 288 #define FORCE_INTEL
 289 #define ARCHITECTURE    "X86"
 290 #define SUBARCHITECTURE "NEHALEM"
 291 #define ARCHCONFIG   "-DNEHALEM " \
 292                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 293                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 294                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 295                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 296 #define LIBNAME   "nehalem"
 297 #define CORENAME  "NEHALEM"
 298 #endif
 299
 300 #ifdef FORCE_SANDYBRIDGE
 301 #define FORCE
 302 #define FORCE_INTEL
 303 #define ARCHITECTURE    "X86"
 304 #define SUBARCHITECTURE "SANDYBRIDGE"
 305 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 306                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 307                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 308                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 309                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 310 #define LIBNAME   "sandybridge"
 311 #define CORENAME  "SANDYBRIDGE"
 312 #endif
 313
 314 #ifdef FORCE_HASWELL
 315 #define FORCE
 316 #define FORCE_INTEL
 317 #define ARCHITECTURE    "X86"
 318 #define SUBARCHITECTURE "HASWELL"
 319 #define ARCHCONFIG   "-DHASWELL " \
 320                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 321                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 322                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 323                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 324                      "-DFMA3"
 325 #define LIBNAME   "haswell"
 326 #define CORENAME  "HASWELL"
 327 #endif
 328
 329 #ifdef FORCE_SKYLAKEX
 330 #define FORCE
 331 #define FORCE_INTEL
 332 #define ARCHITECTURE    "X86"
 333 #define SUBARCHITECTURE "SKYLAKEX"
 334 #define ARCHCONFIG   "-DSKYLAKEX " \
 335                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 336                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 337                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 338                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 339                      "-DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 340 #define LIBNAME   "skylakex"
 341 #define CORENAME  "SKYLAKEX"
 342 #endif
 343
 344 #ifdef FORCE_ATOM
 345 #define FORCE
 346 #define FORCE_INTEL
 347 #define ARCHITECTURE    "X86"
 348 #define SUBARCHITECTURE "ATOM"
 349 #define ARCHCONFIG   "-DATOM " \
 350                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 351                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 352                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 353                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 354 #define LIBNAME   "atom"
 355 #define CORENAME  "ATOM"
 356 #endif
 357
 358 #ifdef FORCE_ATHLON
 359 #define FORCE
 360 #define FORCE_INTEL
 361 #define ARCHITECTURE    "X86"
 362 #define SUBARCHITECTURE "ATHLON"
 363 #define ARCHCONFIG   "-DATHLON " \
 364                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 365                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 366                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 367                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 368 #define LIBNAME   "athlon"
 369 #define CORENAME  "ATHLON"
 370 #endif
 371
 372 #ifdef FORCE_OPTERON
 373 #define FORCE
 374 #define FORCE_INTEL
 375 #define ARCHITECTURE    "X86"
 376 #define SUBARCHITECTURE "OPTERON"
 377 #define ARCHCONFIG   "-DOPTERON " \
 378                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 379                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 380                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 381                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 382 #define LIBNAME   "opteron"
 383 #define CORENAME  "OPTERON"
 384 #endif
 385
 386 #ifdef FORCE_OPTERON_SSE3
 387 #define FORCE
 388 #define FORCE_INTEL
 389 #define ARCHITECTURE    "X86"
 390 #define SUBARCHITECTURE "OPTERON"
 391 #define ARCHCONFIG   "-DOPTERON " \
 392                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 393                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 394                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 395                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 396 #define LIBNAME   "opteron"
 397 #define CORENAME  "OPTERON"
 398 #endif
 399
 400 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 401 #define FORCE
 402 #define FORCE_INTEL
 403 #define ARCHITECTURE    "X86"
 404 #define SUBARCHITECTURE "BARCELONA"
 405 #define ARCHCONFIG   "-DBARCELONA " \
 406                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 407                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 408                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 409                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 410                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 411 #define LIBNAME   "barcelona"
 412 #define CORENAME  "BARCELONA"
 413 #endif
 414
 415 #if defined(FORCE_BOBCAT)
 416 #define FORCE
 417 #define FORCE_INTEL
 418 #define ARCHITECTURE    "X86"
 419 #define SUBARCHITECTURE "BOBCAT"
 420 #define ARCHCONFIG   "-DBOBCAT " \
 421                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 422                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 423                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 424                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 425                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 426 #define LIBNAME   "bobcat"
 427 #define CORENAME  "BOBCAT"
 428 #endif
 429
 430 #if defined (FORCE_BULLDOZER)
 431 #define FORCE
 432 #define FORCE_INTEL
 433 #define ARCHITECTURE    "X86"
 434 #define SUBARCHITECTURE "BULLDOZER"
 435 #define ARCHCONFIG   "-DBULLDOZER " \
 436                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 437                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 438                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 439                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 440                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 441                      "-DHAVE_AVX -DHAVE_FMA4"
 442 #define LIBNAME   "bulldozer"
 443 #define CORENAME  "BULLDOZER"
 444 #endif
 445
 446 #if defined (FORCE_PILEDRIVER)
 447 #define FORCE
 448 #define FORCE_INTEL
 449 #define ARCHITECTURE    "X86"
 450 #define SUBARCHITECTURE "PILEDRIVER"
 451 #define ARCHCONFIG   "-DPILEDRIVER " \
 452                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 453                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 454                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 455                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 456                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 457                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 458 #define LIBNAME   "piledriver"
 459 #define CORENAME  "PILEDRIVER"
 460 #endif
 461
 462 #if defined (FORCE_STEAMROLLER)
 463 #define FORCE
 464 #define FORCE_INTEL
 465 #define ARCHITECTURE    "X86"
 466 #define SUBARCHITECTURE "STEAMROLLER"
 467 #define ARCHCONFIG   "-DSTEAMROLLER " \
 468                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 469                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 470                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 471                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 472                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 473                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 474 #define LIBNAME   "steamroller"
 475 #define CORENAME  "STEAMROLLER"
 476 #endif
 477
 478 #if defined (FORCE_EXCAVATOR)
 479 #define FORCE
 480 #define FORCE_INTEL
 481 #define ARCHITECTURE    "X86"
 482 #define SUBARCHITECTURE "EXCAVATOR"
 483 #define ARCHCONFIG   "-DEXCAVATOR " \
 484                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 485                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 486                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 487                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 488                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 489                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 490 #define LIBNAME   "excavator"
 491 #define CORENAME  "EXCAVATOR"
 492 #endif
 493
 494 #if defined (FORCE_ZEN)
 495 #define FORCE
 496 #define FORCE_INTEL
 497 #define ARCHITECTURE    "X86"
 498 #define SUBARCHITECTURE "ZEN"
 499 #define ARCHCONFIG   "-DZEN " \
 500                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 501                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 502                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 503                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 504                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 505                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 506                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 507                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 508                      "-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
 509 #define LIBNAME   "zen"
 510 #define CORENAME  "ZEN"
 511 #endif
 512
 513
 514 #ifdef FORCE_SSE_GENERIC
 515 #define FORCE
 516 #define FORCE_INTEL
 517 #define ARCHITECTURE    "X86"
 518 #define SUBARCHITECTURE "GENERIC"
 519 #define ARCHCONFIG   "-DGENERIC " \
 520                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 521                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 522                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 523                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 524 #define LIBNAME   "generic"
 525 #define CORENAME  "GENERIC"
 526 #endif
 527
 528 #ifdef FORCE_VIAC3
 529 #define FORCE
 530 #define FORCE_INTEL
 531 #define ARCHITECTURE    "X86"
 532 #define SUBARCHITECTURE "VIAC3"
 533 #define ARCHCONFIG   "-DVIAC3 " \
 534                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 535                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 536                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 537                      "-DHAVE_MMX -DHAVE_SSE "
 538 #define LIBNAME   "viac3"
 539 #define CORENAME  "VIAC3"
 540 #endif
 541
 542 #ifdef FORCE_NANO
 543 #define FORCE
 544 #define FORCE_INTEL
 545 #define ARCHITECTURE    "X86"
 546 #define SUBARCHITECTURE "NANO"
 547 #define ARCHCONFIG   "-DNANO " \
 548                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 549                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 550                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 551                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 552 #define LIBNAME   "nano"
 553 #define CORENAME  "NANO"
 554 #endif
 555
 556 #ifdef FORCE_POWER3
 557 #define FORCE
 558 #define ARCHITECTURE    "POWER"
 559 #define SUBARCHITECTURE "POWER3"
 560 #define SUBDIRNAME      "power"
 561 #define ARCHCONFIG   "-DPOWER3 " \
 562                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 563                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 564                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 565 #define LIBNAME   "power3"
 566 #define CORENAME  "POWER3"
 567 #endif
 568
 569 #ifdef FORCE_POWER4
 570 #define FORCE
 571 #define ARCHITECTURE    "POWER"
 572 #define SUBARCHITECTURE "POWER4"
 573 #define SUBDIRNAME      "power"
 574 #define ARCHCONFIG   "-DPOWER4 " \
 575                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 576                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 577                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 578 #define LIBNAME   "power4"
 579 #define CORENAME  "POWER4"
 580 #endif
 581
 582 #ifdef FORCE_POWER5
 583 #define FORCE
 584 #define ARCHITECTURE    "POWER"
 585 #define SUBARCHITECTURE "POWER5"
 586 #define SUBDIRNAME      "power"
 587 #define ARCHCONFIG   "-DPOWER5 " \
 588                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 589                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 590                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 591 #define LIBNAME   "power5"
 592 #define CORENAME  "POWER5"
 593 #endif
 594
 595 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 596 #define FORCE
 597 #define ARCHITECTURE    "POWER"
 598 #define SUBARCHITECTURE "POWER6"
 599 #define SUBDIRNAME      "power"
 600 #define ARCHCONFIG   "-DPOWER6 " \
 601                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 602                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 603                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 604 #define LIBNAME   "power6"
 605 #define CORENAME  "POWER6"
 606 #endif
 607
 608 #if defined(FORCE_POWER8)
 609 #define FORCE
 610 #define ARCHITECTURE    "POWER"
 611 #define SUBARCHITECTURE "POWER8"
 612 #define SUBDIRNAME      "power"
 613 #define ARCHCONFIG   "-DPOWER8 " \
 614                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 615                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 616                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 617 #define LIBNAME   "power8"
 618 #define CORENAME  "POWER8"
 619 #endif
 620
 621 #if defined(FORCE_POWER9)
 622 #define FORCE
 623 #define ARCHITECTURE    "POWER"
 624 #define SUBARCHITECTURE "POWER9"
 625 #define SUBDIRNAME      "power"
 626 #define ARCHCONFIG   "-DPOWER9 " \
 627                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 628                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 629                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 630 #define LIBNAME   "power9"
 631 #define CORENAME  "POWER9"
 632 #endif
 633
 634 #ifdef FORCE_PPCG4
 635 #define FORCE
 636 #define ARCHITECTURE    "POWER"
 637 #define SUBARCHITECTURE "PPCG4"
 638 #define SUBDIRNAME      "power"
 639 #define ARCHCONFIG   "-DPPCG4 " \
 640                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 641                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 642                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 643 #define LIBNAME   "ppcg4"
 644 #define CORENAME  "PPCG4"
 645 #endif
 646
 647 #ifdef FORCE_PPC970
 648 #define FORCE
 649 #define ARCHITECTURE    "POWER"
 650 #define SUBARCHITECTURE "PPC970"
 651 #define SUBDIRNAME      "power"
 652 #define ARCHCONFIG   "-DPPC970 " \
 653                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 654                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 655                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 656 #define LIBNAME   "ppc970"
 657 #define CORENAME  "PPC970"
 658 #endif
 659
 660 #ifdef FORCE_PPC970MP
 661 #define FORCE
 662 #define ARCHITECTURE    "POWER"
 663 #define SUBARCHITECTURE "PPC970"
 664 #define SUBDIRNAME      "power"
 665 #define ARCHCONFIG   "-DPPC970 " \
 666                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 667                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 668                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 669 #define LIBNAME   "ppc970mp"
 670 #define CORENAME  "PPC970"
 671 #endif
 672
 673 #ifdef FORCE_PPC440
 674 #define FORCE
 675 #define ARCHITECTURE    "POWER"
 676 #define SUBARCHITECTURE "PPC440"
 677 #define SUBDIRNAME      "power"
 678 #define ARCHCONFIG   "-DPPC440 " \
 679                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 680                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 681                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 682 #define LIBNAME   "ppc440"
 683 #define CORENAME  "PPC440"
 684 #endif
 685
 686 #ifdef FORCE_PPC440FP2
 687 #define FORCE
 688 #define ARCHITECTURE    "POWER"
 689 #define SUBARCHITECTURE "PPC440FP2"
 690 #define SUBDIRNAME      "power"
 691 #define ARCHCONFIG   "-DPPC440FP2 " \
 692                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 693                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 694                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 695 #define LIBNAME   "ppc440FP2"
 696 #define CORENAME  "PPC440FP2"
 697 #endif
 698
 699 #ifdef FORCE_CELL
 700 #define FORCE
 701 #define ARCHITECTURE    "POWER"
 702 #define SUBARCHITECTURE "CELL"
 703 #define SUBDIRNAME      "power"
 704 #define ARCHCONFIG   "-DCELL " \
 705                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 706                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 707                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 708 #define LIBNAME   "cell"
 709 #define CORENAME  "CELL"
 710 #endif
 711
 712 #ifdef FORCE_SICORTEX
 713 #define FORCE
 714 #define ARCHITECTURE    "MIPS"
 715 #define SUBARCHITECTURE "SICORTEX"
 716 #define SUBDIRNAME      "mips"
 717 #define ARCHCONFIG   "-DSICORTEX " \
 718                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 719                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 720                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 721 #define LIBNAME   "mips"
 722 #define CORENAME  "sicortex"
 723 #endif
 724
 725
 726 #ifdef FORCE_LOONGSON3A
 727 #define FORCE
 728 #define ARCHITECTURE    "MIPS"
 729 #define SUBARCHITECTURE "LOONGSON3A"
 730 #define SUBDIRNAME      "mips64"
 731 #define ARCHCONFIG   "-DLOONGSON3A " \
 732        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 733        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 734        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 735 #define LIBNAME   "loongson3a"
 736 #define CORENAME  "LOONGSON3A"
 737 #else
 738 #endif
 739
 740 #ifdef FORCE_LOONGSON3B
 741 #define FORCE
 742 #define ARCHITECTURE    "MIPS"
 743 #define SUBARCHITECTURE "LOONGSON3B"
 744 #define SUBDIRNAME      "mips64"
 745 #define ARCHCONFIG   "-DLOONGSON3B " \
 746        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 747        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 748        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 749 #define LIBNAME   "loongson3b"
 750 #define CORENAME  "LOONGSON3B"
 751 #else
 752 #endif
 753
 754 #ifdef FORCE_I6400
 755 #define FORCE
 756 #define ARCHITECTURE    "MIPS"
 757 #define SUBARCHITECTURE "I6400"
 758 #define SUBDIRNAME      "mips64"
 759 #define ARCHCONFIG   "-DI6400 " \
 760        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 761        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 762        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 763 #define LIBNAME   "i6400"
 764 #define CORENAME  "I6400"
 765 #else
 766 #endif
 767
 768 #ifdef FORCE_P6600
 769 #define FORCE
 770 #define ARCHITECTURE    "MIPS"
 771 #define SUBARCHITECTURE "P6600"
 772 #define SUBDIRNAME      "mips64"
 773 #define ARCHCONFIG   "-DP6600 " \
 774        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 775        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 776        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 777 #define LIBNAME   "p6600"
 778 #define CORENAME  "P6600"
 779 #else
 780 #endif
 781
 782 #ifdef FORCE_P5600
 783 #define FORCE
 784 #define ARCHITECTURE    "MIPS"
 785 #define SUBARCHITECTURE "P5600"
 786 #define SUBDIRNAME      "mips"
 787 #define ARCHCONFIG   "-DP5600 " \
 788        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 789        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 790        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 791 #define LIBNAME   "p5600"
 792 #define CORENAME  "P5600"
 793 #else
 794 #endif
 795
 796 #ifdef FORCE_I6500
 797 #define FORCE
 798 #define ARCHITECTURE    "MIPS"
 799 #define SUBARCHITECTURE "I6500"
 800 #define SUBDIRNAME      "mips64"
 801 #define ARCHCONFIG   "-DI6500 " \
 802        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 803        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 804        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 805 #define LIBNAME   "i6500"
 806 #define CORENAME  "I6500"
 807 #else
 808 #endif
 809
 810 #ifdef FORCE_ITANIUM2
 811 #define FORCE
 812 #define ARCHITECTURE    "IA64"
 813 #define SUBARCHITECTURE "ITANIUM2"
 814 #define SUBDIRNAME      "ia64"
 815 #define ARCHCONFIG   "-DITANIUM2 " \
 816                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 817                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 818 #define LIBNAME   "itanium2"
 819 #define CORENAME  "itanium2"
 820 #endif
 821
 822 #ifdef FORCE_SPARC
 823 #define FORCE
 824 #define ARCHITECTURE    "SPARC"
 825 #define SUBARCHITECTURE "SPARC"
 826 #define SUBDIRNAME      "sparc"
 827 #define ARCHCONFIG   "-DSPARC -DV9 " \
 828                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 829                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 830 #define LIBNAME   "sparc"
 831 #define CORENAME  "sparc"
 832 #endif
 833
 834 #ifdef FORCE_SPARCV7
 835 #define FORCE
 836 #define ARCHITECTURE    "SPARC"
 837 #define SUBARCHITECTURE "SPARC"
 838 #define SUBDIRNAME      "sparc"
 839 #define ARCHCONFIG   "-DSPARC -DV7 " \
 840                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 841                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 842 #define LIBNAME   "sparcv7"
 843 #define CORENAME  "sparcv7"
 844 #endif
 845
 846 #ifdef FORCE_GENERIC
 847 #define FORCE
 848 #define ARCHITECTURE    "GENERIC"
 849 #define SUBARCHITECTURE "GENERIC"
 850 #define SUBDIRNAME      "generic"
 851 #define ARCHCONFIG   "-DGENERIC " \
 852                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 853                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 854                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 855 #define LIBNAME   "generic"
 856 #define CORENAME  "generic"
 857 #endif
 858
 859 #ifdef FORCE_ARMV7
 860 #define FORCE
 861 #define ARCHITECTURE    "ARM"
 862 #define SUBARCHITECTURE "ARMV7"
 863 #define SUBDIRNAME      "arm"
 864 #define ARCHCONFIG   "-DARMV7 " \
 865        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 866        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 867        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 868        "-DHAVE_VFPV3 -DHAVE_VFP"
 869 #define LIBNAME   "armv7"
 870 #define CORENAME  "ARMV7"
 871 #else
 872 #endif
 873
 874 #ifdef FORCE_CORTEXA9
 875 #define FORCE
 876 #define ARCHITECTURE    "ARM"
 877 #define SUBARCHITECTURE "CORTEXA9"
 878 #define SUBDIRNAME      "arm"
 879 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 880        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 881        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 882        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 883        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 884 #define LIBNAME   "cortexa9"
 885 #define CORENAME  "CORTEXA9"
 886 #else
 887 #endif
 888
 889 #ifdef FORCE_CORTEXA15
 890 #define FORCE
 891 #define ARCHITECTURE    "ARM"
 892 #define SUBARCHITECTURE "CORTEXA15"
 893 #define SUBDIRNAME      "arm"
 894 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 895        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 896        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 897        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 898        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 899 #define LIBNAME   "cortexa15"
 900 #define CORENAME  "CORTEXA15"
 901 #else
 902 #endif
 903
 904 #ifdef FORCE_ARMV6
 905 #define FORCE
 906 #define ARCHITECTURE    "ARM"
 907 #define SUBARCHITECTURE "ARMV6"
 908 #define SUBDIRNAME      "arm"
 909 #define ARCHCONFIG   "-DARMV6 " \
 910        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 911        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 912        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 913        "-DHAVE_VFP"
 914 #define LIBNAME   "armv6"
 915 #define CORENAME  "ARMV6"
 916 #else
 917 #endif
 918
 919 #ifdef FORCE_ARMV5
 920 #define FORCE
 921 #define ARCHITECTURE    "ARM"
 922 #define SUBARCHITECTURE "ARMV5"
 923 #define SUBDIRNAME      "arm"
 924 #define ARCHCONFIG   "-DARMV5 " \
 925        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 926        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 927        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 928 #define LIBNAME   "armv5"
 929 #define CORENAME  "ARMV5"
 930 #else
 931 #endif
 932
 933
 934 #ifdef FORCE_ARMV8
 935 #define FORCE
 936 #define ARCHITECTURE    "ARM64"
 937 #define SUBARCHITECTURE "ARMV8"
 938 #define SUBDIRNAME      "arm64"
 939 #define ARCHCONFIG   "-DARMV8 " \
 940        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 941        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 942        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
 943        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
 944 #define LIBNAME   "armv8"
 945 #define CORENAME  "ARMV8"
 946 #endif
 947
 948 #ifdef FORCE_CORTEXA53
 949 #define FORCE
 950 #define ARCHITECTURE    "ARM64"
 951 #define SUBARCHITECTURE "CORTEXA53"
 952 #define SUBDIRNAME      "arm64"
 953 #define ARCHCONFIG   "-DCORTEXA53 " \
 954        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 955        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 956        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 957        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 958        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
 959 #define LIBNAME   "cortexa53"
 960 #define CORENAME  "CORTEXA53"
 961 #else
 962 #endif
 963
 964 #ifdef FORCE_CORTEXA57
 965 #define FORCE
 966 #define ARCHITECTURE    "ARM64"
 967 #define SUBARCHITECTURE "CORTEXA57"
 968 #define SUBDIRNAME      "arm64"
 969 #define ARCHCONFIG   "-DCORTEXA57 " \
 970        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 971        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 972        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 973        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 974        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
 975 #define LIBNAME   "cortexa57"
 976 #define CORENAME  "CORTEXA57"
 977 #else
 978 #endif
 979
 980 #ifdef FORCE_CORTEXA72
 981 #define FORCE
 982 #define ARCHITECTURE    "ARM64"
 983 #define SUBARCHITECTURE "CORTEXA72"
 984 #define SUBDIRNAME      "arm64"
 985 #define ARCHCONFIG   "-DCORTEXA72 " \
 986        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 987        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 988        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 989        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 990        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
 991 #define LIBNAME   "cortexa72"
 992 #define CORENAME  "CORTEXA72"
 993 #else
 994 #endif
 995
 996 #ifdef FORCE_CORTEXA73
 997 #define FORCE
 998 #define ARCHITECTURE    "ARM64"
 999 #define SUBARCHITECTURE "CORTEXA73"
1000 #define SUBDIRNAME      "arm64"
1001 #define ARCHCONFIG   "-DCORTEXA73 " \
1002        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1003        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1004        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1005        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1006        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1007 #define LIBNAME   "cortexa73"
1008 #define CORENAME  "CORTEXA73"
1009 #else
1010 #endif
1011
1012 #ifdef FORCE_FALKOR
1013 #define FORCE
1014 #define ARCHITECTURE    "ARM64"
1015 #define SUBARCHITECTURE "FALKOR"
1016 #define SUBDIRNAME      "arm64"
1017 #define ARCHCONFIG   "-DFALKOR " \
1018        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1019        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1020        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1021        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1022        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1023 #define LIBNAME   "falkor"
1024 #define CORENAME  "FALKOR"
1025 #else
1026 #endif
1027
1028 #ifdef FORCE_THUNDERX
1029 #define FORCE
1030 #define ARCHITECTURE    "ARM64"
1031 #define SUBARCHITECTURE "THUNDERX"
1032 #define SUBDIRNAME      "arm64"
1033 #define ARCHCONFIG   "-DTHUNDERX " \
1034        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1035        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1036        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1037        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1038 #define LIBNAME   "thunderx"
1039 #define CORENAME  "THUNDERX"
1040 #else
1041 #endif
1042
1043 #ifdef FORCE_THUNDERX2T99
1044 #define ARMV8
1045 #define FORCE
1046 #define ARCHITECTURE    "ARM64"
1047 #define SUBARCHITECTURE "THUNDERX2T99"
1048 #define SUBDIRNAME      "arm64"
1049 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1050        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1051        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1052        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1053        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1054        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1055        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1056 #define LIBNAME   "thunderx2t99"
1057 #define CORENAME  "THUNDERX2T99"
1058 #else
1059 #endif
1060
1061 #ifdef FORCE_ZARCH_GENERIC
1062 #define FORCE
1063 #define ARCHITECTURE    "ZARCH"
1064 #define SUBARCHITECTURE "ZARCH_GENERIC"
1065 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1066        "-DDTB_DEFAULT_ENTRIES=64"
1067 #define LIBNAME   "zarch_generic"
1068 #define CORENAME  "ZARCH_GENERIC"
1069 #endif
1070
1071 #ifdef FORCE_Z13
1072 #define FORCE
1073 #define ARCHITECTURE    "ZARCH"
1074 #define SUBARCHITECTURE "Z13"
1075 #define ARCHCONFIG   "-DZ13 " \
1076        "-DDTB_DEFAULT_ENTRIES=64"
1077 #define LIBNAME   "z13"
1078 #define CORENAME  "Z13"
1079 #endif
1080
1081 #ifndef FORCE
1082
1083 #ifdef USER_TARGET
1084 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1085 #endif
1086
1087 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1088     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1089 #ifndef POWER
1090 #define POWER
1091 #endif
1092 #define OPENBLAS_SUPPORTED
1093 #endif
1094
1095 #if defined(__zarch__) || defined(__s390x__)
1096 #define ZARCH
1097 #include "cpuid_zarch.c"
1098 #define OPENBLAS_SUPPORTED
1099 #endif
1100
1101 #ifdef INTEL_AMD
1102 #include "cpuid_x86.c"
1103 #define OPENBLAS_SUPPORTED
1104 #endif
1105
1106 #ifdef __ia64__
1107 #include "cpuid_ia64.c"
1108 #define OPENBLAS_SUPPORTED
1109 #endif
1110
1111 #ifdef __alpha
1112 #include "cpuid_alpha.c"
1113 #define OPENBLAS_SUPPORTED
1114 #endif
1115
1116 #ifdef POWER
1117 #include "cpuid_power.c"
1118 #define OPENBLAS_SUPPORTED
1119 #endif
1120
1121 #ifdef sparc
1122 #include "cpuid_sparc.c"
1123 #define OPENBLAS_SUPPORTED
1124 #endif
1125
1126 #ifdef __mips__
1127 #ifdef __mips64
1128 #include "cpuid_mips64.c"
1129 #else
1130 #include "cpuid_mips.c"
1131 #endif
1132 #define OPENBLAS_SUPPORTED
1133 #endif
1134
1135 #ifdef __arm__
1136 #include "cpuid_arm.c"
1137 #define OPENBLAS_SUPPORTED
1138 #endif
1139
1140 #ifdef __aarch64__
1141 #include "cpuid_arm64.c"
1142 #define OPENBLAS_SUPPORTED
1143 #endif
1144
1145
1146 #ifndef OPENBLAS_SUPPORTED
1147 #error "This arch/CPU is not supported by OpenBLAS."
1148 #endif
1149
1150 #else
1151
1152 #endif
1153
1154 static int get_num_cores(void) {
1155
1156 #ifdef OS_WINDOWS
1157   SYSTEM_INFO sysinfo;
1158 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1159   int m[2], count;
1160   size_t len;
1161 #endif
1162
1163 #if defined(linux) || defined(__sun__)
1164   //returns the number of processors which are currently online
1165   return sysconf(_SC_NPROCESSORS_CONF);
1166
1167 #elif defined(OS_WINDOWS)
1168
1169   GetSystemInfo(&sysinfo);
1170   return sysinfo.dwNumberOfProcessors;
1171
1172 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1173   m[0] = CTL_HW;
1174   m[1] = HW_NCPU;
1175   len = sizeof(int);
1176   sysctl(m, 2, &count, &len, NULL, 0);
1177
1178   return count;
1179 #else
1180   return 2;
1181 #endif
1182 }
1183
1184 int main(int argc, char *argv[]){
1185
1186 #ifdef FORCE
1187   char buffer[8192], *p, *q;
1188   int length;
1189 #endif
1190
1191   if (argc == 1) return 0;
1192
1193   switch (argv[1][0]) {
1194
1195   case '0' : /* for Makefile */
1196
1197 #ifdef FORCE
1198     printf("CORE=%s\n", CORENAME);
1199 #else
1200 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1201     printf("CORE=%s\n", get_corename());
1202 #endif
1203 #endif
1204
1205 #ifdef FORCE
1206     printf("LIBCORE=%s\n", LIBNAME);
1207 #else
1208     printf("LIBCORE=");
1209     get_libname();
1210     printf("\n");
1211 #endif
1212
1213     printf("NUM_CORES=%d\n", get_num_cores());
1214
1215 #if defined(__arm__) && !defined(FORCE)
1216         get_features();
1217 #endif
1218
1219
1220 #ifdef INTEL_AMD
1221 #ifndef FORCE
1222     get_sse();
1223 #else
1224
1225     sprintf(buffer, "%s", ARCHCONFIG);
1226
1227     p = &buffer[0];
1228
1229     while (*p) {
1230       if ((*p == '-') && (*(p + 1) == 'D')) {
1231         p += 2;
1232
1233         while ((*p != ' ') && (*p != '\0')) {
1234
1235           if (*p == '=') {
1236             printf("=");
1237             p ++;
1238             while ((*p != ' ') && (*p != '\0')) {
1239               printf("%c", *p);
1240               p ++;
1241             }
1242           } else {
1243             printf("%c", *p);
1244             p ++;
1245             if ((*p == ' ') || (*p =='\0')) printf("=1");
1246           }
1247         }
1248
1249         printf("\n");
1250       } else p ++;
1251     }
1252 #endif
1253 #endif
1254
1255 #ifdef MAKE_NB_JOBS
1256   #if MAKE_NB_JOBS > 0
1257     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1258   #else
1259     // Let make use parent -j argument or -j1 if there
1260     // is no make parent
1261   #endif
1262 #elif NO_PARALLEL_MAKE==1
1263     printf("MAKE += -j 1\n");
1264 #else
1265     printf("MAKE += -j %d\n", get_num_cores());
1266 #endif
1267
1268     break;
1269
1270   case '1' : /* For config.h */
1271 #ifdef FORCE
1272     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1273
1274     p = &buffer[0];
1275     while (*p) {
1276       if ((*p == '-') && (*(p + 1) == 'D')) {
1277         p += 2;
1278         printf("#define ");
1279
1280         while ((*p != ' ') && (*p != '\0')) {
1281
1282           if (*p == '=') {
1283             printf(" ");
1284             p ++;
1285             while ((*p != ' ') && (*p != '\0')) {
1286               printf("%c", *p);
1287               p ++;
1288             }
1289           } else {
1290             if (*p != '\n')
1291             printf("%c", *p);
1292             p ++;
1293           }
1294         }
1295
1296         printf("\n");
1297       } else p ++;
1298     }
1299 #else
1300     get_cpuconfig();
1301 #endif
1302
1303 #ifdef FORCE
1304     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1305 #else
1306 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1307     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1308 #endif
1309 #endif
1310
1311  break;
1312
1313   case '2' : /* SMP */
1314     if (get_num_cores() > 1) printf("SMP=1\n");
1315     break;
1316   }
1317
1318   fflush(stdout);
1319
1320   return 0;
1321 }
1322