getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P6600          */
 136 /* #define FORCE_P5600          */
 137 /* #define FORCE_I6500          */
 138 /* #define FORCE_ITANIUM2       */
 139 /* #define FORCE_SPARC          */
 140 /* #define FORCE_SPARCV7        */
 141 /* #define FORCE_ZARCH_GENERIC  */
 142 /* #define FORCE_Z13            */
 143 /* #define FORCE_GENERIC        */
 144
 145 #ifdef FORCE_P2
 146 #define FORCE
 147 #define FORCE_INTEL
 148 #define ARCHITECTURE    "X86"
 149 #define SUBARCHITECTURE "PENTIUM2"
 150 #define ARCHCONFIG   "-DPENTIUM2 " \
 151                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 152                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 153                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 154                      "-DHAVE_CMOV -DHAVE_MMX"
 155 #define LIBNAME   "p2"
 156 #define CORENAME  "P5"
 157 #endif
 158
 159 #ifdef FORCE_KATMAI
 160 #define FORCE
 161 #define FORCE_INTEL
 162 #define ARCHITECTURE    "X86"
 163 #define SUBARCHITECTURE "PENTIUM3"
 164 #define ARCHCONFIG   "-DPENTIUM3 " \
 165                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 166                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 167                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 168                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 169 #define LIBNAME   "katmai"
 170 #define CORENAME  "KATMAI"
 171 #endif
 172
 173 #ifdef FORCE_COPPERMINE
 174 #define FORCE
 175 #define FORCE_INTEL
 176 #define ARCHITECTURE    "X86"
 177 #define SUBARCHITECTURE "PENTIUM3"
 178 #define ARCHCONFIG   "-DPENTIUM3 " \
 179                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 180                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 181                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 182                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 183 #define LIBNAME   "coppermine"
 184 #define CORENAME  "COPPERMINE"
 185 #endif
 186
 187 #ifdef FORCE_NORTHWOOD
 188 #define FORCE
 189 #define FORCE_INTEL
 190 #define ARCHITECTURE    "X86"
 191 #define SUBARCHITECTURE "PENTIUM4"
 192 #define ARCHCONFIG   "-DPENTIUM4 " \
 193                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 194                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 195                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 196                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 197 #define LIBNAME   "northwood"
 198 #define CORENAME  "NORTHWOOD"
 199 #endif
 200
 201 #ifdef FORCE_PRESCOTT
 202 #define FORCE
 203 #define FORCE_INTEL
 204 #define ARCHITECTURE    "X86"
 205 #define SUBARCHITECTURE "PENTIUM4"
 206 #define ARCHCONFIG   "-DPENTIUM4 " \
 207                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 208                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 209                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 210                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 211 #define LIBNAME   "prescott"
 212 #define CORENAME  "PRESCOTT"
 213 #endif
 214
 215 #ifdef FORCE_BANIAS
 216 #define FORCE
 217 #define FORCE_INTEL
 218 #define ARCHITECTURE    "X86"
 219 #define SUBARCHITECTURE "BANIAS"
 220 #define ARCHCONFIG   "-DPENTIUMM " \
 221                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 222                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 223                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 224                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 225 #define LIBNAME   "banias"
 226 #define CORENAME  "BANIAS"
 227 #endif
 228
 229 #ifdef FORCE_YONAH
 230 #define FORCE
 231 #define FORCE_INTEL
 232 #define ARCHITECTURE    "X86"
 233 #define SUBARCHITECTURE "YONAH"
 234 #define ARCHCONFIG   "-DPENTIUMM " \
 235                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 236                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 237                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 238                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 239 #define LIBNAME   "yonah"
 240 #define CORENAME  "YONAH"
 241 #endif
 242
 243 #ifdef FORCE_CORE2
 244 #define FORCE
 245 #define FORCE_INTEL
 246 #define ARCHITECTURE    "X86"
 247 #define SUBARCHITECTURE "CONRORE"
 248 #define ARCHCONFIG   "-DCORE2 " \
 249                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 250                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 251                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 252                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 253 #define LIBNAME   "core2"
 254 #define CORENAME  "CORE2"
 255 #endif
 256
 257 #ifdef FORCE_PENRYN
 258 #define FORCE
 259 #define FORCE_INTEL
 260 #define ARCHITECTURE    "X86"
 261 #define SUBARCHITECTURE "PENRYN"
 262 #define ARCHCONFIG   "-DPENRYN " \
 263                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 264                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 265                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 266                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 267 #define LIBNAME   "penryn"
 268 #define CORENAME  "PENRYN"
 269 #endif
 270
 271 #ifdef FORCE_DUNNINGTON
 272 #define FORCE
 273 #define FORCE_INTEL
 274 #define ARCHITECTURE    "X86"
 275 #define SUBARCHITECTURE "DUNNINGTON"
 276 #define ARCHCONFIG   "-DDUNNINGTON " \
 277                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 278                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 279                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 280                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 281                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 282 #define LIBNAME   "dunnington"
 283 #define CORENAME  "DUNNINGTON"
 284 #endif
 285
 286 #ifdef FORCE_NEHALEM
 287 #define FORCE
 288 #define FORCE_INTEL
 289 #define ARCHITECTURE    "X86"
 290 #define SUBARCHITECTURE "NEHALEM"
 291 #define ARCHCONFIG   "-DNEHALEM " \
 292                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 293                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 294                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 295                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 296 #define LIBNAME   "nehalem"
 297 #define CORENAME  "NEHALEM"
 298 #endif
 299
 300 #ifdef FORCE_SANDYBRIDGE
 301 #define FORCE
 302 #define FORCE_INTEL
 303 #define ARCHITECTURE    "X86"
 304 #define SUBARCHITECTURE "SANDYBRIDGE"
 305 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 306                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 307                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 308                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 309                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 310 #define LIBNAME   "sandybridge"
 311 #define CORENAME  "SANDYBRIDGE"
 312 #endif
 313
 314 #ifdef FORCE_HASWELL
 315 #define FORCE
 316 #define FORCE_INTEL
 317 #define ARCHITECTURE    "X86"
 318 #define SUBARCHITECTURE "HASWELL"
 319 #define ARCHCONFIG   "-DHASWELL " \
 320                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 321                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 322                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 323                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 324                      "-DFMA3"
 325 #define LIBNAME   "haswell"
 326 #define CORENAME  "HASWELL"
 327 #endif
 328
 329 #ifdef FORCE_SKYLAKEX
 330 #define FORCE
 331 #define FORCE_INTEL
 332 #define ARCHITECTURE    "X86"
 333 #define SUBARCHITECTURE "SKYLAKEX"
 334 #define ARCHCONFIG   "-DSKYLAKEX " \
 335                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 336                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 337                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 338                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 339                      "-DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 340 #define LIBNAME   "skylakex"
 341 #define CORENAME  "SKYLAKEX"
 342 #endif
 343
 344 #ifdef FORCE_ATOM
 345 #define FORCE
 346 #define FORCE_INTEL
 347 #define ARCHITECTURE    "X86"
 348 #define SUBARCHITECTURE "ATOM"
 349 #define ARCHCONFIG   "-DATOM " \
 350                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 351                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 352                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 353                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 354 #define LIBNAME   "atom"
 355 #define CORENAME  "ATOM"
 356 #endif
 357
 358 #ifdef FORCE_ATHLON
 359 #define FORCE
 360 #define FORCE_INTEL
 361 #define ARCHITECTURE    "X86"
 362 #define SUBARCHITECTURE "ATHLON"
 363 #define ARCHCONFIG   "-DATHLON " \
 364                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 365                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 366                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 367                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 368 #define LIBNAME   "athlon"
 369 #define CORENAME  "ATHLON"
 370 #endif
 371
 372 #ifdef FORCE_OPTERON
 373 #define FORCE
 374 #define FORCE_INTEL
 375 #define ARCHITECTURE    "X86"
 376 #define SUBARCHITECTURE "OPTERON"
 377 #define ARCHCONFIG   "-DOPTERON " \
 378                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 379                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 380                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 381                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 382 #define LIBNAME   "opteron"
 383 #define CORENAME  "OPTERON"
 384 #endif
 385
 386 #ifdef FORCE_OPTERON_SSE3
 387 #define FORCE
 388 #define FORCE_INTEL
 389 #define ARCHITECTURE    "X86"
 390 #define SUBARCHITECTURE "OPTERON"
 391 #define ARCHCONFIG   "-DOPTERON " \
 392                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 393                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 394                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 395                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 396 #define LIBNAME   "opteron"
 397 #define CORENAME  "OPTERON"
 398 #endif
 399
 400 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 401 #define FORCE
 402 #define FORCE_INTEL
 403 #define ARCHITECTURE    "X86"
 404 #define SUBARCHITECTURE "BARCELONA"
 405 #define ARCHCONFIG   "-DBARCELONA " \
 406                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 407                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 408                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 409                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 410                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 411 #define LIBNAME   "barcelona"
 412 #define CORENAME  "BARCELONA"
 413 #endif
 414
 415 #if defined(FORCE_BOBCAT)
 416 #define FORCE
 417 #define FORCE_INTEL
 418 #define ARCHITECTURE    "X86"
 419 #define SUBARCHITECTURE "BOBCAT"
 420 #define ARCHCONFIG   "-DBOBCAT " \
 421                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 422                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 423                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 424                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 425                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 426 #define LIBNAME   "bobcat"
 427 #define CORENAME  "BOBCAT"
 428 #endif
 429
 430 #if defined (FORCE_BULLDOZER)
 431 #define FORCE
 432 #define FORCE_INTEL
 433 #define ARCHITECTURE    "X86"
 434 #define SUBARCHITECTURE "BULLDOZER"
 435 #define ARCHCONFIG   "-DBULLDOZER " \
 436                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 437                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 438                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 439                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 440                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 441                      "-DHAVE_AVX -DHAVE_FMA4"
 442 #define LIBNAME   "bulldozer"
 443 #define CORENAME  "BULLDOZER"
 444 #endif
 445
 446 #if defined (FORCE_PILEDRIVER)
 447 #define FORCE
 448 #define FORCE_INTEL
 449 #define ARCHITECTURE    "X86"
 450 #define SUBARCHITECTURE "PILEDRIVER"
 451 #define ARCHCONFIG   "-DPILEDRIVER " \
 452                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 453                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 454                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 455                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 456                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 457                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 458 #define LIBNAME   "piledriver"
 459 #define CORENAME  "PILEDRIVER"
 460 #endif
 461
 462 #if defined (FORCE_STEAMROLLER)
 463 #define FORCE
 464 #define FORCE_INTEL
 465 #define ARCHITECTURE    "X86"
 466 #define SUBARCHITECTURE "STEAMROLLER"
 467 #define ARCHCONFIG   "-DSTEAMROLLER " \
 468                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 469                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 470                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 471                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 472                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 473                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 474 #define LIBNAME   "steamroller"
 475 #define CORENAME  "STEAMROLLER"
 476 #endif
 477
 478 #if defined (FORCE_EXCAVATOR)
 479 #define FORCE
 480 #define FORCE_INTEL
 481 #define ARCHITECTURE    "X86"
 482 #define SUBARCHITECTURE "EXCAVATOR"
 483 #define ARCHCONFIG   "-DEXCAVATOR " \
 484                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 485                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 486                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 487                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 488                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 489                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 490 #define LIBNAME   "excavator"
 491 #define CORENAME  "EXCAVATOR"
 492 #endif
 493
 494 #if defined (FORCE_ZEN)
 495 #define FORCE
 496 #define FORCE_INTEL
 497 #define ARCHITECTURE    "X86"
 498 #define SUBARCHITECTURE "ZEN"
 499 #define ARCHCONFIG   "-DZEN " \
 500                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 501                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 502                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 503                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 504                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 505                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 506                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 507                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 508                      "-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
 509 #define LIBNAME   "zen"
 510 #define CORENAME  "ZEN"
 511 #endif
 512
 513
 514 #ifdef FORCE_SSE_GENERIC
 515 #define FORCE
 516 #define FORCE_INTEL
 517 #define ARCHITECTURE    "X86"
 518 #define SUBARCHITECTURE "GENERIC"
 519 #define ARCHCONFIG   "-DGENERIC " \
 520                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 521                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 522                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 523                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 524 #define LIBNAME   "generic"
 525 #define CORENAME  "GENERIC"
 526 #endif
 527
 528 #ifdef FORCE_VIAC3
 529 #define FORCE
 530 #define FORCE_INTEL
 531 #define ARCHITECTURE    "X86"
 532 #define SUBARCHITECTURE "VIAC3"
 533 #define ARCHCONFIG   "-DVIAC3 " \
 534                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 535                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 536                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 537                      "-DHAVE_MMX -DHAVE_SSE "
 538 #define LIBNAME   "viac3"
 539 #define CORENAME  "VIAC3"
 540 #endif
 541
 542 #ifdef FORCE_NANO
 543 #define FORCE
 544 #define FORCE_INTEL
 545 #define ARCHITECTURE    "X86"
 546 #define SUBARCHITECTURE "NANO"
 547 #define ARCHCONFIG   "-DNANO " \
 548                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 549                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 550                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 551                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 552 #define LIBNAME   "nano"
 553 #define CORENAME  "NANO"
 554 #endif
 555
 556 #ifdef FORCE_POWER3
 557 #define FORCE
 558 #define ARCHITECTURE    "POWER"
 559 #define SUBARCHITECTURE "POWER3"
 560 #define SUBDIRNAME      "power"
 561 #define ARCHCONFIG   "-DPOWER3 " \
 562                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 563                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 564                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 565 #define LIBNAME   "power3"
 566 #define CORENAME  "POWER3"
 567 #endif
 568
 569 #ifdef FORCE_POWER4
 570 #define FORCE
 571 #define ARCHITECTURE    "POWER"
 572 #define SUBARCHITECTURE "POWER4"
 573 #define SUBDIRNAME      "power"
 574 #define ARCHCONFIG   "-DPOWER4 " \
 575                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 576                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 577                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 578 #define LIBNAME   "power4"
 579 #define CORENAME  "POWER4"
 580 #endif
 581
 582 #ifdef FORCE_POWER5
 583 #define FORCE
 584 #define ARCHITECTURE    "POWER"
 585 #define SUBARCHITECTURE "POWER5"
 586 #define SUBDIRNAME      "power"
 587 #define ARCHCONFIG   "-DPOWER5 " \
 588                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 589                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 590                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 591 #define LIBNAME   "power5"
 592 #define CORENAME  "POWER5"
 593 #endif
 594
 595 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 596 #define FORCE
 597 #define ARCHITECTURE    "POWER"
 598 #define SUBARCHITECTURE "POWER6"
 599 #define SUBDIRNAME      "power"
 600 #define ARCHCONFIG   "-DPOWER6 " \
 601                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 602                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 603                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 604 #define LIBNAME   "power6"
 605 #define CORENAME  "POWER6"
 606 #endif
 607
 608 #if defined(FORCE_POWER8)
 609 #define FORCE
 610 #define ARCHITECTURE    "POWER"
 611 #define SUBARCHITECTURE "POWER8"
 612 #define SUBDIRNAME      "power"
 613 #define ARCHCONFIG   "-DPOWER8 " \
 614                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 615                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 616                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 617 #define LIBNAME   "power8"
 618 #define CORENAME  "POWER8"
 619 #endif
 620
 621
 622 #ifdef FORCE_PPCG4
 623 #define FORCE
 624 #define ARCHITECTURE    "POWER"
 625 #define SUBARCHITECTURE "PPCG4"
 626 #define SUBDIRNAME      "power"
 627 #define ARCHCONFIG   "-DPPCG4 " \
 628                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 629                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 630                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 631 #define LIBNAME   "ppcg4"
 632 #define CORENAME  "PPCG4"
 633 #endif
 634
 635 #ifdef FORCE_PPC970
 636 #define FORCE
 637 #define ARCHITECTURE    "POWER"
 638 #define SUBARCHITECTURE "PPC970"
 639 #define SUBDIRNAME      "power"
 640 #define ARCHCONFIG   "-DPPC970 " \
 641                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 642                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 643                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 644 #define LIBNAME   "ppc970"
 645 #define CORENAME  "PPC970"
 646 #endif
 647
 648 #ifdef FORCE_PPC970MP
 649 #define FORCE
 650 #define ARCHITECTURE    "POWER"
 651 #define SUBARCHITECTURE "PPC970"
 652 #define SUBDIRNAME      "power"
 653 #define ARCHCONFIG   "-DPPC970 " \
 654                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 655                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 656                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 657 #define LIBNAME   "ppc970mp"
 658 #define CORENAME  "PPC970"
 659 #endif
 660
 661 #ifdef FORCE_PPC440
 662 #define FORCE
 663 #define ARCHITECTURE    "POWER"
 664 #define SUBARCHITECTURE "PPC440"
 665 #define SUBDIRNAME      "power"
 666 #define ARCHCONFIG   "-DPPC440 " \
 667                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 668                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 669                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 670 #define LIBNAME   "ppc440"
 671 #define CORENAME  "PPC440"
 672 #endif
 673
 674 #ifdef FORCE_PPC440FP2
 675 #define FORCE
 676 #define ARCHITECTURE    "POWER"
 677 #define SUBARCHITECTURE "PPC440FP2"
 678 #define SUBDIRNAME      "power"
 679 #define ARCHCONFIG   "-DPPC440FP2 " \
 680                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 681                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 682                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 683 #define LIBNAME   "ppc440FP2"
 684 #define CORENAME  "PPC440FP2"
 685 #endif
 686
 687 #ifdef FORCE_CELL
 688 #define FORCE
 689 #define ARCHITECTURE    "POWER"
 690 #define SUBARCHITECTURE "CELL"
 691 #define SUBDIRNAME      "power"
 692 #define ARCHCONFIG   "-DCELL " \
 693                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 694                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 695                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 696 #define LIBNAME   "cell"
 697 #define CORENAME  "CELL"
 698 #endif
 699
 700 #ifdef FORCE_SICORTEX
 701 #define FORCE
 702 #define ARCHITECTURE    "MIPS"
 703 #define SUBARCHITECTURE "SICORTEX"
 704 #define SUBDIRNAME      "mips"
 705 #define ARCHCONFIG   "-DSICORTEX " \
 706                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 707                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 708                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 709 #define LIBNAME   "mips"
 710 #define CORENAME  "sicortex"
 711 #endif
 712
 713
 714 #ifdef FORCE_LOONGSON3A
 715 #define FORCE
 716 #define ARCHITECTURE    "MIPS"
 717 #define SUBARCHITECTURE "LOONGSON3A"
 718 #define SUBDIRNAME      "mips64"
 719 #define ARCHCONFIG   "-DLOONGSON3A " \
 720        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 721        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 722        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 723 #define LIBNAME   "loongson3a"
 724 #define CORENAME  "LOONGSON3A"
 725 #else
 726 #endif
 727
 728 #ifdef FORCE_LOONGSON3B
 729 #define FORCE
 730 #define ARCHITECTURE    "MIPS"
 731 #define SUBARCHITECTURE "LOONGSON3B"
 732 #define SUBDIRNAME      "mips64"
 733 #define ARCHCONFIG   "-DLOONGSON3B " \
 734        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 735        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 736        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 737 #define LIBNAME   "loongson3b"
 738 #define CORENAME  "LOONGSON3B"
 739 #else
 740 #endif
 741
 742 #ifdef FORCE_I6400
 743 #define FORCE
 744 #define ARCHITECTURE    "MIPS"
 745 #define SUBARCHITECTURE "I6400"
 746 #define SUBDIRNAME      "mips64"
 747 #define ARCHCONFIG   "-DI6400 " \
 748        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 749        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 750        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 751 #define LIBNAME   "i6400"
 752 #define CORENAME  "I6400"
 753 #else
 754 #endif
 755
 756 #ifdef FORCE_P6600
 757 #define FORCE
 758 #define ARCHITECTURE    "MIPS"
 759 #define SUBARCHITECTURE "P6600"
 760 #define SUBDIRNAME      "mips64"
 761 #define ARCHCONFIG   "-DP6600 " \
 762        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 763        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 764        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 765 #define LIBNAME   "p6600"
 766 #define CORENAME  "P6600"
 767 #else
 768 #endif
 769
 770 #ifdef FORCE_P5600
 771 #define FORCE
 772 #define ARCHITECTURE    "MIPS"
 773 #define SUBARCHITECTURE "P5600"
 774 #define SUBDIRNAME      "mips"
 775 #define ARCHCONFIG   "-DP5600 " \
 776        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 777        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 778        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 779 #define LIBNAME   "p5600"
 780 #define CORENAME  "P5600"
 781 #else
 782 #endif
 783
 784 #ifdef FORCE_I6500
 785 #define FORCE
 786 #define ARCHITECTURE    "MIPS"
 787 #define SUBARCHITECTURE "I6500"
 788 #define SUBDIRNAME      "mips64"
 789 #define ARCHCONFIG   "-DI6500 " \
 790        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 791        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 792        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 793 #define LIBNAME   "i6500"
 794 #define CORENAME  "I6500"
 795 #else
 796 #endif
 797
 798 #ifdef FORCE_ITANIUM2
 799 #define FORCE
 800 #define ARCHITECTURE    "IA64"
 801 #define SUBARCHITECTURE "ITANIUM2"
 802 #define SUBDIRNAME      "ia64"
 803 #define ARCHCONFIG   "-DITANIUM2 " \
 804                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 805                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 806 #define LIBNAME   "itanium2"
 807 #define CORENAME  "itanium2"
 808 #endif
 809
 810 #ifdef FORCE_SPARC
 811 #define FORCE
 812 #define ARCHITECTURE    "SPARC"
 813 #define SUBARCHITECTURE "SPARC"
 814 #define SUBDIRNAME      "sparc"
 815 #define ARCHCONFIG   "-DSPARC -DV9 " \
 816                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 817                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 818 #define LIBNAME   "sparc"
 819 #define CORENAME  "sparc"
 820 #endif
 821
 822 #ifdef FORCE_SPARCV7
 823 #define FORCE
 824 #define ARCHITECTURE    "SPARC"
 825 #define SUBARCHITECTURE "SPARC"
 826 #define SUBDIRNAME      "sparc"
 827 #define ARCHCONFIG   "-DSPARC -DV7 " \
 828                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 829                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 830 #define LIBNAME   "sparcv7"
 831 #define CORENAME  "sparcv7"
 832 #endif
 833
 834 #ifdef FORCE_GENERIC
 835 #define FORCE
 836 #define ARCHITECTURE    "GENERIC"
 837 #define SUBARCHITECTURE "GENERIC"
 838 #define SUBDIRNAME      "generic"
 839 #define ARCHCONFIG   "-DGENERIC " \
 840                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 841                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 842                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 843 #define LIBNAME   "generic"
 844 #define CORENAME  "generic"
 845 #endif
 846
 847 #ifdef FORCE_ARMV7
 848 #define FORCE
 849 #define ARCHITECTURE    "ARM"
 850 #define SUBARCHITECTURE "ARMV7"
 851 #define SUBDIRNAME      "arm"
 852 #define ARCHCONFIG   "-DARMV7 " \
 853        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 854        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 855        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 856        "-DHAVE_VFPV3 -DHAVE_VFP"
 857 #define LIBNAME   "armv7"
 858 #define CORENAME  "ARMV7"
 859 #else
 860 #endif
 861
 862 #ifdef FORCE_CORTEXA9
 863 #define FORCE
 864 #define ARCHITECTURE    "ARM"
 865 #define SUBARCHITECTURE "CORTEXA9"
 866 #define SUBDIRNAME      "arm"
 867 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 868        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 869        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 870        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 871        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 872 #define LIBNAME   "cortexa9"
 873 #define CORENAME  "CORTEXA9"
 874 #else
 875 #endif
 876
 877 #ifdef FORCE_CORTEXA15
 878 #define FORCE
 879 #define ARCHITECTURE    "ARM"
 880 #define SUBARCHITECTURE "CORTEXA15"
 881 #define SUBDIRNAME      "arm"
 882 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 883        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 884        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 885        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 886        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 887 #define LIBNAME   "cortexa15"
 888 #define CORENAME  "CORTEXA15"
 889 #else
 890 #endif
 891
 892 #ifdef FORCE_ARMV6
 893 #define FORCE
 894 #define ARCHITECTURE    "ARM"
 895 #define SUBARCHITECTURE "ARMV6"
 896 #define SUBDIRNAME      "arm"
 897 #define ARCHCONFIG   "-DARMV6 " \
 898        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 899        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 900        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 901        "-DHAVE_VFP"
 902 #define LIBNAME   "armv6"
 903 #define CORENAME  "ARMV6"
 904 #else
 905 #endif
 906
 907 #ifdef FORCE_ARMV5
 908 #define FORCE
 909 #define ARCHITECTURE    "ARM"
 910 #define SUBARCHITECTURE "ARMV5"
 911 #define SUBDIRNAME      "arm"
 912 #define ARCHCONFIG   "-DARMV5 " \
 913        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 914        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 915        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 916 #define LIBNAME   "armv5"
 917 #define CORENAME  "ARMV5"
 918 #else
 919 #endif
 920
 921
 922 #ifdef FORCE_ARMV8
 923 #define FORCE
 924 #define ARCHITECTURE    "ARM64"
 925 #define SUBARCHITECTURE "ARMV8"
 926 #define SUBDIRNAME      "arm64"
 927 #define ARCHCONFIG   "-DARMV8 " \
 928        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 929        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 930        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 931 #define LIBNAME   "armv8"
 932 #define CORENAME  "ARMV8"
 933 #endif
 934
 935 #ifdef FORCE_CORTEXA57
 936 #define FORCE
 937 #define ARCHITECTURE    "ARM64"
 938 #define SUBARCHITECTURE "CORTEXA57"
 939 #define SUBDIRNAME      "arm64"
 940 #define ARCHCONFIG   "-DCORTEXA57 " \
 941        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 942        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 943        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 944        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 945        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 946 #define LIBNAME   "cortexa57"
 947 #define CORENAME  "CORTEXA57"
 948 #else
 949 #endif
 950
 951 #ifdef FORCE_VULCAN
 952 #define FORCE
 953 #define ARCHITECTURE    "ARM64"
 954 #define SUBARCHITECTURE "VULCAN"
 955 #define SUBDIRNAME      "arm64"
 956 #define ARCHCONFIG   "-DVULCAN " \
 957        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 958        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 959        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 960        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 961        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 962        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 963 #define LIBNAME   "vulcan"
 964 #define CORENAME  "VULCAN"
 965 #else
 966 #endif
 967
 968 #ifdef FORCE_THUNDERX
 969 #define FORCE
 970 #define ARCHITECTURE    "ARM64"
 971 #define SUBARCHITECTURE "THUNDERX"
 972 #define SUBDIRNAME      "arm64"
 973 #define ARCHCONFIG   "-DTHUNDERX " \
 974        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 975        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
 976        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 "
 977 #define LIBNAME   "thunderx"
 978 #define CORENAME  "THUNDERX"
 979 #else
 980 #endif
 981
 982 #ifdef FORCE_THUNDERX2T99
 983 #define FORCE
 984 #define ARCHITECTURE    "ARM64"
 985 #define SUBARCHITECTURE "THUNDERX2T99"
 986 #define SUBDIRNAME      "arm64"
 987 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
 988        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 989        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
 990        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 991        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
 992        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 993        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 994 #define LIBNAME   "thunderx2t99"
 995 #define CORENAME  "THUNDERX2T99"
 996 #else
 997 #endif
 998
 999 #ifdef FORCE_ZARCH_GENERIC
1000 #define FORCE
1001 #define ARCHITECTURE    "ZARCH"
1002 #define SUBARCHITECTURE "ZARCH_GENERIC"
1003 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1004        "-DDTB_DEFAULT_ENTRIES=64"
1005 #define LIBNAME   "zarch_generic"
1006 #define CORENAME  "ZARCH_GENERIC"
1007 #endif
1008
1009 #ifdef FORCE_Z13
1010 #define FORCE
1011 #define ARCHITECTURE    "ZARCH"
1012 #define SUBARCHITECTURE "Z13"
1013 #define ARCHCONFIG   "-DZ13 " \
1014        "-DDTB_DEFAULT_ENTRIES=64"
1015 #define LIBNAME   "z13"
1016 #define CORENAME  "Z13"
1017 #endif
1018
1019 #ifndef FORCE
1020
1021 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1022     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1023 #ifndef POWER
1024 #define POWER
1025 #endif
1026 #define OPENBLAS_SUPPORTED
1027 #endif
1028
1029 #if defined(__zarch__) || defined(__s390x__)
1030 #define ZARCH
1031 #include "cpuid_zarch.c"
1032 #define OPENBLAS_SUPPORTED
1033 #endif
1034
1035 #ifdef INTEL_AMD
1036 #include "cpuid_x86.c"
1037 #define OPENBLAS_SUPPORTED
1038 #endif
1039
1040 #ifdef __ia64__
1041 #include "cpuid_ia64.c"
1042 #define OPENBLAS_SUPPORTED
1043 #endif
1044
1045 #ifdef __alpha
1046 #include "cpuid_alpha.c"
1047 #define OPENBLAS_SUPPORTED
1048 #endif
1049
1050 #ifdef POWER
1051 #include "cpuid_power.c"
1052 #define OPENBLAS_SUPPORTED
1053 #endif
1054
1055 #ifdef sparc
1056 #include "cpuid_sparc.c"
1057 #define OPENBLAS_SUPPORTED
1058 #endif
1059
1060 #ifdef __mips__
1061 #ifdef __mips64
1062 #include "cpuid_mips64.c"
1063 #else
1064 #include "cpuid_mips.c"
1065 #endif
1066 #define OPENBLAS_SUPPORTED
1067 #endif
1068
1069 #ifdef __arm__
1070 #include "cpuid_arm.c"
1071 #define OPENBLAS_SUPPORTED
1072 #endif
1073
1074 #ifdef __aarch64__
1075 #include "cpuid_arm64.c"
1076 #define OPENBLAS_SUPPORTED
1077 #endif
1078
1079
1080 #ifndef OPENBLAS_SUPPORTED
1081 #error "This arch/CPU is not supported by OpenBLAS."
1082 #endif
1083
1084 #else
1085
1086 #endif
1087
1088 static int get_num_cores(void) {
1089
1090 #ifdef OS_WINDOWS
1091   SYSTEM_INFO sysinfo;
1092 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1093   int m[2], count;
1094   size_t len;
1095 #endif
1096
1097 #if defined(linux) || defined(__sun__)
1098   //returns the number of processors which are currently online
1099   return sysconf(_SC_NPROCESSORS_CONF);
1100
1101 #elif defined(OS_WINDOWS)
1102
1103   GetSystemInfo(&sysinfo);
1104   return sysinfo.dwNumberOfProcessors;
1105
1106 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1107   m[0] = CTL_HW;
1108   m[1] = HW_NCPU;
1109   len = sizeof(int);
1110   sysctl(m, 2, &count, &len, NULL, 0);
1111
1112   return count;
1113 #else
1114   return 2;
1115 #endif
1116 }
1117
1118 int main(int argc, char *argv[]){
1119
1120 #ifdef FORCE
1121   char buffer[8192], *p, *q;
1122   int length;
1123 #endif
1124
1125   if (argc == 1) return 0;
1126
1127   switch (argv[1][0]) {
1128
1129   case '0' : /* for Makefile */
1130
1131 #ifdef FORCE
1132     printf("CORE=%s\n", CORENAME);
1133 #else
1134 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1135     printf("CORE=%s\n", get_corename());
1136 #endif
1137 #endif
1138
1139 #ifdef FORCE
1140     printf("LIBCORE=%s\n", LIBNAME);
1141 #else
1142     printf("LIBCORE=");
1143     get_libname();
1144     printf("\n");
1145 #endif
1146
1147     printf("NUM_CORES=%d\n", get_num_cores());
1148
1149 #if defined(__arm__) && !defined(FORCE)
1150         get_features();
1151 #endif
1152
1153
1154 #ifdef INTEL_AMD
1155 #ifndef FORCE
1156     get_sse();
1157 #else
1158
1159     sprintf(buffer, "%s", ARCHCONFIG);
1160
1161     p = &buffer[0];
1162
1163     while (*p) {
1164       if ((*p == '-') && (*(p + 1) == 'D')) {
1165         p += 2;
1166
1167         while ((*p != ' ') && (*p != '\0')) {
1168
1169           if (*p == '=') {
1170             printf("=");
1171             p ++;
1172             while ((*p != ' ') && (*p != '\0')) {
1173               printf("%c", *p);
1174               p ++;
1175             }
1176           } else {
1177             printf("%c", *p);
1178             p ++;
1179             if ((*p == ' ') || (*p =='\0')) printf("=1");
1180           }
1181         }
1182
1183         printf("\n");
1184       } else p ++;
1185     }
1186 #endif
1187 #endif
1188
1189 #ifdef MAKE_NB_JOBS
1190   #if MAKE_NB_JOBS > 0
1191     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1192   #else
1193     // Let make use parent -j argument or -j1 if there
1194     // is no make parent
1195   #endif
1196 #elif NO_PARALLEL_MAKE==1
1197     printf("MAKE += -j 1\n");
1198 #else
1199     printf("MAKE += -j %d\n", get_num_cores());
1200 #endif
1201
1202     break;
1203
1204   case '1' : /* For config.h */
1205 #ifdef FORCE
1206     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1207
1208     p = &buffer[0];
1209     while (*p) {
1210       if ((*p == '-') && (*(p + 1) == 'D')) {
1211         p += 2;
1212         printf("#define ");
1213
1214         while ((*p != ' ') && (*p != '\0')) {
1215
1216           if (*p == '=') {
1217             printf(" ");
1218             p ++;
1219             while ((*p != ' ') && (*p != '\0')) {
1220               printf("%c", *p);
1221               p ++;
1222             }
1223           } else {
1224             if (*p != '\n')
1225             printf("%c", *p);
1226             p ++;
1227           }
1228         }
1229
1230         printf("\n");
1231       } else p ++;
1232     }
1233 #else
1234     get_cpuconfig();
1235 #endif
1236
1237 #ifdef FORCE
1238     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1239 #else
1240 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
1241     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1242 #endif
1243 #endif
1244
1245  break;
1246
1247   case '2' : /* SMP */
1248     if (get_num_cores() > 1) printf("SMP=1\n");
1249     break;
1250   }
1251
1252   fflush(stdout);
1253
1254   return 0;
1255 }
1256