getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93 #if defined(AIX)
  94 #include <sys/sysinfo.h>
  95 #endif
  96
  97 /* #define FORCE_P2             */
  98 /* #define FORCE_KATMAI         */
  99 /* #define FORCE_COPPERMINE     */
 100 /* #define FORCE_NORTHWOOD      */
 101 /* #define FORCE_PRESCOTT       */
 102 /* #define FORCE_BANIAS         */
 103 /* #define FORCE_YONAH          */
 104 /* #define FORCE_CORE2          */
 105 /* #define FORCE_PENRYN         */
 106 /* #define FORCE_DUNNINGTON     */
 107 /* #define FORCE_NEHALEM        */
 108 /* #define FORCE_SANDYBRIDGE    */
 109 /* #define FORCE_ATOM           */
 110 /* #define FORCE_ATHLON         */
 111 /* #define FORCE_OPTERON        */
 112 /* #define FORCE_OPTERON_SSE3   */
 113 /* #define FORCE_BARCELONA      */
 114 /* #define FORCE_SHANGHAI       */
 115 /* #define FORCE_ISTANBUL       */
 116 /* #define FORCE_BOBCAT         */
 117 /* #define FORCE_BULLDOZER      */
 118 /* #define FORCE_PILEDRIVER     */
 119 /* #define FORCE_SSE_GENERIC    */
 120 /* #define FORCE_VIAC3          */
 121 /* #define FORCE_NANO           */
 122 /* #define FORCE_POWER3         */
 123 /* #define FORCE_POWER4         */
 124 /* #define FORCE_POWER5         */
 125 /* #define FORCE_POWER6         */
 126 /* #define FORCE_POWER7         */
 127 /* #define FORCE_POWER8         */
 128 /* #define FORCE_PPCG4          */
 129 /* #define FORCE_PPC970         */
 130 /* #define FORCE_PPC970MP       */
 131 /* #define FORCE_PPC440         */
 132 /* #define FORCE_PPC440FP2      */
 133 /* #define FORCE_CELL           */
 134 /* #define FORCE_SICORTEX       */
 135 /* #define FORCE_LOONGSON3R3    */
 136 /* #define FORCE_LOONGSON3R4    */
 137 /* #define FORCE_LOONGSON3R5    */
 138 /* #define FORCE_I6400          */
 139 /* #define FORCE_P6600          */
 140 /* #define FORCE_P5600          */
 141 /* #define FORCE_I6500          */
 142 /* #define FORCE_ITANIUM2       */
 143 /* #define FORCE_SPARC          */
 144 /* #define FORCE_SPARCV7        */
 145 /* #define FORCE_ZARCH_GENERIC  */
 146 /* #define FORCE_Z13            */
 147 /* #define FORCE_GENERIC        */
 148
 149 #ifdef FORCE_P2
 150 #define FORCE
 151 #define FORCE_INTEL
 152 #define ARCHITECTURE    "X86"
 153 #define SUBARCHITECTURE "PENTIUM2"
 154 #define ARCHCONFIG   "-DPENTIUM2 " \
 155                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 156                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 157                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 158                      "-DHAVE_CMOV -DHAVE_MMX"
 159 #define LIBNAME   "p2"
 160 #define CORENAME  "P5"
 161 #endif
 162
 163 #ifdef FORCE_KATMAI
 164 #define FORCE
 165 #define FORCE_INTEL
 166 #define ARCHITECTURE    "X86"
 167 #define SUBARCHITECTURE "PENTIUM3"
 168 #define ARCHCONFIG   "-DPENTIUM3 " \
 169                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 170                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 171                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 172                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 173 #define LIBNAME   "katmai"
 174 #define CORENAME  "KATMAI"
 175 #endif
 176
 177 #ifdef FORCE_COPPERMINE
 178 #define FORCE
 179 #define FORCE_INTEL
 180 #define ARCHITECTURE    "X86"
 181 #define SUBARCHITECTURE "PENTIUM3"
 182 #define ARCHCONFIG   "-DPENTIUM3 " \
 183                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 184                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 185                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 186                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 187 #define LIBNAME   "coppermine"
 188 #define CORENAME  "COPPERMINE"
 189 #endif
 190
 191 #ifdef FORCE_NORTHWOOD
 192 #define FORCE
 193 #define FORCE_INTEL
 194 #define ARCHITECTURE    "X86"
 195 #define SUBARCHITECTURE "PENTIUM4"
 196 #define ARCHCONFIG   "-DPENTIUM4 " \
 197                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 198                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 199                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 200                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 201 #define LIBNAME   "northwood"
 202 #define CORENAME  "NORTHWOOD"
 203 #endif
 204
 205 #ifdef FORCE_PRESCOTT
 206 #define FORCE
 207 #define FORCE_INTEL
 208 #define ARCHITECTURE    "X86"
 209 #define SUBARCHITECTURE "PENTIUM4"
 210 #define ARCHCONFIG   "-DPENTIUM4 " \
 211                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 212                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 213                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 214                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 215 #define LIBNAME   "prescott"
 216 #define CORENAME  "PRESCOTT"
 217 #endif
 218
 219 #ifdef FORCE_BANIAS
 220 #define FORCE
 221 #define FORCE_INTEL
 222 #define ARCHITECTURE    "X86"
 223 #define SUBARCHITECTURE "BANIAS"
 224 #define ARCHCONFIG   "-DPENTIUMM " \
 225                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 226                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 227                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 228                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 229 #define LIBNAME   "banias"
 230 #define CORENAME  "BANIAS"
 231 #endif
 232
 233 #ifdef FORCE_YONAH
 234 #define FORCE
 235 #define FORCE_INTEL
 236 #define ARCHITECTURE    "X86"
 237 #define SUBARCHITECTURE "YONAH"
 238 #define ARCHCONFIG   "-DPENTIUMM " \
 239                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 240                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 241                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 242                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 243 #define LIBNAME   "yonah"
 244 #define CORENAME  "YONAH"
 245 #endif
 246
 247 #ifdef FORCE_CORE2
 248 #define FORCE
 249 #define FORCE_INTEL
 250 #define ARCHITECTURE    "X86"
 251 #define SUBARCHITECTURE "CONRORE"
 252 #define ARCHCONFIG   "-DCORE2 " \
 253                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 254                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 255                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 256                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 257 #define LIBNAME   "core2"
 258 #define CORENAME  "CORE2"
 259 #endif
 260
 261 #ifdef FORCE_PENRYN
 262 #define FORCE
 263 #define FORCE_INTEL
 264 #define ARCHITECTURE    "X86"
 265 #define SUBARCHITECTURE "PENRYN"
 266 #define ARCHCONFIG   "-DPENRYN " \
 267                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 268                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 269                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 270                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 271 #define LIBNAME   "penryn"
 272 #define CORENAME  "PENRYN"
 273 #endif
 274
 275 #ifdef FORCE_DUNNINGTON
 276 #define FORCE
 277 #define FORCE_INTEL
 278 #define ARCHITECTURE    "X86"
 279 #define SUBARCHITECTURE "DUNNINGTON"
 280 #define ARCHCONFIG   "-DDUNNINGTON " \
 281                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 282                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 283                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 284                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 285                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 286 #define LIBNAME   "dunnington"
 287 #define CORENAME  "DUNNINGTON"
 288 #endif
 289
 290 #ifdef FORCE_NEHALEM
 291 #define FORCE
 292 #define FORCE_INTEL
 293 #define ARCHITECTURE    "X86"
 294 #define SUBARCHITECTURE "NEHALEM"
 295 #define ARCHCONFIG   "-DNEHALEM " \
 296                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 297                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 298                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 299                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 300 #define LIBNAME   "nehalem"
 301 #define CORENAME  "NEHALEM"
 302 #endif
 303
 304 #ifdef FORCE_SANDYBRIDGE
 305 #define FORCE
 306 #define FORCE_INTEL
 307 #define ARCHITECTURE    "X86"
 308 #ifdef NO_AVX
 309 #define SUBARCHITECTURE "NEHALEM"
 310 #define ARCHCONFIG   "-DNEHALEM " \
 311                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 312                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 313                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 314                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 315 #define LIBNAME   "nehalem"
 316 #define CORENAME  "NEHALEM"
 317 #else
 318 #define SUBARCHITECTURE "SANDYBRIDGE"
 319 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 320                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 321                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 322                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 323                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 324 #define LIBNAME   "sandybridge"
 325 #define CORENAME  "SANDYBRIDGE"
 326 #endif
 327 #endif
 328
 329 #ifdef FORCE_HASWELL
 330 #define FORCE
 331 #define FORCE_INTEL
 332 #define ARCHITECTURE    "X86"
 333 #ifdef NO_AVX2
 334 #ifdef NO_AVX
 335 #define SUBARCHITECTURE "NEHALEM"
 336 #define ARCHCONFIG   "-DNEHALEM " \
 337                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 338                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 339                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 340                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 341 #define LIBNAME   "nehalem"
 342 #define CORENAME  "NEHALEM"
 343 #else
 344 #define SUBARCHITECTURE "SANDYBRIDGE"
 345 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 346                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 347                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 348                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 349                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 350 #define LIBNAME   "sandybridge"
 351 #define CORENAME  "SANDYBRIDGE"
 352 #endif
 353 #else
 354 #define SUBARCHITECTURE "HASWELL"
 355 #define ARCHCONFIG   "-DHASWELL " \
 356                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 357                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 358                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 359                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 360                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 361 #define LIBNAME   "haswell"
 362 #define CORENAME  "HASWELL"
 363 #endif
 364 #endif
 365
 366 #ifdef FORCE_SKYLAKEX
 367 #define FORCE
 368 #define FORCE_INTEL
 369 #define ARCHITECTURE    "X86"
 370 #ifdef NO_AVX512
 371 #ifdef NO_AVX2
 372 #ifdef NO_AVX
 373 #define SUBARCHITECTURE "NEHALEM"
 374 #define ARCHCONFIG   "-DNEHALEM " \
 375                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 376                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 377                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 378                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 379 #define LIBNAME   "nehalem"
 380 #define CORENAME  "NEHALEM"
 381 #else
 382 #define SUBARCHITECTURE "SANDYBRIDGE"
 383 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 384                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 385                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 386                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 387                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 388 #define LIBNAME   "sandybridge"
 389 #define CORENAME  "SANDYBRIDGE"
 390 #endif
 391 #else
 392 #define SUBARCHITECTURE "HASWELL"
 393 #define ARCHCONFIG   "-DHASWELL " \
 394                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 395                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 396                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 397                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 398                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 399 #define LIBNAME   "haswell"
 400 #define CORENAME  "HASWELL"
 401 #endif
 402 #else
 403 #define SUBARCHITECTURE "SKYLAKEX"
 404 #define ARCHCONFIG   "-DSKYLAKEX " \
 405                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 406                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 407                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 408                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 409                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 410 #define LIBNAME   "skylakex"
 411 #define CORENAME  "SKYLAKEX"
 412 #endif
 413 #endif
 414
 415 #ifdef FORCE_COOPERLAKE
 416 #define FORCE
 417 #define FORCE_INTEL
 418 #define ARCHITECTURE    "X86"
 419 #ifdef NO_AVX512
 420 #ifdef NO_AVX2
 421 #ifdef NO_AVX
 422 #define SUBARCHITECTURE "NEHALEM"
 423 #define ARCHCONFIG   "-DNEHALEM " \
 424                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 425                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 426                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 427                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 428 #define LIBNAME   "nehalem"
 429 #define CORENAME  "NEHALEM"
 430 #else
 431 #define SUBARCHITECTURE "SANDYBRIDGE"
 432 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 433                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 434                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 435                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 436                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 437 #define LIBNAME   "sandybridge"
 438 #define CORENAME  "SANDYBRIDGE"
 439 #endif
 440 #else
 441 #define SUBARCHITECTURE "HASWELL"
 442 #define ARCHCONFIG   "-DHASWELL " \
 443                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 444                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 445                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 446                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 447                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 448 #define LIBNAME   "haswell"
 449 #define CORENAME  "HASWELL"
 450 #endif
 451 #else
 452 #define SUBARCHITECTURE "COOPERLAKE"
 453 #define ARCHCONFIG   "-DCOOPERLAKE " \
 454                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 455                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 456                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 457                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 458                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
 459 #define LIBNAME   "cooperlake"
 460 #define CORENAME  "COOPERLAKE"
 461 #endif
 462 #endif
 463
 464 #ifdef FORCE_SAPPHIRERAPIDS
 465 #define FORCE
 466 #define FORCE_INTEL
 467 #define ARCHITECTURE    "X86"
 468 #ifdef NO_AVX512
 469 #ifdef NO_AVX2
 470 #ifdef NO_AVX
 471 #define SUBARCHITECTURE "NEHALEM"
 472 #define ARCHCONFIG   "-DNEHALEM " \
 473                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 474                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 475                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 476                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 477 #define LIBNAME   "nehalem"
 478 #define CORENAME  "NEHALEM"
 479 #else
 480 #define SUBARCHITECTURE "SANDYBRIDGE"
 481 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 482                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 483                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 484                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 485                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 486 #define LIBNAME   "sandybridge"
 487 #define CORENAME  "SANDYBRIDGE"
 488 #endif
 489 #else
 490 #define SUBARCHITECTURE "HASWELL"
 491 #define ARCHCONFIG   "-DHASWELL " \
 492                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 493                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 494                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 495                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 496                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 497 #define LIBNAME   "haswell"
 498 #define CORENAME  "HASWELL"
 499 #endif
 500 #else
 501 #define SUBARCHITECTURE "SAPPHIRERAPIDS"
 502 #define ARCHCONFIG   "-DSAPPHIRERAPIDS " \
 503                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 504                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 505                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 506                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 507                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=sapphirerapids"
 508 #define LIBNAME   "sapphirerapids"
 509 #define CORENAME  "SAPPHIRERAPIDS"
 510 #endif
 511 #endif
 512
 513 #ifdef FORCE_ATOM
 514 #define FORCE
 515 #define FORCE_INTEL
 516 #define ARCHITECTURE    "X86"
 517 #define SUBARCHITECTURE "ATOM"
 518 #define ARCHCONFIG   "-DATOM " \
 519                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 520                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 521                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 522                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 523 #define LIBNAME   "atom"
 524 #define CORENAME  "ATOM"
 525 #endif
 526
 527 #ifdef FORCE_ATHLON
 528 #define FORCE
 529 #define FORCE_INTEL
 530 #define ARCHITECTURE    "X86"
 531 #define SUBARCHITECTURE "ATHLON"
 532 #define ARCHCONFIG   "-DATHLON " \
 533                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 534                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 535                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 536                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 537 #define LIBNAME   "athlon"
 538 #define CORENAME  "ATHLON"
 539 #endif
 540
 541 #ifdef FORCE_OPTERON
 542 #define FORCE
 543 #define FORCE_INTEL
 544 #define ARCHITECTURE    "X86"
 545 #define SUBARCHITECTURE "OPTERON"
 546 #define ARCHCONFIG   "-DOPTERON " \
 547                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 548                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 549                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 550                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 551 #define LIBNAME   "opteron"
 552 #define CORENAME  "OPTERON"
 553 #endif
 554
 555 #ifdef FORCE_OPTERON_SSE3
 556 #define FORCE
 557 #define FORCE_INTEL
 558 #define ARCHITECTURE    "X86"
 559 #define SUBARCHITECTURE "OPTERON"
 560 #define ARCHCONFIG   "-DOPTERON " \
 561                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 562                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 563                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 564                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 565 #define LIBNAME   "opteron"
 566 #define CORENAME  "OPTERON"
 567 #endif
 568
 569 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 570 #define FORCE
 571 #define FORCE_INTEL
 572 #define ARCHITECTURE    "X86"
 573 #define SUBARCHITECTURE "BARCELONA"
 574 #define ARCHCONFIG   "-DBARCELONA " \
 575                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 576                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 577                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 578                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 579                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 580 #define LIBNAME   "barcelona"
 581 #define CORENAME  "BARCELONA"
 582 #endif
 583
 584 #if defined(FORCE_BOBCAT)
 585 #define FORCE
 586 #define FORCE_INTEL
 587 #define ARCHITECTURE    "X86"
 588 #define SUBARCHITECTURE "BOBCAT"
 589 #define ARCHCONFIG   "-DBOBCAT " \
 590                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 591                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 592                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 593                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 594                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 595 #define LIBNAME   "bobcat"
 596 #define CORENAME  "BOBCAT"
 597 #endif
 598
 599 #if defined (FORCE_BULLDOZER)
 600 #define FORCE
 601 #define FORCE_INTEL
 602 #define ARCHITECTURE    "X86"
 603 #define SUBARCHITECTURE "BULLDOZER"
 604 #define ARCHCONFIG   "-DBULLDOZER " \
 605                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 606                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 607                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 608                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 609                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 610                      "-DHAVE_AVX"
 611 #define LIBNAME   "bulldozer"
 612 #define CORENAME  "BULLDOZER"
 613 #endif
 614
 615 #if defined (FORCE_PILEDRIVER)
 616 #define FORCE
 617 #define FORCE_INTEL
 618 #define ARCHITECTURE    "X86"
 619 #define SUBARCHITECTURE "PILEDRIVER"
 620 #define ARCHCONFIG   "-DPILEDRIVER " \
 621                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 622                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 623                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 624                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 625                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 626                      "-DHAVE_AVX -DHAVE_FMA3"
 627 #define LIBNAME   "piledriver"
 628 #define CORENAME  "PILEDRIVER"
 629 #endif
 630
 631 #if defined (FORCE_STEAMROLLER)
 632 #define FORCE
 633 #define FORCE_INTEL
 634 #define ARCHITECTURE    "X86"
 635 #define SUBARCHITECTURE "STEAMROLLER"
 636 #define ARCHCONFIG   "-DSTEAMROLLER " \
 637                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 638                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 639                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 640                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 641                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 642                      "-DHAVE_AVX -DHAVE_FMA3"
 643 #define LIBNAME   "steamroller"
 644 #define CORENAME  "STEAMROLLER"
 645 #endif
 646
 647 #if defined (FORCE_EXCAVATOR)
 648 #define FORCE
 649 #define FORCE_INTEL
 650 #define ARCHITECTURE    "X86"
 651 #define SUBARCHITECTURE "EXCAVATOR"
 652 #define ARCHCONFIG   "-DEXCAVATOR " \
 653                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 654                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 655                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 656                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 657                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 658                      "-DHAVE_AVX -DHAVE_FMA3"
 659 #define LIBNAME   "excavator"
 660 #define CORENAME  "EXCAVATOR"
 661 #endif
 662
 663 #if defined (FORCE_ZEN)
 664 #define FORCE
 665 #define FORCE_INTEL
 666 #define ARCHITECTURE    "X86"
 667 #ifdef NO_AVX2
 668 #ifdef NO_AVX
 669 #define SUBARCHITECTURE "NEHALEM"
 670 #define ARCHCONFIG   "-DNEHALEM " \
 671                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 672                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 673                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 674                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 675 #define LIBNAME   "nehalem"
 676 #define CORENAME  "NEHALEM"
 677 #else
 678 #define SUBARCHITECTURE "SANDYBRIDGE"
 679 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 680                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 681                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 682                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 683                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 684 #define LIBNAME   "sandybridge"
 685 #define CORENAME  "SANDYBRIDGE"
 686 #endif
 687 #else
 688 #define SUBARCHITECTURE "ZEN"
 689 #define ARCHCONFIG   "-DZEN " \
 690                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 691                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 692                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 693                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 694                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 695                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 696                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 697                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 698                      "-DHAVE_AVX -DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 699 #define LIBNAME   "zen"
 700 #define CORENAME  "ZEN"
 701 #endif
 702 #endif
 703
 704
 705 #ifdef FORCE_SSE_GENERIC
 706 #define FORCE
 707 #define FORCE_INTEL
 708 #define ARCHITECTURE    "X86"
 709 #define SUBARCHITECTURE "GENERIC"
 710 #define ARCHCONFIG   "-DGENERIC " \
 711                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 712                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 713                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 714                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 715 #define LIBNAME   "generic"
 716 #define CORENAME  "GENERIC"
 717 #endif
 718
 719 #ifdef FORCE_VIAC3
 720 #define FORCE
 721 #define FORCE_INTEL
 722 #define ARCHITECTURE    "X86"
 723 #define SUBARCHITECTURE "VIAC3"
 724 #define ARCHCONFIG   "-DVIAC3 " \
 725                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 726                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 727                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 728                      "-DHAVE_MMX -DHAVE_SSE "
 729 #define LIBNAME   "viac3"
 730 #define CORENAME  "VIAC3"
 731 #endif
 732
 733 #ifdef FORCE_NANO
 734 #define FORCE
 735 #define FORCE_INTEL
 736 #define ARCHITECTURE    "X86"
 737 #define SUBARCHITECTURE "NANO"
 738 #define ARCHCONFIG   "-DNANO " \
 739                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 740                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 741                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 742                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 743 #define LIBNAME   "nano"
 744 #define CORENAME  "NANO"
 745 #endif
 746
 747 #ifdef FORCE_POWER3
 748 #define FORCE
 749 #define ARCHITECTURE    "POWER"
 750 #define SUBARCHITECTURE "POWER3"
 751 #define SUBDIRNAME      "power"
 752 #define ARCHCONFIG   "-DPOWER3 " \
 753                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 754                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 755                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 756 #define LIBNAME   "power3"
 757 #define CORENAME  "POWER3"
 758 #endif
 759
 760 #ifdef FORCE_POWER4
 761 #define FORCE
 762 #define ARCHITECTURE    "POWER"
 763 #define SUBARCHITECTURE "POWER4"
 764 #define SUBDIRNAME      "power"
 765 #define ARCHCONFIG   "-DPOWER4 " \
 766                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 767                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 768                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 769 #define LIBNAME   "power4"
 770 #define CORENAME  "POWER4"
 771 #endif
 772
 773 #ifdef FORCE_POWER5
 774 #define FORCE
 775 #define ARCHITECTURE    "POWER"
 776 #define SUBARCHITECTURE "POWER5"
 777 #define SUBDIRNAME      "power"
 778 #define ARCHCONFIG   "-DPOWER5 " \
 779                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 780                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 781                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 782 #define LIBNAME   "power5"
 783 #define CORENAME  "POWER5"
 784 #endif
 785
 786 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 787 #define FORCE
 788 #define ARCHITECTURE    "POWER"
 789 #define SUBARCHITECTURE "POWER6"
 790 #define SUBDIRNAME      "power"
 791 #define ARCHCONFIG   "-DPOWER6 " \
 792                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 793                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 794                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 795 #define LIBNAME   "power6"
 796 #define CORENAME  "POWER6"
 797 #endif
 798
 799 #if defined(FORCE_POWER8)
 800 #define FORCE
 801 #define ARCHITECTURE    "POWER"
 802 #define SUBARCHITECTURE "POWER8"
 803 #define SUBDIRNAME      "power"
 804 #define ARCHCONFIG   "-DPOWER8 " \
 805                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 806                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 807                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 808 #define LIBNAME   "power8"
 809 #define CORENAME  "POWER8"
 810 #endif
 811
 812 #if defined(FORCE_POWER9)
 813 #define FORCE
 814 #define ARCHITECTURE    "POWER"
 815 #define SUBARCHITECTURE "POWER9"
 816 #define SUBDIRNAME      "power"
 817 #define ARCHCONFIG   "-DPOWER9 " \
 818                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 819                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 820                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 821 #define LIBNAME   "power9"
 822 #define CORENAME  "POWER9"
 823 #endif
 824
 825 #if defined(FORCE_POWER10)
 826 #define FORCE
 827 #define ARCHITECTURE    "POWER"
 828 #define SUBARCHITECTURE "POWER10"
 829 #define SUBDIRNAME      "power"
 830 #define ARCHCONFIG   "-DPOWER10 " \
 831                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 832                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 833                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 834 #define LIBNAME   "power10"
 835 #define CORENAME  "POWER10"
 836 #endif
 837
 838 #ifdef FORCE_PPCG4
 839 #define FORCE
 840 #define ARCHITECTURE    "POWER"
 841 #define SUBARCHITECTURE "PPCG4"
 842 #define SUBDIRNAME      "power"
 843 #define ARCHCONFIG   "-DPPCG4 " \
 844                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 845                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 846                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 847 #define LIBNAME   "ppcg4"
 848 #define CORENAME  "PPCG4"
 849 #endif
 850
 851 #ifdef FORCE_PPC970
 852 #define FORCE
 853 #define ARCHITECTURE    "POWER"
 854 #define SUBARCHITECTURE "PPC970"
 855 #define SUBDIRNAME      "power"
 856 #define ARCHCONFIG   "-DPPC970 " \
 857                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 858                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 859                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 860 #define LIBNAME   "ppc970"
 861 #define CORENAME  "PPC970"
 862 #endif
 863
 864 #ifdef FORCE_PPC970MP
 865 #define FORCE
 866 #define ARCHITECTURE    "POWER"
 867 #define SUBARCHITECTURE "PPC970"
 868 #define SUBDIRNAME      "power"
 869 #define ARCHCONFIG   "-DPPC970 " \
 870                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 871                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 872                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 873 #define LIBNAME   "ppc970mp"
 874 #define CORENAME  "PPC970"
 875 #endif
 876
 877 #ifdef FORCE_PPC440
 878 #define FORCE
 879 #define ARCHITECTURE    "POWER"
 880 #define SUBARCHITECTURE "PPC440"
 881 #define SUBDIRNAME      "power"
 882 #define ARCHCONFIG   "-DPPC440 " \
 883                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 884                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 885                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 886 #define LIBNAME   "ppc440"
 887 #define CORENAME  "PPC440"
 888 #endif
 889
 890 #ifdef FORCE_PPC440FP2
 891 #define FORCE
 892 #define ARCHITECTURE    "POWER"
 893 #define SUBARCHITECTURE "PPC440FP2"
 894 #define SUBDIRNAME      "power"
 895 #define ARCHCONFIG   "-DPPC440FP2 " \
 896                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 897                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 898                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 899 #define LIBNAME   "ppc440FP2"
 900 #define CORENAME  "PPC440FP2"
 901 #endif
 902
 903 #ifdef FORCE_CELL
 904 #define FORCE
 905 #define ARCHITECTURE    "POWER"
 906 #define SUBARCHITECTURE "CELL"
 907 #define SUBDIRNAME      "power"
 908 #define ARCHCONFIG   "-DCELL " \
 909                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 910                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 911                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 912 #define LIBNAME   "cell"
 913 #define CORENAME  "CELL"
 914 #endif
 915
 916 #ifdef FORCE_SICORTEX
 917 #define FORCE
 918 #define ARCHITECTURE    "MIPS"
 919 #define SUBARCHITECTURE "SICORTEX"
 920 #define SUBDIRNAME      "mips"
 921 #define ARCHCONFIG   "-DSICORTEX " \
 922                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 923                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 924                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 925 #define LIBNAME   "mips"
 926 #define CORENAME  "sicortex"
 927 #endif
 928
 929
 930 #if defined FORCE_LOONGSON3R3 || defined FORCE_LOONGSON3A || defined FORCE_LOONGSON3B
 931 #define FORCE
 932 #define ARCHITECTURE    "MIPS"
 933 #define SUBARCHITECTURE "LOONGSON3R3"
 934 #define SUBDIRNAME      "mips64"
 935 #define ARCHCONFIG   "-DLOONGSON3R3 " \
 936        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 937        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 938        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 939 #define LIBNAME   "loongson3r3"
 940 #define CORENAME  "LOONGSON3R3"
 941 #else
 942 #endif
 943
 944 #ifdef FORCE_LOONGSON3R4
 945 #define FORCE
 946 #define ARCHITECTURE    "MIPS"
 947 #define SUBARCHITECTURE "LOONGSON3R4"
 948 #define SUBDIRNAME      "mips64"
 949 #define ARCHCONFIG   "-DLOONGSON3R4 " \
 950        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 951        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 952        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 953 #define LIBNAME   "loongson3r4"
 954 #define CORENAME  "LOONGSON3R4"
 955 #else
 956 #endif
 957
 958 #ifdef FORCE_LOONGSON3R5
 959 #define FORCE
 960 #define ARCHITECTURE    "LOONGARCH"
 961 #define SUBARCHITECTURE "LOONGSON3R5"
 962 #define SUBDIRNAME      "loongarch64"
 963 #define ARCHCONFIG   "-DLOONGSON3R5 " \
 964        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 965        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 966        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 967 #define LIBNAME   "loongson3r5"
 968 #define CORENAME  "LOONGSON3R5"
 969 #else
 970 #endif
 971
 972 #ifdef FORCE_I6400
 973 #define FORCE
 974 #define ARCHITECTURE    "MIPS"
 975 #define SUBARCHITECTURE "I6400"
 976 #define SUBDIRNAME      "mips64"
 977 #define ARCHCONFIG   "-DI6400 " \
 978        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 979        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 980        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 981 #define LIBNAME   "i6400"
 982 #define CORENAME  "I6400"
 983 #else
 984 #endif
 985
 986 #ifdef FORCE_P6600
 987 #define FORCE
 988 #define ARCHITECTURE    "MIPS"
 989 #define SUBARCHITECTURE "P6600"
 990 #define SUBDIRNAME      "mips64"
 991 #define ARCHCONFIG   "-DP6600 " \
 992        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 993        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 994        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 995 #define LIBNAME   "p6600"
 996 #define CORENAME  "P6600"
 997 #else
 998 #endif
 999
1000 #ifdef FORCE_P5600
1001 #define FORCE
1002 #define ARCHITECTURE    "MIPS"
1003 #define SUBARCHITECTURE "P5600"
1004 #define SUBDIRNAME      "mips"
1005 #define ARCHCONFIG   "-DP5600 " \
1006        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1007        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1008        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1009 #define LIBNAME   "p5600"
1010 #define CORENAME  "P5600"
1011 #else
1012 #endif
1013
1014 #ifdef FORCE_MIPS1004K
1015 #define FORCE
1016 #define ARCHITECTURE    "MIPS"
1017 #define SUBARCHITECTURE "MIPS1004K"
1018 #define SUBDIRNAME      "mips"
1019 #define ARCHCONFIG   "-DMIPS1004K " \
1020        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1021        "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
1022        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1023 #define LIBNAME   "mips1004K"
1024 #define CORENAME  "MIPS1004K"
1025 #else
1026 #endif
1027
1028 #ifdef FORCE_MIPS24K
1029 #define FORCE
1030 #define ARCHITECTURE    "MIPS"
1031 #define SUBARCHITECTURE "MIPS24K"
1032 #define SUBDIRNAME      "mips"
1033 #define ARCHCONFIG   "-DMIPS24K " \
1034        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1035        "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
1036        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1037 #define LIBNAME   "mips24K"
1038 #define CORENAME  "MIPS24K"
1039 #else
1040 #endif
1041
1042 #ifdef FORCE_I6500
1043 #define FORCE
1044 #define ARCHITECTURE    "MIPS"
1045 #define SUBARCHITECTURE "I6500"
1046 #define SUBDIRNAME      "mips64"
1047 #define ARCHCONFIG   "-DI6500 " \
1048        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1049        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1050        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1051 #define LIBNAME   "i6500"
1052 #define CORENAME  "I6500"
1053 #else
1054 #endif
1055
1056 #ifdef FORCE_ITANIUM2
1057 #define FORCE
1058 #define ARCHITECTURE    "IA64"
1059 #define SUBARCHITECTURE "ITANIUM2"
1060 #define SUBDIRNAME      "ia64"
1061 #define ARCHCONFIG   "-DITANIUM2 " \
1062                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
1063                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
1064 #define LIBNAME   "itanium2"
1065 #define CORENAME  "itanium2"
1066 #endif
1067
1068 #ifdef FORCE_SPARC
1069 #define FORCE
1070 #define ARCHITECTURE    "SPARC"
1071 #define SUBARCHITECTURE "SPARC"
1072 #define SUBDIRNAME      "sparc"
1073 #define ARCHCONFIG   "-DSPARC -DV9 " \
1074                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1075                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1076 #define LIBNAME   "sparc"
1077 #define CORENAME  "sparc"
1078 #endif
1079
1080 #ifdef FORCE_SPARCV7
1081 #define FORCE
1082 #define ARCHITECTURE    "SPARC"
1083 #define SUBARCHITECTURE "SPARC"
1084 #define SUBDIRNAME      "sparc"
1085 #define ARCHCONFIG   "-DSPARC -DV7 " \
1086                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1087                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1088 #define LIBNAME   "sparcv7"
1089 #define CORENAME  "sparcv7"
1090 #endif
1091
1092 #ifdef FORCE_GENERIC
1093 #define FORCE
1094 #define ARCHITECTURE    "GENERIC"
1095 #define SUBARCHITECTURE "GENERIC"
1096 #define SUBDIRNAME      "generic"
1097 #define ARCHCONFIG   "-DGENERIC " \
1098                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1099                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
1100                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1101 #define LIBNAME   "generic"
1102 #define CORENAME  "generic"
1103 #endif
1104
1105 #ifdef FORCE_ARMV7
1106 #define FORCE
1107 #define ARCHITECTURE    "ARM"
1108 #define SUBARCHITECTURE "ARMV7"
1109 #define SUBDIRNAME      "arm"
1110 #define ARCHCONFIG   "-DARMV7 " \
1111        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1112        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1113        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1114        "-DHAVE_VFPV3 -DHAVE_VFP"
1115 #define LIBNAME   "armv7"
1116 #define CORENAME  "ARMV7"
1117 #else
1118 #endif
1119
1120 #ifdef FORCE_CORTEXA9
1121 #define FORCE
1122 #define ARCHITECTURE    "ARM"
1123 #define SUBARCHITECTURE "CORTEXA9"
1124 #define SUBDIRNAME      "arm"
1125 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
1126        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1127        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1128        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1129        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1130 #define LIBNAME   "cortexa9"
1131 #define CORENAME  "CORTEXA9"
1132 #else
1133 #endif
1134
1135 #ifdef FORCE_RISCV64_GENERIC
1136 #define FORCE
1137 #define ARCHITECTURE    "RISCV64"
1138 #define SUBARCHITECTURE "RISCV64_GENERIC"
1139 #define SUBDIRNAME      "riscv64"
1140 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
1141        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1142        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1143        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1144 #define LIBNAME   "riscv64_generic"
1145 #define CORENAME  "RISCV64_GENERIC"
1146 #else
1147 #endif
1148
1149 #ifdef FORCE_CORTEXA15
1150 #define FORCE
1151 #define ARCHITECTURE    "ARM"
1152 #define SUBARCHITECTURE "CORTEXA15"
1153 #define SUBDIRNAME      "arm"
1154 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
1155        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1156        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1157        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1158        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1159 #define LIBNAME   "cortexa15"
1160 #define CORENAME  "CORTEXA15"
1161 #else
1162 #endif
1163
1164 #ifdef FORCE_ARMV6
1165 #define FORCE
1166 #define ARCHITECTURE    "ARM"
1167 #define SUBARCHITECTURE "ARMV6"
1168 #define SUBDIRNAME      "arm"
1169 #define ARCHCONFIG   "-DARMV6 " \
1170        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1171        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1172        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1173        "-DHAVE_VFP"
1174 #define LIBNAME   "armv6"
1175 #define CORENAME  "ARMV6"
1176 #else
1177 #endif
1178
1179 #ifdef FORCE_ARMV5
1180 #define FORCE
1181 #define ARCHITECTURE    "ARM"
1182 #define SUBARCHITECTURE "ARMV5"
1183 #define SUBDIRNAME      "arm"
1184 #define ARCHCONFIG   "-DARMV5 " \
1185        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1186        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1187        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1188 #define LIBNAME   "armv5"
1189 #define CORENAME  "ARMV5"
1190 #else
1191 #endif
1192
1193 #ifdef FORCE_ARMV8SVE
1194 #define FORCE
1195 #define ARCHITECTURE    "ARM64"
1196 #define SUBARCHITECTURE "ARMV8SVE"
1197 #define SUBDIRNAME      "arm64"
1198 #define ARCHCONFIG   "-DARMV8SVE " \
1199        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1200        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1201        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1202        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8"
1203 #define LIBNAME   "armv8sve"
1204 #define CORENAME  "ARMV8SVE"
1205 #endif
1206
1207
1208 #ifdef FORCE_ARMV8
1209 #define FORCE
1210 #define ARCHITECTURE    "ARM64"
1211 #define SUBARCHITECTURE "ARMV8"
1212 #define SUBDIRNAME      "arm64"
1213 #define ARCHCONFIG   "-DARMV8 " \
1214        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1215        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1216        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1217        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1218 #define LIBNAME   "armv8"
1219 #define CORENAME  "ARMV8"
1220 #endif
1221
1222 #ifdef FORCE_CORTEXA53
1223 #define FORCE
1224 #define ARCHITECTURE    "ARM64"
1225 #define SUBARCHITECTURE "CORTEXA53"
1226 #define SUBDIRNAME      "arm64"
1227 #define ARCHCONFIG   "-DCORTEXA53 " \
1228        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1229        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1230        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1231        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1232        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1233 #define LIBNAME   "cortexa53"
1234 #define CORENAME  "CORTEXA53"
1235 #endif
1236
1237 #ifdef FORCE_CORTEXA57
1238 #define FORCE
1239 #define ARCHITECTURE    "ARM64"
1240 #define SUBARCHITECTURE "CORTEXA57"
1241 #define SUBDIRNAME      "arm64"
1242 #define ARCHCONFIG   "-DCORTEXA57 " \
1243        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1244        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1245        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1246        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1247        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1248 #define LIBNAME   "cortexa57"
1249 #define CORENAME  "CORTEXA57"
1250 #endif
1251
1252 #ifdef FORCE_CORTEXA72
1253 #define FORCE
1254 #define ARCHITECTURE    "ARM64"
1255 #define SUBARCHITECTURE "CORTEXA72"
1256 #define SUBDIRNAME      "arm64"
1257 #define ARCHCONFIG   "-DCORTEXA72 " \
1258        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1259        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1260        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1261        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1262        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1263 #define LIBNAME   "cortexa72"
1264 #define CORENAME  "CORTEXA72"
1265 #endif
1266
1267 #ifdef FORCE_CORTEXA73
1268 #define FORCE
1269 #define ARCHITECTURE    "ARM64"
1270 #define SUBARCHITECTURE "CORTEXA73"
1271 #define SUBDIRNAME      "arm64"
1272 #define ARCHCONFIG   "-DCORTEXA73 " \
1273        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1274        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1275        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1276        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1277        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1278 #define LIBNAME   "cortexa73"
1279 #define CORENAME  "CORTEXA73"
1280 #endif
1281
1282 #ifdef FORCE_CORTEXX1
1283 #define FORCE
1284 #define ARCHITECTURE    "ARM64"
1285 #define SUBARCHITECTURE "CORTEXX1"
1286 #define SUBDIRNAME      "arm64"
1287 #define ARCHCONFIG   "-DCORTEXX1 " \
1288        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1289        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1290        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1291        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1292 #define LIBNAME   "cortexx1"
1293 #define CORENAME  "CORTEXX1"
1294 #endif
1295
1296 #ifdef FORCE_CORTEXX2
1297 #define FORCE
1298 #define ARCHITECTURE    "ARM64"
1299 #define SUBARCHITECTURE "CORTEXX2"
1300 #define SUBDIRNAME      "arm64"
1301 #define ARCHCONFIG   "-DCORTEXX2 " \
1302        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1303        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1304        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1305        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1306 #define LIBNAME   "cortexx2"
1307 #define CORENAME  "CORTEXX2"
1308 #endif
1309
1310 #ifdef FORCE_CORTEXA510
1311 #define FORCE
1312 #define ARCHITECTURE    "ARM64"
1313 #define SUBARCHITECTURE "CORTEXA510"
1314 #define SUBDIRNAME      "arm64"
1315 #define ARCHCONFIG   "-DCORTEXA510 " \
1316        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1317        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1318        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1319        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1320 #define LIBNAME   "cortexa510"
1321 #define CORENAME  "CORTEXA510"
1322 #endif
1323
1324 #ifdef FORCE_CORTEXA710
1325 #define FORCE
1326 #define ARCHITECTURE    "ARM64"
1327 #define SUBARCHITECTURE "CORTEXA710"
1328 #define SUBDIRNAME      "arm64"
1329 #define ARCHCONFIG   "-DCORTEXA710 " \
1330        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1331        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1332        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1333        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
1334 #define LIBNAME   "cortexa710"
1335 #define CORENAME  "CORTEXA710"
1336 #endif
1337
1338 #ifdef FORCE_NEOVERSEN1
1339 #define FORCE
1340 #define ARCHITECTURE    "ARM64"
1341 #define SUBARCHITECTURE "NEOVERSEN1"
1342 #define SUBDIRNAME      "arm64"
1343 #define ARCHCONFIG   "-DNEOVERSEN1 " \
1344        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1345        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1346        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1347        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1348        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1349        "-march=armv8.2-a -mtune=neoverse-n1"
1350 #define LIBNAME   "neoversen1"
1351 #define CORENAME  "NEOVERSEN1"
1352 #endif
1353
1354 #ifdef FORCE_NEOVERSEV1
1355 #define FORCE
1356 #define ARCHITECTURE    "ARM64"
1357 #define SUBARCHITECTURE "NEOVERSEV1"
1358 #define SUBDIRNAME      "arm64"
1359 #define ARCHCONFIG   "-DNEOVERSEV1 " \
1360        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1361        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1362        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1363        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1364        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 " \
1365        "-march=armv8.4-a -mtune=neoverse-v1"
1366 #define LIBNAME   "neoversev1"
1367 #define CORENAME  "NEOVERSEV1"
1368 #endif
1369
1370
1371 #ifdef FORCE_NEOVERSEN2
1372 #define FORCE
1373 #define ARCHITECTURE    "ARM64"
1374 #define SUBARCHITECTURE "NEOVERSEN2"
1375 #define SUBDIRNAME      "arm64"
1376 #define ARCHCONFIG   "-DNEOVERSEN2 " \
1377        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1378        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1379        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1380        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1381        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 " \
1382        "-march=armv8.5-a -mtune=neoverse-n2"
1383 #define LIBNAME   "neoversen2"
1384 #define CORENAME  "NEOVERSEN2"
1385 #endif
1386
1387 #ifdef FORCE_CORTEXA55
1388 #define FORCE
1389 #define ARCHITECTURE    "ARM64"
1390 #define SUBARCHITECTURE "CORTEXA55"
1391 #define SUBDIRNAME      "arm64"
1392 #define ARCHCONFIG   "-DCORTEXA55 " \
1393        "-DL1_CODE_SIZE=16384 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1394        "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1395        "-DL2_SIZE=65536 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1396        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1397        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1398 #define LIBNAME   "cortexa55"
1399 #define CORENAME  "CORTEXA55"
1400 #endif
1401
1402 #ifdef FORCE_FALKOR
1403 #define FORCE
1404 #define ARCHITECTURE    "ARM64"
1405 #define SUBARCHITECTURE "FALKOR"
1406 #define SUBDIRNAME      "arm64"
1407 #define ARCHCONFIG   "-DFALKOR " \
1408        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1409        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1410        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1411        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1412        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1413 #define LIBNAME   "falkor"
1414 #define CORENAME  "FALKOR"
1415 #endif
1416
1417 #ifdef FORCE_THUNDERX
1418 #define FORCE
1419 #define ARCHITECTURE    "ARM64"
1420 #define SUBARCHITECTURE "THUNDERX"
1421 #define SUBDIRNAME      "arm64"
1422 #define ARCHCONFIG   "-DTHUNDERX " \
1423        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1424        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1425        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1426        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1427 #define LIBNAME   "thunderx"
1428 #define CORENAME  "THUNDERX"
1429 #endif
1430
1431 #ifdef FORCE_THUNDERX2T99
1432 #define ARMV8
1433 #define FORCE
1434 #define ARCHITECTURE    "ARM64"
1435 #define SUBARCHITECTURE "THUNDERX2T99"
1436 #define SUBDIRNAME      "arm64"
1437 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1438        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1439        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1440        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1441        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1442        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1443        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1444 #define LIBNAME   "thunderx2t99"
1445 #define CORENAME  "THUNDERX2T99"
1446 #endif
1447
1448 #ifdef FORCE_TSV110
1449 #define FORCE
1450 #define ARCHITECTURE    "ARM64"
1451 #define SUBARCHITECTURE "TSV110"
1452 #define SUBDIRNAME      "arm64"
1453 #define ARCHCONFIG   "-DTSV110 " \
1454        "-DL1_CODE_SIZE=65536  -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1455        "-DL1_DATA_SIZE=65536  -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1456        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1457        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1458        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1459 #define LIBNAME   "tsv110"
1460 #define CORENAME  "TSV110"
1461 #endif
1462
1463 #ifdef FORCE_EMAG8180
1464 #define ARMV8
1465 #define FORCE
1466 #define ARCHITECTURE    "ARM64"
1467 #define SUBARCHITECTURE "EMAG8180"
1468 #define SUBDIRNAME      "arm64"
1469 #define ARCHCONFIG   "-DEMAG8180 " \
1470        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1471        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1472        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1473        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1474        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1475        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1476 #define LIBNAME   "emag8180"
1477 #define CORENAME  "EMAG8180"
1478 #endif
1479
1480 #ifdef FORCE_THUNDERX3T110
1481 #define ARMV8
1482 #define FORCE
1483 #define ARCHITECTURE    "ARM64"
1484 #define SUBARCHITECTURE "THUNDERX3T110"
1485 #define SUBDIRNAME      "arm64"
1486 #define ARCHCONFIG   "-DTHUNDERX3T110 " \
1487        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1488        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1489        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1490        "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1491        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1492        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1493 #define LIBNAME   "thunderx3t110"
1494 #define CORENAME  "THUNDERX3T110"
1495 #endif
1496
1497 #ifdef FORCE_VORTEX
1498 #define FORCE
1499 #define ARCHITECTURE    "ARM64"
1500 #define SUBARCHITECTURE "VORTEX"
1501 #define SUBDIRNAME      "arm64"
1502 #define ARCHCONFIG   "-DVORTEX " \
1503        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1504        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1505        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1506        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1507 #define LIBNAME   "vortex"
1508 #define CORENAME  "VORTEX"
1509 #endif
1510
1511 #ifdef FORCE_A64FX
1512 #define ARMV8
1513 #define FORCE
1514 #define ARCHITECTURE    "ARM64"
1515 #define SUBARCHITECTURE "A64FX"
1516 #define SUBDIRNAME      "arm64"
1517 #define ARCHCONFIG   "-DA64FX " \
1518        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=256 -DL1_CODE_ASSOCIATIVE=8 " \
1519        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=256 -DL1_DATA_ASSOCIATIVE=8 " \
1520        "-DL2_SIZE=8388608 -DL2_LINESIZE=256 -DL2_ASSOCIATIVE=8 " \
1521        "-DL3_SIZE=0 -DL3_LINESIZE=0 -DL3_ASSOCIATIVE=0 " \
1522        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1523        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8"
1524 #define LIBNAME   "a64fx"
1525 #define CORENAME  "A64FX"
1526 #endif
1527
1528 #ifdef FORCE_FT2000
1529 #define ARMV8
1530 #define FORCE
1531 #define ARCHITECTURE    "ARM64"
1532 #define SUBARCHITECTURE "FT2000"
1533 #define SUBDIRNAME      "arm64"
1534 #define ARCHCONFIG   "-DFT2000 " \
1535        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1536        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1537        "-DL2_SIZE=33554426-DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1538        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1539        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1540 #define LIBNAME   "ft2000"
1541 #define CORENAME  "FT2000"
1542 #endif
1543
1544 #ifdef FORCE_ZARCH_GENERIC
1545 #define FORCE
1546 #define ARCHITECTURE    "ZARCH"
1547 #define SUBARCHITECTURE "ZARCH_GENERIC"
1548 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1549        "-DDTB_DEFAULT_ENTRIES=64"
1550 #define LIBNAME   "zarch_generic"
1551 #define CORENAME  "ZARCH_GENERIC"
1552 #endif
1553
1554 #ifdef FORCE_Z13
1555 #define FORCE
1556 #define ARCHITECTURE    "ZARCH"
1557 #define SUBARCHITECTURE "Z13"
1558 #define ARCHCONFIG   "-DZ13 " \
1559        "-DDTB_DEFAULT_ENTRIES=64"
1560 #define LIBNAME   "z13"
1561 #define CORENAME  "Z13"
1562 #endif
1563
1564 #ifdef FORCE_Z14
1565 #define FORCE
1566 #define ARCHITECTURE    "ZARCH"
1567 #define SUBARCHITECTURE "Z14"
1568 #define ARCHCONFIG   "-DZ14 " \
1569        "-DDTB_DEFAULT_ENTRIES=64"
1570 #define LIBNAME   "z14"
1571 #define CORENAME  "Z14"
1572 #endif
1573
1574 #ifdef FORCE_C910V
1575 #define FORCE
1576 #define ARCHITECTURE    "RISCV64"
1577 #define SUBARCHITECTURE "C910V"
1578 #define SUBDIRNAME      "riscv64"
1579 #define ARCHCONFIG   "-DC910V " \
1580        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1581        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1582        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1583 #define LIBNAME   "c910v"
1584 #define CORENAME  "C910V"
1585 #else
1586 #endif
1587
1588
1589 #if defined(FORCE_E2K) || defined(__e2k__)
1590 #define FORCE
1591 #define ARCHITECTURE "E2K"
1592 #define ARCHCONFIG   "-DGENERIC " \
1593                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
1594                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
1595                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1596 #define LIBNAME   "generic"
1597 #define CORENAME  "generic"
1598 #endif
1599
1600 #ifndef FORCE
1601
1602 #ifdef USER_TARGET
1603 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1604 #endif
1605
1606 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1607     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1608 #ifndef POWER
1609 #define POWER
1610 #endif
1611 #define OPENBLAS_SUPPORTED
1612 #endif
1613
1614 #if defined(__zarch__) || defined(__s390x__)
1615 #define ZARCH
1616 #include "cpuid_zarch.c"
1617 #define OPENBLAS_SUPPORTED
1618 #endif
1619
1620 #ifdef INTEL_AMD
1621 #include "cpuid_x86.c"
1622 #define OPENBLAS_SUPPORTED
1623 #endif
1624
1625 #ifdef __ia64__
1626 #include "cpuid_ia64.c"
1627 #define OPENBLAS_SUPPORTED
1628 #endif
1629
1630 #ifdef __alpha
1631 #include "cpuid_alpha.c"
1632 #define OPENBLAS_SUPPORTED
1633 #endif
1634
1635 #ifdef POWER
1636 #include "cpuid_power.c"
1637 #define OPENBLAS_SUPPORTED
1638 #endif
1639
1640 #ifdef sparc
1641 #include "cpuid_sparc.c"
1642 #define OPENBLAS_SUPPORTED
1643 #endif
1644
1645 #ifdef __mips__
1646 #ifdef __mips64
1647 #include "cpuid_mips64.c"
1648 #else
1649 #include "cpuid_mips.c"
1650 #endif
1651 #define OPENBLAS_SUPPORTED
1652 #endif
1653
1654 #ifdef __loongarch64
1655 #include "cpuid_loongarch64.c"
1656 #define OPENBLAS_SUPPORTED
1657 #endif
1658
1659 #ifdef __riscv
1660 #include "cpuid_riscv64.c"
1661 #define OPENBLAS_SUPPORTED
1662 #endif
1663
1664 #ifdef __arm__
1665 #include "cpuid_arm.c"
1666 #define OPENBLAS_SUPPORTED
1667 #endif
1668
1669 #ifdef __aarch64__
1670 #include "cpuid_arm64.c"
1671 #define OPENBLAS_SUPPORTED
1672 #endif
1673
1674
1675 #ifndef OPENBLAS_SUPPORTED
1676 #error "This arch/CPU is not supported by OpenBLAS."
1677 #endif
1678
1679 #else
1680
1681 #endif
1682
1683 static int get_num_cores(void) {
1684
1685 #ifdef OS_WINDOWS
1686   SYSTEM_INFO sysinfo;
1687 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1688   int m[2], count;
1689   size_t len;
1690 #endif
1691
1692 #if defined(linux) || defined(__sun__)
1693   //returns the number of processors which are currently online
1694   return sysconf(_SC_NPROCESSORS_CONF);
1695
1696 #elif defined(OS_WINDOWS)
1697
1698   GetSystemInfo(&sysinfo);
1699   return sysinfo.dwNumberOfProcessors;
1700
1701 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1702   m[0] = CTL_HW;
1703   m[1] = HW_NCPU;
1704   len = sizeof(int);
1705   sysctl(m, 2, &count, &len, NULL, 0);
1706
1707   return count;
1708
1709 #elif defined(AIX)
1710   //returns the number of processors which are currently online
1711   return sysconf(_SC_NPROCESSORS_ONLN);
1712
1713 #else
1714   return 2;
1715 #endif
1716 }
1717
1718 int main(int argc, char *argv[]){
1719
1720 #ifdef FORCE
1721   char buffer[8192], *p, *q;
1722   int length;
1723 #endif
1724
1725   if (argc == 1) return 0;
1726
1727   switch (argv[1][0]) {
1728
1729   case '0' : /* for Makefile */
1730
1731 #ifdef FORCE
1732     printf("CORE=%s\n", CORENAME);
1733 #else
1734 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
1735     printf("CORE=%s\n", get_corename());
1736 #endif
1737 #endif
1738
1739 #ifdef FORCE
1740     printf("LIBCORE=%s\n", LIBNAME);
1741 #else
1742     printf("LIBCORE=");
1743     get_libname();
1744     printf("\n");
1745 #endif
1746
1747     printf("NUM_CORES=%d\n", get_num_cores());
1748
1749 #if defined(__arm__)
1750 #if !defined(FORCE)
1751     fprintf(stderr,"get features!\n");
1752         get_features();
1753 #else
1754     fprintf(stderr,"split archconfig!\n");
1755     sprintf(buffer, "%s", ARCHCONFIG);
1756
1757     p = &buffer[0];
1758
1759     while (*p) {
1760       if ((*p == '-') && (*(p + 1) == 'D')) {
1761         p += 2;
1762         if (*p != 'H') {
1763                 while( (*p != ' ') && (*p != '-') && (*p != '\0') && (*p != '\n')) {p++; }
1764                 if (*p == '-') continue;
1765         }
1766         while ((*p != ' ') && (*p != '\0')) {
1767
1768           if (*p == '=') {
1769             printf("=");
1770             p ++;
1771             while ((*p != ' ') && (*p != '\0')) {
1772               printf("%c", *p);
1773               p ++;
1774             }
1775           } else {
1776             printf("%c", *p);
1777             p ++;
1778             if ((*p == ' ') || (*p =='\0')) printf("=1\n");
1779           }
1780         }
1781       } else p ++;
1782     }
1783 #endif
1784 #endif
1785
1786
1787 #ifdef INTEL_AMD
1788 #ifndef FORCE
1789     get_sse();
1790 #else
1791
1792     sprintf(buffer, "%s", ARCHCONFIG);
1793
1794     p = &buffer[0];
1795
1796     while (*p) {
1797       if ((*p == '-') && (*(p + 1) == 'D')) {
1798         p += 2;
1799
1800         while ((*p != ' ') && (*p != '\0')) {
1801
1802           if (*p == '=') {
1803             printf("=");
1804             p ++;
1805             while ((*p != ' ') && (*p != '\0')) {
1806               printf("%c", *p);
1807               p ++;
1808             }
1809           } else {
1810             printf("%c", *p);
1811             p ++;
1812             if ((*p == ' ') || (*p =='\0')) printf("=1");
1813           }
1814         }
1815
1816         printf("\n");
1817       } else p ++;
1818     }
1819 #endif
1820 #endif
1821
1822 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1823 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1824 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1825 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1826 #endif
1827 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1828 printf("ELF_VERSION=2\n");
1829 #endif
1830
1831 #ifdef MAKE_NB_JOBS
1832   #if MAKE_NB_JOBS > 0
1833     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1834   #else
1835     // Let make use parent -j argument or -j1 if there
1836     // is no make parent
1837   #endif
1838 #elif NO_PARALLEL_MAKE==1
1839     printf("MAKE += -j 1\n");
1840 #else
1841     printf("MAKE += -j %d\n", get_num_cores());
1842 #endif
1843
1844     break;
1845
1846   case '1' : /* For config.h */
1847 #ifdef FORCE
1848     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1849
1850     p = &buffer[0];
1851     while (*p) {
1852       if ((*p == '-') && (*(p + 1) == 'D')) {
1853         p += 2;
1854         printf("#define ");
1855
1856         while ((*p != ' ') && (*p != '\0')) {
1857
1858           if (*p == '=') {
1859             printf(" ");
1860             p ++;
1861             while ((*p != ' ') && (*p != '\0')) {
1862               printf("%c", *p);
1863               p ++;
1864             }
1865           } else {
1866             if (*p != '\n')
1867             printf("%c", *p);
1868             p ++;
1869           }
1870         }
1871
1872         printf("\n");
1873       } else p ++;
1874     }
1875 #else
1876     get_cpuconfig();
1877 #endif
1878
1879 #ifdef FORCE
1880     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1881 #else
1882 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
1883     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1884 #endif
1885 #endif
1886
1887  break;
1888
1889   case '2' : /* SMP */
1890     if (get_num_cores() > 1) printf("SMP=1\n");
1891     break;
1892   }
1893
1894   fflush(stdout);
1895
1896   return 0;
1897 }
1898