1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
23 whenever the "tdep" structure changes in an incompatible way. */
25 #define XTENSA_TDEP_VERSION 0x60
27 /* Xtensa register type. */
31 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
32 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
33 xtRegisterTypeUserReg, /* User defined registers (rur). */
34 xtRegisterTypeTieRegfile, /* User define register files. */
35 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
36 xtRegisterTypeMapped, /* Mapped on Special Registers. */
37 xtRegisterTypeUnmapped, /* Special case of masked registers. */
38 xtRegisterTypeWindow, /* Live window registers (a0..a15). */
39 xtRegisterTypeVirtual, /* PC, FP. */
41 } xtensa_register_type_t;
44 /* Xtensa register group. */
46 #define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */
50 xtRegisterGroupUnknown = 0,
51 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */
52 xtRegisterGroupAddrReg = 0x0002, /* ARx. */
53 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */
54 xtRegisterGroupUserReg = 0x0008, /* URxx. */
55 xtRegisterGroupState = 0x0010, /* States. */
57 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */
58 xtRegisterGroupUser = 0x0200, /* User registers. */
59 xtRegisterGroupFloat = 0x0400, /* Floating Point. */
60 xtRegisterGroupVectra = 0x0800, /* Vectra. */
61 xtRegisterGroupSystem = 0x1000, /* System. */
63 xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */
64 xtRegisterGroupCP0 = 0x01000000, /* CP0. */
65 xtRegisterGroupCP1 = 0x02000000, /* CP1. */
66 xtRegisterGroupCP2 = 0x04000000, /* CP2. */
67 xtRegisterGroupCP3 = 0x08000000, /* CP3. */
68 xtRegisterGroupCP4 = 0x10000000, /* CP4. */
69 xtRegisterGroupCP5 = 0x20000000, /* CP5. */
70 xtRegisterGroupCP6 = 0x40000000, /* CP6. */
71 xtRegisterGroupCP7 = 0x80000000, /* CP7. */
73 } xtensa_register_group_t;
76 /* Xtensa target flags. */
80 xtTargetFlagsNonVisibleRegs = 0x0001,
81 xtTargetFlagsUseFetchStore = 0x0002,
82 } xtensa_target_flags_t;
85 /* Xtensa ELF core file register set representation ('.reg' section).
86 Copied from target-side ELF header <xtensa/elf.h>. */
88 typedef unsigned long xtensa_elf_greg_t;
94 xtensa_elf_greg_t lbeg;
95 xtensa_elf_greg_t lend;
96 xtensa_elf_greg_t lcount;
97 xtensa_elf_greg_t sar;
98 xtensa_elf_greg_t windowstart;
99 xtensa_elf_greg_t windowbase;
100 xtensa_elf_greg_t reserved[8+48];
101 xtensa_elf_greg_t ar[64];
102 } xtensa_elf_gregset_t;
104 #define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
105 / sizeof (xtensa_elf_greg_t))
119 xtensa_reg_mask_t *mask;
123 /* Xtensa register representation. */
127 char* name; /* Register name. */
128 int offset; /* Offset. */
129 xtensa_register_type_t type; /* Register type. */
130 xtensa_register_group_t group;/* Register group. */
131 struct type* ctype; /* C-type. */
132 int bit_size; /* The actual bit size in the target. */
133 int byte_size; /* Actual space allocated in registers[]. */
134 int align; /* Alignment for this register. */
136 unsigned int target_number; /* Register target number. */
138 int flags; /* Flags. */
139 int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */
141 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */
142 const char *fetch; /* Instruction sequence to fetch register. */
143 const char *store; /* Instruction sequence to store register. */
146 /* For xtensa-config.c to expand to the structure above. */
147 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
148 {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \
149 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
150 #define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
152 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
153 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002
154 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
155 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
157 /* Call-ABI for stack frame. */
161 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */
162 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */
166 /* Xtensa-specific target dependencies. */
170 unsigned int target_flags;
172 /* Spill location for TIE register files under ocd. */
174 unsigned int spill_location;
175 unsigned int spill_size;
177 char *unused; /* Placeholder for compatibility. */
178 call_abi_t call_abi; /* Calling convention. */
180 /* CPU configuration. */
182 unsigned int debug_interrupt_level;
184 unsigned int icache_line_bytes;
185 unsigned int dcache_line_bytes;
186 unsigned int dcache_writeback;
188 unsigned int isa_use_windowed_registers;
189 unsigned int isa_use_density_instructions;
190 unsigned int isa_use_exceptions;
191 unsigned int isa_use_ext_l32r;
192 unsigned int isa_max_insn_size; /* Maximum instruction length. */
193 unsigned int debug_num_ibreaks; /* Number of IBREAKs. */
194 unsigned int debug_num_dbreaks;
198 xtensa_register_t* regmap;
200 unsigned int num_regs; /* Number of registers in register map. */
201 unsigned int num_nopriv_regs; /* Number of non-privileged registers. */
202 unsigned int num_pseudo_regs; /* Number of pseudo registers. */
203 unsigned int num_aregs; /* Size of register file. */
204 unsigned int num_contexts;
206 int ar_base; /* Register number for AR0. */
207 int a0_base; /* Register number for A0 (pseudo). */
208 int wb_regnum; /* Register number for WB. */
209 int ws_regnum; /* Register number for WS. */
210 int pc_regnum; /* Register number for PC. */
211 int ps_regnum; /* Register number for PS. */
212 int lbeg_regnum; /* Register numbers for count regs. */
215 int sar_regnum; /* Register number of SAR. */
216 int litbase_regnum; /* Register number of LITBASE. */
218 int interrupt_regnum; /* Register number for interrupt. */
219 int interrupt2_regnum; /* Register number for interrupt2. */
220 int cpenable_regnum; /* Register number for cpenable. */
221 int debugcause_regnum; /* Register number for debugcause. */
222 int exccause_regnum; /* Register number for exccause. */
223 int excvaddr_regnum; /* Register number for excvaddr. */
225 int max_register_raw_size;
226 int max_register_virtual_size;
227 unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */
228 unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */
229 unsigned long *gregmap;
231 /* Cached register types. */
234 struct ctype_cache *next;
236 struct type *virtual_type;
240 /* Macro to instantiate a gdbarch_tdep structure. */
242 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
245 .spill_location = -1, \
246 .spill_size = (spillsz), \
249 .debug_interrupt_level = XCHAL_DEBUGLEVEL, \
250 .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
251 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
252 .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \
253 .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
254 .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \
255 .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \
256 .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \
257 .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
258 .debug_num_ibreaks = XCHAL_NUM_IBREAK, \
259 .debug_num_dbreaks = XCHAL_NUM_DBREAK, \
262 .num_nopriv_regs = 0, \
263 .num_pseudo_regs = 0, \
264 .num_aregs = XCHAL_NUM_AREGS, \
265 .num_contexts = XCHAL_NUM_CONTEXTS, \
274 .lcount_regnum = -1, \
276 .litbase_regnum = -1, \
277 .interrupt_regnum = -1, \
278 .interrupt2_regnum = -1, \
279 .cpenable_regnum = -1, \
280 .debugcause_regnum = -1, \
281 .exccause_regnum = -1, \
282 .excvaddr_regnum = -1, \
283 .max_register_raw_size = 0, \
284 .max_register_virtual_size = 0, \
286 .fp_layout_bytes = 0, \
289 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \
290 struct gdbarch_tdep xtensa_tdep = \
291 XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
293 #ifndef XCHAL_NUM_CONTEXTS
294 #define XCHAL_NUM_CONTEXTS 0
296 #ifndef XCHAL_HAVE_EXCEPTIONS
297 #define XCHAL_HAVE_EXCEPTIONS 1
301 /* We assign fixed numbers to the registers of the "current" window
302 (i.e., relative to WB). The registers get remapped via the reg_map
303 data structure to their corresponding register in the AR register
304 file (see xtensa-tdep.c). */