1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-tdep.h"
57 static int xtensa_debug_level = 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* We use a6 through a11 for passing arguments to a function called by GDB. */
83 #define ARGS_FIRST_REG A6_REGNUM
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or ps register. */
90 #define PS_CALLINC_SHIFT 16
91 #define PS_CALLINC_MASK 0x00030000
92 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
93 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
96 /* Convert a live Ax register number to the corresponding Areg number. */
98 #define AREG_NUMBER(r, wb) \
99 ((((r) - A0_REGNUM + (((wb) & WB_MASK)<<WB_SHIFT)) & AREGS_MASK) + AR_BASE)
102 /* Define prototypes. */
104 extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *);
105 extern int xtensa_config_byte_order (struct gdbarch_info *);
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(op1) \
112 ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) ? ((op1) == 0x6c) : ((op1) == 0x36))
114 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
122 windowing_enabled (CORE_ADDR ps)
124 return ((ps & (1 << 4)) == 0 && (ps & (1 << 18)) != 0);
127 /* Return the window size of the previous call to the function from which we
130 This function is used to extract the return value after a called function
131 has returned to the callee. On Xtensa, the register that holds the return
132 value (from the perspective of the caller) depends on what call
133 instruction was used. For now, we are assuming that the call instruction
134 precedes the current address, so we simply analyze the call instruction.
135 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
136 method to call the inferior function. */
139 extract_call_winsize (CORE_ADDR pc)
141 int winsize = 4; /* Default: No call, e.g. dummy frame. */
145 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
147 /* Read the previous instruction (should be a call[x]{4|8|12}. */
148 read_memory (pc-3, buf, 3);
149 insn = extract_unsigned_integer (buf, 3);
151 /* Decode call instruction:
153 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
154 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
156 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
157 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
160 (Return the default value (4) if we can't find a valid call insn. */
162 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
164 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
165 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12 */
169 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
170 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12 */
176 /* REGISTER INFORMATION */
178 /* Returns the name of a register. */
181 xtensa_register_name (int regnum)
183 /* Return the name stored in the register map. */
184 if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
185 return REGMAP[regnum].name;
187 /* Invalid register number. */
188 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
193 /* Return the type of a register. Create a new type, if necessary. */
195 static struct ctype_cache
197 struct ctype_cache *next;
199 struct type *virtual_type;
200 } *type_entries = NULL;
203 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
205 /* Return signed integer for ARx and Ax registers. */
206 if ((regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
207 || (regnum >= A0_BASE && regnum < A0_BASE + 16))
208 return builtin_type_int;
210 if (regnum == PC_REGNUM || regnum == A1_REGNUM)
211 return lookup_pointer_type (builtin_type_void);
213 /* Return the stored type for all other registers. */
214 else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
216 xtensa_register_t* reg = ®MAP[regnum];
218 /* Set ctype for this register (only the first time we ask for it). */
222 struct ctype_cache *tp;
223 int size = reg->byte_size;
225 /* We always use the memory representation, even if the register
230 reg->ctype = builtin_type_uint8;
234 reg->ctype = builtin_type_uint16;
238 reg->ctype = builtin_type_uint32;
242 reg->ctype = builtin_type_uint64;
246 reg->ctype = builtin_type_uint128;
250 for (tp = type_entries; tp != NULL; tp = tp->next)
251 if (tp->size == size)
256 char *name = xmalloc (16);
257 tp = xmalloc (sizeof (struct ctype_cache));
258 tp->next = type_entries;
262 sprintf (name, "int%d", size * 8);
263 tp->virtual_type = init_type (TYPE_CODE_INT, size,
264 TYPE_FLAG_UNSIGNED, name,
268 reg->ctype = tp->virtual_type;
274 /* Invalid register number. */
275 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
280 /* Returns the 'local' register number for stubs, dwarf2, etc.
281 The debugging information enumerates registers starting from 0 for A0
282 to n for An. So, we only have to add the base number for A0. */
285 xtensa_reg_to_regnum (int regnum)
289 if (regnum >= 0 && regnum < 16)
290 return A0_BASE + regnum;
292 for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++)
293 if (regnum == REGMAP[i].target_number)
296 /* Invalid register number. */
297 internal_error (__FILE__, __LINE__,
298 _("invalid dwarf/stabs register number %d"), regnum);
303 /* Handle the special case of masked registers. */
305 /* Write the bits of a masked register to the various registers that
306 are combined into this register. Only the masked areas of these
307 registers are modified; the other fields are untouched.
308 (Note: The size of masked registers is always less or equal 32 bits.) */
311 xtensa_register_write_masked (xtensa_register_t *reg, unsigned char *buffer)
313 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
315 const xtensa_mask_t *mask = reg->mask;
317 int shift = 0; /* Shift for next mask (mod 32). */
318 int start, size; /* Start bit and size of current mask. */
320 unsigned int *ptr = value;
321 unsigned int regval, m, mem = 0;
323 int bytesize = reg->byte_size;
324 int bitsize = bytesize * 8;
327 DEBUGTRACE ("xtensa_register_write_masked ()\n");
329 /* Copy the masked register to host byte-order. */
330 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
331 for (i = 0; i < bytesize; i++)
334 mem |= (buffer[bytesize - i - 1] << 24);
339 for (i = 0; i < bytesize; i++)
342 mem |= (buffer[i] << 24);
347 /* We might have to shift the final value:
348 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
349 bytesize & 3 == x -> shift (4-x) * 8. */
351 *ptr = mem >> (((0 - bytesize) & 3) * 8);
355 /* Write the bits to the masked areas of the other registers. */
356 for (i = 0; i < mask->count; i++)
358 start = mask->mask[i].bit_start;
359 size = mask->mask[i].bit_size;
360 regval = mem >> shift;
362 if ((shift += size) > bitsize)
363 error (_("size of all masks is larger than the register"));
372 regval |= mem << (size - shift);
375 /* Make sure we have a valid register. */
376 r = mask->mask[i].reg_num;
377 if (r >= 0 && size > 0)
379 /* Don't overwrite the unmasked areas. */
380 m = 0xffffffff >> (32 - size) << start;
382 regval = (regval & m) | (read_register (r) & ~m);
383 write_register (r, regval);
389 /* Read the masked areas of the registers and assemble it into a single
393 xtensa_register_read_masked (xtensa_register_t *reg, unsigned char *buffer)
395 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
397 const xtensa_mask_t *mask = reg->mask;
402 unsigned int *ptr = value;
403 unsigned int regval, mem = 0;
405 int bytesize = reg->byte_size;
406 int bitsize = bytesize * 8;
409 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
410 reg->name == 0 ? "" : reg->name);
412 /* Assemble the register from the masked areas of other registers. */
413 for (i = 0; i < mask->count; i++)
415 int r = mask->mask[i].reg_num;
416 regval = (r >= 0) ? read_register (r) : 0;
417 start = mask->mask[i].bit_start;
418 size = mask->mask[i].bit_size;
423 regval &= (0xffffffff >> (32 - size));
425 mem |= regval << shift;
427 if ((shift += size) > bitsize)
428 error (_("size of all masks is larger than the register"));
439 mem = regval >> (size - shift);
446 /* Copy value to target byte order. */
450 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
451 for (i = 0; i < bytesize; i++)
455 buffer[bytesize - i - 1] = mem & 0xff;
459 for (i = 0; i < bytesize; i++)
463 buffer[i] = mem & 0xff;
469 /* Read pseudo registers. */
472 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
473 struct regcache *regcache,
477 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
478 regnum, xtensa_register_name (regnum));
480 /* Check if it is FP (renumber it in this case -> A0...A15). */
481 if (regnum == FP_ALIAS)
482 error (_("trying to read FP"));
484 /* Read aliases a0..a15. */
485 if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
487 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
489 regcache_raw_read (regcache, WB_REGNUM, buf);
490 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
493 /* We can always read 'regular' registers. */
494 if (regnum >= 0 && regnum < NUM_REGS)
495 regcache_raw_read (regcache, regnum, buffer);
497 /* Pseudo registers. */
498 else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
500 xtensa_register_t *reg = ®MAP[regnum];
501 xtensa_register_type_t type = reg->type;
502 int flags = XTENSA_TARGET_FLAGS;
504 /* Can we read Unknown or Unmapped registers? */
505 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
507 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
509 warning (_("cannot read register %s"),
510 xtensa_register_name (regnum));
515 /* Some targets cannot read TIE register files. */
516 else if (type == xtRegisterTypeTieRegfile)
518 /* Use 'fetch' to get register? */
519 if (flags & xtTargetFlagsUseFetchStore)
521 warning (_("cannot read register"));
525 /* On some targets (esp. simulators), we can always read the reg. */
526 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
528 warning (_("cannot read register"));
533 /* We can always read mapped registers. */
534 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
536 xtensa_register_read_masked (reg, (unsigned char *) buffer);
540 /* Assume that we can read the register. */
541 regcache_raw_read (regcache, regnum, buffer);
545 internal_error (__FILE__, __LINE__,
546 _("invalid register number %d"), regnum);
550 /* Write pseudo registers. */
553 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
554 struct regcache *regcache,
556 const gdb_byte *buffer)
558 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
559 regnum, xtensa_register_name (regnum));
561 /* Check if this is FP. */
562 if (regnum == FP_ALIAS)
563 error (_("trying to write FP"));
565 /* Renumber register, if aliase a0..a15. */
566 if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
568 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
571 regcache_raw_read (regcache, WB_REGNUM, buf);
572 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
575 /* We can always write 'core' registers.
576 Note: We might have converted Ax->ARy. */
577 if (regnum >= 0 && regnum < NUM_REGS)
578 regcache_raw_write (regcache, regnum, buffer);
580 /* Pseudo registers. */
581 else if (regnum >= 0 && regnum < NUM_REGS + NUM_PSEUDO_REGS)
583 xtensa_register_t *reg = ®MAP[regnum];
584 xtensa_register_type_t type = reg->type;
585 int flags = XTENSA_TARGET_FLAGS;
587 /* On most targets, we can't write registers of type "Unknown"
589 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
591 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
593 warning (_("cannot write register %s"),
594 xtensa_register_name (regnum));
599 /* Some targets cannot read TIE register files. */
600 else if (type == xtRegisterTypeTieRegfile)
602 /* Use 'store' to get register? */
603 if (flags & xtTargetFlagsUseFetchStore)
605 warning (_("cannot write register"));
609 /* On some targets (esp. simulators), we can always write
612 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
614 warning (_("cannot write register"));
619 /* We can always write mapped registers. */
620 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
622 xtensa_register_write_masked (reg, (unsigned char *) buffer);
626 /* Assume that we can write the register. */
627 regcache_raw_write (regcache, regnum, buffer);
631 internal_error (__FILE__, __LINE__,
632 _("invalid register number %d"), regnum);
636 static struct reggroup *xtensa_ar_reggroup;
637 static struct reggroup *xtensa_user_reggroup;
638 static struct reggroup *xtensa_vectra_reggroup;
641 xtensa_init_reggroups (void)
643 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
644 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
645 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
650 xtensa_add_reggroups (struct gdbarch *gdbarch)
652 reggroup_add (gdbarch, all_reggroup);
653 reggroup_add (gdbarch, save_reggroup);
654 reggroup_add (gdbarch, restore_reggroup);
655 reggroup_add (gdbarch, system_reggroup);
656 reggroup_add (gdbarch, vector_reggroup); /* vectra */
657 reggroup_add (gdbarch, general_reggroup); /* core */
658 reggroup_add (gdbarch, float_reggroup); /* float */
660 reggroup_add (gdbarch, xtensa_ar_reggroup); /* ar */
661 reggroup_add (gdbarch, xtensa_user_reggroup); /* user */
662 reggroup_add (gdbarch, xtensa_vectra_reggroup); /* vectra */
666 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
667 | XTENSA_REGISTER_FLAGS_WRITABLE \
668 | XTENSA_REGISTER_FLAGS_VOLATILE)
670 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
671 | XTENSA_REGISTER_FLAGS_WRITABLE)
674 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
676 struct reggroup *group)
678 xtensa_register_t* reg = ®MAP[regnum];
679 xtensa_register_type_t type = reg->type;
680 xtensa_register_group_t rg = reg->group;
682 /* First, skip registers that are not visible to this target
683 (unknown and unmapped registers when not using ISS). */
685 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
687 if (group == all_reggroup)
689 if (group == xtensa_ar_reggroup)
690 return rg & xtRegisterGroupAddrReg;
691 if (group == xtensa_user_reggroup)
692 return rg & xtRegisterGroupUser;
693 if (group == float_reggroup)
694 return rg & xtRegisterGroupFloat;
695 if (group == general_reggroup)
696 return rg & xtRegisterGroupGeneral;
697 if (group == float_reggroup)
698 return rg & xtRegisterGroupFloat;
699 if (group == system_reggroup)
700 return rg & xtRegisterGroupState;
701 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
702 return rg & xtRegisterGroupVectra;
703 if (group == save_reggroup || group == restore_reggroup)
704 return (regnum < NUM_REGS
705 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
711 /* CORE FILE SUPPORT */
713 /* Supply register REGNUM from the buffer specified by GREGS and LEN
714 in the general-purpose register set REGSET to register cache
715 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
718 xtensa_supply_gregset (const struct regset *regset,
724 const xtensa_elf_gregset_t *regs = gregs;
727 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
729 if (regnum == PC_REGNUM || regnum == -1)
730 regcache_raw_supply (rc, PC_REGNUM, (char *) ®s->pc);
731 if (regnum == PS_REGNUM || regnum == -1)
732 regcache_raw_supply (rc, PS_REGNUM, (char *) ®s->ps);
733 if (regnum == WB_REGNUM || regnum == -1)
734 regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase);
735 if (regnum == WS_REGNUM || regnum == -1)
736 regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart);
737 if (regnum == LBEG_REGNUM || regnum == -1)
738 regcache_raw_supply (rc, LBEG_REGNUM, (char *) ®s->lbeg);
739 if (regnum == LEND_REGNUM || regnum == -1)
740 regcache_raw_supply (rc, LEND_REGNUM, (char *) ®s->lend);
741 if (regnum == LCOUNT_REGNUM || regnum == -1)
742 regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount);
743 if (regnum == SAR_REGNUM || regnum == -1)
744 regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar);
745 if (regnum == EXCCAUSE_REGNUM || regnum == -1)
746 regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause);
747 if (regnum == EXCVADDR_REGNUM || regnum == -1)
748 regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr);
749 if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
750 regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]);
751 else if (regnum == -1)
753 for (i = 0; i < NUM_AREGS; ++i)
754 regcache_raw_supply (rc, AR_BASE + i, (char *) ®s->ar[i]);
759 /* Xtensa register set. */
765 xtensa_supply_gregset
769 /* Return the appropriate register set for the core section identified
770 by SECT_NAME and SECT_SIZE. */
772 static const struct regset *
773 xtensa_regset_from_core_section (struct gdbarch *core_arch,
774 const char *sect_name,
777 DEBUGTRACE ("xtensa_regset_from_core_section "
778 "(..., sect_name==\"%s\", sect_size==%x) \n",
779 sect_name, sect_size);
781 if (strcmp (sect_name, ".reg") == 0
782 && sect_size >= sizeof(xtensa_elf_gregset_t))
783 return &xtensa_gregset;
791 /* We currently don't support the call0-abi, so we have at max. 12 registers
792 saved on the stack. */
794 #define XTENSA_NUM_SAVED_AREGS 12
796 typedef struct xtensa_frame_cache
800 CORE_ADDR ra; /* The raw return address; use to compute call_inc. */
802 int wb; /* Base for this frame; -1 if not in regfile. */
803 int callsize; /* Call size to next frame. */
805 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
807 } xtensa_frame_cache_t;
810 static struct xtensa_frame_cache *
811 xtensa_alloc_frame_cache (void)
813 xtensa_frame_cache_t *cache;
816 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
818 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
825 cache->callsize = -1;
828 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
829 cache->aregs[i] = -1;
836 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
838 return address & ~15;
843 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
847 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
849 frame_unwind_register (next_frame, PC_REGNUM, buf);
851 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
852 extract_typed_address (buf, builtin_type_void_func_ptr));
854 return extract_typed_address (buf, builtin_type_void_func_ptr);
858 static struct frame_id
859 xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
864 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
866 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
868 pc = frame_pc_unwind (next_frame);
869 frame_unwind_register (next_frame, A1_REGNUM, buf);
870 fp = extract_unsigned_integer (buf, 4);
872 /* Make dummy frame ID unique by adding a constant. */
873 return frame_id_build (fp+SP_ALIGNMENT, pc);
877 static struct xtensa_frame_cache *
878 xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
880 xtensa_frame_cache_t *cache;
882 CORE_ADDR ra, wb, ws, pc, sp, ps;
885 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
886 next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
888 /* Already cached? */
892 /* Get pristine xtensa-frame. */
893 cache = xtensa_alloc_frame_cache ();
896 /* Get windowbase, windowstart, ps, and pc. */
897 wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM);
898 ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM);
899 ps = frame_unwind_register_unsigned (next_frame, PS_REGNUM);
900 pc = frame_unwind_register_unsigned (next_frame, PC_REGNUM);
902 op1 = read_memory_integer (pc, 1);
903 if (XTENSA_IS_ENTRY (op1) || !windowing_enabled (read_register (PS_REGNUM)))
905 int callinc = CALLINC (frame_unwind_register_unsigned (next_frame,
907 ra = frame_unwind_register_unsigned (next_frame,
908 A0_REGNUM + callinc * 4);
910 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
913 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
917 cache->prev_sp = read_register (A1_REGNUM);
921 ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM);
922 cache->callsize = WINSIZE (ra);
923 cache->wb = (wb - (cache->callsize / 4)) & ((NUM_AREGS / 4) - 1);
924 cache->ws = ws & ~(1 << wb);
927 cache->pc = ((frame_func_unwind (next_frame) & 0xc0000000)
928 | (ra & 0x3fffffff));
929 cache->ps = (ps & ~PS_CALLINC_MASK) | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
932 /* Note: We could also calculate the location on stack when we actually
933 access the register. However, this approach, saving the location
934 in the cache frame, is probably easier to support the call0 ABI. */
941 sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16;
943 for (i = 0; i < 4; i++, sp += 4)
945 cache->aregs[i] = sp;
948 if (cache->callsize > 4)
950 /* Set A4...A7/A11. */
952 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
953 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
954 sp -= cache->callsize * 4;
956 for ( /* i=4 */ ; i < cache->callsize; i++, sp += 4)
958 cache->aregs[i] = sp;
963 if (cache->prev_sp == 0)
967 /* Register window overflow already happened.
968 We can read caller's frame SP from the proper spill loction. */
970 read_memory_integer (cache->aregs[1],
971 register_size (current_gdbarch,
976 /* Read caller's frame SP directly from the previous window. */
978 int regnum = AREG_NUMBER (A1_REGNUM, cache->wb);
980 cache->prev_sp = read_register (regnum);
984 cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM);
986 DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, "
987 "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n",
988 (unsigned int) cache->base, (unsigned int) cache->wb,
989 cache->ws, cache->callsize, (unsigned int) cache->pc,
990 (unsigned int) cache->ps, (unsigned int) cache->prev_sp);
997 xtensa_frame_this_id (struct frame_info *next_frame,
999 struct frame_id *this_id)
1001 struct xtensa_frame_cache *cache =
1002 xtensa_frame_cache (next_frame, this_cache);
1004 DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n",
1005 (unsigned int) next_frame, (unsigned int) *this_cache);
1007 if (cache->prev_sp == 0)
1010 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1015 xtensa_frame_prev_register (struct frame_info *next_frame,
1019 enum lval_type *lvalp,
1024 struct xtensa_frame_cache *cache =
1025 xtensa_frame_cache (next_frame, this_cache);
1026 CORE_ADDR saved_reg = 0;
1029 DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, "
1030 "*this 0x%08x, regnum %d (%s), ...)\n",
1031 (unsigned int) next_frame,
1032 *this_cache? (unsigned int) *this_cache : 0, regnum,
1033 xtensa_register_name (regnum));
1035 if (regnum == WS_REGNUM)
1038 saved_reg = cache->ws;
1040 saved_reg = 1 << cache->wb;
1042 else if (regnum == WB_REGNUM)
1043 saved_reg = cache->wb;
1044 else if (regnum == PC_REGNUM)
1045 saved_reg = cache->pc;
1046 else if (regnum == PS_REGNUM)
1047 saved_reg = cache->ps;
1058 store_unsigned_integer (valuep, 4, saved_reg);
1063 /* Convert Ax register numbers to ARx register numbers. */
1064 if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
1065 regnum = AREG_NUMBER (regnum, cache->wb);
1067 /* Check if ARx register has been saved to stack. */
1068 if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS))
1070 int areg = regnum - AR_BASE - (cache->wb * 4);
1073 && areg < XTENSA_NUM_SAVED_AREGS
1074 && cache->aregs[areg] != -1)
1077 *lvalp = lval_memory;
1078 *addrp = cache->aregs[areg];
1082 read_memory (*addrp, valuep,
1083 register_size (current_gdbarch, regnum));
1085 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1090 /* Note: All other registers have been either saved to the dummy stack
1091 or are still alive in the processor. */
1094 *lvalp = lval_register;
1098 frame_unwind_register (next_frame, (*realnump), valuep);
1102 static const struct frame_unwind
1103 xtensa_frame_unwind =
1106 xtensa_frame_this_id,
1107 xtensa_frame_prev_register
1110 static const struct frame_unwind *
1111 xtensa_frame_sniffer (struct frame_info *next_frame)
1113 return &xtensa_frame_unwind;
1117 xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache)
1119 struct xtensa_frame_cache *cache =
1120 xtensa_frame_cache (next_frame, this_cache);
1125 static const struct frame_base
1128 &xtensa_frame_unwind,
1129 xtensa_frame_base_address,
1130 xtensa_frame_base_address,
1131 xtensa_frame_base_address
1136 xtensa_extract_return_value (struct type *type,
1137 struct regcache *regcache,
1140 bfd_byte *valbuf = dst;
1141 int len = TYPE_LENGTH (type);
1146 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1148 gdb_assert(len > 0);
1150 /* First, we have to find the caller window in the register file. */
1151 regcache_raw_read_unsigned (regcache, PC_REGNUM, &pc);
1152 callsize = extract_call_winsize (pc);
1154 /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */
1155 if (len > (callsize > 8 ? 8 : 16))
1156 internal_error (__FILE__, __LINE__,
1157 _("cannot extract return value of %d bytes long"), len);
1159 /* Get the register offset of the return register (A2) in the caller
1161 regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
1162 areg = AREG_NUMBER(A2_REGNUM + callsize, wb);
1164 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1166 if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1169 for (; len > 0; len -= 4, areg++, valbuf += 4)
1172 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1174 regcache_raw_read (regcache, areg, valbuf);
1180 xtensa_store_return_value (struct type *type,
1181 struct regcache *regcache,
1184 const bfd_byte *valbuf = dst;
1188 int len = TYPE_LENGTH (type);
1191 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1193 regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
1194 regcache_raw_read_unsigned (regcache, PC_REGNUM, &pc);
1195 callsize = extract_call_winsize (pc);
1197 if (len > (callsize > 8 ? 8 : 16))
1198 internal_error (__FILE__, __LINE__,
1199 _("unimplemented for this length: %d"),
1200 TYPE_LENGTH (type));
1202 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1203 callsize, (int) wb);
1205 if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1208 areg = AREG_NUMBER (A2_REGNUM + callsize, wb);
1210 for (; len > 0; len -= 4, areg++, valbuf += 4)
1213 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1215 regcache_raw_write (regcache, areg, valbuf);
1220 enum return_value_convention
1221 xtensa_return_value (struct gdbarch *gdbarch,
1222 struct type *valtype,
1223 struct regcache *regcache,
1225 const gdb_byte *writebuf)
1227 /* Note: Structures up to 16 bytes are returned in registers. */
1229 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1230 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1231 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1232 && TYPE_LENGTH (valtype) > 16);
1235 return RETURN_VALUE_STRUCT_CONVENTION;
1237 DEBUGTRACE ("xtensa_return_value(...)\n");
1239 if (writebuf != NULL)
1241 xtensa_store_return_value (valtype, regcache, writebuf);
1244 if (readbuf != NULL)
1246 gdb_assert (!struct_return);
1247 xtensa_extract_return_value (valtype, regcache, readbuf);
1249 return RETURN_VALUE_REGISTER_CONVENTION;
1256 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1257 struct value *function,
1258 struct regcache *regcache,
1261 struct value **args,
1264 CORE_ADDR struct_addr)
1267 int size, onstack_size;
1268 gdb_byte *buf = (gdb_byte *) alloca (16);
1270 struct argument_info
1272 const bfd_byte *contents;
1274 int onstack; /* onstack == 0 => in reg */
1275 int align; /* alignment */
1278 int offset; /* stack offset if on stack */
1279 int regno; /* regno if in register */
1283 struct argument_info *arg_info =
1284 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1288 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1290 if (xtensa_debug_level > 3)
1293 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1294 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1295 "struct_addr=0x%x\n",
1296 (int) sp, (int) struct_return, (int) struct_addr);
1298 for (i = 0; i < nargs; i++)
1300 struct value *arg = args[i];
1301 struct type *arg_type = check_typedef (value_type (arg));
1302 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%08x %3d ",
1303 i, (int) arg, TYPE_LENGTH (arg_type));
1304 switch (TYPE_CODE (arg_type))
1307 fprintf_unfiltered (gdb_stdlog, "int");
1309 case TYPE_CODE_STRUCT:
1310 fprintf_unfiltered (gdb_stdlog, "struct");
1313 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1316 fprintf_unfiltered (gdb_stdlog, " 0x%08x\n",
1317 (unsigned int) value_contents (arg));
1321 /* First loop: collect information.
1322 Cast into type_long. (This shouldn't happen often for C because
1323 GDB already does this earlier.) It's possible that GDB could
1324 do it all the time but it's harmless to leave this code here. */
1331 size = REGISTER_SIZE;
1333 for (i = 0; i < nargs; i++)
1335 struct argument_info *info = &arg_info[i];
1336 struct value *arg = args[i];
1337 struct type *arg_type = check_typedef (value_type (arg));
1339 switch (TYPE_CODE (arg_type))
1342 case TYPE_CODE_BOOL:
1343 case TYPE_CODE_CHAR:
1344 case TYPE_CODE_RANGE:
1345 case TYPE_CODE_ENUM:
1347 /* Cast argument to long if necessary as the mask does it too. */
1348 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1350 arg_type = builtin_type_long;
1351 arg = value_cast (arg_type, arg);
1353 info->align = TYPE_LENGTH (builtin_type_long);
1358 /* Align doubles correctly. */
1359 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1360 info->align = TYPE_LENGTH (builtin_type_double);
1362 info->align = TYPE_LENGTH (builtin_type_long);
1365 case TYPE_CODE_STRUCT:
1367 info->align = TYPE_LENGTH (builtin_type_long);
1370 info->length = TYPE_LENGTH (arg_type);
1371 info->contents = value_contents (arg);
1373 /* Align size and onstack_size. */
1374 size = (size + info->align - 1) & ~(info->align - 1);
1375 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1377 if (size + info->length > REGISTER_SIZE * ARGS_NUM_REGS)
1380 info->u.offset = onstack_size;
1381 onstack_size += info->length;
1386 info->u.regno = ARGS_FIRST_REG + size / REGISTER_SIZE;
1388 size += info->length;
1391 /* Adjust the stack pointer and align it. */
1392 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1394 /* Simulate MOVSP. */
1397 read_memory (osp - 16, buf, 16);
1398 write_memory (sp - 16, buf, 16);
1401 /* Second Loop: Load arguments. */
1405 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1406 regcache_cooked_write (regcache, ARGS_FIRST_REG, buf);
1409 for (i = 0; i < nargs; i++)
1411 struct argument_info *info = &arg_info[i];
1415 int n = info->length;
1416 CORE_ADDR offset = sp + info->u.offset;
1418 /* Odd-sized structs are aligned to the lower side of a memory
1419 word in big-endian mode and require a shift. This only
1420 applies for structures smaller than one word. */
1422 if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1423 offset += (REGISTER_SIZE - n);
1425 write_memory (offset, info->contents, info->length);
1430 int n = info->length;
1431 const bfd_byte *cp = info->contents;
1432 int r = info->u.regno;
1434 /* Odd-sized structs are aligned to the lower side of registers in
1435 big-endian mode and require a shift. The odd-sized leftover will
1436 be at the end. Note that this is only true for structures smaller
1437 than REGISTER_SIZE; for larger odd-sized structures the excess
1438 will be left-aligned in the register on both endiannesses. */
1440 if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1442 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1443 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1445 store_unsigned_integer (buf, REGISTER_SIZE, v);
1446 regcache_cooked_write (regcache, r, buf);
1448 cp += REGISTER_SIZE;
1455 /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/
1456 regcache_cooked_write (regcache, r, cp);
1458 /* write_register (r, v); */
1459 cp += REGISTER_SIZE;
1467 /* Set the return address of dummy frame to the dummy address.
1468 Note: The return address for the current function (in A0) is
1469 saved in the dummy frame, so we can savely overwrite A0 here. */
1471 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1472 regcache_raw_read (regcache, PS_REGNUM, buf);
1473 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1474 regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra);
1475 regcache_cooked_write_unsigned (regcache, PS_REGNUM, ps | 0x00010000);
1477 /* Set new stack pointer and return it. */
1478 regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp);
1479 /* Make dummy frame ID unique by adding a constant. */
1480 return sp + SP_ALIGNMENT;
1484 /* Return a breakpoint for the current location of PC. We always use
1485 the density version if we have density instructions (regardless of the
1486 current instruction at PC), and use regular instructions otherwise. */
1488 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1489 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1490 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1491 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1493 const unsigned char *
1494 xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1496 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1497 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1498 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1499 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1501 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1503 if (ISA_USE_DENSITY_INSTRUCTIONS)
1505 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1507 *lenptr = sizeof (density_big_breakpoint);
1508 return density_big_breakpoint;
1512 *lenptr = sizeof (density_little_breakpoint);
1513 return density_little_breakpoint;
1518 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1520 *lenptr = sizeof (big_breakpoint);
1521 return big_breakpoint;
1525 *lenptr = sizeof (little_breakpoint);
1526 return little_breakpoint;
1532 /* Return the pc of the first real instruction. We assume that this
1533 machine uses register windows.
1535 If we have debug info ( line-number info, in particular ) we simply skip
1536 the code associated with the first function line effectively skipping
1537 the prologue code. It works even in cases like
1540 { int local_var = 1;
1544 because, for this source code, both Xtensa compilers will generate two
1545 separate entries ( with the same line number ) in dwarf line-number
1546 section to make sure there is a boundary between the prologue code and
1547 the rest of the function.
1549 If there is no debug info, we need to analyze the code. */
1552 xtensa_skip_prologue (CORE_ADDR start_pc)
1554 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
1556 if (ISA_USE_WINDOWED_REGISTERS)
1559 struct symtab_and_line prologue_sal;
1561 op1 = read_memory_integer (start_pc, 1);
1562 if (!XTENSA_IS_ENTRY (op1))
1565 prologue_sal = find_pc_line (start_pc, 0);
1566 if (prologue_sal.line != 0)
1567 return prologue_sal.end;
1569 return start_pc + XTENSA_ENTRY_LENGTH;
1573 internal_error (__FILE__, __LINE__,
1574 _("non-windowed configurations are not supported"));
1580 /* CONFIGURATION CHECK */
1582 /* Verify the current configuration. */
1585 xtensa_verify_config (struct gdbarch *gdbarch)
1587 struct ui_file *log;
1588 struct cleanup *cleanups;
1589 struct gdbarch_tdep *tdep;
1593 tdep = gdbarch_tdep (gdbarch);
1594 log = mem_fileopen ();
1595 cleanups = make_cleanup_ui_file_delete (log);
1597 /* Verify that we got a reasonable number of AREGS. */
1598 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
1599 fprintf_unfiltered (log, "\n\tnum_aregs: Number of AR registers (%d) "
1600 "is not a power of two!", tdep->num_aregs);
1602 /* Verify that certain registers exist. */
1603 if (tdep->pc_regnum == -1)
1604 fprintf_unfiltered (log, "\n\tpc_regnum: No PC register");
1605 if (tdep->ps_regnum == -1)
1606 fprintf_unfiltered (log, "\n\tps_regnum: No PS register");
1607 if (tdep->wb_regnum == -1)
1608 fprintf_unfiltered (log, "\n\twb_regnum: No WB register");
1609 if (tdep->ws_regnum == -1)
1610 fprintf_unfiltered (log, "\n\tws_regnum: No WS register");
1611 if (tdep->ar_base == -1)
1612 fprintf_unfiltered (log, "\n\tar_base: No AR registers");
1613 if (tdep->a0_base == -1)
1614 fprintf_unfiltered (log, "\n\ta0_base: No Ax registers");
1616 buf = ui_file_xstrdup (log, &dummy);
1617 make_cleanup (xfree, buf);
1618 if (strlen (buf) > 0)
1619 internal_error (__FILE__, __LINE__,
1620 _("the following are invalid: %s"), buf);
1621 do_cleanups (cleanups);
1625 /* Module "constructor" function. */
1627 static struct gdbarch *
1628 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1630 struct gdbarch_tdep *tdep;
1631 struct gdbarch *gdbarch;
1632 struct xtensa_abi_handler *abi_handler;
1634 DEBUGTRACE ("gdbarch_init()\n");
1636 /* We have to set the byte order before we call gdbarch_alloc. */
1637 info.byte_order = xtensa_config_byte_order (&info);
1639 tdep = xtensa_config_tdep (&info);
1640 gdbarch = gdbarch_alloc (&info, tdep);
1642 /* Verify our configuration. */
1643 xtensa_verify_config (gdbarch);
1645 /* Pseudo-Register read/write */
1646 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
1647 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
1649 /* Set target information. */
1650 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
1651 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
1652 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
1653 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
1654 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
1656 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
1657 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
1658 set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
1659 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
1661 /* We provide our own function to get register information. */
1662 set_gdbarch_register_name (gdbarch, xtensa_register_name);
1663 set_gdbarch_register_type (gdbarch, xtensa_register_type);
1665 /* To call functions from GDB using dummy frame */
1666 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
1668 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
1670 set_gdbarch_return_value (gdbarch, xtensa_return_value);
1672 /* Advance PC across any prologue instructions to reach "real" code. */
1673 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
1675 /* Stack grows downward. */
1676 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1678 /* Set breakpoints. */
1679 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
1681 /* After breakpoint instruction or illegal instruction, pc still
1682 points at break instruction, so don't decrement. */
1683 set_gdbarch_decr_pc_after_break (gdbarch, 0);
1685 /* We don't skip args. */
1686 set_gdbarch_frame_args_skip (gdbarch, 0);
1688 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
1690 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
1692 set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id);
1694 /* Frame handling. */
1695 frame_base_set_default (gdbarch, &xtensa_frame_base);
1696 frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer);
1698 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
1700 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
1702 xtensa_add_reggroups (gdbarch);
1703 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
1705 set_gdbarch_regset_from_core_section (gdbarch,
1706 xtensa_regset_from_core_section);
1712 /* Dump xtensa tdep structure. */
1715 xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
1717 error (_("xtensa_dump_tdep(): not implemented"));
1722 _initialize_xtensa_tdep (void)
1724 struct cmd_list_element *c;
1726 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
1727 xtensa_init_reggroups ();
1729 add_setshow_zinteger_cmd ("xtensa",
1731 &xtensa_debug_level, _("\
1732 Set Xtensa debugging."), _("\
1733 Show Xtensa debugging."), _("\
1734 When non-zero, Xtensa-specific debugging is enabled. \
1735 Can be 1, 2, 3, or 4 indicating the level of debugging."),
1738 &setdebuglist, &showdebuglist);