1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* ABI-independent macros. */
95 #define ARG_NOF(gdbarch) \
96 (gdbarch_tdep (gdbarch)->call_abi \
97 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
98 #define ARG_1ST(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
100 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
101 : (gdbarch_tdep (gdbarch)->a0_base + 6))
103 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
104 indicates that the instruction is an ENTRY instruction. */
106 #define XTENSA_IS_ENTRY(gdbarch, op1) \
107 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
108 ? ((op1) == 0x6c) : ((op1) == 0x36))
110 #define XTENSA_ENTRY_LENGTH 3
112 /* windowing_enabled() returns true, if windowing is enabled.
113 WOE must be set to 1; EXCM to 0.
114 Note: We assume that EXCM is always 0 for XEA1. */
116 #define PS_WOE (1<<18)
117 #define PS_EXC (1<<4)
119 /* Convert a live A-register number to the corresponding AR-register number. */
121 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
123 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
126 arreg = a_regnum - tdep->a0_base;
127 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
128 arreg &= tdep->num_aregs - 1;
130 return arreg + tdep->ar_base;
133 /* Convert a live AR-register number to the corresponding A-register order
134 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
136 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
141 areg = ar_regnum - tdep->ar_base;
142 if (areg < 0 || areg >= tdep->num_aregs)
144 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
145 return (areg > 15) ? -1 : areg;
149 windowing_enabled (CORE_ADDR ps)
151 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
154 /* Return the window size of the previous call to the function from which we
157 This function is used to extract the return value after a called function
158 has returned to the caller. On Xtensa, the register that holds the return
159 value (from the perspective of the caller) depends on what call
160 instruction was used. For now, we are assuming that the call instruction
161 precedes the current address, so we simply analyze the call instruction.
162 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
163 method to call the inferior function. */
166 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
172 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
174 /* Read the previous instruction (should be a call[x]{4|8|12}. */
175 read_memory (pc-3, buf, 3);
176 insn = extract_unsigned_integer (buf, 3);
178 /* Decode call instruction:
180 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
181 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
183 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
184 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
186 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
188 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
189 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
193 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
194 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
200 /* REGISTER INFORMATION */
202 /* Returns the name of a register. */
204 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
206 /* Return the name stored in the register map. */
207 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
208 + gdbarch_num_pseudo_regs (gdbarch))
209 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
211 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
215 /* Return the type of a register. Create a new type, if necessary. */
217 static struct ctype_cache
219 struct ctype_cache *next;
221 struct type *virtual_type;
222 } *type_entries = NULL;
225 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
227 /* Return signed integer for ARx and Ax registers. */
228 if ((regnum >= gdbarch_tdep (gdbarch)->ar_base
229 && regnum < gdbarch_tdep (gdbarch)->ar_base
230 + gdbarch_tdep (gdbarch)->num_aregs)
231 || (regnum >= gdbarch_tdep (gdbarch)->a0_base
232 && regnum < gdbarch_tdep (gdbarch)->a0_base + 16))
233 return builtin_type (gdbarch)->builtin_int;
235 if (regnum == gdbarch_pc_regnum (gdbarch)
236 || regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
237 return builtin_type (gdbarch)->builtin_data_ptr;
239 /* Return the stored type for all other registers. */
240 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
241 + gdbarch_num_pseudo_regs (gdbarch))
243 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
245 /* Set ctype for this register (only the first time). */
249 struct ctype_cache *tp;
250 int size = reg->byte_size;
252 /* We always use the memory representation,
253 even if the register width is smaller. */
257 reg->ctype = builtin_type_uint8;
261 reg->ctype = builtin_type_uint16;
265 reg->ctype = builtin_type_uint32;
269 reg->ctype = builtin_type_uint64;
273 reg->ctype = builtin_type_uint128;
277 for (tp = type_entries; tp != NULL; tp = tp->next)
278 if (tp->size == size)
283 char *name = xmalloc (16);
284 tp = xmalloc (sizeof (struct ctype_cache));
285 tp->next = type_entries;
289 sprintf (name, "int%d", size * 8);
290 tp->virtual_type = init_type (TYPE_CODE_INT, size,
291 TYPE_FLAG_UNSIGNED, name,
295 reg->ctype = tp->virtual_type;
301 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
306 /* Return the 'local' register number for stubs, dwarf2, etc.
307 The debugging information enumerates registers starting from 0 for A0
308 to n for An. So, we only have to add the base number for A0. */
311 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
315 if (regnum >= 0 && regnum < 16)
316 return gdbarch_tdep (gdbarch)->a0_base + regnum;
319 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
321 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
324 internal_error (__FILE__, __LINE__,
325 _("invalid dwarf/stabs register number %d"), regnum);
330 /* Write the bits of a masked register to the various registers.
331 Only the masked areas of these registers are modified; the other
332 fields are untouched. The size of masked registers is always less
333 than or equal to 32 bits. */
336 xtensa_register_write_masked (struct regcache *regcache,
337 xtensa_register_t *reg, const gdb_byte *buffer)
339 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
340 const xtensa_mask_t *mask = reg->mask;
342 int shift = 0; /* Shift for next mask (mod 32). */
343 int start, size; /* Start bit and size of current mask. */
345 unsigned int *ptr = value;
346 unsigned int regval, m, mem = 0;
348 int bytesize = reg->byte_size;
349 int bitsize = bytesize * 8;
352 DEBUGTRACE ("xtensa_register_write_masked ()\n");
354 /* Copy the masked register to host byte-order. */
355 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
356 for (i = 0; i < bytesize; i++)
359 mem |= (buffer[bytesize - i - 1] << 24);
364 for (i = 0; i < bytesize; i++)
367 mem |= (buffer[i] << 24);
372 /* We might have to shift the final value:
373 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
374 bytesize & 3 == x -> shift (4-x) * 8. */
376 *ptr = mem >> (((0 - bytesize) & 3) * 8);
380 /* Write the bits to the masked areas of the other registers. */
381 for (i = 0; i < mask->count; i++)
383 start = mask->mask[i].bit_start;
384 size = mask->mask[i].bit_size;
385 regval = mem >> shift;
387 if ((shift += size) > bitsize)
388 error (_("size of all masks is larger than the register"));
397 regval |= mem << (size - shift);
400 /* Make sure we have a valid register. */
401 r = mask->mask[i].reg_num;
402 if (r >= 0 && size > 0)
404 /* Don't overwrite the unmasked areas. */
406 regcache_cooked_read_unsigned (regcache, r, &old_val);
407 m = 0xffffffff >> (32 - size) << start;
409 regval = (regval & m) | (old_val & ~m);
410 regcache_cooked_write_unsigned (regcache, r, regval);
416 /* Read a tie state or mapped registers. Read the masked areas
417 of the registers and assemble them into a single value. */
420 xtensa_register_read_masked (struct regcache *regcache,
421 xtensa_register_t *reg, gdb_byte *buffer)
423 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
424 const xtensa_mask_t *mask = reg->mask;
429 unsigned int *ptr = value;
430 unsigned int regval, mem = 0;
432 int bytesize = reg->byte_size;
433 int bitsize = bytesize * 8;
436 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
437 reg->name == 0 ? "" : reg->name);
439 /* Assemble the register from the masked areas of other registers. */
440 for (i = 0; i < mask->count; i++)
442 int r = mask->mask[i].reg_num;
446 regcache_cooked_read_unsigned (regcache, r, &val);
447 regval = (unsigned int) val;
452 start = mask->mask[i].bit_start;
453 size = mask->mask[i].bit_size;
458 regval &= (0xffffffff >> (32 - size));
460 mem |= regval << shift;
462 if ((shift += size) > bitsize)
463 error (_("size of all masks is larger than the register"));
474 mem = regval >> (size - shift);
481 /* Copy value to target byte order. */
485 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
486 for (i = 0; i < bytesize; i++)
490 buffer[bytesize - i - 1] = mem & 0xff;
494 for (i = 0; i < bytesize; i++)
498 buffer[i] = mem & 0xff;
504 /* Read pseudo registers. */
507 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
508 struct regcache *regcache,
512 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
513 regnum, xtensa_register_name (gdbarch, regnum));
515 if (regnum == gdbarch_num_regs (gdbarch)
516 + gdbarch_num_pseudo_regs (gdbarch) - 1)
517 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
519 /* Read aliases a0..a15, if this is a Windowed ABI. */
520 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
521 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
522 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
524 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
526 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
527 regnum = arreg_number (gdbarch, regnum,
528 extract_unsigned_integer (buf, 4));
531 /* We can always read non-pseudo registers. */
532 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
533 regcache_raw_read (regcache, regnum, buffer);
536 /* We have to find out how to deal with priveleged registers.
537 Let's treat them as pseudo-registers, but we cannot read/write them. */
539 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
541 buffer[0] = (gdb_byte)0;
542 buffer[1] = (gdb_byte)0;
543 buffer[2] = (gdb_byte)0;
544 buffer[3] = (gdb_byte)0;
546 /* Pseudo registers. */
548 && regnum < gdbarch_num_regs (gdbarch)
549 + gdbarch_num_pseudo_regs (gdbarch))
551 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
552 xtensa_register_type_t type = reg->type;
553 int flags = gdbarch_tdep (gdbarch)->target_flags;
555 /* We cannot read Unknown or Unmapped registers. */
556 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
558 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
560 warning (_("cannot read register %s"),
561 xtensa_register_name (gdbarch, regnum));
566 /* Some targets cannot read TIE register files. */
567 else if (type == xtRegisterTypeTieRegfile)
569 /* Use 'fetch' to get register? */
570 if (flags & xtTargetFlagsUseFetchStore)
572 warning (_("cannot read register"));
576 /* On some targets (esp. simulators), we can always read the reg. */
577 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
579 warning (_("cannot read register"));
584 /* We can always read mapped registers. */
585 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
587 xtensa_register_read_masked (regcache, reg, buffer);
591 /* Assume that we can read the register. */
592 regcache_raw_read (regcache, regnum, buffer);
595 internal_error (__FILE__, __LINE__,
596 _("invalid register number %d"), regnum);
600 /* Write pseudo registers. */
603 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
604 struct regcache *regcache,
606 const gdb_byte *buffer)
608 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
609 regnum, xtensa_register_name (gdbarch, regnum));
611 if (regnum == gdbarch_num_regs (gdbarch)
612 + gdbarch_num_pseudo_regs (gdbarch) -1)
613 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
615 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
616 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
617 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
618 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
620 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
623 regcache_raw_read (regcache,
624 gdbarch_tdep (gdbarch)->wb_regnum, buf);
625 regnum = arreg_number (gdbarch, regnum,
626 extract_unsigned_integer (buf, 4));
629 /* We can always write 'core' registers.
630 Note: We might have converted Ax->ARy. */
631 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
632 regcache_raw_write (regcache, regnum, buffer);
634 /* We have to find out how to deal with priveleged registers.
635 Let's treat them as pseudo-registers, but we cannot read/write them. */
637 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
641 /* Pseudo registers. */
643 && regnum < gdbarch_num_regs (gdbarch)
644 + gdbarch_num_pseudo_regs (gdbarch))
646 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
647 xtensa_register_type_t type = reg->type;
648 int flags = gdbarch_tdep (gdbarch)->target_flags;
650 /* On most targets, we cannot write registers
651 of type "Unknown" or "Unmapped". */
652 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
654 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
656 warning (_("cannot write register %s"),
657 xtensa_register_name (gdbarch, regnum));
662 /* Some targets cannot read TIE register files. */
663 else if (type == xtRegisterTypeTieRegfile)
665 /* Use 'store' to get register? */
666 if (flags & xtTargetFlagsUseFetchStore)
668 warning (_("cannot write register"));
672 /* On some targets (esp. simulators), we can always write
674 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
676 warning (_("cannot write register"));
681 /* We can always write mapped registers. */
682 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
684 xtensa_register_write_masked (regcache, reg, buffer);
688 /* Assume that we can write the register. */
689 regcache_raw_write (regcache, regnum, buffer);
692 internal_error (__FILE__, __LINE__,
693 _("invalid register number %d"), regnum);
696 static struct reggroup *xtensa_ar_reggroup;
697 static struct reggroup *xtensa_user_reggroup;
698 static struct reggroup *xtensa_vectra_reggroup;
699 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
702 xtensa_init_reggroups (void)
704 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
705 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
706 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
708 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
709 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
710 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
711 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
712 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
713 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
714 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
715 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
719 xtensa_add_reggroups (struct gdbarch *gdbarch)
723 /* Predefined groups. */
724 reggroup_add (gdbarch, all_reggroup);
725 reggroup_add (gdbarch, save_reggroup);
726 reggroup_add (gdbarch, restore_reggroup);
727 reggroup_add (gdbarch, system_reggroup);
728 reggroup_add (gdbarch, vector_reggroup);
729 reggroup_add (gdbarch, general_reggroup);
730 reggroup_add (gdbarch, float_reggroup);
732 /* Xtensa-specific groups. */
733 reggroup_add (gdbarch, xtensa_ar_reggroup);
734 reggroup_add (gdbarch, xtensa_user_reggroup);
735 reggroup_add (gdbarch, xtensa_vectra_reggroup);
737 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
738 reggroup_add (gdbarch, xtensa_cp[i]);
742 xtensa_coprocessor_register_group (struct reggroup *group)
746 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
747 if (group == xtensa_cp[i])
753 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
754 | XTENSA_REGISTER_FLAGS_WRITABLE \
755 | XTENSA_REGISTER_FLAGS_VOLATILE)
757 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
758 | XTENSA_REGISTER_FLAGS_WRITABLE)
761 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
763 struct reggroup *group)
765 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
766 xtensa_register_type_t type = reg->type;
767 xtensa_register_group_t rg = reg->group;
770 /* First, skip registers that are not visible to this target
771 (unknown and unmapped registers when not using ISS). */
773 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
775 if (group == all_reggroup)
777 if (group == xtensa_ar_reggroup)
778 return rg & xtRegisterGroupAddrReg;
779 if (group == xtensa_user_reggroup)
780 return rg & xtRegisterGroupUser;
781 if (group == float_reggroup)
782 return rg & xtRegisterGroupFloat;
783 if (group == general_reggroup)
784 return rg & xtRegisterGroupGeneral;
785 if (group == float_reggroup)
786 return rg & xtRegisterGroupFloat;
787 if (group == system_reggroup)
788 return rg & xtRegisterGroupState;
789 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
790 return rg & xtRegisterGroupVectra;
791 if (group == save_reggroup || group == restore_reggroup)
792 return (regnum < gdbarch_num_regs (gdbarch)
793 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
794 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
795 return rg & (xtRegisterGroupCP0 << cp_number);
801 /* Supply register REGNUM from the buffer specified by GREGS and LEN
802 in the general-purpose register set REGSET to register cache
803 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
806 xtensa_supply_gregset (const struct regset *regset,
812 const xtensa_elf_gregset_t *regs = gregs;
813 struct gdbarch *gdbarch = get_regcache_arch (rc);
816 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
818 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
819 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
820 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
821 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
822 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
823 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
824 (char *) ®s->windowbase);
825 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
826 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
827 (char *) ®s->windowstart);
828 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
829 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
830 (char *) ®s->lbeg);
831 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
832 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
833 (char *) ®s->lend);
834 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
835 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
836 (char *) ®s->lcount);
837 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
838 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
839 (char *) ®s->sar);
840 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
841 && regnum < gdbarch_tdep (gdbarch)->ar_base
842 + gdbarch_tdep (gdbarch)->num_aregs)
843 regcache_raw_supply (rc, regnum,
844 (char *) ®s->ar[regnum - gdbarch_tdep
845 (gdbarch)->ar_base]);
846 else if (regnum == -1)
848 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
849 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
850 (char *) ®s->ar[i]);
855 /* Xtensa register set. */
861 xtensa_supply_gregset
865 /* Return the appropriate register set for the core
866 section identified by SECT_NAME and SECT_SIZE. */
868 static const struct regset *
869 xtensa_regset_from_core_section (struct gdbarch *core_arch,
870 const char *sect_name,
873 DEBUGTRACE ("xtensa_regset_from_core_section "
874 "(..., sect_name==\"%s\", sect_size==%x) \n",
875 sect_name, (unsigned int) sect_size);
877 if (strcmp (sect_name, ".reg") == 0
878 && sect_size >= sizeof(xtensa_elf_gregset_t))
879 return &xtensa_gregset;
885 /* Handling frames. */
887 /* Number of registers to save in case of Windowed ABI. */
888 #define XTENSA_NUM_SAVED_AREGS 12
890 /* Frame cache part for Windowed ABI. */
891 typedef struct xtensa_windowed_frame_cache
893 int wb; /* WINDOWBASE of the previous frame. */
894 int callsize; /* Call size of this frame. */
895 int ws; /* WINDOWSTART of the previous frame. It keeps track of
896 life windows only. If there is no bit set for the
897 window, that means it had been already spilled
898 because of window overflow. */
900 /* Spilled A-registers from the previous frame.
901 AREGS[i] == -1, if corresponding AR is alive. */
902 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
903 } xtensa_windowed_frame_cache_t;
905 /* Call0 ABI Definitions. */
907 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
908 #define C0_NREGS 16 /* Number of A-registers to track. */
909 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
910 #define C0_SP 1 /* Register used as SP. */
911 #define C0_FP 15 /* Register used as FP. */
912 #define C0_RA 0 /* Register used as return address. */
913 #define C0_ARGS 2 /* Register used as first arg/retval. */
914 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
916 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
917 A-register where the current content of the reg came from (in terms
918 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
919 mean that the orignal content of the register was saved to the stack.
920 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
921 know where SP will end up until the entire prologue has been analyzed. */
923 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
924 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
925 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
927 extern xtensa_isa xtensa_default_isa;
929 typedef struct xtensa_c0reg
931 int fr_reg; /* original register from which register content
932 is derived, or C0_CONST, or C0_INEXP. */
933 int fr_ofs; /* constant offset from reg, or immediate value. */
934 int to_stk; /* offset from original SP to register (4-byte aligned),
935 or C0_NOSTK if register has not been saved. */
939 /* Frame cache part for Call0 ABI. */
940 typedef struct xtensa_call0_frame_cache
942 int c0_frmsz; /* Stack frame size. */
943 int c0_hasfp; /* Current frame uses frame pointer. */
944 int fp_regnum; /* A-register used as FP. */
945 int c0_fp; /* Actual value of frame pointer. */
946 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
947 } xtensa_call0_frame_cache_t;
949 typedef struct xtensa_frame_cache
951 CORE_ADDR base; /* Stack pointer of this frame. */
952 CORE_ADDR pc; /* PC at the entry point to the function. */
953 CORE_ADDR ra; /* The raw return address (without CALLINC). */
954 CORE_ADDR ps; /* The PS register of this frame. */
955 CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
956 int call0; /* It's a call0 framework (else windowed). */
959 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
960 xtensa_call0_frame_cache_t c0; /* call0 == true. */
962 } xtensa_frame_cache_t;
965 static struct xtensa_frame_cache *
966 xtensa_alloc_frame_cache (int windowed)
968 xtensa_frame_cache_t *cache;
971 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
973 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
980 cache->call0 = !windowed;
983 cache->c0.c0_frmsz = -1;
984 cache->c0.c0_hasfp = 0;
985 cache->c0.fp_regnum = -1;
986 cache->c0.c0_fp = -1;
988 for (i = 0; i < C0_NREGS; i++)
990 cache->c0.c0_rt[i].fr_reg = i;
991 cache->c0.c0_rt[i].fr_ofs = 0;
992 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
999 cache->wd.callsize = -1;
1001 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1002 cache->wd.aregs[i] = -1;
1009 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1011 return address & ~15;
1016 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1021 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1022 host_address_to_string (next_frame));
1024 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1025 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1027 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1033 static struct frame_id
1034 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1038 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1040 pc = get_frame_pc (this_frame);
1041 fp = get_frame_register_unsigned
1042 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1044 /* Make dummy frame ID unique by adding a constant. */
1045 return frame_id_build (fp + SP_ALIGNMENT, pc);
1048 /* Returns the best guess about which register is a frame pointer
1049 for the function containing CURRENT_PC. */
1051 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1054 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1056 #define RETURN_FP goto done
1058 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1059 CORE_ADDR start_addr;
1061 xtensa_insnbuf ins, slot;
1062 char ibuf[XTENSA_ISA_BSZ];
1063 CORE_ADDR ia, bt, ba;
1065 int ilen, islots, is;
1067 const char *opcname;
1069 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1070 if (start_addr == 0)
1073 if (!xtensa_default_isa)
1074 xtensa_default_isa = xtensa_isa_init (0, 0);
1075 isa = xtensa_default_isa;
1076 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1077 ins = xtensa_insnbuf_alloc (isa);
1078 slot = xtensa_insnbuf_alloc (isa);
1081 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1083 if (ia + xtensa_isa_maxlength (isa) > bt)
1086 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1087 ? ba + XTENSA_ISA_BSZ : current_pc;
1088 read_memory (ba, ibuf, bt - ba);
1091 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1092 ifmt = xtensa_format_decode (isa, ins);
1093 if (ifmt == XTENSA_UNDEFINED)
1095 ilen = xtensa_format_length (isa, ifmt);
1096 if (ilen == XTENSA_UNDEFINED)
1098 islots = xtensa_format_num_slots (isa, ifmt);
1099 if (islots == XTENSA_UNDEFINED)
1102 for (is = 0; is < islots; ++is)
1104 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1107 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1108 if (opc == XTENSA_UNDEFINED)
1111 opcname = xtensa_opcode_name (isa, opc);
1113 if (strcasecmp (opcname, "mov.n") == 0
1114 || strcasecmp (opcname, "or") == 0)
1116 unsigned int register_operand;
1118 /* Possible candidate for setting frame pointer
1119 from A1. This is what we are looking for. */
1121 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1122 is, slot, ®ister_operand) != 0)
1124 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1126 if (register_operand == 1) /* Mov{.n} FP A1. */
1128 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1129 ®ister_operand) != 0)
1131 if (xtensa_operand_decode (isa, opc, 0,
1132 ®ister_operand) != 0)
1135 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1141 /* We have problems decoding the memory. */
1143 || strcasecmp (opcname, "ill") == 0
1144 || strcasecmp (opcname, "ill.n") == 0
1145 /* Hit planted breakpoint. */
1146 || strcasecmp (opcname, "break") == 0
1147 || strcasecmp (opcname, "break.n") == 0
1148 /* Flow control instructions finish prologue. */
1149 || xtensa_opcode_is_branch (isa, opc) > 0
1150 || xtensa_opcode_is_jump (isa, opc) > 0
1151 || xtensa_opcode_is_loop (isa, opc) > 0
1152 || xtensa_opcode_is_call (isa, opc) > 0
1153 || strcasecmp (opcname, "simcall") == 0
1154 || strcasecmp (opcname, "syscall") == 0)
1155 /* Can not continue analysis. */
1160 xtensa_insnbuf_free(isa, slot);
1161 xtensa_insnbuf_free(isa, ins);
1165 /* The key values to identify the frame using "cache" are
1167 cache->base = SP (or best guess about FP) of this frame;
1168 cache->pc = entry-PC (entry point of the frame function);
1169 cache->prev_sp = SP of the previous frame.
1173 call0_frame_cache (struct frame_info *this_frame,
1174 xtensa_frame_cache_t *cache,
1175 CORE_ADDR pc, CORE_ADDR litbase);
1177 static struct xtensa_frame_cache *
1178 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1180 xtensa_frame_cache_t *cache;
1181 CORE_ADDR ra, wb, ws, pc, sp, ps;
1182 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1183 unsigned int fp_regnum;
1190 ps = get_frame_register_unsigned (this_frame, gdbarch_ps_regnum (gdbarch));
1191 windowed = windowing_enabled (ps);
1193 /* Get pristine xtensa-frame. */
1194 cache = xtensa_alloc_frame_cache (windowed);
1195 *this_cache = cache;
1197 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1201 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1202 wb = get_frame_register_unsigned (this_frame,
1203 gdbarch_tdep (gdbarch)->wb_regnum);
1204 ws = get_frame_register_unsigned (this_frame,
1205 gdbarch_tdep (gdbarch)->ws_regnum);
1207 op1 = read_memory_integer (pc, 1);
1208 if (XTENSA_IS_ENTRY (gdbarch, op1))
1210 int callinc = CALLINC (ps);
1211 ra = get_frame_register_unsigned
1212 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1214 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1215 cache->wd.callsize = 0;
1218 cache->prev_sp = get_frame_register_unsigned
1219 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1221 /* This only can be the outermost frame since we are
1222 just about to execute ENTRY. SP hasn't been set yet.
1223 We can assume any frame size, because it does not
1224 matter, and, let's fake frame base in cache. */
1225 cache->base = cache->prev_sp + 16;
1228 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1229 cache->ps = (ps & ~PS_CALLINC_MASK)
1230 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1236 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1237 ra = get_frame_register_unsigned (this_frame,
1238 gdbarch_tdep (gdbarch)->a0_base);
1239 cache->wd.callsize = WINSIZE (ra);
1240 cache->wd.wb = (wb - cache->wd.callsize / 4)
1241 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1242 cache->wd.ws = ws & ~(1 << wb);
1244 cache->pc = get_frame_func (this_frame);
1245 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1246 cache->ps = (ps & ~PS_CALLINC_MASK)
1247 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1250 if (cache->wd.ws == 0)
1255 sp = get_frame_register_unsigned
1256 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1258 for (i = 0; i < 4; i++, sp += 4)
1260 cache->wd.aregs[i] = sp;
1263 if (cache->wd.callsize > 4)
1265 /* Set A4...A7/A11. */
1266 /* Get the SP of the frame previous to the previous one.
1267 To achieve this, we have to dereference SP twice. */
1268 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1269 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1270 sp -= cache->wd.callsize * 4;
1272 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1274 cache->wd.aregs[i] = sp;
1279 if ((cache->prev_sp == 0) && ( ra != 0 ))
1280 /* If RA is equal to 0 this frame is an outermost frame. Leave
1281 cache->prev_sp unchanged marking the boundary of the frame stack. */
1283 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1285 /* Register window overflow already happened.
1286 We can read caller's SP from the proper spill loction. */
1287 sp = get_frame_register_unsigned
1288 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1289 cache->prev_sp = read_memory_integer (sp - 12, 4);
1293 /* Read caller's frame SP directly from the previous window. */
1294 int regnum = arreg_number
1295 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1298 cache->prev_sp = get_frame_register_unsigned (this_frame, regnum);
1302 else /* Call0 framework. */
1304 unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
1305 CORE_ADDR litbase = (litbase_regnum == -1)
1306 ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
1308 call0_frame_cache (this_frame, cache, pc, litbase);
1309 fp_regnum = cache->c0.fp_regnum;
1312 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1318 xtensa_frame_this_id (struct frame_info *this_frame,
1320 struct frame_id *this_id)
1322 struct xtensa_frame_cache *cache =
1323 xtensa_frame_cache (this_frame, this_cache);
1325 if (cache->prev_sp == 0)
1328 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1331 static struct value *
1332 xtensa_frame_prev_register (struct frame_info *this_frame,
1336 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1337 struct xtensa_frame_cache *cache;
1338 ULONGEST saved_reg = 0;
1341 if (*this_cache == NULL)
1342 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1343 cache = *this_cache;
1345 if (regnum ==gdbarch_pc_regnum (gdbarch))
1346 saved_reg = cache->ra;
1347 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1348 saved_reg = cache->prev_sp;
1349 else if (!cache->call0)
1351 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1352 saved_reg = cache->wd.ws;
1353 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1354 saved_reg = cache->wd.wb;
1355 else if (regnum == gdbarch_ps_regnum (gdbarch))
1356 saved_reg = cache->ps;
1364 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1366 if (!cache->call0) /* Windowed ABI. */
1368 /* Convert A-register numbers to AR-register numbers,
1369 if we deal with A-register. */
1370 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1371 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1372 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1374 /* Check, if we deal with AR-register saved on stack. */
1375 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1376 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1377 + gdbarch_tdep (gdbarch)->num_aregs))
1379 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1382 && areg < XTENSA_NUM_SAVED_AREGS
1383 && cache->wd.aregs[areg] != -1)
1384 return frame_unwind_got_memory (this_frame, regnum,
1385 cache->wd.aregs[areg]);
1388 else /* Call0 ABI. */
1390 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1391 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1393 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1400 /* If register was saved in the prologue, retrieve it. */
1401 stkofs = cache->c0.c0_rt[reg].to_stk;
1402 if (stkofs != C0_NOSTK)
1404 /* Determine SP on entry based on FP. */
1405 spe = cache->c0.c0_fp
1406 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1408 return frame_unwind_got_memory (this_frame, regnum, spe + stkofs);
1413 /* All other registers have been either saved to
1414 the stack or are still alive in the processor. */
1416 return frame_unwind_got_register (this_frame, regnum, regnum);
1420 static const struct frame_unwind
1424 xtensa_frame_this_id,
1425 xtensa_frame_prev_register,
1427 default_frame_sniffer
1431 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1433 struct xtensa_frame_cache *cache =
1434 xtensa_frame_cache (this_frame, this_cache);
1439 static const struct frame_base
1443 xtensa_frame_base_address,
1444 xtensa_frame_base_address,
1445 xtensa_frame_base_address
1450 xtensa_extract_return_value (struct type *type,
1451 struct regcache *regcache,
1454 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1455 bfd_byte *valbuf = dst;
1456 int len = TYPE_LENGTH (type);
1461 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1463 gdb_assert(len > 0);
1465 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1467 /* First, we have to find the caller window in the register file. */
1468 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1469 callsize = extract_call_winsize (gdbarch, pc);
1471 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1472 if (len > (callsize > 8 ? 8 : 16))
1473 internal_error (__FILE__, __LINE__,
1474 _("cannot extract return value of %d bytes long"), len);
1476 /* Get the register offset of the return
1477 register (A2) in the caller window. */
1478 regcache_raw_read_unsigned
1479 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1480 areg = arreg_number (gdbarch,
1481 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1485 /* No windowing hardware - Call0 ABI. */
1486 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1489 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1491 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1494 for (; len > 0; len -= 4, areg++, valbuf += 4)
1497 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1499 regcache_raw_read (regcache, areg, valbuf);
1505 xtensa_store_return_value (struct type *type,
1506 struct regcache *regcache,
1509 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1510 const bfd_byte *valbuf = dst;
1514 int len = TYPE_LENGTH (type);
1517 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1519 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1521 regcache_raw_read_unsigned
1522 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1523 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1524 callsize = extract_call_winsize (gdbarch, pc);
1526 if (len > (callsize > 8 ? 8 : 16))
1527 internal_error (__FILE__, __LINE__,
1528 _("unimplemented for this length: %d"),
1529 TYPE_LENGTH (type));
1530 areg = arreg_number (gdbarch,
1531 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1533 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1534 callsize, (int) wb);
1538 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1541 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1544 for (; len > 0; len -= 4, areg++, valbuf += 4)
1547 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1549 regcache_raw_write (regcache, areg, valbuf);
1554 static enum return_value_convention
1555 xtensa_return_value (struct gdbarch *gdbarch,
1556 struct type *func_type,
1557 struct type *valtype,
1558 struct regcache *regcache,
1560 const gdb_byte *writebuf)
1562 /* Structures up to 16 bytes are returned in registers. */
1564 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1565 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1566 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1567 && TYPE_LENGTH (valtype) > 16);
1570 return RETURN_VALUE_STRUCT_CONVENTION;
1572 DEBUGTRACE ("xtensa_return_value(...)\n");
1574 if (writebuf != NULL)
1576 xtensa_store_return_value (valtype, regcache, writebuf);
1579 if (readbuf != NULL)
1581 gdb_assert (!struct_return);
1582 xtensa_extract_return_value (valtype, regcache, readbuf);
1584 return RETURN_VALUE_REGISTER_CONVENTION;
1591 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1592 struct value *function,
1593 struct regcache *regcache,
1596 struct value **args,
1599 CORE_ADDR struct_addr)
1602 int size, onstack_size;
1603 gdb_byte *buf = (gdb_byte *) alloca (16);
1605 struct argument_info
1607 const bfd_byte *contents;
1609 int onstack; /* onstack == 0 => in reg */
1610 int align; /* alignment */
1613 int offset; /* stack offset if on stack */
1614 int regno; /* regno if in register */
1618 struct argument_info *arg_info =
1619 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1623 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1625 if (xtensa_debug_level > 3)
1628 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1629 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1630 "struct_addr=0x%x\n",
1631 (int) sp, (int) struct_return, (int) struct_addr);
1633 for (i = 0; i < nargs; i++)
1635 struct value *arg = args[i];
1636 struct type *arg_type = check_typedef (value_type (arg));
1637 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
1638 i, (unsigned long) arg, TYPE_LENGTH (arg_type));
1639 switch (TYPE_CODE (arg_type))
1642 fprintf_unfiltered (gdb_stdlog, "int");
1644 case TYPE_CODE_STRUCT:
1645 fprintf_unfiltered (gdb_stdlog, "struct");
1648 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1651 fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
1652 (unsigned long) value_contents (arg));
1656 /* First loop: collect information.
1657 Cast into type_long. (This shouldn't happen often for C because
1658 GDB already does this earlier.) It's possible that GDB could
1659 do it all the time but it's harmless to leave this code here. */
1666 size = REGISTER_SIZE;
1668 for (i = 0; i < nargs; i++)
1670 struct argument_info *info = &arg_info[i];
1671 struct value *arg = args[i];
1672 struct type *arg_type = check_typedef (value_type (arg));
1674 switch (TYPE_CODE (arg_type))
1677 case TYPE_CODE_BOOL:
1678 case TYPE_CODE_CHAR:
1679 case TYPE_CODE_RANGE:
1680 case TYPE_CODE_ENUM:
1682 /* Cast argument to long if necessary as the mask does it too. */
1683 if (TYPE_LENGTH (arg_type)
1684 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1686 arg_type = builtin_type (gdbarch)->builtin_long;
1687 arg = value_cast (arg_type, arg);
1689 /* Aligment is equal to the type length for the basic types. */
1690 info->align = TYPE_LENGTH (arg_type);
1695 /* Align doubles correctly. */
1696 if (TYPE_LENGTH (arg_type)
1697 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1698 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1700 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1703 case TYPE_CODE_STRUCT:
1705 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1708 info->length = TYPE_LENGTH (arg_type);
1709 info->contents = value_contents (arg);
1711 /* Align size and onstack_size. */
1712 size = (size + info->align - 1) & ~(info->align - 1);
1713 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1715 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1718 info->u.offset = onstack_size;
1719 onstack_size += info->length;
1724 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1726 size += info->length;
1729 /* Adjust the stack pointer and align it. */
1730 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1732 /* Simulate MOVSP, if Windowed ABI. */
1733 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1736 read_memory (osp - 16, buf, 16);
1737 write_memory (sp - 16, buf, 16);
1740 /* Second Loop: Load arguments. */
1744 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1745 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1748 for (i = 0; i < nargs; i++)
1750 struct argument_info *info = &arg_info[i];
1754 int n = info->length;
1755 CORE_ADDR offset = sp + info->u.offset;
1757 /* Odd-sized structs are aligned to the lower side of a memory
1758 word in big-endian mode and require a shift. This only
1759 applies for structures smaller than one word. */
1761 if (n < REGISTER_SIZE
1762 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1763 offset += (REGISTER_SIZE - n);
1765 write_memory (offset, info->contents, info->length);
1770 int n = info->length;
1771 const bfd_byte *cp = info->contents;
1772 int r = info->u.regno;
1774 /* Odd-sized structs are aligned to the lower side of registers in
1775 big-endian mode and require a shift. The odd-sized leftover will
1776 be at the end. Note that this is only true for structures smaller
1777 than REGISTER_SIZE; for larger odd-sized structures the excess
1778 will be left-aligned in the register on both endiannesses. */
1780 if (n < REGISTER_SIZE
1781 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1783 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1784 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1786 store_unsigned_integer (buf, REGISTER_SIZE, v);
1787 regcache_cooked_write (regcache, r, buf);
1789 cp += REGISTER_SIZE;
1796 regcache_cooked_write (regcache, r, cp);
1798 cp += REGISTER_SIZE;
1805 /* Set the return address of dummy frame to the dummy address.
1806 The return address for the current function (in A0) is
1807 saved in the dummy frame, so we can savely overwrite A0 here. */
1809 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1811 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1812 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
1813 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1814 regcache_cooked_write_unsigned
1815 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1816 regcache_cooked_write_unsigned (regcache,
1817 gdbarch_ps_regnum (gdbarch),
1820 /* All the registers have been saved. After executing
1821 dummy call, they all will be restored. So it's safe
1822 to modify WINDOWSTART register to make it look like there
1823 is only one register window corresponding to WINDOWEBASE. */
1825 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1826 regcache_cooked_write_unsigned (regcache,
1827 gdbarch_tdep (gdbarch)->ws_regnum,
1828 1 << extract_unsigned_integer (buf, 4));
1832 /* Simulate CALL0: write RA into A0 register. */
1833 regcache_cooked_write_unsigned
1834 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1837 /* Set new stack pointer and return it. */
1838 regcache_cooked_write_unsigned (regcache,
1839 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1840 /* Make dummy frame ID unique by adding a constant. */
1841 return sp + SP_ALIGNMENT;
1845 /* Return a breakpoint for the current location of PC. We always use
1846 the density version if we have density instructions (regardless of the
1847 current instruction at PC), and use regular instructions otherwise. */
1849 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1850 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1851 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1852 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1854 static const unsigned char *
1855 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1858 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1859 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1860 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1861 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1863 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1865 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1867 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1869 *lenptr = sizeof (density_big_breakpoint);
1870 return density_big_breakpoint;
1874 *lenptr = sizeof (density_little_breakpoint);
1875 return density_little_breakpoint;
1880 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1882 *lenptr = sizeof (big_breakpoint);
1883 return big_breakpoint;
1887 *lenptr = sizeof (little_breakpoint);
1888 return little_breakpoint;
1893 /* Call0 ABI support routines. */
1895 /* Call0 opcode class. Opcodes are preclassified according to what they
1896 mean for Call0 prologue analysis, and their number of significant operands.
1897 The purpose of this is to simplify prologue analysis by separating
1898 instruction decoding (libisa) from the semantics of prologue analysis. */
1901 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1902 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1903 c0opc_flow, /* Flow control insn. */
1904 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1905 c0opc_break, /* Debugger software breakpoints. */
1906 c0opc_add, /* Adding two registers. */
1907 c0opc_addi, /* Adding a register and an immediate. */
1908 c0opc_sub, /* Subtracting a register from a register. */
1909 c0opc_mov, /* Moving a register to a register. */
1910 c0opc_movi, /* Moving an immediate to a register. */
1911 c0opc_l32r, /* Loading a literal. */
1912 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1913 c0opc_NrOf /* Number of opcode classifications. */
1917 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1919 static xtensa_insn_kind
1920 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1922 const char *opcname;
1923 xtensa_insn_kind opclass = c0opc_uninteresting;
1925 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1927 /* Get opcode name and handle special classifications. */
1929 opcname = xtensa_opcode_name (isa, opc);
1932 || strcasecmp (opcname, "ill") == 0
1933 || strcasecmp (opcname, "ill.n") == 0)
1934 opclass = c0opc_illegal;
1935 else if (strcasecmp (opcname, "break") == 0
1936 || strcasecmp (opcname, "break.n") == 0)
1937 opclass = c0opc_break;
1938 else if (strcasecmp (opcname, "entry") == 0)
1939 opclass = c0opc_entry;
1940 else if (xtensa_opcode_is_branch (isa, opc) > 0
1941 || xtensa_opcode_is_jump (isa, opc) > 0
1942 || xtensa_opcode_is_loop (isa, opc) > 0
1943 || xtensa_opcode_is_call (isa, opc) > 0
1944 || strcasecmp (opcname, "simcall") == 0
1945 || strcasecmp (opcname, "syscall") == 0)
1946 opclass = c0opc_flow;
1948 /* Also, classify specific opcodes that need to be tracked. */
1949 else if (strcasecmp (opcname, "add") == 0
1950 || strcasecmp (opcname, "add.n") == 0)
1951 opclass = c0opc_add;
1952 else if (strcasecmp (opcname, "addi") == 0
1953 || strcasecmp (opcname, "addi.n") == 0
1954 || strcasecmp (opcname, "addmi") == 0)
1955 opclass = c0opc_addi;
1956 else if (strcasecmp (opcname, "sub") == 0)
1957 opclass = c0opc_sub;
1958 else if (strcasecmp (opcname, "mov.n") == 0
1959 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1960 opclass = c0opc_mov;
1961 else if (strcasecmp (opcname, "movi") == 0
1962 || strcasecmp (opcname, "movi.n") == 0)
1963 opclass = c0opc_movi;
1964 else if (strcasecmp (opcname, "l32r") == 0)
1965 opclass = c0opc_l32r;
1966 else if (strcasecmp (opcname, "s32i") == 0
1967 || strcasecmp (opcname, "s32i.n") == 0)
1968 opclass = c0opc_s32i;
1973 /* Tracks register movement/mutation for a given operation, which may
1974 be within a bundle. Updates the destination register tracking info
1975 accordingly. The pc is needed only for pc-relative load instructions
1976 (eg. l32r). The SP register number is needed to identify stores to
1980 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1981 xtensa_insn_kind opclass, int nods, unsigned odv[],
1982 CORE_ADDR pc, CORE_ADDR litbase, int spreg)
1984 unsigned litaddr, litval;
1989 /* 3 operands: dst, src, imm. */
1990 gdb_assert (nods == 3);
1991 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1992 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1995 /* 3 operands: dst, src1, src2. */
1996 gdb_assert (nods == 3);
1997 if (src[odv[1]].fr_reg == C0_CONST)
1999 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2000 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2002 else if (src[odv[2]].fr_reg == C0_CONST)
2004 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2005 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2007 else dst[odv[0]].fr_reg = C0_INEXP;
2010 /* 3 operands: dst, src1, src2. */
2011 gdb_assert (nods == 3);
2012 if (src[odv[2]].fr_reg == C0_CONST)
2014 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2015 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2017 else dst[odv[0]].fr_reg = C0_INEXP;
2020 /* 2 operands: dst, src [, src]. */
2021 gdb_assert (nods == 2);
2022 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2023 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2026 /* 2 operands: dst, imm. */
2027 gdb_assert (nods == 2);
2028 dst[odv[0]].fr_reg = C0_CONST;
2029 dst[odv[0]].fr_ofs = odv[1];
2032 /* 2 operands: dst, literal offset. */
2033 gdb_assert (nods == 2);
2034 litaddr = litbase & 1
2035 ? (litbase & ~1) + (signed)odv[1]
2036 : (pc + 3 + (signed)odv[1]) & ~3;
2037 litval = read_memory_integer(litaddr, 4);
2038 dst[odv[0]].fr_reg = C0_CONST;
2039 dst[odv[0]].fr_ofs = litval;
2042 /* 3 operands: value, base, offset. */
2043 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2044 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2045 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2046 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2047 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2048 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2050 /* ISA encoding guarantees alignment. But, check it anyway. */
2051 gdb_assert ((odv[2] & 3) == 0);
2052 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2060 /* Analyze prologue of the function at start address to determine if it uses
2061 the Call0 ABI, and if so track register moves and linear modifications
2062 in the prologue up to the PC or just beyond the prologue, whichever is first.
2063 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2064 The prologue may overlap non-prologue instructions but is guaranteed to end
2065 by the first flow-control instruction (jump, branch, call or return).
2066 Since an optimized function may move information around and change the
2067 stack frame arbitrarily during the prologue, the information is guaranteed
2068 valid only at the point in the function indicated by the PC.
2069 May be used to skip the prologue or identify the ABI, w/o tracking.
2071 Returns: Address of first instruction after prologue, or PC (whichever
2072 is first), or 0, if decoding failed (in libisa).
2074 start Start address of function/prologue.
2075 pc Program counter to stop at. Use 0 to continue to end of prologue.
2076 If 0, avoids infinite run-on in corrupt code memory by bounding
2077 the scan to the end of the function if that can be determined.
2078 nregs Number of general registers to track (size of rt[] array).
2080 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2081 If NULL, registers are not tracked.
2083 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2084 (more accurately, non-zero until 'entry' insn is encountered).
2086 Note that these may produce useful results even if decoding fails
2087 because they begin with default assumptions that analysis may change. */
2090 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
2091 int nregs, xtensa_c0reg_t rt[], int *call0)
2093 CORE_ADDR ia; /* Current insn address in prologue. */
2094 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2095 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2096 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2097 xtensa_isa isa; /* libisa ISA handle. */
2098 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2099 xtensa_format ifmt; /* libisa instruction format. */
2100 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2101 xtensa_opcode opc; /* Opcode in current slot. */
2102 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2103 int nods; /* Opcode number of operands. */
2104 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2105 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2106 int j; /* General loop counter. */
2107 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2108 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2109 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2111 struct symtab_and_line prologue_sal;
2113 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2114 (int)start, (int)pc);
2116 /* Try to limit the scan to the end of the function if a non-zero pc
2117 arg was not supplied to avoid probing beyond the end of valid memory.
2118 If memory is full of garbage that classifies as c0opc_uninteresting.
2119 If this fails (eg. if no symbols) pc ends up 0 as it was.
2120 Intialize the Call0 frame and register tracking info.
2121 Assume it's Call0 until an 'entry' instruction is encountered.
2122 Assume we may be in the prologue until we hit a flow control instr. */
2128 /* Find out, if we have an information about the prologue from DWARF. */
2129 prologue_sal = find_pc_line (start, 0);
2130 if (prologue_sal.line != 0) /* Found debug info. */
2131 body_pc = prologue_sal.end;
2133 /* If we are going to analyze the prologue in general without knowing about
2134 the current PC, make the best assumtion for the end of the prologue. */
2137 find_pc_partial_function (start, 0, NULL, &end_pc);
2138 body_pc = min (end_pc, body_pc);
2141 body_pc = min (pc, body_pc);
2148 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2149 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2153 if (!xtensa_default_isa)
2154 xtensa_default_isa = xtensa_isa_init (0, 0);
2155 isa = xtensa_default_isa;
2156 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2157 ins = xtensa_insnbuf_alloc (isa);
2158 slot = xtensa_insnbuf_alloc (isa);
2160 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2162 /* (Re)fill instruction buffer from memory if necessary, but do not
2163 read memory beyond PC to be sure we stay within text section
2164 (this protection only works if a non-zero pc is supplied). */
2166 if (ia + xtensa_isa_maxlength (isa) > bt)
2169 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2170 read_memory (ba, ibuf, bt - ba);
2173 /* Decode format information. */
2175 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2176 ifmt = xtensa_format_decode (isa, ins);
2177 if (ifmt == XTENSA_UNDEFINED)
2182 ilen = xtensa_format_length (isa, ifmt);
2183 if (ilen == XTENSA_UNDEFINED)
2188 islots = xtensa_format_num_slots (isa, ifmt);
2189 if (islots == XTENSA_UNDEFINED)
2195 /* Analyze a bundle or a single instruction, using a snapshot of
2196 the register tracking info as input for the entire bundle so that
2197 register changes do not take effect within this bundle. */
2199 for (j = 0; j < nregs; ++j)
2202 for (is = 0; is < islots; ++is)
2204 /* Decode a slot and classify the opcode. */
2206 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2210 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2211 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2213 if (opc == XTENSA_UNDEFINED)
2214 opclass = c0opc_illegal;
2216 opclass = call0_classify_opcode (isa, opc);
2218 /* Decide whether to track this opcode, ignore it, or bail out. */
2227 case c0opc_uninteresting:
2236 ia += ilen; /* Skip over 'entry' insn. */
2244 /* Only expected opcodes should get this far. */
2248 /* Extract and decode the operands. */
2249 nods = xtensa_opcode_num_operands (isa, opc);
2250 if (nods == XTENSA_UNDEFINED)
2256 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2258 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2263 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2268 /* Check operands to verify use of 'mov' assembler macro. */
2269 if (opclass == c0opc_mov && nods == 3)
2271 if (odv[2] == odv[1])
2275 opclass = c0opc_uninteresting;
2280 /* Track register movement and modification for this operation. */
2281 call0_track_op (rt, rtmp, opclass, nods, odv, ia, litbase, 1);
2285 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2286 (unsigned)ia, fail ? "failed" : "succeeded");
2287 xtensa_insnbuf_free(isa, slot);
2288 xtensa_insnbuf_free(isa, ins);
2289 return fail ? 0 : ia;
2292 /* Initialize frame cache for the current frame in CALL0 ABI. */
2295 call0_frame_cache (struct frame_info *this_frame,
2296 xtensa_frame_cache_t *cache, CORE_ADDR pc, CORE_ADDR litbase)
2298 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2299 CORE_ADDR start_pc; /* The beginning of the function. */
2300 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2301 CORE_ADDR sp, fp, ra;
2302 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2304 /* Find the beginning of the prologue of the function containing the PC
2305 and analyze it up to the PC or the end of the prologue. */
2307 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2309 body_pc = call0_analyze_prologue (start_pc, pc, litbase, C0_NREGS,
2310 &cache->c0.c0_rt[0],
2314 sp = get_frame_register_unsigned
2315 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2316 fp = sp; /* Assume FP == SP until proven otherwise. */
2318 /* Get the frame information and FP (if used) at the current PC.
2319 If PC is in the prologue, the prologue analysis is more reliable
2320 than DWARF info. We don't not know for sure if PC is in the prologue,
2321 but we know no calls have yet taken place, so we can almost
2322 certainly rely on the prologue analysis. */
2326 /* Prologue analysis was successful up to the PC.
2327 It includes the cases when PC == START_PC. */
2328 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2329 /* c0_hasfp == true means there is a frame pointer because
2330 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2331 was derived from SP. Otherwise, it would be C0_FP. */
2332 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2333 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2334 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2336 else /* No data from the prologue analysis. */
2339 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2344 prev_sp = fp + c0_frmsz;
2346 /* Frame size from debug info or prologue tracking does not account for
2347 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2350 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2352 /* Recalculate previous SP. */
2353 prev_sp = fp + c0_frmsz;
2354 /* Update the stack frame size. */
2355 c0_frmsz += fp - sp;
2358 /* Get the return address (RA) from the stack if saved,
2359 or try to get it from a register. */
2361 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2362 if (to_stk != C0_NOSTK)
2364 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2366 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2367 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2369 /* Special case for terminating backtrace at a function that wants to
2370 be seen as the outermost. Such a function will clear it's RA (A0)
2371 register to 0 in the prologue instead of saving its original value. */
2376 /* RA was copied to another register or (before any function call) may
2377 still be in the original RA register. This is not always reliable:
2378 even in a leaf function, register tracking stops after prologue, and
2379 even in prologue, non-prologue instructions (not tracked) may overwrite
2380 RA or any register it was copied to. If likely in prologue or before
2381 any call, use retracking info and hope for the best (compiler should
2382 have saved RA in stack if not in a leaf function). If not in prologue,
2388 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2390 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2394 ra = get_frame_register_unsigned
2396 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2401 cache->pc = start_pc;
2403 /* RA == 0 marks the outermost frame. Do not go past it. */
2404 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2405 cache->c0.fp_regnum = fp_regnum;
2406 cache->c0.c0_frmsz = c0_frmsz;
2407 cache->c0.c0_hasfp = c0_hasfp;
2408 cache->c0.c0_fp = fp;
2412 /* Skip function prologue.
2414 Return the pc of the first instruction after prologue. GDB calls this to
2415 find the address of the first line of the function or (if there is no line
2416 number information) to skip the prologue for planting breakpoints on
2417 function entries. Use debug info (if present) or prologue analysis to skip
2418 the prologue to achieve reliable debugging behavior. For windowed ABI,
2419 only the 'entry' instruction is skipped. It is not strictly necessary to
2420 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2421 backtrace at any point in the prologue, however certain potential hazards
2422 are avoided and a more "normal" debugging experience is ensured by
2423 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2424 For example, if we don't skip the prologue:
2425 - Some args may not yet have been saved to the stack where the debug
2426 info expects to find them (true anyway when only 'entry' is skipped);
2427 - Software breakpoints ('break' instrs) may not have been unplanted
2428 when the prologue analysis is done on initializing the frame cache,
2429 and breaks in the prologue will throw off the analysis.
2431 If we have debug info ( line-number info, in particular ) we simply skip
2432 the code associated with the first function line effectively skipping
2433 the prologue code. It works even in cases like
2436 { int local_var = 1;
2440 because, for this source code, both Xtensa compilers will generate two
2441 separate entries ( with the same line number ) in dwarf line-number
2442 section to make sure there is a boundary between the prologue code and
2443 the rest of the function.
2445 If there is no debug info, we need to analyze the code. */
2447 /* #define DONT_SKIP_PROLOGUE */
2450 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2452 struct symtab_and_line prologue_sal;
2455 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2457 #if DONT_SKIP_PROLOGUE
2461 /* Try to find first body line from debug info. */
2463 prologue_sal = find_pc_line (start_pc, 0);
2464 if (prologue_sal.line != 0) /* Found debug info. */
2466 /* In Call0, it is possible to have a function with only one instruction
2467 ('ret') resulting from a 1-line optimized function that does nothing.
2468 In that case, prologue_sal.end may actually point to the start of the
2469 next function in the text section, causing a breakpoint to be set at
2470 the wrong place. Check if the end address is in a different function,
2471 and if so return the start PC. We know we have symbol info. */
2475 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2476 if (end_func != start_pc)
2479 return prologue_sal.end;
2482 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2483 body_pc = call0_analyze_prologue(start_pc, 0, 0, 0, NULL, NULL);
2484 return body_pc != 0 ? body_pc : start_pc;
2487 /* Verify the current configuration. */
2489 xtensa_verify_config (struct gdbarch *gdbarch)
2491 struct ui_file *log;
2492 struct cleanup *cleanups;
2493 struct gdbarch_tdep *tdep;
2497 tdep = gdbarch_tdep (gdbarch);
2498 log = mem_fileopen ();
2499 cleanups = make_cleanup_ui_file_delete (log);
2501 /* Verify that we got a reasonable number of AREGS. */
2502 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2503 fprintf_unfiltered (log, _("\
2504 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2507 /* Verify that certain registers exist. */
2509 if (tdep->pc_regnum == -1)
2510 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2511 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2512 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2514 if (tdep->isa_use_windowed_registers)
2516 if (tdep->wb_regnum == -1)
2517 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2518 if (tdep->ws_regnum == -1)
2519 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2520 if (tdep->ar_base == -1)
2521 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2524 if (tdep->a0_base == -1)
2525 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2527 buf = ui_file_xstrdup (log, &dummy);
2528 make_cleanup (xfree, buf);
2529 if (strlen (buf) > 0)
2530 internal_error (__FILE__, __LINE__,
2531 _("the following are invalid: %s"), buf);
2532 do_cleanups (cleanups);
2536 /* Derive specific register numbers from the array of registers. */
2539 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2541 xtensa_register_t* rmap;
2542 int n, max_size = 4;
2545 tdep->num_nopriv_regs = 0;
2547 /* Special registers 0..255 (core). */
2548 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2550 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2552 if (rmap->target_number == 0x0020)
2553 tdep->pc_regnum = n;
2554 else if (rmap->target_number == 0x0100)
2556 else if (rmap->target_number == 0x0000)
2558 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2559 tdep->wb_regnum = n;
2560 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2561 tdep->ws_regnum = n;
2562 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2563 tdep->debugcause_regnum = n;
2564 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2565 tdep->exccause_regnum = n;
2566 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2567 tdep->excvaddr_regnum = n;
2568 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2569 tdep->lbeg_regnum = n;
2570 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2571 tdep->lend_regnum = n;
2572 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2573 tdep->lcount_regnum = n;
2574 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2575 tdep->sar_regnum = n;
2576 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2577 tdep->litbase_regnum = n;
2578 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2579 tdep->ps_regnum = n;
2581 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2582 tdep->interrupt_regnum = n;
2583 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2584 tdep->interrupt2_regnum = n;
2585 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2586 tdep->cpenable_regnum = n;
2589 if (rmap->byte_size > max_size)
2590 max_size = rmap->byte_size;
2591 if (rmap->mask != 0 && tdep->num_regs == 0)
2593 /* Find out out how to deal with priveleged registers.
2595 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2596 && tdep->num_nopriv_regs == 0)
2597 tdep->num_nopriv_regs = n;
2599 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2600 && tdep->num_regs == 0)
2604 /* Number of pseudo registers. */
2605 tdep->num_pseudo_regs = n - tdep->num_regs;
2607 /* Empirically determined maximum sizes. */
2608 tdep->max_register_raw_size = max_size;
2609 tdep->max_register_virtual_size = max_size;
2612 /* Module "constructor" function. */
2614 extern struct gdbarch_tdep xtensa_tdep;
2616 static struct gdbarch *
2617 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2619 struct gdbarch_tdep *tdep;
2620 struct gdbarch *gdbarch;
2621 struct xtensa_abi_handler *abi_handler;
2623 DEBUGTRACE ("gdbarch_init()\n");
2625 /* We have to set the byte order before we call gdbarch_alloc. */
2626 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
2628 tdep = &xtensa_tdep;
2629 gdbarch = gdbarch_alloc (&info, tdep);
2630 xtensa_derive_tdep (tdep);
2632 /* Verify our configuration. */
2633 xtensa_verify_config (gdbarch);
2635 /* Pseudo-Register read/write. */
2636 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2637 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2639 /* Set target information. */
2640 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2641 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2642 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2643 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2644 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2646 /* Renumber registers for known formats (stabs and dwarf2). */
2647 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2648 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2650 /* We provide our own function to get register information. */
2651 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2652 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2654 /* To call functions from GDB using dummy frame */
2655 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2657 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2659 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2661 /* Advance PC across any prologue instructions to reach "real" code. */
2662 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2664 /* Stack grows downward. */
2665 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2667 /* Set breakpoints. */
2668 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2670 /* After breakpoint instruction or illegal instruction, pc still
2671 points at break instruction, so don't decrement. */
2672 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2674 /* We don't skip args. */
2675 set_gdbarch_frame_args_skip (gdbarch, 0);
2677 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2679 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2681 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
2683 /* Frame handling. */
2684 frame_base_set_default (gdbarch, &xtensa_frame_base);
2685 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
2686 dwarf2_append_unwinders (gdbarch);
2688 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2690 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2692 xtensa_add_reggroups (gdbarch);
2693 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2695 set_gdbarch_regset_from_core_section (gdbarch,
2696 xtensa_regset_from_core_section);
2698 set_solib_svr4_fetch_link_map_offsets
2699 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
2705 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2707 error (_("xtensa_dump_tdep(): not implemented"));
2710 /* Provide a prototype to silence -Wmissing-prototypes. */
2711 extern initialize_file_ftype _initialize_xtensa_tdep;
2714 _initialize_xtensa_tdep (void)
2716 struct cmd_list_element *c;
2718 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2719 xtensa_init_reggroups ();
2721 add_setshow_zinteger_cmd ("xtensa",
2723 &xtensa_debug_level, _("\
2724 Set Xtensa debugging."), _("\
2725 Show Xtensa debugging."), _("\
2726 When non-zero, Xtensa-specific debugging is enabled. \
2727 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2730 &setdebuglist, &showdebuglist);