1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* ABI-independent macros. */
95 #define ARG_NOF(gdbarch) \
96 (gdbarch_tdep (gdbarch)->call_abi \
97 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
98 #define ARG_1ST(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
100 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
101 : (gdbarch_tdep (gdbarch)->a0_base + 6))
103 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
104 indicates that the instruction is an ENTRY instruction. */
106 #define XTENSA_IS_ENTRY(gdbarch, op1) \
107 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
108 ? ((op1) == 0x6c) : ((op1) == 0x36))
110 #define XTENSA_ENTRY_LENGTH 3
112 /* windowing_enabled() returns true, if windowing is enabled.
113 WOE must be set to 1; EXCM to 0.
114 Note: We assume that EXCM is always 0 for XEA1. */
116 #define PS_WOE (1<<18)
117 #define PS_EXC (1<<4)
119 /* Convert a live A-register number to the corresponding AR-register number. */
121 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
123 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
126 arreg = a_regnum - tdep->a0_base;
127 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
128 arreg &= tdep->num_aregs - 1;
130 return arreg + tdep->ar_base;
133 /* Convert a live AR-register number to the corresponding A-register order
134 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
136 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
141 areg = ar_regnum - tdep->ar_base;
142 if (areg < 0 || areg >= tdep->num_aregs)
144 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
145 return (areg > 15) ? -1 : areg;
149 windowing_enabled (CORE_ADDR ps)
151 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
154 /* Return the window size of the previous call to the function from which we
157 This function is used to extract the return value after a called function
158 has returned to the caller. On Xtensa, the register that holds the return
159 value (from the perspective of the caller) depends on what call
160 instruction was used. For now, we are assuming that the call instruction
161 precedes the current address, so we simply analyze the call instruction.
162 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
163 method to call the inferior function. */
166 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
168 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
173 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
175 /* Read the previous instruction (should be a call[x]{4|8|12}. */
176 read_memory (pc-3, buf, 3);
177 insn = extract_unsigned_integer (buf, 3, byte_order);
179 /* Decode call instruction:
181 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
182 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
184 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
185 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
187 if (byte_order == BFD_ENDIAN_LITTLE)
189 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
190 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
194 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
195 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
201 /* REGISTER INFORMATION */
203 /* Returns the name of a register. */
205 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
207 /* Return the name stored in the register map. */
208 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
209 + gdbarch_num_pseudo_regs (gdbarch))
210 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
212 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
216 /* Return the type of a register. Create a new type, if necessary. */
219 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
221 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
223 /* Return signed integer for ARx and Ax registers. */
224 if ((regnum >= tdep->ar_base
225 && regnum < tdep->ar_base + tdep->num_aregs)
226 || (regnum >= tdep->a0_base
227 && regnum < tdep->a0_base + 16))
228 return builtin_type (gdbarch)->builtin_int;
230 if (regnum == gdbarch_pc_regnum (gdbarch)
231 || regnum == tdep->a0_base + 1)
232 return builtin_type (gdbarch)->builtin_data_ptr;
234 /* Return the stored type for all other registers. */
235 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
236 + gdbarch_num_pseudo_regs (gdbarch))
238 xtensa_register_t* reg = &tdep->regmap[regnum];
240 /* Set ctype for this register (only the first time). */
244 struct ctype_cache *tp;
245 int size = reg->byte_size;
247 /* We always use the memory representation,
248 even if the register width is smaller. */
252 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
256 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
260 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
264 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
268 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
272 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
273 if (tp->size == size)
278 char *name = xmalloc (16);
279 tp = xmalloc (sizeof (struct ctype_cache));
280 tp->next = tdep->type_entries;
281 tdep->type_entries = tp;
284 sprintf (name, "int%d", size * 8);
286 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
289 reg->ctype = tp->virtual_type;
295 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
300 /* Return the 'local' register number for stubs, dwarf2, etc.
301 The debugging information enumerates registers starting from 0 for A0
302 to n for An. So, we only have to add the base number for A0. */
305 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
309 if (regnum >= 0 && regnum < 16)
310 return gdbarch_tdep (gdbarch)->a0_base + regnum;
313 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
315 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
318 internal_error (__FILE__, __LINE__,
319 _("invalid dwarf/stabs register number %d"), regnum);
324 /* Write the bits of a masked register to the various registers.
325 Only the masked areas of these registers are modified; the other
326 fields are untouched. The size of masked registers is always less
327 than or equal to 32 bits. */
330 xtensa_register_write_masked (struct regcache *regcache,
331 xtensa_register_t *reg, const gdb_byte *buffer)
333 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
334 const xtensa_mask_t *mask = reg->mask;
336 int shift = 0; /* Shift for next mask (mod 32). */
337 int start, size; /* Start bit and size of current mask. */
339 unsigned int *ptr = value;
340 unsigned int regval, m, mem = 0;
342 int bytesize = reg->byte_size;
343 int bitsize = bytesize * 8;
346 DEBUGTRACE ("xtensa_register_write_masked ()\n");
348 /* Copy the masked register to host byte-order. */
349 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
350 for (i = 0; i < bytesize; i++)
353 mem |= (buffer[bytesize - i - 1] << 24);
358 for (i = 0; i < bytesize; i++)
361 mem |= (buffer[i] << 24);
366 /* We might have to shift the final value:
367 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
368 bytesize & 3 == x -> shift (4-x) * 8. */
370 *ptr = mem >> (((0 - bytesize) & 3) * 8);
374 /* Write the bits to the masked areas of the other registers. */
375 for (i = 0; i < mask->count; i++)
377 start = mask->mask[i].bit_start;
378 size = mask->mask[i].bit_size;
379 regval = mem >> shift;
381 if ((shift += size) > bitsize)
382 error (_("size of all masks is larger than the register"));
391 regval |= mem << (size - shift);
394 /* Make sure we have a valid register. */
395 r = mask->mask[i].reg_num;
396 if (r >= 0 && size > 0)
398 /* Don't overwrite the unmasked areas. */
400 regcache_cooked_read_unsigned (regcache, r, &old_val);
401 m = 0xffffffff >> (32 - size) << start;
403 regval = (regval & m) | (old_val & ~m);
404 regcache_cooked_write_unsigned (regcache, r, regval);
410 /* Read a tie state or mapped registers. Read the masked areas
411 of the registers and assemble them into a single value. */
414 xtensa_register_read_masked (struct regcache *regcache,
415 xtensa_register_t *reg, gdb_byte *buffer)
417 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
418 const xtensa_mask_t *mask = reg->mask;
423 unsigned int *ptr = value;
424 unsigned int regval, mem = 0;
426 int bytesize = reg->byte_size;
427 int bitsize = bytesize * 8;
430 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
431 reg->name == 0 ? "" : reg->name);
433 /* Assemble the register from the masked areas of other registers. */
434 for (i = 0; i < mask->count; i++)
436 int r = mask->mask[i].reg_num;
440 regcache_cooked_read_unsigned (regcache, r, &val);
441 regval = (unsigned int) val;
446 start = mask->mask[i].bit_start;
447 size = mask->mask[i].bit_size;
452 regval &= (0xffffffff >> (32 - size));
454 mem |= regval << shift;
456 if ((shift += size) > bitsize)
457 error (_("size of all masks is larger than the register"));
468 mem = regval >> (size - shift);
475 /* Copy value to target byte order. */
479 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
480 for (i = 0; i < bytesize; i++)
484 buffer[bytesize - i - 1] = mem & 0xff;
488 for (i = 0; i < bytesize; i++)
492 buffer[i] = mem & 0xff;
498 /* Read pseudo registers. */
501 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
502 struct regcache *regcache,
506 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
508 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
509 regnum, xtensa_register_name (gdbarch, regnum));
511 if (regnum == gdbarch_num_regs (gdbarch)
512 + gdbarch_num_pseudo_regs (gdbarch) - 1)
513 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
515 /* Read aliases a0..a15, if this is a Windowed ABI. */
516 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
517 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
518 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
520 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
522 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
523 regnum = arreg_number (gdbarch, regnum,
524 extract_unsigned_integer (buf, 4, byte_order));
527 /* We can always read non-pseudo registers. */
528 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
529 regcache_raw_read (regcache, regnum, buffer);
532 /* We have to find out how to deal with priveleged registers.
533 Let's treat them as pseudo-registers, but we cannot read/write them. */
535 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
537 buffer[0] = (gdb_byte)0;
538 buffer[1] = (gdb_byte)0;
539 buffer[2] = (gdb_byte)0;
540 buffer[3] = (gdb_byte)0;
542 /* Pseudo registers. */
544 && regnum < gdbarch_num_regs (gdbarch)
545 + gdbarch_num_pseudo_regs (gdbarch))
547 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
548 xtensa_register_type_t type = reg->type;
549 int flags = gdbarch_tdep (gdbarch)->target_flags;
551 /* We cannot read Unknown or Unmapped registers. */
552 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
554 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
556 warning (_("cannot read register %s"),
557 xtensa_register_name (gdbarch, regnum));
562 /* Some targets cannot read TIE register files. */
563 else if (type == xtRegisterTypeTieRegfile)
565 /* Use 'fetch' to get register? */
566 if (flags & xtTargetFlagsUseFetchStore)
568 warning (_("cannot read register"));
572 /* On some targets (esp. simulators), we can always read the reg. */
573 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
575 warning (_("cannot read register"));
580 /* We can always read mapped registers. */
581 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
583 xtensa_register_read_masked (regcache, reg, buffer);
587 /* Assume that we can read the register. */
588 regcache_raw_read (regcache, regnum, buffer);
591 internal_error (__FILE__, __LINE__,
592 _("invalid register number %d"), regnum);
596 /* Write pseudo registers. */
599 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
600 struct regcache *regcache,
602 const gdb_byte *buffer)
604 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
606 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
607 regnum, xtensa_register_name (gdbarch, regnum));
609 if (regnum == gdbarch_num_regs (gdbarch)
610 + gdbarch_num_pseudo_regs (gdbarch) -1)
611 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
613 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
614 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
615 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
616 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
618 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
621 regcache_raw_read (regcache,
622 gdbarch_tdep (gdbarch)->wb_regnum, buf);
623 regnum = arreg_number (gdbarch, regnum,
624 extract_unsigned_integer (buf, 4, byte_order));
627 /* We can always write 'core' registers.
628 Note: We might have converted Ax->ARy. */
629 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
630 regcache_raw_write (regcache, regnum, buffer);
632 /* We have to find out how to deal with priveleged registers.
633 Let's treat them as pseudo-registers, but we cannot read/write them. */
635 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
639 /* Pseudo registers. */
641 && regnum < gdbarch_num_regs (gdbarch)
642 + gdbarch_num_pseudo_regs (gdbarch))
644 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
645 xtensa_register_type_t type = reg->type;
646 int flags = gdbarch_tdep (gdbarch)->target_flags;
648 /* On most targets, we cannot write registers
649 of type "Unknown" or "Unmapped". */
650 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
652 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
654 warning (_("cannot write register %s"),
655 xtensa_register_name (gdbarch, regnum));
660 /* Some targets cannot read TIE register files. */
661 else if (type == xtRegisterTypeTieRegfile)
663 /* Use 'store' to get register? */
664 if (flags & xtTargetFlagsUseFetchStore)
666 warning (_("cannot write register"));
670 /* On some targets (esp. simulators), we can always write
672 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
674 warning (_("cannot write register"));
679 /* We can always write mapped registers. */
680 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
682 xtensa_register_write_masked (regcache, reg, buffer);
686 /* Assume that we can write the register. */
687 regcache_raw_write (regcache, regnum, buffer);
690 internal_error (__FILE__, __LINE__,
691 _("invalid register number %d"), regnum);
694 static struct reggroup *xtensa_ar_reggroup;
695 static struct reggroup *xtensa_user_reggroup;
696 static struct reggroup *xtensa_vectra_reggroup;
697 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
700 xtensa_init_reggroups (void)
702 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
703 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
704 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
706 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
707 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
708 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
709 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
710 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
711 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
712 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
713 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
717 xtensa_add_reggroups (struct gdbarch *gdbarch)
721 /* Predefined groups. */
722 reggroup_add (gdbarch, all_reggroup);
723 reggroup_add (gdbarch, save_reggroup);
724 reggroup_add (gdbarch, restore_reggroup);
725 reggroup_add (gdbarch, system_reggroup);
726 reggroup_add (gdbarch, vector_reggroup);
727 reggroup_add (gdbarch, general_reggroup);
728 reggroup_add (gdbarch, float_reggroup);
730 /* Xtensa-specific groups. */
731 reggroup_add (gdbarch, xtensa_ar_reggroup);
732 reggroup_add (gdbarch, xtensa_user_reggroup);
733 reggroup_add (gdbarch, xtensa_vectra_reggroup);
735 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
736 reggroup_add (gdbarch, xtensa_cp[i]);
740 xtensa_coprocessor_register_group (struct reggroup *group)
744 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
745 if (group == xtensa_cp[i])
751 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
752 | XTENSA_REGISTER_FLAGS_WRITABLE \
753 | XTENSA_REGISTER_FLAGS_VOLATILE)
755 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
756 | XTENSA_REGISTER_FLAGS_WRITABLE)
759 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
761 struct reggroup *group)
763 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
764 xtensa_register_type_t type = reg->type;
765 xtensa_register_group_t rg = reg->group;
768 /* First, skip registers that are not visible to this target
769 (unknown and unmapped registers when not using ISS). */
771 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
773 if (group == all_reggroup)
775 if (group == xtensa_ar_reggroup)
776 return rg & xtRegisterGroupAddrReg;
777 if (group == xtensa_user_reggroup)
778 return rg & xtRegisterGroupUser;
779 if (group == float_reggroup)
780 return rg & xtRegisterGroupFloat;
781 if (group == general_reggroup)
782 return rg & xtRegisterGroupGeneral;
783 if (group == float_reggroup)
784 return rg & xtRegisterGroupFloat;
785 if (group == system_reggroup)
786 return rg & xtRegisterGroupState;
787 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
788 return rg & xtRegisterGroupVectra;
789 if (group == save_reggroup || group == restore_reggroup)
790 return (regnum < gdbarch_num_regs (gdbarch)
791 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
792 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
793 return rg & (xtRegisterGroupCP0 << cp_number);
799 /* Supply register REGNUM from the buffer specified by GREGS and LEN
800 in the general-purpose register set REGSET to register cache
801 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
804 xtensa_supply_gregset (const struct regset *regset,
810 const xtensa_elf_gregset_t *regs = gregs;
811 struct gdbarch *gdbarch = get_regcache_arch (rc);
814 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
816 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
817 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
818 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
819 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
820 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
821 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
822 (char *) ®s->windowbase);
823 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
824 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
825 (char *) ®s->windowstart);
826 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
827 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
828 (char *) ®s->lbeg);
829 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
830 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
831 (char *) ®s->lend);
832 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
833 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
834 (char *) ®s->lcount);
835 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
836 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
837 (char *) ®s->sar);
838 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
839 && regnum < gdbarch_tdep (gdbarch)->ar_base
840 + gdbarch_tdep (gdbarch)->num_aregs)
841 regcache_raw_supply (rc, regnum,
842 (char *) ®s->ar[regnum - gdbarch_tdep
843 (gdbarch)->ar_base]);
844 else if (regnum == -1)
846 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
847 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
848 (char *) ®s->ar[i]);
853 /* Xtensa register set. */
859 xtensa_supply_gregset
863 /* Return the appropriate register set for the core
864 section identified by SECT_NAME and SECT_SIZE. */
866 static const struct regset *
867 xtensa_regset_from_core_section (struct gdbarch *core_arch,
868 const char *sect_name,
871 DEBUGTRACE ("xtensa_regset_from_core_section "
872 "(..., sect_name==\"%s\", sect_size==%x)\n",
873 sect_name, (unsigned int) sect_size);
875 if (strcmp (sect_name, ".reg") == 0
876 && sect_size >= sizeof(xtensa_elf_gregset_t))
877 return &xtensa_gregset;
883 /* Handling frames. */
885 /* Number of registers to save in case of Windowed ABI. */
886 #define XTENSA_NUM_SAVED_AREGS 12
888 /* Frame cache part for Windowed ABI. */
889 typedef struct xtensa_windowed_frame_cache
891 int wb; /* WINDOWBASE of the previous frame. */
892 int callsize; /* Call size of this frame. */
893 int ws; /* WINDOWSTART of the previous frame. It keeps track of
894 life windows only. If there is no bit set for the
895 window, that means it had been already spilled
896 because of window overflow. */
898 /* Spilled A-registers from the previous frame.
899 AREGS[i] == -1, if corresponding AR is alive. */
900 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
901 } xtensa_windowed_frame_cache_t;
903 /* Call0 ABI Definitions. */
905 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
906 #define C0_NREGS 16 /* Number of A-registers to track. */
907 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
908 #define C0_SP 1 /* Register used as SP. */
909 #define C0_FP 15 /* Register used as FP. */
910 #define C0_RA 0 /* Register used as return address. */
911 #define C0_ARGS 2 /* Register used as first arg/retval. */
912 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
914 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
915 A-register where the current content of the reg came from (in terms
916 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
917 mean that the orignal content of the register was saved to the stack.
918 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
919 know where SP will end up until the entire prologue has been analyzed. */
921 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
922 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
923 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
925 extern xtensa_isa xtensa_default_isa;
927 typedef struct xtensa_c0reg
929 int fr_reg; /* original register from which register content
930 is derived, or C0_CONST, or C0_INEXP. */
931 int fr_ofs; /* constant offset from reg, or immediate value. */
932 int to_stk; /* offset from original SP to register (4-byte aligned),
933 or C0_NOSTK if register has not been saved. */
937 /* Frame cache part for Call0 ABI. */
938 typedef struct xtensa_call0_frame_cache
940 int c0_frmsz; /* Stack frame size. */
941 int c0_hasfp; /* Current frame uses frame pointer. */
942 int fp_regnum; /* A-register used as FP. */
943 int c0_fp; /* Actual value of frame pointer. */
944 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
945 } xtensa_call0_frame_cache_t;
947 typedef struct xtensa_frame_cache
949 CORE_ADDR base; /* Stack pointer of this frame. */
950 CORE_ADDR pc; /* PC at the entry point to the function. */
951 CORE_ADDR ra; /* The raw return address (without CALLINC). */
952 CORE_ADDR ps; /* The PS register of this frame. */
953 CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
954 int call0; /* It's a call0 framework (else windowed). */
957 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
958 xtensa_call0_frame_cache_t c0; /* call0 == true. */
960 } xtensa_frame_cache_t;
963 static struct xtensa_frame_cache *
964 xtensa_alloc_frame_cache (int windowed)
966 xtensa_frame_cache_t *cache;
969 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
971 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
978 cache->call0 = !windowed;
981 cache->c0.c0_frmsz = -1;
982 cache->c0.c0_hasfp = 0;
983 cache->c0.fp_regnum = -1;
984 cache->c0.c0_fp = -1;
986 for (i = 0; i < C0_NREGS; i++)
988 cache->c0.c0_rt[i].fr_reg = i;
989 cache->c0.c0_rt[i].fr_ofs = 0;
990 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
997 cache->wd.callsize = -1;
999 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1000 cache->wd.aregs[i] = -1;
1007 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1009 return address & ~15;
1014 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1019 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1020 host_address_to_string (next_frame));
1022 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1023 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1025 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1031 static struct frame_id
1032 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1036 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1038 pc = get_frame_pc (this_frame);
1039 fp = get_frame_register_unsigned
1040 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1042 /* Make dummy frame ID unique by adding a constant. */
1043 return frame_id_build (fp + SP_ALIGNMENT, pc);
1046 /* Returns the best guess about which register is a frame pointer
1047 for the function containing CURRENT_PC. */
1049 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1050 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1053 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1055 #define RETURN_FP goto done
1057 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1058 CORE_ADDR start_addr;
1060 xtensa_insnbuf ins, slot;
1061 char ibuf[XTENSA_ISA_BSZ];
1062 CORE_ADDR ia, bt, ba;
1064 int ilen, islots, is;
1066 const char *opcname;
1068 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1069 if (start_addr == 0)
1072 if (!xtensa_default_isa)
1073 xtensa_default_isa = xtensa_isa_init (0, 0);
1074 isa = xtensa_default_isa;
1075 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1076 ins = xtensa_insnbuf_alloc (isa);
1077 slot = xtensa_insnbuf_alloc (isa);
1080 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1082 if (ia + xtensa_isa_maxlength (isa) > bt)
1085 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1086 ? ba + XTENSA_ISA_BSZ : current_pc;
1087 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1091 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1092 ifmt = xtensa_format_decode (isa, ins);
1093 if (ifmt == XTENSA_UNDEFINED)
1095 ilen = xtensa_format_length (isa, ifmt);
1096 if (ilen == XTENSA_UNDEFINED)
1098 islots = xtensa_format_num_slots (isa, ifmt);
1099 if (islots == XTENSA_UNDEFINED)
1102 for (is = 0; is < islots; ++is)
1104 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1107 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1108 if (opc == XTENSA_UNDEFINED)
1111 opcname = xtensa_opcode_name (isa, opc);
1113 if (strcasecmp (opcname, "mov.n") == 0
1114 || strcasecmp (opcname, "or") == 0)
1116 unsigned int register_operand;
1118 /* Possible candidate for setting frame pointer
1119 from A1. This is what we are looking for. */
1121 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1122 is, slot, ®ister_operand) != 0)
1124 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1126 if (register_operand == 1) /* Mov{.n} FP A1. */
1128 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1129 ®ister_operand) != 0)
1131 if (xtensa_operand_decode (isa, opc, 0,
1132 ®ister_operand) != 0)
1135 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1141 /* We have problems decoding the memory. */
1143 || strcasecmp (opcname, "ill") == 0
1144 || strcasecmp (opcname, "ill.n") == 0
1145 /* Hit planted breakpoint. */
1146 || strcasecmp (opcname, "break") == 0
1147 || strcasecmp (opcname, "break.n") == 0
1148 /* Flow control instructions finish prologue. */
1149 || xtensa_opcode_is_branch (isa, opc) > 0
1150 || xtensa_opcode_is_jump (isa, opc) > 0
1151 || xtensa_opcode_is_loop (isa, opc) > 0
1152 || xtensa_opcode_is_call (isa, opc) > 0
1153 || strcasecmp (opcname, "simcall") == 0
1154 || strcasecmp (opcname, "syscall") == 0)
1155 /* Can not continue analysis. */
1160 xtensa_insnbuf_free(isa, slot);
1161 xtensa_insnbuf_free(isa, ins);
1165 /* The key values to identify the frame using "cache" are
1167 cache->base = SP (or best guess about FP) of this frame;
1168 cache->pc = entry-PC (entry point of the frame function);
1169 cache->prev_sp = SP of the previous frame.
1173 call0_frame_cache (struct frame_info *this_frame,
1174 xtensa_frame_cache_t *cache,
1175 CORE_ADDR pc, CORE_ADDR litbase);
1177 static struct xtensa_frame_cache *
1178 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1180 xtensa_frame_cache_t *cache;
1181 CORE_ADDR ra, wb, ws, pc, sp, ps;
1182 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1183 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1184 unsigned int fp_regnum;
1191 ps = get_frame_register_unsigned (this_frame, gdbarch_ps_regnum (gdbarch));
1192 windowed = windowing_enabled (ps);
1194 /* Get pristine xtensa-frame. */
1195 cache = xtensa_alloc_frame_cache (windowed);
1196 *this_cache = cache;
1198 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1202 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1203 wb = get_frame_register_unsigned (this_frame,
1204 gdbarch_tdep (gdbarch)->wb_regnum);
1205 ws = get_frame_register_unsigned (this_frame,
1206 gdbarch_tdep (gdbarch)->ws_regnum);
1208 op1 = read_memory_integer (pc, 1, byte_order);
1209 if (XTENSA_IS_ENTRY (gdbarch, op1))
1211 int callinc = CALLINC (ps);
1212 ra = get_frame_register_unsigned
1213 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1215 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1216 cache->wd.callsize = 0;
1219 cache->prev_sp = get_frame_register_unsigned
1220 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1222 /* This only can be the outermost frame since we are
1223 just about to execute ENTRY. SP hasn't been set yet.
1224 We can assume any frame size, because it does not
1225 matter, and, let's fake frame base in cache. */
1226 cache->base = cache->prev_sp + 16;
1229 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1230 cache->ps = (ps & ~PS_CALLINC_MASK)
1231 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1237 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1238 ra = get_frame_register_unsigned (this_frame,
1239 gdbarch_tdep (gdbarch)->a0_base);
1240 cache->wd.callsize = WINSIZE (ra);
1241 cache->wd.wb = (wb - cache->wd.callsize / 4)
1242 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1243 cache->wd.ws = ws & ~(1 << wb);
1245 cache->pc = get_frame_func (this_frame);
1246 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1247 cache->ps = (ps & ~PS_CALLINC_MASK)
1248 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1251 if (cache->wd.ws == 0)
1256 sp = get_frame_register_unsigned
1257 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1259 for (i = 0; i < 4; i++, sp += 4)
1261 cache->wd.aregs[i] = sp;
1264 if (cache->wd.callsize > 4)
1266 /* Set A4...A7/A11. */
1267 /* Get the SP of the frame previous to the previous one.
1268 To achieve this, we have to dereference SP twice. */
1269 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1270 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1271 sp -= cache->wd.callsize * 4;
1273 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1275 cache->wd.aregs[i] = sp;
1280 if ((cache->prev_sp == 0) && ( ra != 0 ))
1281 /* If RA is equal to 0 this frame is an outermost frame. Leave
1282 cache->prev_sp unchanged marking the boundary of the frame stack. */
1284 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1286 /* Register window overflow already happened.
1287 We can read caller's SP from the proper spill loction. */
1288 sp = get_frame_register_unsigned
1289 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1290 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1294 /* Read caller's frame SP directly from the previous window. */
1295 int regnum = arreg_number
1296 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1299 cache->prev_sp = get_frame_register_unsigned (this_frame, regnum);
1303 else /* Call0 framework. */
1305 unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
1306 CORE_ADDR litbase = (litbase_regnum == -1)
1307 ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
1309 call0_frame_cache (this_frame, cache, pc, litbase);
1310 fp_regnum = cache->c0.fp_regnum;
1313 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1319 xtensa_frame_this_id (struct frame_info *this_frame,
1321 struct frame_id *this_id)
1323 struct xtensa_frame_cache *cache =
1324 xtensa_frame_cache (this_frame, this_cache);
1326 if (cache->prev_sp == 0)
1329 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1332 static struct value *
1333 xtensa_frame_prev_register (struct frame_info *this_frame,
1337 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1338 struct xtensa_frame_cache *cache;
1339 ULONGEST saved_reg = 0;
1342 if (*this_cache == NULL)
1343 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1344 cache = *this_cache;
1346 if (regnum ==gdbarch_pc_regnum (gdbarch))
1347 saved_reg = cache->ra;
1348 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1349 saved_reg = cache->prev_sp;
1350 else if (!cache->call0)
1352 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1353 saved_reg = cache->wd.ws;
1354 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1355 saved_reg = cache->wd.wb;
1356 else if (regnum == gdbarch_ps_regnum (gdbarch))
1357 saved_reg = cache->ps;
1365 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1367 if (!cache->call0) /* Windowed ABI. */
1369 /* Convert A-register numbers to AR-register numbers,
1370 if we deal with A-register. */
1371 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1372 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1373 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1375 /* Check, if we deal with AR-register saved on stack. */
1376 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1377 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1378 + gdbarch_tdep (gdbarch)->num_aregs))
1380 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1383 && areg < XTENSA_NUM_SAVED_AREGS
1384 && cache->wd.aregs[areg] != -1)
1385 return frame_unwind_got_memory (this_frame, regnum,
1386 cache->wd.aregs[areg]);
1389 else /* Call0 ABI. */
1391 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1392 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1394 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1401 /* If register was saved in the prologue, retrieve it. */
1402 stkofs = cache->c0.c0_rt[reg].to_stk;
1403 if (stkofs != C0_NOSTK)
1405 /* Determine SP on entry based on FP. */
1406 spe = cache->c0.c0_fp
1407 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1409 return frame_unwind_got_memory (this_frame, regnum, spe + stkofs);
1414 /* All other registers have been either saved to
1415 the stack or are still alive in the processor. */
1417 return frame_unwind_got_register (this_frame, regnum, regnum);
1421 static const struct frame_unwind
1425 xtensa_frame_this_id,
1426 xtensa_frame_prev_register,
1428 default_frame_sniffer
1432 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1434 struct xtensa_frame_cache *cache =
1435 xtensa_frame_cache (this_frame, this_cache);
1440 static const struct frame_base
1444 xtensa_frame_base_address,
1445 xtensa_frame_base_address,
1446 xtensa_frame_base_address
1451 xtensa_extract_return_value (struct type *type,
1452 struct regcache *regcache,
1455 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1456 bfd_byte *valbuf = dst;
1457 int len = TYPE_LENGTH (type);
1462 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1464 gdb_assert(len > 0);
1466 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1468 /* First, we have to find the caller window in the register file. */
1469 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1470 callsize = extract_call_winsize (gdbarch, pc);
1472 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1473 if (len > (callsize > 8 ? 8 : 16))
1474 internal_error (__FILE__, __LINE__,
1475 _("cannot extract return value of %d bytes long"), len);
1477 /* Get the register offset of the return
1478 register (A2) in the caller window. */
1479 regcache_raw_read_unsigned
1480 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1481 areg = arreg_number (gdbarch,
1482 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1486 /* No windowing hardware - Call0 ABI. */
1487 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1490 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1492 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1495 for (; len > 0; len -= 4, areg++, valbuf += 4)
1498 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1500 regcache_raw_read (regcache, areg, valbuf);
1506 xtensa_store_return_value (struct type *type,
1507 struct regcache *regcache,
1510 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1511 const bfd_byte *valbuf = dst;
1515 int len = TYPE_LENGTH (type);
1518 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1520 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1522 regcache_raw_read_unsigned
1523 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1524 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1525 callsize = extract_call_winsize (gdbarch, pc);
1527 if (len > (callsize > 8 ? 8 : 16))
1528 internal_error (__FILE__, __LINE__,
1529 _("unimplemented for this length: %d"),
1530 TYPE_LENGTH (type));
1531 areg = arreg_number (gdbarch,
1532 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1534 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1535 callsize, (int) wb);
1539 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1542 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1545 for (; len > 0; len -= 4, areg++, valbuf += 4)
1548 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1550 regcache_raw_write (regcache, areg, valbuf);
1555 static enum return_value_convention
1556 xtensa_return_value (struct gdbarch *gdbarch,
1557 struct type *func_type,
1558 struct type *valtype,
1559 struct regcache *regcache,
1561 const gdb_byte *writebuf)
1563 /* Structures up to 16 bytes are returned in registers. */
1565 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1566 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1567 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1568 && TYPE_LENGTH (valtype) > 16);
1571 return RETURN_VALUE_STRUCT_CONVENTION;
1573 DEBUGTRACE ("xtensa_return_value(...)\n");
1575 if (writebuf != NULL)
1577 xtensa_store_return_value (valtype, regcache, writebuf);
1580 if (readbuf != NULL)
1582 gdb_assert (!struct_return);
1583 xtensa_extract_return_value (valtype, regcache, readbuf);
1585 return RETURN_VALUE_REGISTER_CONVENTION;
1592 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1593 struct value *function,
1594 struct regcache *regcache,
1597 struct value **args,
1600 CORE_ADDR struct_addr)
1602 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1604 int size, onstack_size;
1605 gdb_byte *buf = (gdb_byte *) alloca (16);
1607 struct argument_info
1609 const bfd_byte *contents;
1611 int onstack; /* onstack == 0 => in reg */
1612 int align; /* alignment */
1615 int offset; /* stack offset if on stack */
1616 int regno; /* regno if in register */
1620 struct argument_info *arg_info =
1621 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1625 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1627 if (xtensa_debug_level > 3)
1630 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1631 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1632 "struct_addr=0x%x\n",
1633 (int) sp, (int) struct_return, (int) struct_addr);
1635 for (i = 0; i < nargs; i++)
1637 struct value *arg = args[i];
1638 struct type *arg_type = check_typedef (value_type (arg));
1639 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
1640 i, (unsigned long) arg, TYPE_LENGTH (arg_type));
1641 switch (TYPE_CODE (arg_type))
1644 fprintf_unfiltered (gdb_stdlog, "int");
1646 case TYPE_CODE_STRUCT:
1647 fprintf_unfiltered (gdb_stdlog, "struct");
1650 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1653 fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
1654 (unsigned long) value_contents (arg));
1658 /* First loop: collect information.
1659 Cast into type_long. (This shouldn't happen often for C because
1660 GDB already does this earlier.) It's possible that GDB could
1661 do it all the time but it's harmless to leave this code here. */
1668 size = REGISTER_SIZE;
1670 for (i = 0; i < nargs; i++)
1672 struct argument_info *info = &arg_info[i];
1673 struct value *arg = args[i];
1674 struct type *arg_type = check_typedef (value_type (arg));
1676 switch (TYPE_CODE (arg_type))
1679 case TYPE_CODE_BOOL:
1680 case TYPE_CODE_CHAR:
1681 case TYPE_CODE_RANGE:
1682 case TYPE_CODE_ENUM:
1684 /* Cast argument to long if necessary as the mask does it too. */
1685 if (TYPE_LENGTH (arg_type)
1686 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1688 arg_type = builtin_type (gdbarch)->builtin_long;
1689 arg = value_cast (arg_type, arg);
1691 /* Aligment is equal to the type length for the basic types. */
1692 info->align = TYPE_LENGTH (arg_type);
1697 /* Align doubles correctly. */
1698 if (TYPE_LENGTH (arg_type)
1699 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1700 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1702 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1705 case TYPE_CODE_STRUCT:
1707 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1710 info->length = TYPE_LENGTH (arg_type);
1711 info->contents = value_contents (arg);
1713 /* Align size and onstack_size. */
1714 size = (size + info->align - 1) & ~(info->align - 1);
1715 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1717 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1720 info->u.offset = onstack_size;
1721 onstack_size += info->length;
1726 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1728 size += info->length;
1731 /* Adjust the stack pointer and align it. */
1732 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1734 /* Simulate MOVSP, if Windowed ABI. */
1735 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1738 read_memory (osp - 16, buf, 16);
1739 write_memory (sp - 16, buf, 16);
1742 /* Second Loop: Load arguments. */
1746 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1747 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1750 for (i = 0; i < nargs; i++)
1752 struct argument_info *info = &arg_info[i];
1756 int n = info->length;
1757 CORE_ADDR offset = sp + info->u.offset;
1759 /* Odd-sized structs are aligned to the lower side of a memory
1760 word in big-endian mode and require a shift. This only
1761 applies for structures smaller than one word. */
1763 if (n < REGISTER_SIZE
1764 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1765 offset += (REGISTER_SIZE - n);
1767 write_memory (offset, info->contents, info->length);
1772 int n = info->length;
1773 const bfd_byte *cp = info->contents;
1774 int r = info->u.regno;
1776 /* Odd-sized structs are aligned to the lower side of registers in
1777 big-endian mode and require a shift. The odd-sized leftover will
1778 be at the end. Note that this is only true for structures smaller
1779 than REGISTER_SIZE; for larger odd-sized structures the excess
1780 will be left-aligned in the register on both endiannesses. */
1782 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1785 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1786 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1788 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1789 regcache_cooked_write (regcache, r, buf);
1791 cp += REGISTER_SIZE;
1798 regcache_cooked_write (regcache, r, cp);
1800 cp += REGISTER_SIZE;
1807 /* Set the return address of dummy frame to the dummy address.
1808 The return address for the current function (in A0) is
1809 saved in the dummy frame, so we can savely overwrite A0 here. */
1811 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1813 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1814 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
1815 ps = extract_unsigned_integer (buf, 4, byte_order) & ~0x00030000;
1816 regcache_cooked_write_unsigned
1817 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1818 regcache_cooked_write_unsigned (regcache,
1819 gdbarch_ps_regnum (gdbarch),
1822 /* All the registers have been saved. After executing
1823 dummy call, they all will be restored. So it's safe
1824 to modify WINDOWSTART register to make it look like there
1825 is only one register window corresponding to WINDOWEBASE. */
1827 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1828 regcache_cooked_write_unsigned
1829 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1830 1 << extract_unsigned_integer (buf, 4, byte_order));
1834 /* Simulate CALL0: write RA into A0 register. */
1835 regcache_cooked_write_unsigned
1836 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1839 /* Set new stack pointer and return it. */
1840 regcache_cooked_write_unsigned (regcache,
1841 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1842 /* Make dummy frame ID unique by adding a constant. */
1843 return sp + SP_ALIGNMENT;
1847 /* Return a breakpoint for the current location of PC. We always use
1848 the density version if we have density instructions (regardless of the
1849 current instruction at PC), and use regular instructions otherwise. */
1851 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1852 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1853 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1854 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1856 static const unsigned char *
1857 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1860 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1861 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1862 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1863 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1865 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1867 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1869 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1871 *lenptr = sizeof (density_big_breakpoint);
1872 return density_big_breakpoint;
1876 *lenptr = sizeof (density_little_breakpoint);
1877 return density_little_breakpoint;
1882 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1884 *lenptr = sizeof (big_breakpoint);
1885 return big_breakpoint;
1889 *lenptr = sizeof (little_breakpoint);
1890 return little_breakpoint;
1895 /* Call0 ABI support routines. */
1897 /* Call0 opcode class. Opcodes are preclassified according to what they
1898 mean for Call0 prologue analysis, and their number of significant operands.
1899 The purpose of this is to simplify prologue analysis by separating
1900 instruction decoding (libisa) from the semantics of prologue analysis. */
1903 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1904 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1905 c0opc_flow, /* Flow control insn. */
1906 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1907 c0opc_break, /* Debugger software breakpoints. */
1908 c0opc_add, /* Adding two registers. */
1909 c0opc_addi, /* Adding a register and an immediate. */
1910 c0opc_sub, /* Subtracting a register from a register. */
1911 c0opc_mov, /* Moving a register to a register. */
1912 c0opc_movi, /* Moving an immediate to a register. */
1913 c0opc_l32r, /* Loading a literal. */
1914 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1915 c0opc_NrOf /* Number of opcode classifications. */
1919 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1921 static xtensa_insn_kind
1922 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1924 const char *opcname;
1925 xtensa_insn_kind opclass = c0opc_uninteresting;
1927 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1929 /* Get opcode name and handle special classifications. */
1931 opcname = xtensa_opcode_name (isa, opc);
1934 || strcasecmp (opcname, "ill") == 0
1935 || strcasecmp (opcname, "ill.n") == 0)
1936 opclass = c0opc_illegal;
1937 else if (strcasecmp (opcname, "break") == 0
1938 || strcasecmp (opcname, "break.n") == 0)
1939 opclass = c0opc_break;
1940 else if (strcasecmp (opcname, "entry") == 0)
1941 opclass = c0opc_entry;
1942 else if (xtensa_opcode_is_branch (isa, opc) > 0
1943 || xtensa_opcode_is_jump (isa, opc) > 0
1944 || xtensa_opcode_is_loop (isa, opc) > 0
1945 || xtensa_opcode_is_call (isa, opc) > 0
1946 || strcasecmp (opcname, "simcall") == 0
1947 || strcasecmp (opcname, "syscall") == 0)
1948 opclass = c0opc_flow;
1950 /* Also, classify specific opcodes that need to be tracked. */
1951 else if (strcasecmp (opcname, "add") == 0
1952 || strcasecmp (opcname, "add.n") == 0)
1953 opclass = c0opc_add;
1954 else if (strcasecmp (opcname, "addi") == 0
1955 || strcasecmp (opcname, "addi.n") == 0
1956 || strcasecmp (opcname, "addmi") == 0)
1957 opclass = c0opc_addi;
1958 else if (strcasecmp (opcname, "sub") == 0)
1959 opclass = c0opc_sub;
1960 else if (strcasecmp (opcname, "mov.n") == 0
1961 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1962 opclass = c0opc_mov;
1963 else if (strcasecmp (opcname, "movi") == 0
1964 || strcasecmp (opcname, "movi.n") == 0)
1965 opclass = c0opc_movi;
1966 else if (strcasecmp (opcname, "l32r") == 0)
1967 opclass = c0opc_l32r;
1968 else if (strcasecmp (opcname, "s32i") == 0
1969 || strcasecmp (opcname, "s32i.n") == 0)
1970 opclass = c0opc_s32i;
1975 /* Tracks register movement/mutation for a given operation, which may
1976 be within a bundle. Updates the destination register tracking info
1977 accordingly. The pc is needed only for pc-relative load instructions
1978 (eg. l32r). The SP register number is needed to identify stores to
1982 call0_track_op (struct gdbarch *gdbarch,
1983 xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1984 xtensa_insn_kind opclass, int nods, unsigned odv[],
1985 CORE_ADDR pc, CORE_ADDR litbase, int spreg)
1987 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1988 unsigned litaddr, litval;
1993 /* 3 operands: dst, src, imm. */
1994 gdb_assert (nods == 3);
1995 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1996 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1999 /* 3 operands: dst, src1, src2. */
2000 gdb_assert (nods == 3);
2001 if (src[odv[1]].fr_reg == C0_CONST)
2003 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2004 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2006 else if (src[odv[2]].fr_reg == C0_CONST)
2008 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2009 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2011 else dst[odv[0]].fr_reg = C0_INEXP;
2014 /* 3 operands: dst, src1, src2. */
2015 gdb_assert (nods == 3);
2016 if (src[odv[2]].fr_reg == C0_CONST)
2018 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2019 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2021 else dst[odv[0]].fr_reg = C0_INEXP;
2024 /* 2 operands: dst, src [, src]. */
2025 gdb_assert (nods == 2);
2026 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2027 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2030 /* 2 operands: dst, imm. */
2031 gdb_assert (nods == 2);
2032 dst[odv[0]].fr_reg = C0_CONST;
2033 dst[odv[0]].fr_ofs = odv[1];
2036 /* 2 operands: dst, literal offset. */
2037 gdb_assert (nods == 2);
2038 litaddr = litbase & 1
2039 ? (litbase & ~1) + (signed)odv[1]
2040 : (pc + 3 + (signed)odv[1]) & ~3;
2041 litval = read_memory_integer (litaddr, 4, byte_order);
2042 dst[odv[0]].fr_reg = C0_CONST;
2043 dst[odv[0]].fr_ofs = litval;
2046 /* 3 operands: value, base, offset. */
2047 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2048 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2049 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2050 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2051 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2052 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2054 /* ISA encoding guarantees alignment. But, check it anyway. */
2055 gdb_assert ((odv[2] & 3) == 0);
2056 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2060 gdb_assert_not_reached ("unexpected instruction kind");
2064 /* Analyze prologue of the function at start address to determine if it uses
2065 the Call0 ABI, and if so track register moves and linear modifications
2066 in the prologue up to the PC or just beyond the prologue, whichever is first.
2067 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2068 The prologue may overlap non-prologue instructions but is guaranteed to end
2069 by the first flow-control instruction (jump, branch, call or return).
2070 Since an optimized function may move information around and change the
2071 stack frame arbitrarily during the prologue, the information is guaranteed
2072 valid only at the point in the function indicated by the PC.
2073 May be used to skip the prologue or identify the ABI, w/o tracking.
2075 Returns: Address of first instruction after prologue, or PC (whichever
2076 is first), or 0, if decoding failed (in libisa).
2078 start Start address of function/prologue.
2079 pc Program counter to stop at. Use 0 to continue to end of prologue.
2080 If 0, avoids infinite run-on in corrupt code memory by bounding
2081 the scan to the end of the function if that can be determined.
2082 nregs Number of general registers to track (size of rt[] array).
2084 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2085 If NULL, registers are not tracked.
2087 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2088 (more accurately, non-zero until 'entry' insn is encountered).
2090 Note that these may produce useful results even if decoding fails
2091 because they begin with default assumptions that analysis may change. */
2094 call0_analyze_prologue (struct gdbarch *gdbarch,
2095 CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
2096 int nregs, xtensa_c0reg_t rt[], int *call0)
2098 CORE_ADDR ia; /* Current insn address in prologue. */
2099 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2100 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2101 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2102 xtensa_isa isa; /* libisa ISA handle. */
2103 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2104 xtensa_format ifmt; /* libisa instruction format. */
2105 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2106 xtensa_opcode opc; /* Opcode in current slot. */
2107 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2108 int nods; /* Opcode number of operands. */
2109 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2110 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2111 int j; /* General loop counter. */
2112 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2113 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2114 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2116 struct symtab_and_line prologue_sal;
2118 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2119 (int)start, (int)pc);
2121 /* Try to limit the scan to the end of the function if a non-zero pc
2122 arg was not supplied to avoid probing beyond the end of valid memory.
2123 If memory is full of garbage that classifies as c0opc_uninteresting.
2124 If this fails (eg. if no symbols) pc ends up 0 as it was.
2125 Intialize the Call0 frame and register tracking info.
2126 Assume it's Call0 until an 'entry' instruction is encountered.
2127 Assume we may be in the prologue until we hit a flow control instr. */
2133 /* Find out, if we have an information about the prologue from DWARF. */
2134 prologue_sal = find_pc_line (start, 0);
2135 if (prologue_sal.line != 0) /* Found debug info. */
2136 body_pc = prologue_sal.end;
2138 /* If we are going to analyze the prologue in general without knowing about
2139 the current PC, make the best assumtion for the end of the prologue. */
2142 find_pc_partial_function (start, 0, NULL, &end_pc);
2143 body_pc = min (end_pc, body_pc);
2146 body_pc = min (pc, body_pc);
2153 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2154 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2158 if (!xtensa_default_isa)
2159 xtensa_default_isa = xtensa_isa_init (0, 0);
2160 isa = xtensa_default_isa;
2161 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2162 ins = xtensa_insnbuf_alloc (isa);
2163 slot = xtensa_insnbuf_alloc (isa);
2165 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2167 /* (Re)fill instruction buffer from memory if necessary, but do not
2168 read memory beyond PC to be sure we stay within text section
2169 (this protection only works if a non-zero pc is supplied). */
2171 if (ia + xtensa_isa_maxlength (isa) > bt)
2174 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2175 read_memory (ba, ibuf, bt - ba);
2176 /* If there is a memory reading error read_memory () will report it
2177 and then throw an exception, stopping command execution. */
2180 /* Decode format information. */
2182 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2183 ifmt = xtensa_format_decode (isa, ins);
2184 if (ifmt == XTENSA_UNDEFINED)
2189 ilen = xtensa_format_length (isa, ifmt);
2190 if (ilen == XTENSA_UNDEFINED)
2195 islots = xtensa_format_num_slots (isa, ifmt);
2196 if (islots == XTENSA_UNDEFINED)
2202 /* Analyze a bundle or a single instruction, using a snapshot of
2203 the register tracking info as input for the entire bundle so that
2204 register changes do not take effect within this bundle. */
2206 for (j = 0; j < nregs; ++j)
2209 for (is = 0; is < islots; ++is)
2211 /* Decode a slot and classify the opcode. */
2213 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2217 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2218 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2220 if (opc == XTENSA_UNDEFINED)
2221 opclass = c0opc_illegal;
2223 opclass = call0_classify_opcode (isa, opc);
2225 /* Decide whether to track this opcode, ignore it, or bail out. */
2234 case c0opc_uninteresting:
2243 ia += ilen; /* Skip over 'entry' insn. */
2251 /* Only expected opcodes should get this far. */
2255 /* Extract and decode the operands. */
2256 nods = xtensa_opcode_num_operands (isa, opc);
2257 if (nods == XTENSA_UNDEFINED)
2263 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2265 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2270 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2275 /* Check operands to verify use of 'mov' assembler macro. */
2276 if (opclass == c0opc_mov && nods == 3)
2278 if (odv[2] == odv[1])
2282 opclass = c0opc_uninteresting;
2287 /* Track register movement and modification for this operation. */
2288 call0_track_op (gdbarch, rt, rtmp, opclass,
2289 nods, odv, ia, litbase, 1);
2293 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2294 (unsigned)ia, fail ? "failed" : "succeeded");
2295 xtensa_insnbuf_free(isa, slot);
2296 xtensa_insnbuf_free(isa, ins);
2297 return fail ? XTENSA_ISA_BADPC : ia;
2300 /* Initialize frame cache for the current frame in CALL0 ABI. */
2303 call0_frame_cache (struct frame_info *this_frame,
2304 xtensa_frame_cache_t *cache, CORE_ADDR pc, CORE_ADDR litbase)
2306 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2307 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2308 CORE_ADDR start_pc; /* The beginning of the function. */
2309 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2310 CORE_ADDR sp, fp, ra;
2311 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2313 /* Find the beginning of the prologue of the function containing the PC
2314 and analyze it up to the PC or the end of the prologue. */
2316 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2318 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
2320 &cache->c0.c0_rt[0],
2323 if (body_pc == XTENSA_ISA_BADPC)
2324 error (_("Xtensa-specific internal error: CALL0 prologue \
2325 analysis failed in this frame. GDB command execution stopped."));
2328 sp = get_frame_register_unsigned
2329 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2330 fp = sp; /* Assume FP == SP until proven otherwise. */
2332 /* Get the frame information and FP (if used) at the current PC.
2333 If PC is in the prologue, the prologue analysis is more reliable
2334 than DWARF info. We don't not know for sure if PC is in the prologue,
2335 but we know no calls have yet taken place, so we can almost
2336 certainly rely on the prologue analysis. */
2340 /* Prologue analysis was successful up to the PC.
2341 It includes the cases when PC == START_PC. */
2342 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2343 /* c0_hasfp == true means there is a frame pointer because
2344 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2345 was derived from SP. Otherwise, it would be C0_FP. */
2346 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2347 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2348 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2350 else /* No data from the prologue analysis. */
2353 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2358 prev_sp = fp + c0_frmsz;
2360 /* Frame size from debug info or prologue tracking does not account for
2361 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2364 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2366 /* Recalculate previous SP. */
2367 prev_sp = fp + c0_frmsz;
2368 /* Update the stack frame size. */
2369 c0_frmsz += fp - sp;
2372 /* Get the return address (RA) from the stack if saved,
2373 or try to get it from a register. */
2375 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2376 if (to_stk != C0_NOSTK)
2378 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2381 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2382 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2384 /* Special case for terminating backtrace at a function that wants to
2385 be seen as the outermost. Such a function will clear it's RA (A0)
2386 register to 0 in the prologue instead of saving its original value. */
2391 /* RA was copied to another register or (before any function call) may
2392 still be in the original RA register. This is not always reliable:
2393 even in a leaf function, register tracking stops after prologue, and
2394 even in prologue, non-prologue instructions (not tracked) may overwrite
2395 RA or any register it was copied to. If likely in prologue or before
2396 any call, use retracking info and hope for the best (compiler should
2397 have saved RA in stack if not in a leaf function). If not in prologue,
2403 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2405 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2409 ra = get_frame_register_unsigned
2411 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2416 cache->pc = start_pc;
2418 /* RA == 0 marks the outermost frame. Do not go past it. */
2419 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2420 cache->c0.fp_regnum = fp_regnum;
2421 cache->c0.c0_frmsz = c0_frmsz;
2422 cache->c0.c0_hasfp = c0_hasfp;
2423 cache->c0.c0_fp = fp;
2427 /* Skip function prologue.
2429 Return the pc of the first instruction after prologue. GDB calls this to
2430 find the address of the first line of the function or (if there is no line
2431 number information) to skip the prologue for planting breakpoints on
2432 function entries. Use debug info (if present) or prologue analysis to skip
2433 the prologue to achieve reliable debugging behavior. For windowed ABI,
2434 only the 'entry' instruction is skipped. It is not strictly necessary to
2435 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2436 backtrace at any point in the prologue, however certain potential hazards
2437 are avoided and a more "normal" debugging experience is ensured by
2438 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2439 For example, if we don't skip the prologue:
2440 - Some args may not yet have been saved to the stack where the debug
2441 info expects to find them (true anyway when only 'entry' is skipped);
2442 - Software breakpoints ('break' instrs) may not have been unplanted
2443 when the prologue analysis is done on initializing the frame cache,
2444 and breaks in the prologue will throw off the analysis.
2446 If we have debug info ( line-number info, in particular ) we simply skip
2447 the code associated with the first function line effectively skipping
2448 the prologue code. It works even in cases like
2451 { int local_var = 1;
2455 because, for this source code, both Xtensa compilers will generate two
2456 separate entries ( with the same line number ) in dwarf line-number
2457 section to make sure there is a boundary between the prologue code and
2458 the rest of the function.
2460 If there is no debug info, we need to analyze the code. */
2462 /* #define DONT_SKIP_PROLOGUE */
2465 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2467 struct symtab_and_line prologue_sal;
2470 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2472 #if DONT_SKIP_PROLOGUE
2476 /* Try to find first body line from debug info. */
2478 prologue_sal = find_pc_line (start_pc, 0);
2479 if (prologue_sal.line != 0) /* Found debug info. */
2481 /* In Call0, it is possible to have a function with only one instruction
2482 ('ret') resulting from a 1-line optimized function that does nothing.
2483 In that case, prologue_sal.end may actually point to the start of the
2484 next function in the text section, causing a breakpoint to be set at
2485 the wrong place. Check if the end address is in a different function,
2486 and if so return the start PC. We know we have symbol info. */
2490 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2491 if (end_func != start_pc)
2494 return prologue_sal.end;
2497 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2498 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
2499 return body_pc != 0 ? body_pc : start_pc;
2502 /* Verify the current configuration. */
2504 xtensa_verify_config (struct gdbarch *gdbarch)
2506 struct ui_file *log;
2507 struct cleanup *cleanups;
2508 struct gdbarch_tdep *tdep;
2512 tdep = gdbarch_tdep (gdbarch);
2513 log = mem_fileopen ();
2514 cleanups = make_cleanup_ui_file_delete (log);
2516 /* Verify that we got a reasonable number of AREGS. */
2517 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2518 fprintf_unfiltered (log, _("\
2519 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2522 /* Verify that certain registers exist. */
2524 if (tdep->pc_regnum == -1)
2525 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2526 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2527 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2529 if (tdep->isa_use_windowed_registers)
2531 if (tdep->wb_regnum == -1)
2532 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2533 if (tdep->ws_regnum == -1)
2534 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2535 if (tdep->ar_base == -1)
2536 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2539 if (tdep->a0_base == -1)
2540 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2542 buf = ui_file_xstrdup (log, &length);
2543 make_cleanup (xfree, buf);
2545 internal_error (__FILE__, __LINE__,
2546 _("the following are invalid: %s"), buf);
2547 do_cleanups (cleanups);
2551 /* Derive specific register numbers from the array of registers. */
2554 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2556 xtensa_register_t* rmap;
2557 int n, max_size = 4;
2560 tdep->num_nopriv_regs = 0;
2562 /* Special registers 0..255 (core). */
2563 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2565 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2567 if (rmap->target_number == 0x0020)
2568 tdep->pc_regnum = n;
2569 else if (rmap->target_number == 0x0100)
2571 else if (rmap->target_number == 0x0000)
2573 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2574 tdep->wb_regnum = n;
2575 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2576 tdep->ws_regnum = n;
2577 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2578 tdep->debugcause_regnum = n;
2579 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2580 tdep->exccause_regnum = n;
2581 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2582 tdep->excvaddr_regnum = n;
2583 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2584 tdep->lbeg_regnum = n;
2585 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2586 tdep->lend_regnum = n;
2587 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2588 tdep->lcount_regnum = n;
2589 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2590 tdep->sar_regnum = n;
2591 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2592 tdep->litbase_regnum = n;
2593 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2594 tdep->ps_regnum = n;
2596 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2597 tdep->interrupt_regnum = n;
2598 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2599 tdep->interrupt2_regnum = n;
2600 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2601 tdep->cpenable_regnum = n;
2604 if (rmap->byte_size > max_size)
2605 max_size = rmap->byte_size;
2606 if (rmap->mask != 0 && tdep->num_regs == 0)
2608 /* Find out out how to deal with priveleged registers.
2610 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2611 && tdep->num_nopriv_regs == 0)
2612 tdep->num_nopriv_regs = n;
2614 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2615 && tdep->num_regs == 0)
2619 /* Number of pseudo registers. */
2620 tdep->num_pseudo_regs = n - tdep->num_regs;
2622 /* Empirically determined maximum sizes. */
2623 tdep->max_register_raw_size = max_size;
2624 tdep->max_register_virtual_size = max_size;
2627 /* Module "constructor" function. */
2629 extern struct gdbarch_tdep xtensa_tdep;
2631 static struct gdbarch *
2632 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2634 struct gdbarch_tdep *tdep;
2635 struct gdbarch *gdbarch;
2636 struct xtensa_abi_handler *abi_handler;
2638 DEBUGTRACE ("gdbarch_init()\n");
2640 /* We have to set the byte order before we call gdbarch_alloc. */
2641 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
2643 tdep = &xtensa_tdep;
2644 gdbarch = gdbarch_alloc (&info, tdep);
2645 xtensa_derive_tdep (tdep);
2647 /* Verify our configuration. */
2648 xtensa_verify_config (gdbarch);
2650 /* Pseudo-Register read/write. */
2651 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2652 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2654 /* Set target information. */
2655 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2656 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2657 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2658 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2659 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2661 /* Renumber registers for known formats (stabs and dwarf2). */
2662 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2663 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2665 /* We provide our own function to get register information. */
2666 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2667 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2669 /* To call functions from GDB using dummy frame */
2670 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2672 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2674 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2676 /* Advance PC across any prologue instructions to reach "real" code. */
2677 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2679 /* Stack grows downward. */
2680 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2682 /* Set breakpoints. */
2683 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2685 /* After breakpoint instruction or illegal instruction, pc still
2686 points at break instruction, so don't decrement. */
2687 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2689 /* We don't skip args. */
2690 set_gdbarch_frame_args_skip (gdbarch, 0);
2692 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2694 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2696 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
2698 /* Frame handling. */
2699 frame_base_set_default (gdbarch, &xtensa_frame_base);
2700 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
2701 dwarf2_append_unwinders (gdbarch);
2703 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2705 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2707 xtensa_add_reggroups (gdbarch);
2708 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2710 set_gdbarch_regset_from_core_section (gdbarch,
2711 xtensa_regset_from_core_section);
2713 set_solib_svr4_fetch_link_map_offsets
2714 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
2720 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2722 error (_("xtensa_dump_tdep(): not implemented"));
2725 /* Provide a prototype to silence -Wmissing-prototypes. */
2726 extern initialize_file_ftype _initialize_xtensa_tdep;
2729 _initialize_xtensa_tdep (void)
2731 struct cmd_list_element *c;
2733 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2734 xtensa_init_reggroups ();
2736 add_setshow_zinteger_cmd ("xtensa",
2738 &xtensa_debug_level, _("\
2739 Set Xtensa debugging."), _("\
2740 Show Xtensa debugging."), _("\
2741 When non-zero, Xtensa-specific debugging is enabled. \
2742 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2745 &setdebuglist, &showdebuglist);