1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "floatformat.h"
32 #include "reggroups.h"
35 #include "dummy-frame.h"
36 #include "elf/dwarf2.h"
37 #include "dwarf2-frame.h"
38 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
50 #include "gdb_assert.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
54 #include "xtensa-config.h"
57 static int xtensa_debug_level = 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
77 #define SP_ALIGNMENT 16
80 /* On Windowed ABI, we use a6 through a11 for passing arguments
81 to a function called by GDB because CALL4 is used. */
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
92 /* ABI-independent macros. */
93 #define ARG_NOF(gdbarch) \
94 (gdbarch_tdep (gdbarch)->call_abi \
95 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
96 #define ARG_1ST(gdbarch) \
97 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
98 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
99 : (gdbarch_tdep (gdbarch)->a0_base + 6))
101 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
102 indicates that the instruction is an ENTRY instruction. */
104 #define XTENSA_IS_ENTRY(gdbarch, op1) \
105 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
106 ? ((op1) == 0x6c) : ((op1) == 0x36))
108 #define XTENSA_ENTRY_LENGTH 3
110 /* windowing_enabled() returns true, if windowing is enabled.
111 WOE must be set to 1; EXCM to 0.
112 Note: We assume that EXCM is always 0 for XEA1. */
114 #define PS_WOE (1<<18)
115 #define PS_EXC (1<<4)
117 /* Convert a live Ax register number to the corresponding Areg number. */
119 areg_number (struct gdbarch *gdbarch, int regnum, ULONGEST wb)
121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
124 areg = regnum - tdep->a0_base;
125 areg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
126 areg &= tdep->num_aregs - 1;
128 return areg + tdep->ar_base;
132 windowing_enabled (CORE_ADDR ps)
134 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
137 /* Return the window size of the previous call to the function from which we
140 This function is used to extract the return value after a called function
141 has returned to the caller. On Xtensa, the register that holds the return
142 value (from the perspective of the caller) depends on what call
143 instruction was used. For now, we are assuming that the call instruction
144 precedes the current address, so we simply analyze the call instruction.
145 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
146 method to call the inferior function. */
149 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
155 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
157 /* Read the previous instruction (should be a call[x]{4|8|12}. */
158 read_memory (pc-3, buf, 3);
159 insn = extract_unsigned_integer (buf, 3);
161 /* Decode call instruction:
163 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
164 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
166 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
167 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
169 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
171 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
172 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
176 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
177 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
183 /* REGISTER INFORMATION */
185 /* Returns the name of a register. */
187 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
189 /* Return the name stored in the register map. */
190 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
191 + gdbarch_num_pseudo_regs (gdbarch))
192 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
194 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
199 xtensa_read_register (int regnum)
203 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
204 return (unsigned long) value;
207 /* Return the type of a register. Create a new type, if necessary. */
209 static struct ctype_cache
211 struct ctype_cache *next;
213 struct type *virtual_type;
214 } *type_entries = NULL;
217 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
219 /* Return signed integer for ARx and Ax registers. */
220 if ((regnum >= gdbarch_tdep (gdbarch)->ar_base
221 && regnum < gdbarch_tdep (gdbarch)->ar_base
222 + gdbarch_tdep (gdbarch)->num_aregs)
223 || (regnum >= gdbarch_tdep (gdbarch)->a0_base
224 && regnum < gdbarch_tdep (gdbarch)->a0_base + 16))
225 return builtin_type_int;
227 if (regnum == gdbarch_pc_regnum (gdbarch)
228 || regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
229 return lookup_pointer_type (builtin_type_void);
231 /* Return the stored type for all other registers. */
232 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
233 + gdbarch_num_pseudo_regs (gdbarch))
235 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
237 /* Set ctype for this register (only the first time). */
241 struct ctype_cache *tp;
242 int size = reg->byte_size;
244 /* We always use the memory representation,
245 even if the register width is smaller. */
249 reg->ctype = builtin_type_uint8;
253 reg->ctype = builtin_type_uint16;
257 reg->ctype = builtin_type_uint32;
261 reg->ctype = builtin_type_uint64;
265 reg->ctype = builtin_type_uint128;
269 for (tp = type_entries; tp != NULL; tp = tp->next)
270 if (tp->size == size)
275 char *name = xmalloc (16);
276 tp = xmalloc (sizeof (struct ctype_cache));
277 tp->next = type_entries;
281 sprintf (name, "int%d", size * 8);
282 tp->virtual_type = init_type (TYPE_CODE_INT, size,
283 TYPE_FLAG_UNSIGNED, name,
287 reg->ctype = tp->virtual_type;
293 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
298 /* Return the 'local' register number for stubs, dwarf2, etc.
299 The debugging information enumerates registers starting from 0 for A0
300 to n for An. So, we only have to add the base number for A0. */
303 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
307 if (regnum >= 0 && regnum < 16)
308 return gdbarch_tdep (gdbarch)->a0_base + regnum;
311 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
313 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
316 internal_error (__FILE__, __LINE__,
317 _("invalid dwarf/stabs register number %d"), regnum);
322 /* Write the bits of a masked register to the various registers.
323 Only the masked areas of these registers are modified; the other
324 fields are untouched. The size of masked registers is always less
325 than or equal to 32 bits. */
328 xtensa_register_write_masked (struct regcache *regcache,
329 xtensa_register_t *reg, const gdb_byte *buffer)
331 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
332 const xtensa_mask_t *mask = reg->mask;
334 int shift = 0; /* Shift for next mask (mod 32). */
335 int start, size; /* Start bit and size of current mask. */
337 unsigned int *ptr = value;
338 unsigned int regval, m, mem = 0;
340 int bytesize = reg->byte_size;
341 int bitsize = bytesize * 8;
344 DEBUGTRACE ("xtensa_register_write_masked ()\n");
346 /* Copy the masked register to host byte-order. */
347 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
348 for (i = 0; i < bytesize; i++)
351 mem |= (buffer[bytesize - i - 1] << 24);
356 for (i = 0; i < bytesize; i++)
359 mem |= (buffer[i] << 24);
364 /* We might have to shift the final value:
365 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
366 bytesize & 3 == x -> shift (4-x) * 8. */
368 *ptr = mem >> (((0 - bytesize) & 3) * 8);
372 /* Write the bits to the masked areas of the other registers. */
373 for (i = 0; i < mask->count; i++)
375 start = mask->mask[i].bit_start;
376 size = mask->mask[i].bit_size;
377 regval = mem >> shift;
379 if ((shift += size) > bitsize)
380 error (_("size of all masks is larger than the register"));
389 regval |= mem << (size - shift);
392 /* Make sure we have a valid register. */
393 r = mask->mask[i].reg_num;
394 if (r >= 0 && size > 0)
396 /* Don't overwrite the unmasked areas. */
398 regcache_cooked_read_unsigned (regcache, r, &old_val);
399 m = 0xffffffff >> (32 - size) << start;
401 regval = (regval & m) | (old_val & ~m);
402 regcache_cooked_write_unsigned (regcache, r, regval);
408 /* Read a tie state or mapped registers. Read the masked areas
409 of the registers and assemble them into a single value. */
412 xtensa_register_read_masked (struct regcache *regcache,
413 xtensa_register_t *reg, gdb_byte *buffer)
415 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
416 const xtensa_mask_t *mask = reg->mask;
421 unsigned int *ptr = value;
422 unsigned int regval, mem = 0;
424 int bytesize = reg->byte_size;
425 int bitsize = bytesize * 8;
428 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
429 reg->name == 0 ? "" : reg->name);
431 /* Assemble the register from the masked areas of other registers. */
432 for (i = 0; i < mask->count; i++)
434 int r = mask->mask[i].reg_num;
438 regcache_cooked_read_unsigned (regcache, r, &val);
439 regval = (unsigned int) val;
444 start = mask->mask[i].bit_start;
445 size = mask->mask[i].bit_size;
450 regval &= (0xffffffff >> (32 - size));
452 mem |= regval << shift;
454 if ((shift += size) > bitsize)
455 error (_("size of all masks is larger than the register"));
466 mem = regval >> (size - shift);
473 /* Copy value to target byte order. */
477 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
478 for (i = 0; i < bytesize; i++)
482 buffer[bytesize - i - 1] = mem & 0xff;
486 for (i = 0; i < bytesize; i++)
490 buffer[i] = mem & 0xff;
496 /* Read pseudo registers. */
499 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
500 struct regcache *regcache,
504 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
505 regnum, xtensa_register_name (gdbarch, regnum));
507 if (regnum == gdbarch_num_regs (gdbarch)
508 + gdbarch_num_pseudo_regs (gdbarch) - 1)
509 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
511 /* Read aliases a0..a15, if this is a Windowed ABI. */
512 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
513 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
514 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
516 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
518 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
519 regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4));
522 /* We can always read non-pseudo registers. */
523 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
524 regcache_raw_read (regcache, regnum, buffer);
527 /* We have to find out how to deal with priveleged registers.
528 Let's treat them as pseudo-registers, but we cannot read/write them. */
530 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
532 buffer[0] = (gdb_byte)0;
533 buffer[1] = (gdb_byte)0;
534 buffer[2] = (gdb_byte)0;
535 buffer[3] = (gdb_byte)0;
537 /* Pseudo registers. */
539 && regnum < gdbarch_num_regs (gdbarch)
540 + gdbarch_num_pseudo_regs (gdbarch))
542 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
543 xtensa_register_type_t type = reg->type;
544 int flags = gdbarch_tdep (gdbarch)->target_flags;
546 /* We cannot read Unknown or Unmapped registers. */
547 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
549 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
551 warning (_("cannot read register %s"),
552 xtensa_register_name (gdbarch, regnum));
557 /* Some targets cannot read TIE register files. */
558 else if (type == xtRegisterTypeTieRegfile)
560 /* Use 'fetch' to get register? */
561 if (flags & xtTargetFlagsUseFetchStore)
563 warning (_("cannot read register"));
567 /* On some targets (esp. simulators), we can always read the reg. */
568 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
570 warning (_("cannot read register"));
575 /* We can always read mapped registers. */
576 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
578 xtensa_register_read_masked (regcache, reg, buffer);
582 /* Assume that we can read the register. */
583 regcache_raw_read (regcache, regnum, buffer);
586 internal_error (__FILE__, __LINE__,
587 _("invalid register number %d"), regnum);
591 /* Write pseudo registers. */
594 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
595 struct regcache *regcache,
597 const gdb_byte *buffer)
599 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
600 regnum, xtensa_register_name (gdbarch, regnum));
602 if (regnum == gdbarch_num_regs (gdbarch)
603 + gdbarch_num_pseudo_regs (gdbarch) -1)
604 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
606 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
607 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
608 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
609 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
611 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
614 regcache_raw_read (regcache,
615 gdbarch_tdep (gdbarch)->wb_regnum, buf);
616 regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4));
619 /* We can always write 'core' registers.
620 Note: We might have converted Ax->ARy. */
621 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
622 regcache_raw_write (regcache, regnum, buffer);
624 /* We have to find out how to deal with priveleged registers.
625 Let's treat them as pseudo-registers, but we cannot read/write them. */
627 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
631 /* Pseudo registers. */
633 && regnum < gdbarch_num_regs (gdbarch)
634 + gdbarch_num_pseudo_regs (gdbarch))
636 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
637 xtensa_register_type_t type = reg->type;
638 int flags = gdbarch_tdep (gdbarch)->target_flags;
640 /* On most targets, we cannot write registers
641 of type "Unknown" or "Unmapped". */
642 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
644 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
646 warning (_("cannot write register %s"),
647 xtensa_register_name (gdbarch, regnum));
652 /* Some targets cannot read TIE register files. */
653 else if (type == xtRegisterTypeTieRegfile)
655 /* Use 'store' to get register? */
656 if (flags & xtTargetFlagsUseFetchStore)
658 warning (_("cannot write register"));
662 /* On some targets (esp. simulators), we can always write
664 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
666 warning (_("cannot write register"));
671 /* We can always write mapped registers. */
672 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
674 xtensa_register_write_masked (regcache, reg, buffer);
678 /* Assume that we can write the register. */
679 regcache_raw_write (regcache, regnum, buffer);
682 internal_error (__FILE__, __LINE__,
683 _("invalid register number %d"), regnum);
686 static struct reggroup *xtensa_ar_reggroup;
687 static struct reggroup *xtensa_user_reggroup;
688 static struct reggroup *xtensa_vectra_reggroup;
689 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
692 xtensa_init_reggroups (void)
694 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
695 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
696 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
698 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
699 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
700 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
701 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
702 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
703 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
704 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
705 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
709 xtensa_add_reggroups (struct gdbarch *gdbarch)
713 /* Predefined groups. */
714 reggroup_add (gdbarch, all_reggroup);
715 reggroup_add (gdbarch, save_reggroup);
716 reggroup_add (gdbarch, restore_reggroup);
717 reggroup_add (gdbarch, system_reggroup);
718 reggroup_add (gdbarch, vector_reggroup);
719 reggroup_add (gdbarch, general_reggroup);
720 reggroup_add (gdbarch, float_reggroup);
722 /* Xtensa-specific groups. */
723 reggroup_add (gdbarch, xtensa_ar_reggroup);
724 reggroup_add (gdbarch, xtensa_user_reggroup);
725 reggroup_add (gdbarch, xtensa_vectra_reggroup);
727 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
728 reggroup_add (gdbarch, xtensa_cp[i]);
732 xtensa_coprocessor_register_group (struct reggroup *group)
736 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
737 if (group == xtensa_cp[i])
743 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
744 | XTENSA_REGISTER_FLAGS_WRITABLE \
745 | XTENSA_REGISTER_FLAGS_VOLATILE)
747 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
748 | XTENSA_REGISTER_FLAGS_WRITABLE)
751 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
753 struct reggroup *group)
755 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
756 xtensa_register_type_t type = reg->type;
757 xtensa_register_group_t rg = reg->group;
760 /* First, skip registers that are not visible to this target
761 (unknown and unmapped registers when not using ISS). */
763 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
765 if (group == all_reggroup)
767 if (group == xtensa_ar_reggroup)
768 return rg & xtRegisterGroupAddrReg;
769 if (group == xtensa_user_reggroup)
770 return rg & xtRegisterGroupUser;
771 if (group == float_reggroup)
772 return rg & xtRegisterGroupFloat;
773 if (group == general_reggroup)
774 return rg & xtRegisterGroupGeneral;
775 if (group == float_reggroup)
776 return rg & xtRegisterGroupFloat;
777 if (group == system_reggroup)
778 return rg & xtRegisterGroupState;
779 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
780 return rg & xtRegisterGroupVectra;
781 if (group == save_reggroup || group == restore_reggroup)
782 return (regnum < gdbarch_num_regs (gdbarch)
783 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
784 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
785 return rg & (xtRegisterGroupCP0 << cp_number);
791 /* Supply register REGNUM from the buffer specified by GREGS and LEN
792 in the general-purpose register set REGSET to register cache
793 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
796 xtensa_supply_gregset (const struct regset *regset,
802 const xtensa_elf_gregset_t *regs = gregs;
803 struct gdbarch *gdbarch = get_regcache_arch (rc);
806 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
808 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
809 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
810 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
811 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
812 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
813 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
814 (char *) ®s->windowbase);
815 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
816 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
817 (char *) ®s->windowstart);
818 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
819 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
820 (char *) ®s->lbeg);
821 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
822 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
823 (char *) ®s->lend);
824 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
825 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
826 (char *) ®s->lcount);
827 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
828 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
829 (char *) ®s->sar);
830 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
831 && regnum < gdbarch_tdep (gdbarch)->ar_base
832 + gdbarch_tdep (gdbarch)->num_aregs)
833 regcache_raw_supply (rc, regnum,
834 (char *) ®s->ar[regnum - gdbarch_tdep
835 (gdbarch)->ar_base]);
836 else if (regnum == -1)
838 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
839 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
840 (char *) ®s->ar[i]);
845 /* Xtensa register set. */
851 xtensa_supply_gregset
855 /* Return the appropriate register set for the core
856 section identified by SECT_NAME and SECT_SIZE. */
858 static const struct regset *
859 xtensa_regset_from_core_section (struct gdbarch *core_arch,
860 const char *sect_name,
863 DEBUGTRACE ("xtensa_regset_from_core_section "
864 "(..., sect_name==\"%s\", sect_size==%x) \n",
865 sect_name, (unsigned int) sect_size);
867 if (strcmp (sect_name, ".reg") == 0
868 && sect_size >= sizeof(xtensa_elf_gregset_t))
869 return &xtensa_gregset;
875 /* Handling frames. */
877 /* Number of registers to save in case of Windowed ABI. */
878 #define XTENSA_NUM_SAVED_AREGS 12
880 /* Frame cache part for Windowed ABI. */
881 typedef struct xtensa_windowed_frame_cache
883 int wb; /* Base for this frame; -1 if not in regfile. */
884 int callsize; /* Call size to next frame. */
886 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
887 } xtensa_windowed_frame_cache_t;
889 /* Call0 ABI Definitions. */
891 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
892 #define C0_NREGS 16 /* Number of A-registers to track. */
893 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
894 #define C0_SP 1 /* Register used as SP. */
895 #define C0_FP 15 /* Register used as FP. */
896 #define C0_RA 0 /* Register used as return address. */
897 #define C0_ARGS 2 /* Register used as first arg/retval. */
898 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
900 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
901 A-register where the current content of the reg came from (in terms
902 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
903 mean that the orignal content of the register was saved to the stack.
904 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
905 know where SP will end up until the entire prologue has been analyzed. */
907 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
908 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
909 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
911 extern xtensa_isa xtensa_default_isa;
913 typedef struct xtensa_c0reg
915 int fr_reg; /* original register from which register content
916 is derived, or C0_CONST, or C0_INEXP. */
917 int fr_ofs; /* constant offset from reg, or immediate value. */
918 int to_stk; /* offset from original SP to register (4-byte aligned),
919 or C0_NOSTK if register has not been saved. */
923 /* Frame cache part for Call0 ABI. */
924 typedef struct xtensa_call0_frame_cache
926 int c0_frmsz; /* Stack frame size. */
927 int c0_hasfp; /* Current frame uses frame pointer. */
928 int fp_regnum; /* A-register used as FP. */
929 int c0_fp; /* Actual value of frame pointer. */
930 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
931 } xtensa_call0_frame_cache_t;
933 typedef struct xtensa_frame_cache
935 CORE_ADDR base; /* Stack pointer of the next frame. */
936 CORE_ADDR pc; /* PC at the entry point to the function. */
937 CORE_ADDR ra; /* The raw return address. */
938 CORE_ADDR ps; /* The PS register of the frame. */
939 CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
940 int call0; /* It's a call0 framework (else windowed). */
943 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
944 xtensa_call0_frame_cache_t c0; /* call0 == true. */
946 } xtensa_frame_cache_t;
949 static struct xtensa_frame_cache *
950 xtensa_alloc_frame_cache (int windowed)
952 xtensa_frame_cache_t *cache;
955 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
957 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
964 cache->call0 = !windowed;
967 cache->c0.c0_frmsz = -1;
968 cache->c0.c0_hasfp = 0;
969 cache->c0.fp_regnum = -1;
970 cache->c0.c0_fp = -1;
972 for (i = 0; i < C0_NREGS; i++)
974 cache->c0.c0_rt[i].fr_reg = i;
975 cache->c0.c0_rt[i].fr_ofs = 0;
976 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
982 cache->wd.callsize = -1;
984 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
985 cache->wd.aregs[i] = -1;
992 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
994 return address & ~15;
999 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1003 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
1005 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1007 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
1008 extract_typed_address (buf, builtin_type_void_func_ptr));
1010 return extract_typed_address (buf, builtin_type_void_func_ptr);
1014 static struct frame_id
1015 xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1019 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
1021 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
1023 pc = frame_pc_unwind (next_frame);
1024 fp = frame_unwind_register_unsigned
1025 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1027 /* Make dummy frame ID unique by adding a constant. */
1028 return frame_id_build (fp + SP_ALIGNMENT, pc);
1031 /* The key values to identify the frame using "cache" are
1033 cache->base = SP of this frame;
1034 cache->pc = entry-PC (entry point of the frame function);
1035 cache->prev_sp = SP of the previous frame.
1039 call0_frame_cache (struct frame_info *next_frame,
1040 xtensa_frame_cache_t *cache,
1043 static struct xtensa_frame_cache *
1044 xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
1046 xtensa_frame_cache_t *cache;
1047 CORE_ADDR ra, wb, ws, pc, sp, ps;
1048 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1049 unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch);
1053 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
1054 next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
1059 windowed = windowing_enabled (xtensa_read_register (ps_regnum));
1061 /* Get pristine xtensa-frame. */
1062 cache = xtensa_alloc_frame_cache (windowed);
1063 *this_cache = cache;
1065 pc = frame_unwind_register_unsigned (next_frame,
1066 gdbarch_pc_regnum (gdbarch));
1070 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1071 wb = frame_unwind_register_unsigned
1072 (next_frame, gdbarch_tdep (gdbarch)->wb_regnum);
1073 ws = frame_unwind_register_unsigned
1074 (next_frame, gdbarch_tdep (gdbarch)->ws_regnum);
1075 ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
1077 op1 = read_memory_integer (pc, 1);
1078 if (XTENSA_IS_ENTRY (gdbarch, op1))
1080 int callinc = CALLINC (ps);
1081 ra = frame_unwind_register_unsigned
1082 (next_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1084 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
1087 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1088 cache->wd.callsize = 0;
1091 cache->prev_sp = frame_unwind_register_unsigned
1092 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1096 ra = frame_unwind_register_unsigned
1097 (next_frame, gdbarch_tdep (gdbarch)->a0_base);
1098 cache->wd.callsize = WINSIZE (ra);
1099 cache->wd.wb = (wb - cache->wd.callsize / 4)
1100 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1101 cache->wd.ws = ws & ~(1 << wb);
1104 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
1105 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1106 cache->ps = (ps & ~PS_CALLINC_MASK)
1107 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1109 if (cache->wd.ws == 0)
1114 sp = frame_unwind_register_unsigned
1115 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1117 for (i = 0; i < 4; i++, sp += 4)
1119 cache->wd.aregs[i] = sp;
1122 if (cache->wd.callsize > 4)
1124 /* Set A4...A7/A11. */
1125 /* Read an SP of the previous frame. */
1126 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1127 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1128 sp -= cache->wd.callsize * 4;
1130 for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
1132 cache->wd.aregs[i] = sp;
1137 if ((cache->prev_sp == 0) && ( ra != 0 ))
1138 /* If RA is equal to 0 this frame is an outermost frame. Leave
1139 cache->prev_sp unchanged marking the boundary of the frame stack. */
1141 if (cache->wd.ws == 0)
1143 /* Register window overflow already happened.
1144 We can read caller's SP from the proper spill loction. */
1146 read_memory_integer (cache->wd.aregs[1],
1147 register_size (gdbarch,
1148 gdbarch_tdep (gdbarch)->a0_base + 1));
1152 /* Read caller's frame SP directly from the previous window. */
1153 int regnum = areg_number
1154 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1157 cache->prev_sp = xtensa_read_register (regnum);
1161 else /* Call0 framework. */
1163 call0_frame_cache (next_frame, cache, pc);
1166 cache->base = frame_unwind_register_unsigned
1167 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1173 xtensa_frame_this_id (struct frame_info *next_frame,
1175 struct frame_id *this_id)
1177 struct xtensa_frame_cache *cache =
1178 xtensa_frame_cache (next_frame, this_cache);
1181 DEBUGTRACE ("xtensa_frame_this_id (next 0x%lx, *this 0x%lx)\n",
1182 (unsigned long) next_frame, (unsigned long) *this_cache);
1184 if (cache->prev_sp == 0)
1187 id = frame_id_build (cache->prev_sp, cache->pc);
1188 if (frame_id_eq (id, get_frame_id(next_frame)))
1191 Frame stack is corrupted. That could happen because of \
1192 setting register(s) from GDB or stopping execution \
1193 inside exception handler. Frame backtracing has stopped. \
1194 It can make some GDB commands work inappropriately.\n"));
1202 call0_frame_get_reg_at_entry (struct frame_info *next_frame,
1203 struct xtensa_frame_cache *cache,
1206 enum lval_type *lval,
1211 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1212 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1213 && regnum <= (gdbarch_tdep (gdbarch)->ar_base + C0_NREGS))
1214 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1216 /* Determine stack pointer on entry to this function, based on FP. */
1217 spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1219 /* If register was saved to the stack frame in the prologue, retrieve it. */
1220 stkofs = cache->c0.c0_rt[reg].to_stk;
1221 if (stkofs != C0_NOSTK)
1223 *lval = lval_memory;
1224 *addrp = spe + stkofs;
1227 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1232 /* If not callee-saved or if known to have been overwritten, give up. */
1234 || cache->c0.c0_rt[reg].fr_reg != reg
1235 || cache->c0.c0_rt[reg].fr_ofs != 0)
1238 if (get_frame_type (next_frame) != NORMAL_FRAME)
1239 /* TODO: Do we need a special case for DUMMY_FRAME here? */
1242 return call0_frame_get_reg_at_entry (get_next_frame(next_frame),
1243 cache, regnum, addrp, lval, valuep);
1247 xtensa_frame_prev_register (struct frame_info *next_frame,
1251 enum lval_type *lvalp,
1256 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1257 struct xtensa_frame_cache *cache =
1258 xtensa_frame_cache (next_frame, this_cache);
1259 CORE_ADDR saved_reg = 0;
1262 DEBUGTRACE ("xtensa_frame_prev_register (next 0x%lx, "
1263 "*this 0x%lx, regnum %d (%s), ...)\n",
1264 (unsigned long) next_frame,
1265 *this_cache ? (unsigned long) *this_cache : 0, regnum,
1266 xtensa_register_name (gdbarch, regnum));
1268 if (regnum ==gdbarch_pc_regnum (gdbarch))
1269 saved_reg = cache->ra;
1270 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1271 saved_reg = cache->prev_sp;
1272 else if (!cache->call0)
1274 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1276 if (cache->wd.ws != 0)
1277 saved_reg = cache->wd.ws;
1279 saved_reg = 1 << cache->wd.wb;
1281 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1282 saved_reg = cache->wd.wb;
1283 else if (regnum == gdbarch_ps_regnum (gdbarch))
1284 saved_reg = cache->ps;
1298 store_unsigned_integer (valuep, 4, saved_reg);
1303 if (!cache->call0) /* Windowed ABI. */
1305 /* Convert A-register numbers to AR-register numbers. */
1306 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1307 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1308 regnum = areg_number (gdbarch, regnum, cache->wd.wb);
1310 /* Check if AR-register has been saved to stack. */
1311 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1312 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1313 + gdbarch_tdep (gdbarch)->num_aregs))
1315 int areg = regnum - gdbarch_tdep (gdbarch)->ar_base
1316 - (cache->wd.wb * 4);
1319 && areg < XTENSA_NUM_SAVED_AREGS
1320 && cache->wd.aregs[areg] != -1)
1323 *lvalp = lval_memory;
1324 *addrp = cache->wd.aregs[areg];
1328 read_memory (*addrp, valuep,
1329 register_size (gdbarch, regnum));
1331 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1336 else /* Call0 ABI. */
1338 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1339 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1341 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1348 /* If register was saved in the prologue, retrieve it. */
1349 stkofs = cache->c0.c0_rt[reg].to_stk;
1350 if (stkofs != C0_NOSTK)
1352 /* Determine SP on entry based on FP. */
1353 spe = cache->c0.c0_fp
1354 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1356 *lvalp = lval_memory;
1357 *addrp = spe + stkofs;
1361 read_memory (*addrp, valuep,
1362 register_size (gdbarch, regnum));
1364 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1370 /* All other registers have been either saved to
1371 the stack or are still alive in the processor. */
1374 *lvalp = lval_register;
1378 frame_unwind_register (next_frame, (*realnump), valuep);
1382 static const struct frame_unwind
1383 xtensa_frame_unwind =
1386 xtensa_frame_this_id,
1387 xtensa_frame_prev_register
1390 static const struct frame_unwind *
1391 xtensa_frame_sniffer (struct frame_info *next_frame)
1393 return &xtensa_frame_unwind;
1397 xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache)
1399 struct xtensa_frame_cache *cache =
1400 xtensa_frame_cache (next_frame, this_cache);
1405 static const struct frame_base
1408 &xtensa_frame_unwind,
1409 xtensa_frame_base_address,
1410 xtensa_frame_base_address,
1411 xtensa_frame_base_address
1416 xtensa_extract_return_value (struct type *type,
1417 struct regcache *regcache,
1420 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1421 bfd_byte *valbuf = dst;
1422 int len = TYPE_LENGTH (type);
1427 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1429 gdb_assert(len > 0);
1431 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1433 /* First, we have to find the caller window in the register file. */
1434 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1435 callsize = extract_call_winsize (gdbarch, pc);
1437 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1438 if (len > (callsize > 8 ? 8 : 16))
1439 internal_error (__FILE__, __LINE__,
1440 _("cannot extract return value of %d bytes long"), len);
1442 /* Get the register offset of the return
1443 register (A2) in the caller window. */
1444 regcache_raw_read_unsigned
1445 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1446 areg = areg_number (gdbarch,
1447 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1451 /* No windowing hardware - Call0 ABI. */
1452 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1455 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1457 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1460 for (; len > 0; len -= 4, areg++, valbuf += 4)
1463 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1465 regcache_raw_read (regcache, areg, valbuf);
1471 xtensa_store_return_value (struct type *type,
1472 struct regcache *regcache,
1475 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1476 const bfd_byte *valbuf = dst;
1480 int len = TYPE_LENGTH (type);
1483 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1485 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1487 regcache_raw_read_unsigned
1488 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1489 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1490 callsize = extract_call_winsize (gdbarch, pc);
1492 if (len > (callsize > 8 ? 8 : 16))
1493 internal_error (__FILE__, __LINE__,
1494 _("unimplemented for this length: %d"),
1495 TYPE_LENGTH (type));
1496 areg = areg_number (gdbarch,
1497 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1499 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1500 callsize, (int) wb);
1504 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1507 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1510 for (; len > 0; len -= 4, areg++, valbuf += 4)
1513 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1515 regcache_raw_write (regcache, areg, valbuf);
1520 static enum return_value_convention
1521 xtensa_return_value (struct gdbarch *gdbarch,
1522 struct type *func_type,
1523 struct type *valtype,
1524 struct regcache *regcache,
1526 const gdb_byte *writebuf)
1528 /* Structures up to 16 bytes are returned in registers. */
1530 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1531 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1532 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1533 && TYPE_LENGTH (valtype) > 16);
1536 return RETURN_VALUE_STRUCT_CONVENTION;
1538 DEBUGTRACE ("xtensa_return_value(...)\n");
1540 if (writebuf != NULL)
1542 xtensa_store_return_value (valtype, regcache, writebuf);
1545 if (readbuf != NULL)
1547 gdb_assert (!struct_return);
1548 xtensa_extract_return_value (valtype, regcache, readbuf);
1550 return RETURN_VALUE_REGISTER_CONVENTION;
1557 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1558 struct value *function,
1559 struct regcache *regcache,
1562 struct value **args,
1565 CORE_ADDR struct_addr)
1568 int size, onstack_size;
1569 gdb_byte *buf = (gdb_byte *) alloca (16);
1571 struct argument_info
1573 const bfd_byte *contents;
1575 int onstack; /* onstack == 0 => in reg */
1576 int align; /* alignment */
1579 int offset; /* stack offset if on stack */
1580 int regno; /* regno if in register */
1584 struct argument_info *arg_info =
1585 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1589 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1591 if (xtensa_debug_level > 3)
1594 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1595 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1596 "struct_addr=0x%x\n",
1597 (int) sp, (int) struct_return, (int) struct_addr);
1599 for (i = 0; i < nargs; i++)
1601 struct value *arg = args[i];
1602 struct type *arg_type = check_typedef (value_type (arg));
1603 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
1604 i, (unsigned long) arg, TYPE_LENGTH (arg_type));
1605 switch (TYPE_CODE (arg_type))
1608 fprintf_unfiltered (gdb_stdlog, "int");
1610 case TYPE_CODE_STRUCT:
1611 fprintf_unfiltered (gdb_stdlog, "struct");
1614 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1617 fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
1618 (unsigned long) value_contents (arg));
1622 /* First loop: collect information.
1623 Cast into type_long. (This shouldn't happen often for C because
1624 GDB already does this earlier.) It's possible that GDB could
1625 do it all the time but it's harmless to leave this code here. */
1632 size = REGISTER_SIZE;
1634 for (i = 0; i < nargs; i++)
1636 struct argument_info *info = &arg_info[i];
1637 struct value *arg = args[i];
1638 struct type *arg_type = check_typedef (value_type (arg));
1640 switch (TYPE_CODE (arg_type))
1643 case TYPE_CODE_BOOL:
1644 case TYPE_CODE_CHAR:
1645 case TYPE_CODE_RANGE:
1646 case TYPE_CODE_ENUM:
1648 /* Cast argument to long if necessary as the mask does it too. */
1649 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1651 arg_type = builtin_type_long;
1652 arg = value_cast (arg_type, arg);
1654 /* Aligment is equal to the type length for the basic types. */
1655 info->align = TYPE_LENGTH (arg_type);
1660 /* Align doubles correctly. */
1661 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1662 info->align = TYPE_LENGTH (builtin_type_double);
1664 info->align = TYPE_LENGTH (builtin_type_long);
1667 case TYPE_CODE_STRUCT:
1669 info->align = TYPE_LENGTH (builtin_type_long);
1672 info->length = TYPE_LENGTH (arg_type);
1673 info->contents = value_contents (arg);
1675 /* Align size and onstack_size. */
1676 size = (size + info->align - 1) & ~(info->align - 1);
1677 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1679 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1682 info->u.offset = onstack_size;
1683 onstack_size += info->length;
1688 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1690 size += info->length;
1693 /* Adjust the stack pointer and align it. */
1694 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1696 /* Simulate MOVSP, if Windowed ABI. */
1697 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1700 read_memory (osp - 16, buf, 16);
1701 write_memory (sp - 16, buf, 16);
1704 /* Second Loop: Load arguments. */
1708 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1709 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1712 for (i = 0; i < nargs; i++)
1714 struct argument_info *info = &arg_info[i];
1718 int n = info->length;
1719 CORE_ADDR offset = sp + info->u.offset;
1721 /* Odd-sized structs are aligned to the lower side of a memory
1722 word in big-endian mode and require a shift. This only
1723 applies for structures smaller than one word. */
1725 if (n < REGISTER_SIZE
1726 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1727 offset += (REGISTER_SIZE - n);
1729 write_memory (offset, info->contents, info->length);
1734 int n = info->length;
1735 const bfd_byte *cp = info->contents;
1736 int r = info->u.regno;
1738 /* Odd-sized structs are aligned to the lower side of registers in
1739 big-endian mode and require a shift. The odd-sized leftover will
1740 be at the end. Note that this is only true for structures smaller
1741 than REGISTER_SIZE; for larger odd-sized structures the excess
1742 will be left-aligned in the register on both endiannesses. */
1744 if (n < REGISTER_SIZE
1745 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1747 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1748 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1750 store_unsigned_integer (buf, REGISTER_SIZE, v);
1751 regcache_cooked_write (regcache, r, buf);
1753 cp += REGISTER_SIZE;
1760 regcache_cooked_write (regcache, r, cp);
1762 cp += REGISTER_SIZE;
1769 /* Set the return address of dummy frame to the dummy address.
1770 The return address for the current function (in A0) is
1771 saved in the dummy frame, so we can savely overwrite A0 here. */
1773 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1775 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1776 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
1777 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1778 regcache_cooked_write_unsigned
1779 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1780 regcache_cooked_write_unsigned (regcache,
1781 gdbarch_ps_regnum (gdbarch),
1784 /* All the registers have been saved. After executing
1785 dummy call, they all will be restored. So it's safe
1786 to modify WINDOWSTART register to make it look like there
1787 is only one register window corresponding to WINDOWEBASE. */
1789 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1790 regcache_cooked_write_unsigned (regcache,
1791 gdbarch_tdep (gdbarch)->ws_regnum,
1792 1 << extract_unsigned_integer (buf, 4));
1796 /* Simulate CALL0: write RA into A0 register. */
1797 regcache_cooked_write_unsigned
1798 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1801 /* Set new stack pointer and return it. */
1802 regcache_cooked_write_unsigned (regcache,
1803 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1804 /* Make dummy frame ID unique by adding a constant. */
1805 return sp + SP_ALIGNMENT;
1809 /* Return a breakpoint for the current location of PC. We always use
1810 the density version if we have density instructions (regardless of the
1811 current instruction at PC), and use regular instructions otherwise. */
1813 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1814 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1815 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1816 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1818 static const unsigned char *
1819 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1822 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1823 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1824 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1825 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1827 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1829 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1831 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1833 *lenptr = sizeof (density_big_breakpoint);
1834 return density_big_breakpoint;
1838 *lenptr = sizeof (density_little_breakpoint);
1839 return density_little_breakpoint;
1844 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1846 *lenptr = sizeof (big_breakpoint);
1847 return big_breakpoint;
1851 *lenptr = sizeof (little_breakpoint);
1852 return little_breakpoint;
1857 /* Call0 ABI support routines. */
1859 /* Call0 opcode class. Opcodes are preclassified according to what they
1860 mean for Call0 prologue analysis, and their number of significant operands.
1861 The purpose of this is to simplify prologue analysis by separating
1862 instruction decoding (libisa) from the semantics of prologue analysis. */
1865 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1866 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1867 c0opc_flow, /* Flow control insn. */
1868 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1869 c0opc_break, /* Debugger software breakpoints. */
1870 c0opc_add, /* Adding two registers. */
1871 c0opc_addi, /* Adding a register and an immediate. */
1872 c0opc_sub, /* Subtracting a register from a register. */
1873 c0opc_mov, /* Moving a register to a register. */
1874 c0opc_movi, /* Moving an immediate to a register. */
1875 c0opc_l32r, /* Loading a literal. */
1876 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1877 c0opc_NrOf /* Number of opcode classifications. */
1881 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1883 static xtensa_insn_kind
1884 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1886 const char *opcname;
1887 xtensa_insn_kind opclass = c0opc_uninteresting;
1889 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1891 /* Get opcode name and handle special classifications. */
1893 opcname = xtensa_opcode_name (isa, opc);
1896 || strcasecmp (opcname, "ill") == 0
1897 || strcasecmp (opcname, "ill.n") == 0)
1898 opclass = c0opc_illegal;
1899 else if (strcasecmp (opcname, "break") == 0
1900 || strcasecmp (opcname, "break.n") == 0)
1901 opclass = c0opc_break;
1902 else if (strcasecmp (opcname, "entry") == 0)
1903 opclass = c0opc_entry;
1904 else if (xtensa_opcode_is_branch (isa, opc) > 0
1905 || xtensa_opcode_is_jump (isa, opc) > 0
1906 || xtensa_opcode_is_loop (isa, opc) > 0
1907 || xtensa_opcode_is_call (isa, opc) > 0
1908 || strcasecmp (opcname, "simcall") == 0
1909 || strcasecmp (opcname, "syscall") == 0)
1910 opclass = c0opc_flow;
1912 /* Also, classify specific opcodes that need to be tracked. */
1913 else if (strcasecmp (opcname, "add") == 0
1914 || strcasecmp (opcname, "add.n") == 0)
1915 opclass = c0opc_add;
1916 else if (strcasecmp (opcname, "addi") == 0
1917 || strcasecmp (opcname, "addi.n") == 0
1918 || strcasecmp (opcname, "addmi") == 0)
1919 opclass = c0opc_addi;
1920 else if (strcasecmp (opcname, "sub") == 0)
1921 opclass = c0opc_sub;
1922 else if (strcasecmp (opcname, "mov.n") == 0
1923 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1924 opclass = c0opc_mov;
1925 else if (strcasecmp (opcname, "movi") == 0
1926 || strcasecmp (opcname, "movi.n") == 0)
1927 opclass = c0opc_movi;
1928 else if (strcasecmp (opcname, "l32r") == 0)
1929 opclass = c0opc_l32r;
1930 else if (strcasecmp (opcname, "s32i") == 0
1931 || strcasecmp (opcname, "s32i.n") == 0)
1932 opclass = c0opc_s32i;
1937 /* Tracks register movement/mutation for a given operation, which may
1938 be within a bundle. Updates the destination register tracking info
1939 accordingly. The pc is needed only for pc-relative load instructions
1940 (eg. l32r). The SP register number is needed to identify stores to
1944 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1945 xtensa_insn_kind opclass, int nods, unsigned odv[],
1946 CORE_ADDR pc, int spreg)
1948 unsigned litbase, litaddr, litval;
1953 /* 3 operands: dst, src, imm. */
1954 gdb_assert (nods == 3);
1955 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1956 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1959 /* 3 operands: dst, src1, src2. */
1960 gdb_assert (nods == 3);
1961 if (src[odv[1]].fr_reg == C0_CONST)
1963 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
1964 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
1966 else if (src[odv[2]].fr_reg == C0_CONST)
1968 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1969 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
1971 else dst[odv[0]].fr_reg = C0_INEXP;
1974 /* 3 operands: dst, src1, src2. */
1975 gdb_assert (nods == 3);
1976 if (src[odv[2]].fr_reg == C0_CONST)
1978 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1979 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
1981 else dst[odv[0]].fr_reg = C0_INEXP;
1984 /* 2 operands: dst, src [, src]. */
1985 gdb_assert (nods == 2);
1986 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1987 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
1990 /* 2 operands: dst, imm. */
1991 gdb_assert (nods == 2);
1992 dst[odv[0]].fr_reg = C0_CONST;
1993 dst[odv[0]].fr_ofs = odv[1];
1996 /* 2 operands: dst, literal offset. */
1997 gdb_assert (nods == 2);
1998 /* litbase = xtensa_get_litbase (pc); can be also used. */
1999 litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1)
2000 ? 0 : xtensa_read_register
2001 (gdbarch_tdep (current_gdbarch)->litbase_regnum);
2002 litaddr = litbase & 1
2003 ? (litbase & ~1) + (signed)odv[1]
2004 : (pc + 3 + (signed)odv[1]) & ~3;
2005 litval = read_memory_integer(litaddr, 4);
2006 dst[odv[0]].fr_reg = C0_CONST;
2007 dst[odv[0]].fr_ofs = litval;
2010 /* 3 operands: value, base, offset. */
2011 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2012 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2013 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2014 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2015 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2016 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2018 /* ISA encoding guarantees alignment. But, check it anyway. */
2019 gdb_assert ((odv[2] & 3) == 0);
2020 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2028 /* Analyze prologue of the function at start address to determine if it uses
2029 the Call0 ABI, and if so track register moves and linear modifications
2030 in the prologue up to the PC or just beyond the prologue, whichever is first.
2031 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2032 The prologue may overlap non-prologue instructions but is guaranteed to end
2033 by the first flow-control instruction (jump, branch, call or return).
2034 Since an optimized function may move information around and change the
2035 stack frame arbitrarily during the prologue, the information is guaranteed
2036 valid only at the point in the function indicated by the PC.
2037 May be used to skip the prologue or identify the ABI, w/o tracking.
2039 Returns: Address of first instruction after prologue, or PC (whichever
2040 is first), or 0, if decoding failed (in libisa).
2042 start Start address of function/prologue.
2043 pc Program counter to stop at. Use 0 to continue to end of prologue.
2044 If 0, avoids infinite run-on in corrupt code memory by bounding
2045 the scan to the end of the function if that can be determined.
2046 nregs Number of general registers to track (size of rt[] array).
2048 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2049 If NULL, registers are not tracked.
2051 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2052 (more accurately, non-zero until 'entry' insn is encountered).
2054 Note that these may produce useful results even if decoding fails
2055 because they begin with default assumptions that analysis may change. */
2058 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
2059 int nregs, xtensa_c0reg_t rt[], int *call0)
2061 CORE_ADDR ia; /* Current insn address in prologue. */
2062 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2063 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2064 #define BSZ 32 /* Instruction buffer size. */
2065 char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
2066 xtensa_isa isa; /* libisa ISA handle. */
2067 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2068 xtensa_format ifmt; /* libisa instruction format. */
2069 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2070 xtensa_opcode opc; /* Opcode in current slot. */
2071 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2072 int nods; /* Opcode number of operands. */
2073 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2074 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2075 int j; /* General loop counter. */
2076 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2077 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2078 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2080 struct symtab_and_line prologue_sal;
2082 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2083 (int)start, (int)pc);
2085 /* Try to limit the scan to the end of the function if a non-zero pc
2086 arg was not supplied to avoid probing beyond the end of valid memory.
2087 If memory is full of garbage that classifies as c0opc_uninteresting.
2088 If this fails (eg. if no symbols) pc ends up 0 as it was.
2089 Intialize the Call0 frame and register tracking info.
2090 Assume it's Call0 until an 'entry' instruction is encountered.
2091 Assume we may be in the prologue until we hit a flow control instr. */
2097 /* Find out, if we have an information about the prologue from DWARF. */
2098 prologue_sal = find_pc_line (start, 0);
2099 if (prologue_sal.line != 0) /* Found debug info. */
2100 body_pc = prologue_sal.end;
2102 /* If we are going to analyze the prologue in general without knowing about
2103 the current PC, make the best assumtion for the end of the prologue. */
2106 find_pc_partial_function (start, 0, NULL, &end_pc);
2107 body_pc = min (end_pc, body_pc);
2110 body_pc = min (pc, body_pc);
2117 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2118 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2122 if (!xtensa_default_isa)
2123 xtensa_default_isa = xtensa_isa_init (0, 0);
2124 isa = xtensa_default_isa;
2125 gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
2126 ins = xtensa_insnbuf_alloc (isa);
2127 slot = xtensa_insnbuf_alloc (isa);
2129 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2131 /* (Re)fill instruction buffer from memory if necessary, but do not
2132 read memory beyond PC to be sure we stay within text section
2133 (this protection only works if a non-zero pc is supplied). */
2135 if (ia + xtensa_isa_maxlength (isa) > bt)
2138 bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
2139 read_memory (ba, ibuf, bt - ba);
2142 /* Decode format information. */
2144 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2145 ifmt = xtensa_format_decode (isa, ins);
2146 if (ifmt == XTENSA_UNDEFINED)
2151 ilen = xtensa_format_length (isa, ifmt);
2152 if (ilen == XTENSA_UNDEFINED)
2157 islots = xtensa_format_num_slots (isa, ifmt);
2158 if (islots == XTENSA_UNDEFINED)
2164 /* Analyze a bundle or a single instruction, using a snapshot of
2165 the register tracking info as input for the entire bundle so that
2166 register changes do not take effect within this bundle. */
2168 for (j = 0; j < nregs; ++j)
2171 for (is = 0; is < islots; ++is)
2173 /* Decode a slot and classify the opcode. */
2175 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2179 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2180 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2182 if (opc == XTENSA_UNDEFINED)
2183 opclass = c0opc_illegal;
2185 opclass = call0_classify_opcode (isa, opc);
2187 /* Decide whether to track this opcode, ignore it, or bail out. */
2196 case c0opc_uninteresting:
2205 ia += ilen; /* Skip over 'entry' insn. */
2213 /* Only expected opcodes should get this far. */
2217 /* Extract and decode the operands. */
2218 nods = xtensa_opcode_num_operands (isa, opc);
2219 if (nods == XTENSA_UNDEFINED)
2225 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2227 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2232 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2237 /* Check operands to verify use of 'mov' assembler macro. */
2238 if (opclass == c0opc_mov && nods == 3)
2240 if (odv[2] == odv[1])
2244 opclass = c0opc_uninteresting;
2249 /* Track register movement and modification for this operation. */
2250 call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
2254 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2255 (unsigned)ia, fail ? "failed" : "succeeded");
2256 xtensa_insnbuf_free(isa, slot);
2257 xtensa_insnbuf_free(isa, ins);
2258 return fail ? 0 : ia;
2261 /* Initialize frame cache for the current frame. The "next_frame" is the next
2262 one relative to current frame. "cache" is the pointer to the data structure
2263 we have to initialize. "pc" is curretnt PC. */
2266 call0_frame_cache (struct frame_info *next_frame,
2267 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2269 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2270 CORE_ADDR start_pc; /* The beginning of the function. */
2271 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2272 CORE_ADDR sp, fp, ra;
2273 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2275 /* Find the beginning of the prologue of the function containing the PC
2276 and analyze it up to the PC or the end of the prologue. */
2278 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2280 body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
2281 &cache->c0.c0_rt[0],
2285 sp = frame_unwind_register_unsigned
2286 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2287 fp = sp; /* Assume FP == SP until proven otherwise. */
2289 /* Get the frame information and FP (if used) at the current PC.
2290 If PC is in the prologue, the prologue analysis is more reliable
2291 than DWARF info. We don't not know for sure if PC is in the prologue,
2292 but we know no calls have yet taken place, so we can almost
2293 certainly rely on the prologue analysis. */
2297 /* Prologue analysis was successful up to the PC.
2298 It includes the cases when PC == START_PC. */
2299 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2300 /* c0_hasfp == true means there is a frame pointer because
2301 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2302 was derived from SP. Otherwise, it would be C0_FP. */
2303 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2304 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2305 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2307 else /* No data from the prologue analysis. */
2310 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2315 prev_sp = fp + c0_frmsz;
2317 /* Frame size from debug info or prologue tracking does not account for
2318 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2321 fp = frame_unwind_register_unsigned (next_frame, fp_regnum);
2323 /* Recalculate previous SP. */
2324 prev_sp = fp + c0_frmsz;
2325 /* Update the stack frame size. */
2326 c0_frmsz += fp - sp;
2329 /* Get the return address (RA) from the stack if saved,
2330 or try to get it from a register. */
2332 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2333 if (to_stk != C0_NOSTK)
2335 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2337 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2338 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2340 /* Special case for terminating backtrace at a function that wants to
2341 be seen as the outermost. Such a function will clear it's RA (A0)
2342 register to 0 in the prologue instead of saving its original value. */
2347 /* RA was copied to another register or (before any function call) may
2348 still be in the original RA register. This is not always reliable:
2349 even in a leaf function, register tracking stops after prologue, and
2350 even in prologue, non-prologue instructions (not tracked) may overwrite
2351 RA or any register it was copied to. If likely in prologue or before
2352 any call, use retracking info and hope for the best (compiler should
2353 have saved RA in stack if not in a leaf function). If not in prologue,
2359 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2361 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2363 if (i < C0_NREGS) /* Read from the next_frame. */
2365 ra = frame_unwind_register_unsigned
2367 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2372 cache->pc = start_pc;
2374 /* RA == 0 marks the outermost frame. Do not go past it. */
2375 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2376 cache->c0.fp_regnum = fp_regnum;
2377 cache->c0.c0_frmsz = c0_frmsz;
2378 cache->c0.c0_hasfp = c0_hasfp;
2379 cache->c0.c0_fp = fp;
2383 /* Skip function prologue.
2385 Return the pc of the first instruction after prologue. GDB calls this to
2386 find the address of the first line of the function or (if there is no line
2387 number information) to skip the prologue for planting breakpoints on
2388 function entries. Use debug info (if present) or prologue analysis to skip
2389 the prologue to achieve reliable debugging behavior. For windowed ABI,
2390 only the 'entry' instruction is skipped. It is not strictly necessary to
2391 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2392 backtrace at any point in the prologue, however certain potential hazards
2393 are avoided and a more "normal" debugging experience is ensured by
2394 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2395 For example, if we don't skip the prologue:
2396 - Some args may not yet have been saved to the stack where the debug
2397 info expects to find them (true anyway when only 'entry' is skipped);
2398 - Software breakpoints ('break' instrs) may not have been unplanted
2399 when the prologue analysis is done on initializing the frame cache,
2400 and breaks in the prologue will throw off the analysis.
2402 If we have debug info ( line-number info, in particular ) we simply skip
2403 the code associated with the first function line effectively skipping
2404 the prologue code. It works even in cases like
2407 { int local_var = 1;
2411 because, for this source code, both Xtensa compilers will generate two
2412 separate entries ( with the same line number ) in dwarf line-number
2413 section to make sure there is a boundary between the prologue code and
2414 the rest of the function.
2416 If there is no debug info, we need to analyze the code. */
2418 /* #define DONT_SKIP_PROLOGUE */
2421 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2423 struct symtab_and_line prologue_sal;
2426 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2428 #if DONT_SKIP_PROLOGUE
2432 /* Try to find first body line from debug info. */
2434 prologue_sal = find_pc_line (start_pc, 0);
2435 if (prologue_sal.line != 0) /* Found debug info. */
2437 /* In Call0, it is possible to have a function with only one instruction
2438 ('ret') resulting from a 1-line optimized function that does nothing.
2439 In that case, prologue_sal.end may actually point to the start of the
2440 next function in the text section, causing a breakpoint to be set at
2441 the wrong place. Check if the end address is in a different function,
2442 and if so return the start PC. We know we have symbol info. */
2446 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2447 if (end_func != start_pc)
2450 return prologue_sal.end;
2453 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2454 body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
2455 return body_pc != 0 ? body_pc : start_pc;
2458 /* Verify the current configuration. */
2460 xtensa_verify_config (struct gdbarch *gdbarch)
2462 struct ui_file *log;
2463 struct cleanup *cleanups;
2464 struct gdbarch_tdep *tdep;
2468 tdep = gdbarch_tdep (gdbarch);
2469 log = mem_fileopen ();
2470 cleanups = make_cleanup_ui_file_delete (log);
2472 /* Verify that we got a reasonable number of AREGS. */
2473 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2474 fprintf_unfiltered (log, _("\
2475 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2478 /* Verify that certain registers exist. */
2480 if (tdep->pc_regnum == -1)
2481 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2482 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2483 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2485 if (tdep->isa_use_windowed_registers)
2487 if (tdep->wb_regnum == -1)
2488 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2489 if (tdep->ws_regnum == -1)
2490 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2491 if (tdep->ar_base == -1)
2492 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2495 if (tdep->a0_base == -1)
2496 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2498 buf = ui_file_xstrdup (log, &dummy);
2499 make_cleanup (xfree, buf);
2500 if (strlen (buf) > 0)
2501 internal_error (__FILE__, __LINE__,
2502 _("the following are invalid: %s"), buf);
2503 do_cleanups (cleanups);
2507 /* Derive specific register numbers from the array of registers. */
2510 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2512 xtensa_register_t* rmap;
2513 int n, max_size = 4;
2516 tdep->num_nopriv_regs = 0;
2518 /* Special registers 0..255 (core). */
2519 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2521 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2523 if (rmap->target_number == 0x0020)
2524 tdep->pc_regnum = n;
2525 else if (rmap->target_number == 0x0100)
2527 else if (rmap->target_number == 0x0000)
2529 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2530 tdep->wb_regnum = n;
2531 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2532 tdep->ws_regnum = n;
2533 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2534 tdep->debugcause_regnum = n;
2535 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2536 tdep->exccause_regnum = n;
2537 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2538 tdep->excvaddr_regnum = n;
2539 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2540 tdep->lbeg_regnum = n;
2541 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2542 tdep->lend_regnum = n;
2543 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2544 tdep->lcount_regnum = n;
2545 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2546 tdep->sar_regnum = n;
2547 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2548 tdep->litbase_regnum = n;
2549 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2550 tdep->ps_regnum = n;
2552 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2553 tdep->interrupt_regnum = n;
2554 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2555 tdep->interrupt2_regnum = n;
2556 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2557 tdep->cpenable_regnum = n;
2560 if (rmap->byte_size > max_size)
2561 max_size = rmap->byte_size;
2562 if (rmap->mask != 0 && tdep->num_regs == 0)
2564 /* Find out out how to deal with priveleged registers.
2566 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2567 && tdep->num_nopriv_regs == 0)
2568 tdep->num_nopriv_regs = n;
2570 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2571 && tdep->num_regs == 0)
2575 /* Number of pseudo registers. */
2576 tdep->num_pseudo_regs = n - tdep->num_regs;
2578 /* Empirically determined maximum sizes. */
2579 tdep->max_register_raw_size = max_size;
2580 tdep->max_register_virtual_size = max_size;
2583 /* Module "constructor" function. */
2585 extern struct gdbarch_tdep xtensa_tdep;
2587 static struct gdbarch *
2588 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2590 struct gdbarch_tdep *tdep;
2591 struct gdbarch *gdbarch;
2592 struct xtensa_abi_handler *abi_handler;
2594 DEBUGTRACE ("gdbarch_init()\n");
2596 /* We have to set the byte order before we call gdbarch_alloc. */
2597 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
2599 tdep = &xtensa_tdep;
2600 gdbarch = gdbarch_alloc (&info, tdep);
2601 xtensa_derive_tdep (tdep);
2603 /* Verify our configuration. */
2604 xtensa_verify_config (gdbarch);
2606 /* Pseudo-Register read/write. */
2607 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2608 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2610 /* Set target information. */
2611 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2612 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2613 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2614 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2615 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2617 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
2618 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2619 set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2620 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2622 /* We provide our own function to get register information. */
2623 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2624 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2626 /* To call functions from GDB using dummy frame */
2627 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2629 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2631 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2633 /* Advance PC across any prologue instructions to reach "real" code. */
2634 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2636 /* Stack grows downward. */
2637 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2639 /* Set breakpoints. */
2640 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2642 /* After breakpoint instruction or illegal instruction, pc still
2643 points at break instruction, so don't decrement. */
2644 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2646 /* We don't skip args. */
2647 set_gdbarch_frame_args_skip (gdbarch, 0);
2649 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2651 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2653 set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id);
2655 /* Frame handling. */
2656 frame_base_set_default (gdbarch, &xtensa_frame_base);
2657 frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer);
2659 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2661 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2663 xtensa_add_reggroups (gdbarch);
2664 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2666 set_gdbarch_regset_from_core_section (gdbarch,
2667 xtensa_regset_from_core_section);
2673 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2675 error (_("xtensa_dump_tdep(): not implemented"));
2679 _initialize_xtensa_tdep (void)
2681 struct cmd_list_element *c;
2683 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2684 xtensa_init_reggroups ();
2686 add_setshow_zinteger_cmd ("xtensa",
2688 &xtensa_debug_level, _("\
2689 Set Xtensa debugging."), _("\
2690 Show Xtensa debugging."), _("\
2691 When non-zero, Xtensa-specific debugging is enabled. \
2692 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2695 &setdebuglist, &showdebuglist);