1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
58 static int xtensa_debug_level = 0;
60 #define DEBUGWARN(args...) \
61 if (xtensa_debug_level > 0) \
62 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
64 #define DEBUGINFO(args...) \
65 if (xtensa_debug_level > 1) \
66 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
68 #define DEBUGTRACE(args...) \
69 if (xtensa_debug_level > 2) \
70 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
72 #define DEBUGVERB(args...) \
73 if (xtensa_debug_level > 3) \
74 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
77 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* On Windowed ABI, we use a6 through a11 for passing arguments
82 to a function called by GDB because CALL4 is used. */
83 #define ARGS_FIRST_REG A6_REGNUM
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
95 /* Convert a live Ax register number to the corresponding Areg number. */
96 #define AREG_NUMBER(r, wb) \
97 ((((r) - A0_REGNUM + (((wb) & WB_MASK) << WB_SHIFT)) & AREGS_MASK) + AR_BASE)
99 /* ABI-independent macros. */
100 #define ARG_NOF (CALL_ABI == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
101 #define ARG_1ST (CALL_ABI == CallAbiCall0Only \
102 ? (A0_REGNUM) + C0_ARGS : (ARGS_FIRST_REG))
104 extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *);
105 extern int xtensa_config_byte_order (struct gdbarch_info *);
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(op1) \
112 ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (CORE_ADDR ps)
127 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
130 /* Return the window size of the previous call to the function from which we
133 This function is used to extract the return value after a called function
134 has returned to the caller. On Xtensa, the register that holds the return
135 value (from the perspective of the caller) depends on what call
136 instruction was used. For now, we are assuming that the call instruction
137 precedes the current address, so we simply analyze the call instruction.
138 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
139 method to call the inferior function. */
142 extract_call_winsize (CORE_ADDR pc)
148 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
150 /* Read the previous instruction (should be a call[x]{4|8|12}. */
151 read_memory (pc-3, buf, 3);
152 insn = extract_unsigned_integer (buf, 3);
154 /* Decode call instruction:
156 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
157 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
159 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
160 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
162 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
164 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
165 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
169 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
170 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
176 /* REGISTER INFORMATION */
178 /* Returns the name of a register. */
180 xtensa_register_name (int regnum)
182 /* Return the name stored in the register map. */
183 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
184 + gdbarch_num_pseudo_regs (current_gdbarch))
185 return REGMAP[regnum].name;
187 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
192 xtensa_read_register (int regnum)
196 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
197 return (unsigned long) value;
200 /* Return the type of a register. Create a new type, if necessary. */
202 static struct ctype_cache
204 struct ctype_cache *next;
206 struct type *virtual_type;
207 } *type_entries = NULL;
210 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
212 /* Return signed integer for ARx and Ax registers. */
213 if ((regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
214 || (regnum >= A0_BASE && regnum < A0_BASE + 16))
215 return builtin_type_int;
217 if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == A1_REGNUM)
218 return lookup_pointer_type (builtin_type_void);
220 /* Return the stored type for all other registers. */
221 else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
222 + gdbarch_num_pseudo_regs (current_gdbarch))
224 xtensa_register_t* reg = ®MAP[regnum];
226 /* Set ctype for this register (only the first time). */
230 struct ctype_cache *tp;
231 int size = reg->byte_size;
233 /* We always use the memory representation,
234 even if the register width is smaller. */
238 reg->ctype = builtin_type_uint8;
242 reg->ctype = builtin_type_uint16;
246 reg->ctype = builtin_type_uint32;
250 reg->ctype = builtin_type_uint64;
254 reg->ctype = builtin_type_uint128;
258 for (tp = type_entries; tp != NULL; tp = tp->next)
259 if (tp->size == size)
264 char *name = xmalloc (16);
265 tp = xmalloc (sizeof (struct ctype_cache));
266 tp->next = type_entries;
270 sprintf (name, "int%d", size * 8);
271 tp->virtual_type = init_type (TYPE_CODE_INT, size,
272 TYPE_FLAG_UNSIGNED, name,
276 reg->ctype = tp->virtual_type;
282 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
287 /* Return the 'local' register number for stubs, dwarf2, etc.
288 The debugging information enumerates registers starting from 0 for A0
289 to n for An. So, we only have to add the base number for A0. */
292 xtensa_reg_to_regnum (int regnum)
296 if (regnum >= 0 && regnum < 16)
297 return A0_BASE + regnum;
300 i < gdbarch_num_regs (current_gdbarch)
301 + gdbarch_num_pseudo_regs (current_gdbarch);
303 if (regnum == REGMAP[i].target_number)
306 internal_error (__FILE__, __LINE__,
307 _("invalid dwarf/stabs register number %d"), regnum);
312 /* Write the bits of a masked register to the various registers.
313 Only the masked areas of these registers are modified; the other
314 fields are untouched. The size of masked registers is always less
315 than or equal to 32 bits. */
318 xtensa_register_write_masked (struct regcache *regcache,
319 xtensa_register_t *reg, const gdb_byte *buffer)
321 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
322 const xtensa_mask_t *mask = reg->mask;
324 int shift = 0; /* Shift for next mask (mod 32). */
325 int start, size; /* Start bit and size of current mask. */
327 unsigned int *ptr = value;
328 unsigned int regval, m, mem = 0;
330 int bytesize = reg->byte_size;
331 int bitsize = bytesize * 8;
334 DEBUGTRACE ("xtensa_register_write_masked ()\n");
336 /* Copy the masked register to host byte-order. */
337 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
338 for (i = 0; i < bytesize; i++)
341 mem |= (buffer[bytesize - i - 1] << 24);
346 for (i = 0; i < bytesize; i++)
349 mem |= (buffer[i] << 24);
354 /* We might have to shift the final value:
355 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
356 bytesize & 3 == x -> shift (4-x) * 8. */
358 *ptr = mem >> (((0 - bytesize) & 3) * 8);
362 /* Write the bits to the masked areas of the other registers. */
363 for (i = 0; i < mask->count; i++)
365 start = mask->mask[i].bit_start;
366 size = mask->mask[i].bit_size;
367 regval = mem >> shift;
369 if ((shift += size) > bitsize)
370 error (_("size of all masks is larger than the register"));
379 regval |= mem << (size - shift);
382 /* Make sure we have a valid register. */
383 r = mask->mask[i].reg_num;
384 if (r >= 0 && size > 0)
386 /* Don't overwrite the unmasked areas. */
388 regcache_cooked_read_unsigned (regcache, r, &old_val);
389 m = 0xffffffff >> (32 - size) << start;
391 regval = (regval & m) | (old_val & ~m);
392 regcache_cooked_write_unsigned (regcache, r, regval);
398 /* Read a tie state or mapped registers. Read the masked areas
399 of the registers and assemble them into a single value. */
402 xtensa_register_read_masked (struct regcache *regcache,
403 xtensa_register_t *reg, gdb_byte *buffer)
405 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
406 const xtensa_mask_t *mask = reg->mask;
411 unsigned int *ptr = value;
412 unsigned int regval, mem = 0;
414 int bytesize = reg->byte_size;
415 int bitsize = bytesize * 8;
418 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
419 reg->name == 0 ? "" : reg->name);
421 /* Assemble the register from the masked areas of other registers. */
422 for (i = 0; i < mask->count; i++)
424 int r = mask->mask[i].reg_num;
428 regcache_cooked_read_unsigned (regcache, r, &val);
429 regval = (unsigned int) val;
434 start = mask->mask[i].bit_start;
435 size = mask->mask[i].bit_size;
440 regval &= (0xffffffff >> (32 - size));
442 mem |= regval << shift;
444 if ((shift += size) > bitsize)
445 error (_("size of all masks is larger than the register"));
456 mem = regval >> (size - shift);
463 /* Copy value to target byte order. */
467 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
468 for (i = 0; i < bytesize; i++)
472 buffer[bytesize - i - 1] = mem & 0xff;
476 for (i = 0; i < bytesize; i++)
480 buffer[i] = mem & 0xff;
486 /* Read pseudo registers. */
489 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
490 struct regcache *regcache,
494 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
495 regnum, xtensa_register_name (regnum));
497 if (regnum == FP_ALIAS)
500 /* Read aliases a0..a15, if this is a Windowed ABI. */
501 if (ISA_USE_WINDOWED_REGISTERS
502 && (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM))
504 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
506 regcache_raw_read (regcache, WB_REGNUM, buf);
507 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
510 /* We can always read non-pseudo registers. */
511 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
512 regcache_raw_read (regcache, regnum, buffer);
514 /* Pseudo registers. */
516 && regnum < gdbarch_num_regs (current_gdbarch)
517 + gdbarch_num_pseudo_regs (current_gdbarch))
519 xtensa_register_t *reg = ®MAP[regnum];
520 xtensa_register_type_t type = reg->type;
521 int flags = XTENSA_TARGET_FLAGS;
523 /* We cannot read Unknown or Unmapped registers. */
524 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
526 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
528 warning (_("cannot read register %s"),
529 xtensa_register_name (regnum));
534 /* Some targets cannot read TIE register files. */
535 else if (type == xtRegisterTypeTieRegfile)
537 /* Use 'fetch' to get register? */
538 if (flags & xtTargetFlagsUseFetchStore)
540 warning (_("cannot read register"));
544 /* On some targets (esp. simulators), we can always read the reg. */
545 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
547 warning (_("cannot read register"));
552 /* We can always read mapped registers. */
553 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
555 xtensa_register_read_masked (regcache, reg, buffer);
559 /* Assume that we can read the register. */
560 regcache_raw_read (regcache, regnum, buffer);
563 internal_error (__FILE__, __LINE__,
564 _("invalid register number %d"), regnum);
568 /* Write pseudo registers. */
571 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
572 struct regcache *regcache,
574 const gdb_byte *buffer)
576 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
577 regnum, xtensa_register_name (regnum));
579 if (regnum == FP_ALIAS)
582 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
583 if (ISA_USE_WINDOWED_REGISTERS
584 && (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM))
586 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
589 regcache_raw_read (regcache, WB_REGNUM, buf);
590 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
593 /* We can always write 'core' registers.
594 Note: We might have converted Ax->ARy. */
595 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
596 regcache_raw_write (regcache, regnum, buffer);
598 /* Pseudo registers. */
600 && regnum < gdbarch_num_regs (current_gdbarch)
601 + gdbarch_num_pseudo_regs (current_gdbarch))
603 xtensa_register_t *reg = ®MAP[regnum];
604 xtensa_register_type_t type = reg->type;
605 int flags = XTENSA_TARGET_FLAGS;
607 /* On most targets, we cannot write registers
608 of type "Unknown" or "Unmapped". */
609 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
611 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
613 warning (_("cannot write register %s"),
614 xtensa_register_name (regnum));
619 /* Some targets cannot read TIE register files. */
620 else if (type == xtRegisterTypeTieRegfile)
622 /* Use 'store' to get register? */
623 if (flags & xtTargetFlagsUseFetchStore)
625 warning (_("cannot write register"));
629 /* On some targets (esp. simulators), we can always write
631 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
633 warning (_("cannot write register"));
638 /* We can always write mapped registers. */
639 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
641 xtensa_register_write_masked (regcache, reg, buffer);
645 /* Assume that we can write the register. */
646 regcache_raw_write (regcache, regnum, buffer);
649 internal_error (__FILE__, __LINE__,
650 _("invalid register number %d"), regnum);
653 static struct reggroup *xtensa_ar_reggroup;
654 static struct reggroup *xtensa_user_reggroup;
655 static struct reggroup *xtensa_vectra_reggroup;
656 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
659 xtensa_init_reggroups (void)
661 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
662 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
663 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
665 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
666 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
667 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
668 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
669 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
670 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
671 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
672 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
676 xtensa_add_reggroups (struct gdbarch *gdbarch)
680 /* Predefined groups. */
681 reggroup_add (gdbarch, all_reggroup);
682 reggroup_add (gdbarch, save_reggroup);
683 reggroup_add (gdbarch, restore_reggroup);
684 reggroup_add (gdbarch, system_reggroup);
685 reggroup_add (gdbarch, vector_reggroup);
686 reggroup_add (gdbarch, general_reggroup);
687 reggroup_add (gdbarch, float_reggroup);
689 /* Xtensa-specific groups. */
690 reggroup_add (gdbarch, xtensa_ar_reggroup);
691 reggroup_add (gdbarch, xtensa_user_reggroup);
692 reggroup_add (gdbarch, xtensa_vectra_reggroup);
694 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
695 reggroup_add (gdbarch, xtensa_cp[i]);
699 xtensa_coprocessor_register_group (struct reggroup *group)
703 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
704 if (group == xtensa_cp[i])
710 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
711 | XTENSA_REGISTER_FLAGS_WRITABLE \
712 | XTENSA_REGISTER_FLAGS_VOLATILE)
714 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
715 | XTENSA_REGISTER_FLAGS_WRITABLE)
718 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
720 struct reggroup *group)
722 xtensa_register_t* reg = ®MAP[regnum];
723 xtensa_register_type_t type = reg->type;
724 xtensa_register_group_t rg = reg->group;
727 /* First, skip registers that are not visible to this target
728 (unknown and unmapped registers when not using ISS). */
730 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
732 if (group == all_reggroup)
734 if (group == xtensa_ar_reggroup)
735 return rg & xtRegisterGroupAddrReg;
736 if (group == xtensa_user_reggroup)
737 return rg & xtRegisterGroupUser;
738 if (group == float_reggroup)
739 return rg & xtRegisterGroupFloat;
740 if (group == general_reggroup)
741 return rg & xtRegisterGroupGeneral;
742 if (group == float_reggroup)
743 return rg & xtRegisterGroupFloat;
744 if (group == system_reggroup)
745 return rg & xtRegisterGroupState;
746 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
747 return rg & xtRegisterGroupVectra;
748 if (group == save_reggroup || group == restore_reggroup)
749 return (regnum < gdbarch_num_regs (current_gdbarch)
750 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
751 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
752 return rg & (xtRegisterGroupCP0 << cp_number);
758 /* Supply register REGNUM from the buffer specified by GREGS and LEN
759 in the general-purpose register set REGSET to register cache
760 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
763 xtensa_supply_gregset (const struct regset *regset,
769 const xtensa_elf_gregset_t *regs = gregs;
772 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
774 if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == -1)
775 regcache_raw_supply (rc,
776 gdbarch_pc_regnum (current_gdbarch),
778 if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1)
779 regcache_raw_supply (rc, gdbarch_ps_regnum (current_gdbarch),
781 if (regnum == WB_REGNUM || regnum == -1)
782 regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase);
783 if (regnum == WS_REGNUM || regnum == -1)
784 regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart);
785 if (regnum == LBEG_REGNUM || regnum == -1)
786 regcache_raw_supply (rc, LBEG_REGNUM, (char *) ®s->lbeg);
787 if (regnum == LEND_REGNUM || regnum == -1)
788 regcache_raw_supply (rc, LEND_REGNUM, (char *) ®s->lend);
789 if (regnum == LCOUNT_REGNUM || regnum == -1)
790 regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount);
791 if (regnum == SAR_REGNUM || regnum == -1)
792 regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar);
793 if (regnum == EXCCAUSE_REGNUM || regnum == -1)
794 regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause);
795 if (regnum == EXCVADDR_REGNUM || regnum == -1)
796 regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr);
797 if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
798 regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]);
799 else if (regnum == -1)
801 for (i = 0; i < NUM_AREGS; ++i)
802 regcache_raw_supply (rc, AR_BASE + i, (char *) ®s->ar[i]);
807 /* Xtensa register set. */
813 xtensa_supply_gregset
817 /* Return the appropriate register set for the core
818 section identified by SECT_NAME and SECT_SIZE. */
820 static const struct regset *
821 xtensa_regset_from_core_section (struct gdbarch *core_arch,
822 const char *sect_name,
825 DEBUGTRACE ("xtensa_regset_from_core_section "
826 "(..., sect_name==\"%s\", sect_size==%x) \n",
827 sect_name, sect_size);
829 if (strcmp (sect_name, ".reg") == 0
830 && sect_size >= sizeof(xtensa_elf_gregset_t))
831 return &xtensa_gregset;
837 /* Handling frames. */
839 /* Number of registers to save in case of Windowed ABI. */
840 #define XTENSA_NUM_SAVED_AREGS 12
842 /* Frame cache part for Windowed ABI. */
843 typedef struct xtensa_windowed_frame_cache
845 int wb; /* Base for this frame; -1 if not in regfile. */
846 int callsize; /* Call size to next frame. */
848 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
849 } xtensa_windowed_frame_cache_t;
851 /* Call0 ABI Definitions. */
853 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
854 #define C0_NREGS 16 /* Number of A-registers to track. */
855 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
856 #define C0_SP 1 /* Register used as SP. */
857 #define C0_FP 15 /* Register used as FP. */
858 #define C0_RA 0 /* Register used as return address. */
859 #define C0_ARGS 2 /* Register used as first arg/retval. */
860 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
862 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
863 A-register where the current content of the reg came from (in terms
864 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
865 mean that the orignal content of the register was saved to the stack.
866 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
867 know where SP will end up until the entire prologue has been analyzed. */
869 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
870 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
871 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
873 extern xtensa_isa xtensa_default_isa;
875 typedef struct xtensa_c0reg
877 int fr_reg; /* original register from which register content
878 is derived, or C0_CONST, or C0_INEXP. */
879 int fr_ofs; /* constant offset from reg, or immediate value. */
880 int to_stk; /* offset from original SP to register (4-byte aligned),
881 or C0_NOSTK if register has not been saved. */
885 /* Frame cache part for Call0 ABI. */
886 typedef struct xtensa_call0_frame_cache
888 int c0_frmsz; /* Stack frame size. */
889 int c0_hasfp; /* Current frame uses frame pointer. */
890 int fp_regnum; /* A-register used as FP. */
891 int c0_fp; /* Actual value of frame pointer. */
892 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
893 } xtensa_call0_frame_cache_t;
895 typedef struct xtensa_frame_cache
897 CORE_ADDR base; /* Stack pointer of the next frame. */
898 CORE_ADDR pc; /* PC at the entry point to the function. */
899 CORE_ADDR ra; /* The raw return address. */
900 CORE_ADDR ps; /* The PS register of the frame. */
901 CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
902 int call0; /* It's a call0 framework (else windowed). */
905 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
906 xtensa_call0_frame_cache_t c0; /* call0 == true. */
908 } xtensa_frame_cache_t;
911 static struct xtensa_frame_cache *
912 xtensa_alloc_frame_cache (int windowed)
914 xtensa_frame_cache_t *cache;
917 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
919 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
926 cache->call0 = !windowed;
929 cache->c0.c0_frmsz = -1;
930 cache->c0.c0_hasfp = 0;
931 cache->c0.fp_regnum = -1;
932 cache->c0.c0_fp = -1;
934 for (i = 0; i < C0_NREGS; i++)
936 cache->c0.c0_rt[i].fr_reg = i;
937 cache->c0.c0_rt[i].fr_ofs = 0;
938 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
944 cache->wd.callsize = -1;
946 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
947 cache->wd.aregs[i] = -1;
954 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
956 return address & ~15;
961 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
965 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
967 frame_unwind_register (next_frame, gdbarch_pc_regnum (current_gdbarch), buf);
969 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
970 extract_typed_address (buf, builtin_type_void_func_ptr));
972 return extract_typed_address (buf, builtin_type_void_func_ptr);
976 static struct frame_id
977 xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
981 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
983 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
985 pc = frame_pc_unwind (next_frame);
986 fp = frame_unwind_register_unsigned (next_frame, A1_REGNUM);
988 /* Make dummy frame ID unique by adding a constant. */
989 return frame_id_build (fp + SP_ALIGNMENT, pc);
992 /* The key values to identify the frame using "cache" are
994 cache->base = SP of this frame;
995 cache->pc = entry-PC (entry point of the frame function);
996 cache->prev_sp = SP of the previous frame.
1000 call0_frame_cache (struct frame_info *next_frame,
1001 xtensa_frame_cache_t *cache,
1004 static struct xtensa_frame_cache *
1005 xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
1007 xtensa_frame_cache_t *cache;
1008 CORE_ADDR ra, wb, ws, pc, sp, ps;
1009 unsigned int ps_regnum = gdbarch_ps_regnum (current_gdbarch);
1013 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
1014 next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
1019 windowed = windowing_enabled (xtensa_read_register (ps_regnum));
1021 /* Get pristine xtensa-frame. */
1022 cache = xtensa_alloc_frame_cache (windowed);
1023 *this_cache = cache;
1025 pc = frame_unwind_register_unsigned (next_frame,
1026 gdbarch_pc_regnum (current_gdbarch));
1030 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1031 wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM);
1032 ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM);
1033 ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
1035 op1 = read_memory_integer (pc, 1);
1036 if (XTENSA_IS_ENTRY (op1))
1038 int callinc = CALLINC (ps);
1039 ra = frame_unwind_register_unsigned (next_frame,
1040 A0_REGNUM + callinc * 4);
1042 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
1045 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1046 cache->wd.callsize = 0;
1049 cache->prev_sp = frame_unwind_register_unsigned (next_frame,
1054 ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM);
1055 cache->wd.callsize = WINSIZE (ra);
1056 cache->wd.wb = (wb - cache->wd.callsize / 4) & (NUM_AREGS / 4 - 1);
1057 cache->wd.ws = ws & ~(1 << wb);
1060 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
1061 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1062 cache->ps = (ps & ~PS_CALLINC_MASK)
1063 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1065 if (cache->wd.ws == 0)
1070 sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16;
1072 for (i = 0; i < 4; i++, sp += 4)
1074 cache->wd.aregs[i] = sp;
1077 if (cache->wd.callsize > 4)
1079 /* Set A4...A7/A11. */
1080 /* Read an SP of the previous frame. */
1081 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1082 sp -= cache->wd.callsize * 4;
1084 for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
1086 cache->wd.aregs[i] = sp;
1091 if ((cache->prev_sp == 0) && ( ra != 0 ))
1092 /* If RA is equal to 0 this frame is an outermost frame. Leave
1093 cache->prev_sp unchanged marking the boundary of the frame stack. */
1095 if (cache->wd.ws == 0)
1097 /* Register window overflow already happened.
1098 We can read caller's SP from the proper spill loction. */
1100 read_memory_integer (cache->wd.aregs[1],
1101 register_size (current_gdbarch,
1106 /* Read caller's frame SP directly from the previous window. */
1107 int regnum = AREG_NUMBER (A1_REGNUM, cache->wd.wb);
1109 cache->prev_sp = xtensa_read_register (regnum);
1113 else /* Call0 framework. */
1115 call0_frame_cache (next_frame, cache, pc);
1118 cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM);
1124 xtensa_frame_this_id (struct frame_info *next_frame,
1126 struct frame_id *this_id)
1128 struct xtensa_frame_cache *cache =
1129 xtensa_frame_cache (next_frame, this_cache);
1132 DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n",
1133 (unsigned int) next_frame, (unsigned int) *this_cache);
1135 if (cache->prev_sp == 0)
1138 id = frame_id_build (cache->prev_sp, cache->pc);
1139 if (frame_id_eq (id, get_frame_id(next_frame)))
1142 Frame stack is corrupted. That could happen because of \
1143 setting register(s) from GDB or stopping execution \
1144 inside exception handler. Frame backtracing has stopped. \
1145 It can make some GDB commands work inappropriately.\n"));
1153 call0_frame_get_reg_at_entry (struct frame_info *next_frame,
1154 struct xtensa_frame_cache *cache,
1157 enum lval_type *lval,
1162 int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS))
1163 ? regnum - AR_BASE : regnum;
1165 /* Determine stack pointer on entry to this function, based on FP. */
1166 spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1168 /* If register was saved to the stack frame in the prologue, retrieve it. */
1169 stkofs = cache->c0.c0_rt[reg].to_stk;
1170 if (stkofs != C0_NOSTK)
1172 *lval = lval_memory;
1173 *addrp = spe + stkofs;
1176 read_memory (*addrp, valuep, register_size (current_gdbarch, regnum));
1181 /* If not callee-saved or if known to have been overwritten, give up. */
1183 || cache->c0.c0_rt[reg].fr_reg != reg
1184 || cache->c0.c0_rt[reg].fr_ofs != 0)
1187 if (get_frame_type (next_frame) != NORMAL_FRAME)
1188 /* TODO: Do we need a special case for DUMMY_FRAME here? */
1191 return call0_frame_get_reg_at_entry (get_next_frame(next_frame),
1192 cache, regnum, addrp, lval, valuep);
1196 xtensa_frame_prev_register (struct frame_info *next_frame,
1200 enum lval_type *lvalp,
1205 struct xtensa_frame_cache *cache =
1206 xtensa_frame_cache (next_frame, this_cache);
1207 CORE_ADDR saved_reg = 0;
1210 DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, "
1211 "*this 0x%08x, regnum %d (%s), ...)\n",
1212 (unsigned int) next_frame,
1213 *this_cache ? (unsigned int) *this_cache : 0, regnum,
1214 xtensa_register_name (regnum));
1216 if (regnum ==gdbarch_pc_regnum (current_gdbarch))
1217 saved_reg = cache->ra;
1218 else if (regnum == A1_REGNUM)
1219 saved_reg = cache->prev_sp;
1220 else if (!cache->call0)
1222 if (regnum == WS_REGNUM)
1224 if (cache->wd.ws != 0)
1225 saved_reg = cache->wd.ws;
1227 saved_reg = 1 << cache->wd.wb;
1229 else if (regnum == WB_REGNUM)
1230 saved_reg = cache->wd.wb;
1231 else if (regnum == gdbarch_ps_regnum (current_gdbarch))
1232 saved_reg = cache->ps;
1246 store_unsigned_integer (valuep, 4, saved_reg);
1251 if (!cache->call0) /* Windowed ABI. */
1253 /* Convert A-register numbers to AR-register numbers. */
1254 if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
1255 regnum = AREG_NUMBER (regnum, cache->wd.wb);
1257 /* Check if AR-register has been saved to stack. */
1258 if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS))
1260 int areg = regnum - AR_BASE - (cache->wd.wb * 4);
1263 && areg < XTENSA_NUM_SAVED_AREGS
1264 && cache->wd.aregs[areg] != -1)
1267 *lvalp = lval_memory;
1268 *addrp = cache->wd.aregs[areg];
1272 read_memory (*addrp, valuep,
1273 register_size (current_gdbarch, regnum));
1275 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1280 else /* Call0 ABI. */
1282 int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS))
1283 ? regnum - AR_BASE : regnum;
1290 /* If register was saved in the prologue, retrieve it. */
1291 stkofs = cache->c0.c0_rt[reg].to_stk;
1292 if (stkofs != C0_NOSTK)
1294 /* Determine SP on entry based on FP. */
1295 spe = cache->c0.c0_fp
1296 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1298 *lvalp = lval_memory;
1299 *addrp = spe + stkofs;
1303 read_memory (*addrp, valuep,
1304 register_size (current_gdbarch, regnum));
1306 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1312 /* All other registers have been either saved to
1313 the stack or are still alive in the processor. */
1316 *lvalp = lval_register;
1320 frame_unwind_register (next_frame, (*realnump), valuep);
1324 static const struct frame_unwind
1325 xtensa_frame_unwind =
1328 xtensa_frame_this_id,
1329 xtensa_frame_prev_register
1332 static const struct frame_unwind *
1333 xtensa_frame_sniffer (struct frame_info *next_frame)
1335 return &xtensa_frame_unwind;
1339 xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache)
1341 struct xtensa_frame_cache *cache =
1342 xtensa_frame_cache (next_frame, this_cache);
1347 static const struct frame_base
1350 &xtensa_frame_unwind,
1351 xtensa_frame_base_address,
1352 xtensa_frame_base_address,
1353 xtensa_frame_base_address
1358 xtensa_extract_return_value (struct type *type,
1359 struct regcache *regcache,
1362 bfd_byte *valbuf = dst;
1363 int len = TYPE_LENGTH (type);
1368 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1370 gdb_assert(len > 0);
1372 if (CALL_ABI != CallAbiCall0Only)
1374 /* First, we have to find the caller window in the register file. */
1375 regcache_raw_read_unsigned (regcache,
1376 gdbarch_pc_regnum (current_gdbarch), &pc);
1377 callsize = extract_call_winsize (pc);
1379 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1380 if (len > (callsize > 8 ? 8 : 16))
1381 internal_error (__FILE__, __LINE__,
1382 _("cannot extract return value of %d bytes long"), len);
1384 /* Get the register offset of the return
1385 register (A2) in the caller window. */
1386 regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
1387 areg = AREG_NUMBER(A2_REGNUM + callsize, wb);
1391 /* No windowing hardware - Call0 ABI. */
1392 areg = A0_REGNUM + C0_ARGS;
1395 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1397 if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1400 for (; len > 0; len -= 4, areg++, valbuf += 4)
1403 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1405 regcache_raw_read (regcache, areg, valbuf);
1411 xtensa_store_return_value (struct type *type,
1412 struct regcache *regcache,
1415 const bfd_byte *valbuf = dst;
1419 int len = TYPE_LENGTH (type);
1422 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1424 if (CALL_ABI != CallAbiCall0Only)
1426 regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
1427 regcache_raw_read_unsigned (regcache,
1428 gdbarch_pc_regnum (current_gdbarch), &pc);
1429 callsize = extract_call_winsize (pc);
1431 if (len > (callsize > 8 ? 8 : 16))
1432 internal_error (__FILE__, __LINE__,
1433 _("unimplemented for this length: %d"),
1434 TYPE_LENGTH (type));
1435 areg = AREG_NUMBER (A2_REGNUM + callsize, wb);
1437 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1438 callsize, (int) wb);
1442 areg = A0_REGNUM + C0_ARGS;
1445 if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1448 for (; len > 0; len -= 4, areg++, valbuf += 4)
1451 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1453 regcache_raw_write (regcache, areg, valbuf);
1458 static enum return_value_convention
1459 xtensa_return_value (struct gdbarch *gdbarch,
1460 struct type *valtype,
1461 struct regcache *regcache,
1463 const gdb_byte *writebuf)
1465 /* Structures up to 16 bytes are returned in registers. */
1467 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1468 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1469 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1470 && TYPE_LENGTH (valtype) > 16);
1473 return RETURN_VALUE_STRUCT_CONVENTION;
1475 DEBUGTRACE ("xtensa_return_value(...)\n");
1477 if (writebuf != NULL)
1479 xtensa_store_return_value (valtype, regcache, writebuf);
1482 if (readbuf != NULL)
1484 gdb_assert (!struct_return);
1485 xtensa_extract_return_value (valtype, regcache, readbuf);
1487 return RETURN_VALUE_REGISTER_CONVENTION;
1494 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1495 struct value *function,
1496 struct regcache *regcache,
1499 struct value **args,
1502 CORE_ADDR struct_addr)
1505 int size, onstack_size;
1506 gdb_byte *buf = (gdb_byte *) alloca (16);
1508 struct argument_info
1510 const bfd_byte *contents;
1512 int onstack; /* onstack == 0 => in reg */
1513 int align; /* alignment */
1516 int offset; /* stack offset if on stack */
1517 int regno; /* regno if in register */
1521 struct argument_info *arg_info =
1522 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1526 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1528 if (xtensa_debug_level > 3)
1531 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1532 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1533 "struct_addr=0x%x\n",
1534 (int) sp, (int) struct_return, (int) struct_addr);
1536 for (i = 0; i < nargs; i++)
1538 struct value *arg = args[i];
1539 struct type *arg_type = check_typedef (value_type (arg));
1540 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%08x %3d ",
1541 i, (int) arg, TYPE_LENGTH (arg_type));
1542 switch (TYPE_CODE (arg_type))
1545 fprintf_unfiltered (gdb_stdlog, "int");
1547 case TYPE_CODE_STRUCT:
1548 fprintf_unfiltered (gdb_stdlog, "struct");
1551 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1554 fprintf_unfiltered (gdb_stdlog, " 0x%08x\n",
1555 (unsigned int) value_contents (arg));
1559 /* First loop: collect information.
1560 Cast into type_long. (This shouldn't happen often for C because
1561 GDB already does this earlier.) It's possible that GDB could
1562 do it all the time but it's harmless to leave this code here. */
1569 size = REGISTER_SIZE;
1571 for (i = 0; i < nargs; i++)
1573 struct argument_info *info = &arg_info[i];
1574 struct value *arg = args[i];
1575 struct type *arg_type = check_typedef (value_type (arg));
1577 switch (TYPE_CODE (arg_type))
1580 case TYPE_CODE_BOOL:
1581 case TYPE_CODE_CHAR:
1582 case TYPE_CODE_RANGE:
1583 case TYPE_CODE_ENUM:
1585 /* Cast argument to long if necessary as the mask does it too. */
1586 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1588 arg_type = builtin_type_long;
1589 arg = value_cast (arg_type, arg);
1591 /* Aligment is equal to the type length for the basic types. */
1592 info->align = TYPE_LENGTH (arg_type);
1597 /* Align doubles correctly. */
1598 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1599 info->align = TYPE_LENGTH (builtin_type_double);
1601 info->align = TYPE_LENGTH (builtin_type_long);
1604 case TYPE_CODE_STRUCT:
1606 info->align = TYPE_LENGTH (builtin_type_long);
1609 info->length = TYPE_LENGTH (arg_type);
1610 info->contents = value_contents (arg);
1612 /* Align size and onstack_size. */
1613 size = (size + info->align - 1) & ~(info->align - 1);
1614 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1616 if (size + info->length > REGISTER_SIZE * ARG_NOF)
1619 info->u.offset = onstack_size;
1620 onstack_size += info->length;
1625 info->u.regno = ARG_1ST + size / REGISTER_SIZE;
1627 size += info->length;
1630 /* Adjust the stack pointer and align it. */
1631 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1633 /* Simulate MOVSP, if Windowed ABI. */
1634 if ((CALL_ABI != CallAbiCall0Only) && (sp != osp))
1636 read_memory (osp - 16, buf, 16);
1637 write_memory (sp - 16, buf, 16);
1640 /* Second Loop: Load arguments. */
1644 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1645 regcache_cooked_write (regcache, ARG_1ST, buf);
1648 for (i = 0; i < nargs; i++)
1650 struct argument_info *info = &arg_info[i];
1654 int n = info->length;
1655 CORE_ADDR offset = sp + info->u.offset;
1657 /* Odd-sized structs are aligned to the lower side of a memory
1658 word in big-endian mode and require a shift. This only
1659 applies for structures smaller than one word. */
1661 if (n < REGISTER_SIZE
1662 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1663 offset += (REGISTER_SIZE - n);
1665 write_memory (offset, info->contents, info->length);
1670 int n = info->length;
1671 const bfd_byte *cp = info->contents;
1672 int r = info->u.regno;
1674 /* Odd-sized structs are aligned to the lower side of registers in
1675 big-endian mode and require a shift. The odd-sized leftover will
1676 be at the end. Note that this is only true for structures smaller
1677 than REGISTER_SIZE; for larger odd-sized structures the excess
1678 will be left-aligned in the register on both endiannesses. */
1680 if (n < REGISTER_SIZE
1681 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1683 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1684 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1686 store_unsigned_integer (buf, REGISTER_SIZE, v);
1687 regcache_cooked_write (regcache, r, buf);
1689 cp += REGISTER_SIZE;
1696 regcache_cooked_write (regcache, r, cp);
1698 cp += REGISTER_SIZE;
1705 /* Set the return address of dummy frame to the dummy address.
1706 The return address for the current function (in A0) is
1707 saved in the dummy frame, so we can savely overwrite A0 here. */
1709 if (CALL_ABI != CallAbiCall0Only)
1711 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1712 regcache_raw_read (regcache, gdbarch_ps_regnum (current_gdbarch), buf);
1713 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1714 regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra);
1715 regcache_cooked_write_unsigned (regcache,
1716 gdbarch_ps_regnum (current_gdbarch),
1721 /* Simulate CALL0: write RA into A0 register. */
1722 regcache_cooked_write_unsigned (regcache, A0_REGNUM, bp_addr);
1725 /* Set new stack pointer and return it. */
1726 regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp);
1727 /* Make dummy frame ID unique by adding a constant. */
1728 return sp + SP_ALIGNMENT;
1732 /* Return a breakpoint for the current location of PC. We always use
1733 the density version if we have density instructions (regardless of the
1734 current instruction at PC), and use regular instructions otherwise. */
1736 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1737 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1738 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1739 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1741 static const unsigned char *
1742 xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1744 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1745 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1746 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1747 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1749 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1751 if (ISA_USE_DENSITY_INSTRUCTIONS)
1753 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1755 *lenptr = sizeof (density_big_breakpoint);
1756 return density_big_breakpoint;
1760 *lenptr = sizeof (density_little_breakpoint);
1761 return density_little_breakpoint;
1766 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1768 *lenptr = sizeof (big_breakpoint);
1769 return big_breakpoint;
1773 *lenptr = sizeof (little_breakpoint);
1774 return little_breakpoint;
1779 /* Call0 ABI support routines. */
1781 /* Call0 opcode class. Opcodes are preclassified according to what they
1782 mean for Call0 prologue analysis, and their number of significant operands.
1783 The purpose of this is to simplify prologue analysis by separating
1784 instruction decoding (libisa) from the semantics of prologue analysis. */
1787 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1788 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1789 c0opc_flow, /* Flow control insn. */
1790 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1791 c0opc_break, /* Debugger software breakpoints. */
1792 c0opc_add, /* Adding two registers. */
1793 c0opc_addi, /* Adding a register and an immediate. */
1794 c0opc_sub, /* Subtracting a register from a register. */
1795 c0opc_mov, /* Moving a register to a register. */
1796 c0opc_movi, /* Moving an immediate to a register. */
1797 c0opc_l32r, /* Loading a literal. */
1798 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1799 c0opc_NrOf /* Number of opcode classifications. */
1803 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1805 static xtensa_insn_kind
1806 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1808 const char *opcname;
1809 xtensa_insn_kind opclass = c0opc_uninteresting;
1811 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1813 /* Get opcode name and handle special classifications. */
1815 opcname = xtensa_opcode_name (isa, opc);
1818 || strcasecmp (opcname, "ill") == 0
1819 || strcasecmp (opcname, "ill.n") == 0)
1820 opclass = c0opc_illegal;
1821 else if (strcasecmp (opcname, "break") == 0
1822 || strcasecmp (opcname, "break.n") == 0)
1823 opclass = c0opc_break;
1824 else if (strcasecmp (opcname, "entry") == 0)
1825 opclass = c0opc_entry;
1826 else if (xtensa_opcode_is_branch (isa, opc) > 0
1827 || xtensa_opcode_is_jump (isa, opc) > 0
1828 || xtensa_opcode_is_loop (isa, opc) > 0
1829 || xtensa_opcode_is_call (isa, opc) > 0
1830 || strcasecmp (opcname, "simcall") == 0
1831 || strcasecmp (opcname, "syscall") == 0)
1832 opclass = c0opc_flow;
1834 /* Also, classify specific opcodes that need to be tracked. */
1835 else if (strcasecmp (opcname, "add") == 0
1836 || strcasecmp (opcname, "add.n") == 0)
1837 opclass = c0opc_add;
1838 else if (strcasecmp (opcname, "addi") == 0
1839 || strcasecmp (opcname, "addi.n") == 0
1840 || strcasecmp (opcname, "addmi") == 0)
1841 opclass = c0opc_addi;
1842 else if (strcasecmp (opcname, "sub") == 0)
1843 opclass = c0opc_sub;
1844 else if (strcasecmp (opcname, "mov.n") == 0
1845 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1846 opclass = c0opc_mov;
1847 else if (strcasecmp (opcname, "movi") == 0
1848 || strcasecmp (opcname, "movi.n") == 0)
1849 opclass = c0opc_movi;
1850 else if (strcasecmp (opcname, "l32r") == 0)
1851 opclass = c0opc_l32r;
1852 else if (strcasecmp (opcname, "s32i") == 0
1853 || strcasecmp (opcname, "s32i.n") == 0)
1854 opclass = c0opc_s32i;
1859 /* Tracks register movement/mutation for a given operation, which may
1860 be within a bundle. Updates the destination register tracking info
1861 accordingly. The pc is needed only for pc-relative load instructions
1862 (eg. l32r). The SP register number is needed to identify stores to
1866 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1867 xtensa_insn_kind opclass, int nods, unsigned odv[],
1868 CORE_ADDR pc, int spreg)
1870 unsigned litbase, litaddr, litval;
1875 /* 3 operands: dst, src, imm. */
1876 gdb_assert (nods == 3);
1877 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1878 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1881 /* 3 operands: dst, src1, src2. */
1882 gdb_assert (nods == 3);
1883 if (src[odv[1]].fr_reg == C0_CONST)
1885 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
1886 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
1888 else if (src[odv[2]].fr_reg == C0_CONST)
1890 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1891 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
1893 else dst[odv[0]].fr_reg = C0_INEXP;
1896 /* 3 operands: dst, src1, src2. */
1897 gdb_assert (nods == 3);
1898 if (src[odv[2]].fr_reg == C0_CONST)
1900 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1901 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
1903 else dst[odv[0]].fr_reg = C0_INEXP;
1906 /* 2 operands: dst, src [, src]. */
1907 gdb_assert (nods == 2);
1908 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1909 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
1912 /* 2 operands: dst, imm. */
1913 gdb_assert (nods == 2);
1914 dst[odv[0]].fr_reg = C0_CONST;
1915 dst[odv[0]].fr_ofs = odv[1];
1918 /* 2 operands: dst, literal offset. */
1919 gdb_assert (nods == 2);
1920 /* litbase = xtensa_get_litbase (pc); can be also used. */
1921 litbase = (LITBASE_REGNUM == -1)
1922 ? 0 : xtensa_read_register (LITBASE_REGNUM);
1923 litaddr = litbase & 1
1924 ? (litbase & ~1) + (signed)odv[1]
1925 : (pc + 3 + (signed)odv[1]) & ~3;
1926 litval = read_memory_integer(litaddr, 4);
1927 dst[odv[0]].fr_reg = C0_CONST;
1928 dst[odv[0]].fr_ofs = litval;
1931 /* 3 operands: value, base, offset. */
1932 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
1933 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
1934 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
1935 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
1936 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
1937 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
1939 /* ISA encoding guarantees alignment. But, check it anyway. */
1940 gdb_assert ((odv[2] & 3) == 0);
1941 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
1949 /* Analyze prologue of the function at start address to determine if it uses
1950 the Call0 ABI, and if so track register moves and linear modifications
1951 in the prologue up to the PC or just beyond the prologue, whichever is first.
1952 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
1953 The prologue may overlap non-prologue instructions but is guaranteed to end
1954 by the first flow-control instruction (jump, branch, call or return).
1955 Since an optimized function may move information around and change the
1956 stack frame arbitrarily during the prologue, the information is guaranteed
1957 valid only at the point in the function indicated by the PC.
1958 May be used to skip the prologue or identify the ABI, w/o tracking.
1960 Returns: Address of first instruction after prologue, or PC (whichever
1961 is first), or 0, if decoding failed (in libisa).
1963 start Start address of function/prologue.
1964 pc Program counter to stop at. Use 0 to continue to end of prologue.
1965 If 0, avoids infinite run-on in corrupt code memory by bounding
1966 the scan to the end of the function if that can be determined.
1967 nregs Number of general registers to track (size of rt[] array).
1969 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
1970 If NULL, registers are not tracked.
1972 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
1973 (more accurately, non-zero until 'entry' insn is encountered).
1975 Note that these may produce useful results even if decoding fails
1976 because they begin with default assumptions that analysis may change. */
1979 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
1980 int nregs, xtensa_c0reg_t rt[], int *call0)
1982 CORE_ADDR ia; /* Current insn address in prologue. */
1983 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
1984 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
1985 #define BSZ 32 /* Instruction buffer size. */
1986 char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
1987 xtensa_isa isa; /* libisa ISA handle. */
1988 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
1989 xtensa_format ifmt; /* libisa instruction format. */
1990 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
1991 xtensa_opcode opc; /* Opcode in current slot. */
1992 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
1993 int nods; /* Opcode number of operands. */
1994 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
1995 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
1996 int j; /* General loop counter. */
1997 int fail = 0; /* Set non-zero and exit, if decoding fails. */
1998 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
1999 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2001 struct symtab_and_line prologue_sal;
2003 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2004 (int)start, (int)pc);
2006 /* Try to limit the scan to the end of the function if a non-zero pc
2007 arg was not supplied to avoid probing beyond the end of valid memory.
2008 If memory is full of garbage that classifies as c0opc_uninteresting.
2009 If this fails (eg. if no symbols) pc ends up 0 as it was.
2010 Intialize the Call0 frame and register tracking info.
2011 Assume it's Call0 until an 'entry' instruction is encountered.
2012 Assume we may be in the prologue until we hit a flow control instr. */
2018 /* Find out, if we have an information about the prologue from DWARF. */
2019 prologue_sal = find_pc_line (start, 0);
2020 if (prologue_sal.line != 0) /* Found debug info. */
2021 body_pc = prologue_sal.end;
2023 /* If we are going to analyze the prologue in general without knowing about
2024 the current PC, make the best assumtion for the end of the prologue. */
2027 find_pc_partial_function (start, 0, NULL, &end_pc);
2028 body_pc = min (end_pc, body_pc);
2031 body_pc = min (pc, body_pc);
2038 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2039 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2043 isa = xtensa_default_isa;
2044 gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
2045 ins = xtensa_insnbuf_alloc (isa);
2046 slot = xtensa_insnbuf_alloc (isa);
2048 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2050 /* (Re)fill instruction buffer from memory if necessary, but do not
2051 read memory beyond PC to be sure we stay within text section
2052 (this protection only works if a non-zero pc is supplied). */
2054 if (ia + xtensa_isa_maxlength (isa) > bt)
2057 bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
2058 read_memory (ba, ibuf, bt - ba);
2061 /* Decode format information. */
2063 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2064 ifmt = xtensa_format_decode (isa, ins);
2065 if (ifmt == XTENSA_UNDEFINED)
2070 ilen = xtensa_format_length (isa, ifmt);
2071 if (ilen == XTENSA_UNDEFINED)
2076 islots = xtensa_format_num_slots (isa, ifmt);
2077 if (islots == XTENSA_UNDEFINED)
2083 /* Analyze a bundle or a single instruction, using a snapshot of
2084 the register tracking info as input for the entire bundle so that
2085 register changes do not take effect within this bundle. */
2087 for (j = 0; j < nregs; ++j)
2090 for (is = 0; is < islots; ++is)
2092 /* Decode a slot and classify the opcode. */
2094 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2098 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2099 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2101 if (opc == XTENSA_UNDEFINED)
2102 opclass = c0opc_illegal;
2104 opclass = call0_classify_opcode (isa, opc);
2106 /* Decide whether to track this opcode, ignore it, or bail out. */
2115 case c0opc_uninteresting:
2124 ia += ilen; /* Skip over 'entry' insn. */
2132 /* Only expected opcodes should get this far. */
2136 /* Extract and decode the operands. */
2137 nods = xtensa_opcode_num_operands (isa, opc);
2138 if (nods == XTENSA_UNDEFINED)
2144 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2146 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2151 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2156 /* Check operands to verify use of 'mov' assembler macro. */
2157 if (opclass == c0opc_mov && nods == 3)
2159 if (odv[2] == odv[1])
2163 opclass = c0opc_uninteresting;
2168 /* Track register movement and modification for this operation. */
2169 call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
2173 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2174 (unsigned)ia, fail ? "failed" : "succeeded");
2175 xtensa_insnbuf_free(isa, slot);
2176 xtensa_insnbuf_free(isa, ins);
2177 return fail ? 0 : ia;
2180 /* Initialize frame cache for the current frame. The "next_frame" is the next
2181 one relative to current frame. "cache" is the pointer to the data structure
2182 we have to initialize. "pc" is curretnt PC. */
2185 call0_frame_cache (struct frame_info *next_frame,
2186 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2188 CORE_ADDR start_pc; /* The beginning of the function. */
2189 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2190 CORE_ADDR sp, fp, ra;
2191 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2193 /* Find the beginning of the prologue of the function containing the PC
2194 and analyze it up to the PC or the end of the prologue. */
2196 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2198 body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
2199 &cache->c0.c0_rt[0],
2203 sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM);
2204 fp = sp; /* Assume FP == SP until proven otherwise. */
2206 /* Get the frame information and FP (if used) at the current PC.
2207 If PC is in the prologue, the prologue analysis is more reliable
2208 than DWARF info. We don't not know for sure if PC is in the prologue,
2209 but we know no calls have yet taken place, so we can almost
2210 certainly rely on the prologue analysis. */
2214 /* Prologue analysis was successful up to the PC.
2215 It includes the cases when PC == START_PC. */
2216 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2217 /* c0_hasfp == true means there is a frame pointer because
2218 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2219 was derived from SP. Otherwise, it would be C0_FP. */
2220 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2221 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2222 fp_regnum += A0_BASE;
2224 else /* No data from the prologue analysis. */
2227 fp_regnum = A0_BASE + C0_SP;
2232 prev_sp = fp + c0_frmsz;
2234 /* Frame size from debug info or prologue tracking does not account for
2235 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2238 fp = frame_unwind_register_unsigned (next_frame, fp_regnum);
2240 /* Recalculate previous SP. */
2241 prev_sp = fp + c0_frmsz;
2242 /* Update the stack frame size. */
2243 c0_frmsz += fp - sp;
2246 /* Get the return address (RA) from the stack if saved,
2247 or try to get it from a register. */
2249 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2250 if (to_stk != C0_NOSTK)
2252 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2254 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2255 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2257 /* Special case for terminating backtrace at a function that wants to
2258 be seen as the outermost. Such a function will clear it's RA (A0)
2259 register to 0 in the prologue instead of saving its original value. */
2264 /* RA was copied to another register or (before any function call) may
2265 still be in the original RA register. This is not always reliable:
2266 even in a leaf function, register tracking stops after prologue, and
2267 even in prologue, non-prologue instructions (not tracked) may overwrite
2268 RA or any register it was copied to. If likely in prologue or before
2269 any call, use retracking info and hope for the best (compiler should
2270 have saved RA in stack if not in a leaf function). If not in prologue,
2276 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2278 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2280 if (i < C0_NREGS) /* Read from the next_frame. */
2282 ra = frame_unwind_register_unsigned (next_frame,
2283 A0_REGNUM + cache->c0.c0_rt[i].fr_reg);
2288 cache->pc = start_pc;
2290 /* RA == 0 marks the outermost frame. Do not go past it. */
2291 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2292 cache->c0.fp_regnum = fp_regnum;
2293 cache->c0.c0_frmsz = c0_frmsz;
2294 cache->c0.c0_hasfp = c0_hasfp;
2295 cache->c0.c0_fp = fp;
2299 /* Skip function prologue.
2301 Return the pc of the first instruction after prologue. GDB calls this to
2302 find the address of the first line of the function or (if there is no line
2303 number information) to skip the prologue for planting breakpoints on
2304 function entries. Use debug info (if present) or prologue analysis to skip
2305 the prologue to achieve reliable debugging behavior. For windowed ABI,
2306 only the 'entry' instruction is skipped. It is not strictly necessary to
2307 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2308 backtrace at any point in the prologue, however certain potential hazards
2309 are avoided and a more "normal" debugging experience is ensured by
2310 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2311 For example, if we don't skip the prologue:
2312 - Some args may not yet have been saved to the stack where the debug
2313 info expects to find them (true anyway when only 'entry' is skipped);
2314 - Software breakpoints ('break' instrs) may not have been unplanted
2315 when the prologue analysis is done on initializing the frame cache,
2316 and breaks in the prologue will throw off the analysis.
2318 If we have debug info ( line-number info, in particular ) we simply skip
2319 the code associated with the first function line effectively skipping
2320 the prologue code. It works even in cases like
2323 { int local_var = 1;
2327 because, for this source code, both Xtensa compilers will generate two
2328 separate entries ( with the same line number ) in dwarf line-number
2329 section to make sure there is a boundary between the prologue code and
2330 the rest of the function.
2332 If there is no debug info, we need to analyze the code. */
2334 /* #define DONT_SKIP_PROLOGUE */
2337 xtensa_skip_prologue (CORE_ADDR start_pc)
2339 struct symtab_and_line prologue_sal;
2342 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2344 #if DONT_SKIP_PROLOGUE
2348 /* Try to find first body line from debug info. */
2350 prologue_sal = find_pc_line (start_pc, 0);
2351 if (prologue_sal.line != 0) /* Found debug info. */
2353 /* In Call0, it is possible to have a function with only one instruction
2354 ('ret') resulting from a 1-line optimized function that does nothing.
2355 In that case, prologue_sal.end may actually point to the start of the
2356 next function in the text section, causing a breakpoint to be set at
2357 the wrong place. Check if the end address is in a different function,
2358 and if so return the start PC. We know we have symbol info. */
2362 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2363 if (end_func != start_pc)
2366 return prologue_sal.end;
2369 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2370 body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
2371 return body_pc != 0 ? body_pc : start_pc;
2374 /* Verify the current configuration. */
2376 xtensa_verify_config (struct gdbarch *gdbarch)
2378 struct ui_file *log;
2379 struct cleanup *cleanups;
2380 struct gdbarch_tdep *tdep;
2384 tdep = gdbarch_tdep (gdbarch);
2385 log = mem_fileopen ();
2386 cleanups = make_cleanup_ui_file_delete (log);
2388 /* Verify that we got a reasonable number of AREGS. */
2389 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2390 fprintf_unfiltered (log, _("\
2391 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2394 /* Verify that certain registers exist. */
2396 if (tdep->pc_regnum == -1)
2397 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2398 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2399 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2401 if (tdep->isa_use_windowed_registers)
2403 if (tdep->wb_regnum == -1)
2404 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2405 if (tdep->ws_regnum == -1)
2406 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2407 if (tdep->ar_base == -1)
2408 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2411 if (tdep->a0_base == -1)
2412 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2414 buf = ui_file_xstrdup (log, &dummy);
2415 make_cleanup (xfree, buf);
2416 if (strlen (buf) > 0)
2417 internal_error (__FILE__, __LINE__,
2418 _("the following are invalid: %s"), buf);
2419 do_cleanups (cleanups);
2422 /* Module "constructor" function. */
2424 static struct gdbarch *
2425 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2427 struct gdbarch_tdep *tdep;
2428 struct gdbarch *gdbarch;
2429 struct xtensa_abi_handler *abi_handler;
2431 DEBUGTRACE ("gdbarch_init()\n");
2433 /* We have to set the byte order before we call gdbarch_alloc. */
2434 info.byte_order = xtensa_config_byte_order (&info);
2436 tdep = xtensa_config_tdep (&info);
2437 gdbarch = gdbarch_alloc (&info, tdep);
2439 /* Verify our configuration. */
2440 xtensa_verify_config (gdbarch);
2442 /* Pseudo-Register read/write. */
2443 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2444 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2446 /* Set target information. */
2447 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2448 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2449 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2450 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2451 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2453 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
2454 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2455 set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2456 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2458 /* We provide our own function to get register information. */
2459 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2460 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2462 /* To call functions from GDB using dummy frame */
2463 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2465 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2467 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2469 /* Advance PC across any prologue instructions to reach "real" code. */
2470 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2472 /* Stack grows downward. */
2473 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2475 /* Set breakpoints. */
2476 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2478 /* After breakpoint instruction or illegal instruction, pc still
2479 points at break instruction, so don't decrement. */
2480 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2482 /* We don't skip args. */
2483 set_gdbarch_frame_args_skip (gdbarch, 0);
2485 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2487 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2489 set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id);
2491 /* Frame handling. */
2492 frame_base_set_default (gdbarch, &xtensa_frame_base);
2493 frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer);
2495 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2497 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2499 xtensa_add_reggroups (gdbarch);
2500 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2502 set_gdbarch_regset_from_core_section (gdbarch,
2503 xtensa_regset_from_core_section);
2509 xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2511 error (_("xtensa_dump_tdep(): not implemented"));
2515 _initialize_xtensa_tdep (void)
2517 struct cmd_list_element *c;
2519 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2520 xtensa_init_reggroups ();
2522 add_setshow_zinteger_cmd ("xtensa",
2524 &xtensa_debug_level, _("\
2525 Set Xtensa debugging."), _("\
2526 Show Xtensa debugging."), _("\
2527 When non-zero, Xtensa-specific debugging is enabled. \
2528 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2531 &setdebuglist, &showdebuglist);