1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
142 arreg = a_regnum - tdep->a0_base;
143 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
144 arreg &= tdep->num_aregs - 1;
146 return arreg + tdep->ar_base;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 areg = ar_regnum - tdep->ar_base;
158 if (areg < 0 || areg >= tdep->num_aregs)
160 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
161 return (areg > 15) ? -1 : areg;
164 /* Read Xtensa register directly from the hardware. */
166 xtensa_read_register (int regnum)
170 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
171 return (unsigned long) value;
174 /* Write Xtensa register directly to the hardware. */
176 xtensa_write_register (int regnum, ULONGEST value)
178 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
181 /* Return the window size of the previous call to the function from which we
184 This function is used to extract the return value after a called function
185 has returned to the caller. On Xtensa, the register that holds the return
186 value (from the perspective of the caller) depends on what call
187 instruction was used. For now, we are assuming that the call instruction
188 precedes the current address, so we simply analyze the call instruction.
189 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
190 method to call the inferior function. */
193 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
195 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
200 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
202 /* Read the previous instruction (should be a call[x]{4|8|12}. */
203 read_memory (pc-3, buf, 3);
204 insn = extract_unsigned_integer (buf, 3, byte_order);
206 /* Decode call instruction:
208 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
209 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
211 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
212 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
214 if (byte_order == BFD_ENDIAN_LITTLE)
216 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
217 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
221 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
222 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
228 /* REGISTER INFORMATION */
230 /* Find register by name. */
232 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
236 for (i = 0; i < gdbarch_num_regs (gdbarch)
237 + gdbarch_num_pseudo_regs (gdbarch);
240 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
246 /* Returns the name of a register. */
248 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
250 /* Return the name stored in the register map. */
251 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
252 + gdbarch_num_pseudo_regs (gdbarch))
253 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
255 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
259 /* Return the type of a register. Create a new type, if necessary. */
262 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
266 /* Return signed integer for ARx and Ax registers. */
267 if ((regnum >= tdep->ar_base
268 && regnum < tdep->ar_base + tdep->num_aregs)
269 || (regnum >= tdep->a0_base
270 && regnum < tdep->a0_base + 16))
271 return builtin_type (gdbarch)->builtin_int;
273 if (regnum == gdbarch_pc_regnum (gdbarch)
274 || regnum == tdep->a0_base + 1)
275 return builtin_type (gdbarch)->builtin_data_ptr;
277 /* Return the stored type for all other registers. */
278 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
279 + gdbarch_num_pseudo_regs (gdbarch))
281 xtensa_register_t* reg = &tdep->regmap[regnum];
283 /* Set ctype for this register (only the first time). */
287 struct ctype_cache *tp;
288 int size = reg->byte_size;
290 /* We always use the memory representation,
291 even if the register width is smaller. */
295 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
299 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
303 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
307 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
311 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
315 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
316 if (tp->size == size)
321 char *name = xmalloc (16);
322 tp = xmalloc (sizeof (struct ctype_cache));
323 tp->next = tdep->type_entries;
324 tdep->type_entries = tp;
327 sprintf (name, "int%d", size * 8);
329 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
332 reg->ctype = tp->virtual_type;
338 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
343 /* Return the 'local' register number for stubs, dwarf2, etc.
344 The debugging information enumerates registers starting from 0 for A0
345 to n for An. So, we only have to add the base number for A0. */
348 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
352 if (regnum >= 0 && regnum < 16)
353 return gdbarch_tdep (gdbarch)->a0_base + regnum;
356 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
358 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
361 internal_error (__FILE__, __LINE__,
362 _("invalid dwarf/stabs register number %d"), regnum);
367 /* Write the bits of a masked register to the various registers.
368 Only the masked areas of these registers are modified; the other
369 fields are untouched. The size of masked registers is always less
370 than or equal to 32 bits. */
373 xtensa_register_write_masked (struct regcache *regcache,
374 xtensa_register_t *reg, const gdb_byte *buffer)
376 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
377 const xtensa_mask_t *mask = reg->mask;
379 int shift = 0; /* Shift for next mask (mod 32). */
380 int start, size; /* Start bit and size of current mask. */
382 unsigned int *ptr = value;
383 unsigned int regval, m, mem = 0;
385 int bytesize = reg->byte_size;
386 int bitsize = bytesize * 8;
389 DEBUGTRACE ("xtensa_register_write_masked ()\n");
391 /* Copy the masked register to host byte-order. */
392 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
393 for (i = 0; i < bytesize; i++)
396 mem |= (buffer[bytesize - i - 1] << 24);
401 for (i = 0; i < bytesize; i++)
404 mem |= (buffer[i] << 24);
409 /* We might have to shift the final value:
410 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
411 bytesize & 3 == x -> shift (4-x) * 8. */
413 *ptr = mem >> (((0 - bytesize) & 3) * 8);
417 /* Write the bits to the masked areas of the other registers. */
418 for (i = 0; i < mask->count; i++)
420 start = mask->mask[i].bit_start;
421 size = mask->mask[i].bit_size;
422 regval = mem >> shift;
424 if ((shift += size) > bitsize)
425 error (_("size of all masks is larger than the register"));
434 regval |= mem << (size - shift);
437 /* Make sure we have a valid register. */
438 r = mask->mask[i].reg_num;
439 if (r >= 0 && size > 0)
441 /* Don't overwrite the unmasked areas. */
443 regcache_cooked_read_unsigned (regcache, r, &old_val);
444 m = 0xffffffff >> (32 - size) << start;
446 regval = (regval & m) | (old_val & ~m);
447 regcache_cooked_write_unsigned (regcache, r, regval);
453 /* Read a tie state or mapped registers. Read the masked areas
454 of the registers and assemble them into a single value. */
457 xtensa_register_read_masked (struct regcache *regcache,
458 xtensa_register_t *reg, gdb_byte *buffer)
460 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
461 const xtensa_mask_t *mask = reg->mask;
466 unsigned int *ptr = value;
467 unsigned int regval, mem = 0;
469 int bytesize = reg->byte_size;
470 int bitsize = bytesize * 8;
473 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
474 reg->name == 0 ? "" : reg->name);
476 /* Assemble the register from the masked areas of other registers. */
477 for (i = 0; i < mask->count; i++)
479 int r = mask->mask[i].reg_num;
483 regcache_cooked_read_unsigned (regcache, r, &val);
484 regval = (unsigned int) val;
489 start = mask->mask[i].bit_start;
490 size = mask->mask[i].bit_size;
495 regval &= (0xffffffff >> (32 - size));
497 mem |= regval << shift;
499 if ((shift += size) > bitsize)
500 error (_("size of all masks is larger than the register"));
511 mem = regval >> (size - shift);
518 /* Copy value to target byte order. */
522 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
523 for (i = 0; i < bytesize; i++)
527 buffer[bytesize - i - 1] = mem & 0xff;
531 for (i = 0; i < bytesize; i++)
535 buffer[i] = mem & 0xff;
541 /* Read pseudo registers. */
544 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
545 struct regcache *regcache,
549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
551 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
552 regnum, xtensa_register_name (gdbarch, regnum));
554 if (regnum == gdbarch_num_regs (gdbarch)
555 + gdbarch_num_pseudo_regs (gdbarch) - 1)
556 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
558 /* Read aliases a0..a15, if this is a Windowed ABI. */
559 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
560 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
561 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
563 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
565 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
566 regnum = arreg_number (gdbarch, regnum,
567 extract_unsigned_integer (buf, 4, byte_order));
570 /* We can always read non-pseudo registers. */
571 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
572 regcache_raw_read (regcache, regnum, buffer);
575 /* We have to find out how to deal with priveleged registers.
576 Let's treat them as pseudo-registers, but we cannot read/write them. */
578 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
580 buffer[0] = (gdb_byte)0;
581 buffer[1] = (gdb_byte)0;
582 buffer[2] = (gdb_byte)0;
583 buffer[3] = (gdb_byte)0;
585 /* Pseudo registers. */
587 && regnum < gdbarch_num_regs (gdbarch)
588 + gdbarch_num_pseudo_regs (gdbarch))
590 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
591 xtensa_register_type_t type = reg->type;
592 int flags = gdbarch_tdep (gdbarch)->target_flags;
594 /* We cannot read Unknown or Unmapped registers. */
595 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
597 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
599 warning (_("cannot read register %s"),
600 xtensa_register_name (gdbarch, regnum));
605 /* Some targets cannot read TIE register files. */
606 else if (type == xtRegisterTypeTieRegfile)
608 /* Use 'fetch' to get register? */
609 if (flags & xtTargetFlagsUseFetchStore)
611 warning (_("cannot read register"));
615 /* On some targets (esp. simulators), we can always read the reg. */
616 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
618 warning (_("cannot read register"));
623 /* We can always read mapped registers. */
624 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
626 xtensa_register_read_masked (regcache, reg, buffer);
630 /* Assume that we can read the register. */
631 regcache_raw_read (regcache, regnum, buffer);
634 internal_error (__FILE__, __LINE__,
635 _("invalid register number %d"), regnum);
639 /* Write pseudo registers. */
642 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
643 struct regcache *regcache,
645 const gdb_byte *buffer)
647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
649 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
650 regnum, xtensa_register_name (gdbarch, regnum));
652 if (regnum == gdbarch_num_regs (gdbarch)
653 + gdbarch_num_pseudo_regs (gdbarch) -1)
654 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
656 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
657 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
658 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
659 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
661 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
664 regcache_raw_read (regcache,
665 gdbarch_tdep (gdbarch)->wb_regnum, buf);
666 regnum = arreg_number (gdbarch, regnum,
667 extract_unsigned_integer (buf, 4, byte_order));
670 /* We can always write 'core' registers.
671 Note: We might have converted Ax->ARy. */
672 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
673 regcache_raw_write (regcache, regnum, buffer);
675 /* We have to find out how to deal with priveleged registers.
676 Let's treat them as pseudo-registers, but we cannot read/write them. */
678 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
682 /* Pseudo registers. */
684 && regnum < gdbarch_num_regs (gdbarch)
685 + gdbarch_num_pseudo_regs (gdbarch))
687 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
688 xtensa_register_type_t type = reg->type;
689 int flags = gdbarch_tdep (gdbarch)->target_flags;
691 /* On most targets, we cannot write registers
692 of type "Unknown" or "Unmapped". */
693 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
695 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
697 warning (_("cannot write register %s"),
698 xtensa_register_name (gdbarch, regnum));
703 /* Some targets cannot read TIE register files. */
704 else if (type == xtRegisterTypeTieRegfile)
706 /* Use 'store' to get register? */
707 if (flags & xtTargetFlagsUseFetchStore)
709 warning (_("cannot write register"));
713 /* On some targets (esp. simulators), we can always write
715 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
717 warning (_("cannot write register"));
722 /* We can always write mapped registers. */
723 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
725 xtensa_register_write_masked (regcache, reg, buffer);
729 /* Assume that we can write the register. */
730 regcache_raw_write (regcache, regnum, buffer);
733 internal_error (__FILE__, __LINE__,
734 _("invalid register number %d"), regnum);
737 static struct reggroup *xtensa_ar_reggroup;
738 static struct reggroup *xtensa_user_reggroup;
739 static struct reggroup *xtensa_vectra_reggroup;
740 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
743 xtensa_init_reggroups (void)
746 char cpname[] = "cp0";
748 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
749 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
750 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
752 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
755 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
760 xtensa_add_reggroups (struct gdbarch *gdbarch)
764 /* Predefined groups. */
765 reggroup_add (gdbarch, all_reggroup);
766 reggroup_add (gdbarch, save_reggroup);
767 reggroup_add (gdbarch, restore_reggroup);
768 reggroup_add (gdbarch, system_reggroup);
769 reggroup_add (gdbarch, vector_reggroup);
770 reggroup_add (gdbarch, general_reggroup);
771 reggroup_add (gdbarch, float_reggroup);
773 /* Xtensa-specific groups. */
774 reggroup_add (gdbarch, xtensa_ar_reggroup);
775 reggroup_add (gdbarch, xtensa_user_reggroup);
776 reggroup_add (gdbarch, xtensa_vectra_reggroup);
778 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
779 reggroup_add (gdbarch, xtensa_cp[i]);
783 xtensa_coprocessor_register_group (struct reggroup *group)
787 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
788 if (group == xtensa_cp[i])
794 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
795 | XTENSA_REGISTER_FLAGS_WRITABLE \
796 | XTENSA_REGISTER_FLAGS_VOLATILE)
798 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
799 | XTENSA_REGISTER_FLAGS_WRITABLE)
802 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
804 struct reggroup *group)
806 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
807 xtensa_register_type_t type = reg->type;
808 xtensa_register_group_t rg = reg->group;
811 if (group == save_reggroup)
812 /* Every single register should be included into the list of registers
813 to be watched for changes while using -data-list-changed-registers. */
816 /* First, skip registers that are not visible to this target
817 (unknown and unmapped registers when not using ISS). */
819 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
821 if (group == all_reggroup)
823 if (group == xtensa_ar_reggroup)
824 return rg & xtRegisterGroupAddrReg;
825 if (group == xtensa_user_reggroup)
826 return rg & xtRegisterGroupUser;
827 if (group == float_reggroup)
828 return rg & xtRegisterGroupFloat;
829 if (group == general_reggroup)
830 return rg & xtRegisterGroupGeneral;
831 if (group == system_reggroup)
832 return rg & xtRegisterGroupState;
833 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
834 return rg & xtRegisterGroupVectra;
835 if (group == restore_reggroup)
836 return (regnum < gdbarch_num_regs (gdbarch)
837 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
838 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
839 return rg & (xtRegisterGroupCP0 << cp_number);
845 /* Supply register REGNUM from the buffer specified by GREGS and LEN
846 in the general-purpose register set REGSET to register cache
847 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
850 xtensa_supply_gregset (const struct regset *regset,
856 const xtensa_elf_gregset_t *regs = gregs;
857 struct gdbarch *gdbarch = get_regcache_arch (rc);
860 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
862 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
863 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
864 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
865 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
866 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
867 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
868 (char *) ®s->windowbase);
869 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
870 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
871 (char *) ®s->windowstart);
872 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
873 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
874 (char *) ®s->lbeg);
875 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
876 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
877 (char *) ®s->lend);
878 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
879 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
880 (char *) ®s->lcount);
881 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
882 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
883 (char *) ®s->sar);
884 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
885 && regnum < gdbarch_tdep (gdbarch)->ar_base
886 + gdbarch_tdep (gdbarch)->num_aregs)
887 regcache_raw_supply (rc, regnum,
888 (char *) ®s->ar[regnum - gdbarch_tdep
889 (gdbarch)->ar_base]);
890 else if (regnum == -1)
892 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
893 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
894 (char *) ®s->ar[i]);
899 /* Xtensa register set. */
905 xtensa_supply_gregset
909 /* Return the appropriate register set for the core
910 section identified by SECT_NAME and SECT_SIZE. */
912 static const struct regset *
913 xtensa_regset_from_core_section (struct gdbarch *core_arch,
914 const char *sect_name,
917 DEBUGTRACE ("xtensa_regset_from_core_section "
918 "(..., sect_name==\"%s\", sect_size==%x)\n",
919 sect_name, (unsigned int) sect_size);
921 if (strcmp (sect_name, ".reg") == 0
922 && sect_size >= sizeof(xtensa_elf_gregset_t))
923 return &xtensa_gregset;
929 /* Handling frames. */
931 /* Number of registers to save in case of Windowed ABI. */
932 #define XTENSA_NUM_SAVED_AREGS 12
934 /* Frame cache part for Windowed ABI. */
935 typedef struct xtensa_windowed_frame_cache
937 int wb; /* WINDOWBASE of the previous frame. */
938 int callsize; /* Call size of this frame. */
939 int ws; /* WINDOWSTART of the previous frame. It keeps track of
940 life windows only. If there is no bit set for the
941 window, that means it had been already spilled
942 because of window overflow. */
944 /* Addresses of spilled A-registers.
945 AREGS[i] == -1, if corresponding AR is alive. */
946 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
947 } xtensa_windowed_frame_cache_t;
949 /* Call0 ABI Definitions. */
951 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
953 #define C0_NREGS 16 /* Number of A-registers to track. */
954 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
955 #define C0_SP 1 /* Register used as SP. */
956 #define C0_FP 15 /* Register used as FP. */
957 #define C0_RA 0 /* Register used as return address. */
958 #define C0_ARGS 2 /* Register used as first arg/retval. */
959 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
961 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
962 A-register where the current content of the reg came from (in terms
963 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
964 mean that the orignal content of the register was saved to the stack.
965 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
966 know where SP will end up until the entire prologue has been analyzed. */
968 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
969 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
970 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
972 extern xtensa_isa xtensa_default_isa;
974 typedef struct xtensa_c0reg
976 int fr_reg; /* original register from which register content
977 is derived, or C0_CONST, or C0_INEXP. */
978 int fr_ofs; /* constant offset from reg, or immediate value. */
979 int to_stk; /* offset from original SP to register (4-byte aligned),
980 or C0_NOSTK if register has not been saved. */
983 /* Frame cache part for Call0 ABI. */
984 typedef struct xtensa_call0_frame_cache
986 int c0_frmsz; /* Stack frame size. */
987 int c0_hasfp; /* Current frame uses frame pointer. */
988 int fp_regnum; /* A-register used as FP. */
989 int c0_fp; /* Actual value of frame pointer. */
990 int c0_fpalign; /* Dinamic adjustment for the stack
991 pointer. It's an AND mask. Zero,
992 if alignment was not adjusted. */
993 int c0_old_sp; /* In case of dynamic adjustment, it is
994 a register holding unaligned sp.
995 C0_INEXP, when undefined. */
996 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
997 stack offset. C0_NOSTK otherwise. */
999 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
1000 } xtensa_call0_frame_cache_t;
1002 typedef struct xtensa_frame_cache
1004 CORE_ADDR base; /* Stack pointer of this frame. */
1005 CORE_ADDR pc; /* PC of this frame at the function entry point. */
1006 CORE_ADDR ra; /* The raw return address of this frame. */
1007 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1008 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1009 int call0; /* It's a call0 framework (else windowed). */
1012 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1013 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1015 } xtensa_frame_cache_t;
1018 static struct xtensa_frame_cache *
1019 xtensa_alloc_frame_cache (int windowed)
1021 xtensa_frame_cache_t *cache;
1024 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1026 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1033 cache->call0 = !windowed;
1036 cache->c0.c0_frmsz = -1;
1037 cache->c0.c0_hasfp = 0;
1038 cache->c0.fp_regnum = -1;
1039 cache->c0.c0_fp = -1;
1040 cache->c0.c0_fpalign = 0;
1041 cache->c0.c0_old_sp = C0_INEXP;
1042 cache->c0.c0_sp_ofs = C0_NOSTK;
1044 for (i = 0; i < C0_NREGS; i++)
1046 cache->c0.c0_rt[i].fr_reg = i;
1047 cache->c0.c0_rt[i].fr_ofs = 0;
1048 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1055 cache->wd.callsize = -1;
1057 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1058 cache->wd.aregs[i] = -1;
1065 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1067 return address & ~15;
1072 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1077 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1078 host_address_to_string (next_frame));
1080 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1081 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1083 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1089 static struct frame_id
1090 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1094 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1096 pc = get_frame_pc (this_frame);
1097 fp = get_frame_register_unsigned
1098 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1100 /* Make dummy frame ID unique by adding a constant. */
1101 return frame_id_build (fp + SP_ALIGNMENT, pc);
1104 /* Returns true, if instruction to execute next is unique to Xtensa Window
1105 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1108 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1110 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1111 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1114 if (byte_order == BFD_ENDIAN_BIG)
1116 /* Check, if this is L32E or S32E. */
1117 code = insn & 0xf000ff00;
1118 if ((code == 0x00009000) || (code == 0x00009400))
1120 /* Check, if this is RFWU or RFWO. */
1121 code = insn & 0xffffff00;
1122 return ((code == 0x00430000) || (code == 0x00530000));
1126 /* Check, if this is L32E or S32E. */
1127 code = insn & 0x00ff000f;
1128 if ((code == 0x090000) || (code == 0x490000))
1130 /* Check, if this is RFWU or RFWO. */
1131 code = insn & 0x00ffffff;
1132 return ((code == 0x00003400) || (code == 0x00003500));
1136 /* Returns the best guess about which register is a frame pointer
1137 for the function containing CURRENT_PC. */
1139 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1140 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1143 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1145 #define RETURN_FP goto done
1147 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1148 CORE_ADDR start_addr;
1150 xtensa_insnbuf ins, slot;
1151 char ibuf[XTENSA_ISA_BSZ];
1152 CORE_ADDR ia, bt, ba;
1154 int ilen, islots, is;
1156 const char *opcname;
1158 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1159 if (start_addr == 0)
1162 if (!xtensa_default_isa)
1163 xtensa_default_isa = xtensa_isa_init (0, 0);
1164 isa = xtensa_default_isa;
1165 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1166 ins = xtensa_insnbuf_alloc (isa);
1167 slot = xtensa_insnbuf_alloc (isa);
1170 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1172 if (ia + xtensa_isa_maxlength (isa) > bt)
1175 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1176 ? ba + XTENSA_ISA_BSZ : current_pc;
1177 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1181 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1182 ifmt = xtensa_format_decode (isa, ins);
1183 if (ifmt == XTENSA_UNDEFINED)
1185 ilen = xtensa_format_length (isa, ifmt);
1186 if (ilen == XTENSA_UNDEFINED)
1188 islots = xtensa_format_num_slots (isa, ifmt);
1189 if (islots == XTENSA_UNDEFINED)
1192 for (is = 0; is < islots; ++is)
1194 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1197 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1198 if (opc == XTENSA_UNDEFINED)
1201 opcname = xtensa_opcode_name (isa, opc);
1203 if (strcasecmp (opcname, "mov.n") == 0
1204 || strcasecmp (opcname, "or") == 0)
1206 unsigned int register_operand;
1208 /* Possible candidate for setting frame pointer
1209 from A1. This is what we are looking for. */
1211 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1212 is, slot, ®ister_operand) != 0)
1214 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1216 if (register_operand == 1) /* Mov{.n} FP A1. */
1218 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1219 ®ister_operand) != 0)
1221 if (xtensa_operand_decode (isa, opc, 0,
1222 ®ister_operand) != 0)
1226 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1232 /* We have problems decoding the memory. */
1234 || strcasecmp (opcname, "ill") == 0
1235 || strcasecmp (opcname, "ill.n") == 0
1236 /* Hit planted breakpoint. */
1237 || strcasecmp (opcname, "break") == 0
1238 || strcasecmp (opcname, "break.n") == 0
1239 /* Flow control instructions finish prologue. */
1240 || xtensa_opcode_is_branch (isa, opc) > 0
1241 || xtensa_opcode_is_jump (isa, opc) > 0
1242 || xtensa_opcode_is_loop (isa, opc) > 0
1243 || xtensa_opcode_is_call (isa, opc) > 0
1244 || strcasecmp (opcname, "simcall") == 0
1245 || strcasecmp (opcname, "syscall") == 0)
1246 /* Can not continue analysis. */
1251 xtensa_insnbuf_free(isa, slot);
1252 xtensa_insnbuf_free(isa, ins);
1256 /* The key values to identify the frame using "cache" are
1258 cache->base = SP (or best guess about FP) of this frame;
1259 cache->pc = entry-PC (entry point of the frame function);
1260 cache->prev_sp = SP of the previous frame. */
1263 call0_frame_cache (struct frame_info *this_frame,
1264 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1267 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1268 xtensa_frame_cache_t *cache,
1271 static struct xtensa_frame_cache *
1272 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1274 xtensa_frame_cache_t *cache;
1275 CORE_ADDR ra, wb, ws, pc, sp, ps;
1276 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1277 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1278 unsigned int fp_regnum;
1279 int windowed, ps_regnum;
1284 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1285 ps_regnum = gdbarch_ps_regnum (gdbarch);
1286 ps = (ps_regnum >= 0
1287 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1289 windowed = windowing_enabled (gdbarch, ps);
1291 /* Get pristine xtensa-frame. */
1292 cache = xtensa_alloc_frame_cache (windowed);
1293 *this_cache = cache;
1299 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1300 wb = get_frame_register_unsigned (this_frame,
1301 gdbarch_tdep (gdbarch)->wb_regnum);
1302 ws = get_frame_register_unsigned (this_frame,
1303 gdbarch_tdep (gdbarch)->ws_regnum);
1305 op1 = read_memory_integer (pc, 1, byte_order);
1306 if (XTENSA_IS_ENTRY (gdbarch, op1))
1308 int callinc = CALLINC (ps);
1309 ra = get_frame_register_unsigned
1310 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1312 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1313 cache->wd.callsize = 0;
1316 cache->prev_sp = get_frame_register_unsigned
1317 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1319 /* This only can be the outermost frame since we are
1320 just about to execute ENTRY. SP hasn't been set yet.
1321 We can assume any frame size, because it does not
1322 matter, and, let's fake frame base in cache. */
1323 cache->base = cache->prev_sp - 16;
1326 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1327 cache->ps = (ps & ~PS_CALLINC_MASK)
1328 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1334 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1335 ra = get_frame_register_unsigned (this_frame,
1336 gdbarch_tdep (gdbarch)->a0_base);
1337 cache->wd.callsize = WINSIZE (ra);
1338 cache->wd.wb = (wb - cache->wd.callsize / 4)
1339 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1340 cache->wd.ws = ws & ~(1 << wb);
1342 cache->pc = get_frame_func (this_frame);
1343 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1344 cache->ps = (ps & ~PS_CALLINC_MASK)
1345 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1348 if (cache->wd.ws == 0)
1353 sp = get_frame_register_unsigned
1354 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1356 for (i = 0; i < 4; i++, sp += 4)
1358 cache->wd.aregs[i] = sp;
1361 if (cache->wd.callsize > 4)
1363 /* Set A4...A7/A11. */
1364 /* Get the SP of the frame previous to the previous one.
1365 To achieve this, we have to dereference SP twice. */
1366 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1367 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1368 sp -= cache->wd.callsize * 4;
1370 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1372 cache->wd.aregs[i] = sp;
1377 if ((cache->prev_sp == 0) && ( ra != 0 ))
1378 /* If RA is equal to 0 this frame is an outermost frame. Leave
1379 cache->prev_sp unchanged marking the boundary of the frame stack. */
1381 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1383 /* Register window overflow already happened.
1384 We can read caller's SP from the proper spill loction. */
1385 sp = get_frame_register_unsigned
1386 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1387 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1391 /* Read caller's frame SP directly from the previous window. */
1392 int regnum = arreg_number
1393 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1396 cache->prev_sp = xtensa_read_register (regnum);
1400 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1402 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1404 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1405 /* Everything was set already, including cache->base. */
1408 else /* Call0 framework. */
1410 call0_frame_cache (this_frame, cache, pc);
1411 fp_regnum = cache->c0.fp_regnum;
1414 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1419 static int xtensa_session_once_reported = 1;
1421 /* Report a problem with prologue analysis while doing backtracing.
1422 But, do it only once to avoid annoyng repeated messages. */
1424 static void warning_once ()
1426 if (xtensa_session_once_reported == 0)
1428 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1429 This message will not be repeated in this session.\n"));
1431 xtensa_session_once_reported = 1;
1436 xtensa_frame_this_id (struct frame_info *this_frame,
1438 struct frame_id *this_id)
1440 struct xtensa_frame_cache *cache =
1441 xtensa_frame_cache (this_frame, this_cache);
1443 if (cache->prev_sp == 0)
1446 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1449 static struct value *
1450 xtensa_frame_prev_register (struct frame_info *this_frame,
1454 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1455 struct xtensa_frame_cache *cache;
1456 ULONGEST saved_reg = 0;
1459 if (*this_cache == NULL)
1460 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1461 cache = *this_cache;
1463 if (regnum ==gdbarch_pc_regnum (gdbarch))
1464 saved_reg = cache->ra;
1465 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1466 saved_reg = cache->prev_sp;
1467 else if (!cache->call0)
1469 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1470 saved_reg = cache->wd.ws;
1471 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1472 saved_reg = cache->wd.wb;
1473 else if (regnum == gdbarch_ps_regnum (gdbarch))
1474 saved_reg = cache->ps;
1482 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1484 if (!cache->call0) /* Windowed ABI. */
1486 /* Convert A-register numbers to AR-register numbers,
1487 if we deal with A-register. */
1488 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1489 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1490 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1492 /* Check, if we deal with AR-register saved on stack. */
1493 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1494 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1495 + gdbarch_tdep (gdbarch)->num_aregs))
1497 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1500 && areg < XTENSA_NUM_SAVED_AREGS
1501 && cache->wd.aregs[areg] != -1)
1502 return frame_unwind_got_memory (this_frame, regnum,
1503 cache->wd.aregs[areg]);
1506 else /* Call0 ABI. */
1508 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1509 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1511 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1518 /* If register was saved in the prologue, retrieve it. */
1519 stkofs = cache->c0.c0_rt[reg].to_stk;
1520 if (stkofs != C0_NOSTK)
1522 /* Determine SP on entry based on FP. */
1523 spe = cache->c0.c0_fp
1524 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1526 return frame_unwind_got_memory (this_frame, regnum,
1532 /* All other registers have been either saved to
1533 the stack or are still alive in the processor. */
1535 return frame_unwind_got_register (this_frame, regnum, regnum);
1539 static const struct frame_unwind
1543 xtensa_frame_this_id,
1544 xtensa_frame_prev_register,
1546 default_frame_sniffer
1550 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1552 struct xtensa_frame_cache *cache =
1553 xtensa_frame_cache (this_frame, this_cache);
1558 static const struct frame_base
1562 xtensa_frame_base_address,
1563 xtensa_frame_base_address,
1564 xtensa_frame_base_address
1569 xtensa_extract_return_value (struct type *type,
1570 struct regcache *regcache,
1573 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1574 bfd_byte *valbuf = dst;
1575 int len = TYPE_LENGTH (type);
1580 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1582 gdb_assert(len > 0);
1584 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1586 /* First, we have to find the caller window in the register file. */
1587 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1588 callsize = extract_call_winsize (gdbarch, pc);
1590 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1591 if (len > (callsize > 8 ? 8 : 16))
1592 internal_error (__FILE__, __LINE__,
1593 _("cannot extract return value of %d bytes long"),
1596 /* Get the register offset of the return
1597 register (A2) in the caller window. */
1598 regcache_raw_read_unsigned
1599 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1600 areg = arreg_number (gdbarch,
1601 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1605 /* No windowing hardware - Call0 ABI. */
1606 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1609 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1611 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1614 for (; len > 0; len -= 4, areg++, valbuf += 4)
1617 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1619 regcache_raw_read (regcache, areg, valbuf);
1625 xtensa_store_return_value (struct type *type,
1626 struct regcache *regcache,
1629 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1630 const bfd_byte *valbuf = dst;
1634 int len = TYPE_LENGTH (type);
1637 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1639 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1641 regcache_raw_read_unsigned
1642 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1643 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1644 callsize = extract_call_winsize (gdbarch, pc);
1646 if (len > (callsize > 8 ? 8 : 16))
1647 internal_error (__FILE__, __LINE__,
1648 _("unimplemented for this length: %d"),
1649 TYPE_LENGTH (type));
1650 areg = arreg_number (gdbarch,
1651 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1653 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1654 callsize, (int) wb);
1658 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1661 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1664 for (; len > 0; len -= 4, areg++, valbuf += 4)
1667 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1669 regcache_raw_write (regcache, areg, valbuf);
1674 static enum return_value_convention
1675 xtensa_return_value (struct gdbarch *gdbarch,
1676 struct type *func_type,
1677 struct type *valtype,
1678 struct regcache *regcache,
1680 const gdb_byte *writebuf)
1682 /* Structures up to 16 bytes are returned in registers. */
1684 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1685 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1686 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1687 && TYPE_LENGTH (valtype) > 16);
1690 return RETURN_VALUE_STRUCT_CONVENTION;
1692 DEBUGTRACE ("xtensa_return_value(...)\n");
1694 if (writebuf != NULL)
1696 xtensa_store_return_value (valtype, regcache, writebuf);
1699 if (readbuf != NULL)
1701 gdb_assert (!struct_return);
1702 xtensa_extract_return_value (valtype, regcache, readbuf);
1704 return RETURN_VALUE_REGISTER_CONVENTION;
1711 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1712 struct value *function,
1713 struct regcache *regcache,
1716 struct value **args,
1719 CORE_ADDR struct_addr)
1721 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1723 int size, onstack_size;
1724 gdb_byte *buf = (gdb_byte *) alloca (16);
1726 struct argument_info
1728 const bfd_byte *contents;
1730 int onstack; /* onstack == 0 => in reg */
1731 int align; /* alignment */
1734 int offset; /* stack offset if on stack. */
1735 int regno; /* regno if in register. */
1739 struct argument_info *arg_info =
1740 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1744 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1746 if (xtensa_debug_level > 3)
1749 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1750 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1751 "struct_addr=0x%x\n",
1752 (int) sp, (int) struct_return, (int) struct_addr);
1754 for (i = 0; i < nargs; i++)
1756 struct value *arg = args[i];
1757 struct type *arg_type = check_typedef (value_type (arg));
1758 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1759 host_address_to_string (arg),
1760 TYPE_LENGTH (arg_type));
1761 switch (TYPE_CODE (arg_type))
1764 fprintf_unfiltered (gdb_stdlog, "int");
1766 case TYPE_CODE_STRUCT:
1767 fprintf_unfiltered (gdb_stdlog, "struct");
1770 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1773 fprintf_unfiltered (gdb_stdlog, " %s\n",
1774 host_address_to_string (value_contents (arg)));
1778 /* First loop: collect information.
1779 Cast into type_long. (This shouldn't happen often for C because
1780 GDB already does this earlier.) It's possible that GDB could
1781 do it all the time but it's harmless to leave this code here. */
1788 size = REGISTER_SIZE;
1790 for (i = 0; i < nargs; i++)
1792 struct argument_info *info = &arg_info[i];
1793 struct value *arg = args[i];
1794 struct type *arg_type = check_typedef (value_type (arg));
1796 switch (TYPE_CODE (arg_type))
1799 case TYPE_CODE_BOOL:
1800 case TYPE_CODE_CHAR:
1801 case TYPE_CODE_RANGE:
1802 case TYPE_CODE_ENUM:
1804 /* Cast argument to long if necessary as the mask does it too. */
1805 if (TYPE_LENGTH (arg_type)
1806 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1808 arg_type = builtin_type (gdbarch)->builtin_long;
1809 arg = value_cast (arg_type, arg);
1811 /* Aligment is equal to the type length for the basic types. */
1812 info->align = TYPE_LENGTH (arg_type);
1817 /* Align doubles correctly. */
1818 if (TYPE_LENGTH (arg_type)
1819 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1820 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1822 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1825 case TYPE_CODE_STRUCT:
1827 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1830 info->length = TYPE_LENGTH (arg_type);
1831 info->contents = value_contents (arg);
1833 /* Align size and onstack_size. */
1834 size = (size + info->align - 1) & ~(info->align - 1);
1835 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1837 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1840 info->u.offset = onstack_size;
1841 onstack_size += info->length;
1846 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1848 size += info->length;
1851 /* Adjust the stack pointer and align it. */
1852 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1854 /* Simulate MOVSP, if Windowed ABI. */
1855 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1858 read_memory (osp - 16, buf, 16);
1859 write_memory (sp - 16, buf, 16);
1862 /* Second Loop: Load arguments. */
1866 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1867 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1870 for (i = 0; i < nargs; i++)
1872 struct argument_info *info = &arg_info[i];
1876 int n = info->length;
1877 CORE_ADDR offset = sp + info->u.offset;
1879 /* Odd-sized structs are aligned to the lower side of a memory
1880 word in big-endian mode and require a shift. This only
1881 applies for structures smaller than one word. */
1883 if (n < REGISTER_SIZE
1884 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1885 offset += (REGISTER_SIZE - n);
1887 write_memory (offset, info->contents, info->length);
1892 int n = info->length;
1893 const bfd_byte *cp = info->contents;
1894 int r = info->u.regno;
1896 /* Odd-sized structs are aligned to the lower side of registers in
1897 big-endian mode and require a shift. The odd-sized leftover will
1898 be at the end. Note that this is only true for structures smaller
1899 than REGISTER_SIZE; for larger odd-sized structures the excess
1900 will be left-aligned in the register on both endiannesses. */
1902 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1905 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1906 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1908 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1909 regcache_cooked_write (regcache, r, buf);
1911 cp += REGISTER_SIZE;
1918 regcache_cooked_write (regcache, r, cp);
1920 cp += REGISTER_SIZE;
1927 /* Set the return address of dummy frame to the dummy address.
1928 The return address for the current function (in A0) is
1929 saved in the dummy frame, so we can savely overwrite A0 here. */
1931 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1935 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1936 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1937 ps = (unsigned long) val & ~0x00030000;
1938 regcache_cooked_write_unsigned
1939 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1940 regcache_cooked_write_unsigned (regcache,
1941 gdbarch_ps_regnum (gdbarch),
1944 /* All the registers have been saved. After executing
1945 dummy call, they all will be restored. So it's safe
1946 to modify WINDOWSTART register to make it look like there
1947 is only one register window corresponding to WINDOWEBASE. */
1949 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1950 regcache_cooked_write_unsigned
1951 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1952 1 << extract_unsigned_integer (buf, 4, byte_order));
1956 /* Simulate CALL0: write RA into A0 register. */
1957 regcache_cooked_write_unsigned
1958 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1961 /* Set new stack pointer and return it. */
1962 regcache_cooked_write_unsigned (regcache,
1963 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1964 /* Make dummy frame ID unique by adding a constant. */
1965 return sp + SP_ALIGNMENT;
1969 /* Return a breakpoint for the current location of PC. We always use
1970 the density version if we have density instructions (regardless of the
1971 current instruction at PC), and use regular instructions otherwise. */
1973 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1974 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1975 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1976 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1978 static const unsigned char *
1979 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1982 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1983 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1984 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1985 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1987 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1989 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1991 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1993 *lenptr = sizeof (density_big_breakpoint);
1994 return density_big_breakpoint;
1998 *lenptr = sizeof (density_little_breakpoint);
1999 return density_little_breakpoint;
2004 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2006 *lenptr = sizeof (big_breakpoint);
2007 return big_breakpoint;
2011 *lenptr = sizeof (little_breakpoint);
2012 return little_breakpoint;
2017 /* Call0 ABI support routines. */
2019 /* Return true, if PC points to "ret" or "ret.n". */
2022 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2024 #define RETURN_RET goto done
2026 xtensa_insnbuf ins, slot;
2027 char ibuf[XTENSA_ISA_BSZ];
2028 CORE_ADDR ia, bt, ba;
2030 int ilen, islots, is;
2032 const char *opcname;
2035 isa = xtensa_default_isa;
2036 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2037 ins = xtensa_insnbuf_alloc (isa);
2038 slot = xtensa_insnbuf_alloc (isa);
2041 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2043 if (ia + xtensa_isa_maxlength (isa) > bt)
2046 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2047 ? ba + XTENSA_ISA_BSZ : finish_pc;
2048 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2052 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2053 ifmt = xtensa_format_decode (isa, ins);
2054 if (ifmt == XTENSA_UNDEFINED)
2056 ilen = xtensa_format_length (isa, ifmt);
2057 if (ilen == XTENSA_UNDEFINED)
2059 islots = xtensa_format_num_slots (isa, ifmt);
2060 if (islots == XTENSA_UNDEFINED)
2063 for (is = 0; is < islots; ++is)
2065 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2068 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2069 if (opc == XTENSA_UNDEFINED)
2072 opcname = xtensa_opcode_name (isa, opc);
2074 if ((strcasecmp (opcname, "ret.n") == 0)
2075 || (strcasecmp (opcname, "ret") == 0))
2083 xtensa_insnbuf_free(isa, slot);
2084 xtensa_insnbuf_free(isa, ins);
2088 /* Call0 opcode class. Opcodes are preclassified according to what they
2089 mean for Call0 prologue analysis, and their number of significant operands.
2090 The purpose of this is to simplify prologue analysis by separating
2091 instruction decoding (libisa) from the semantics of prologue analysis. */
2095 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2096 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2097 c0opc_flow, /* Flow control insn. */
2098 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2099 c0opc_break, /* Debugger software breakpoints. */
2100 c0opc_add, /* Adding two registers. */
2101 c0opc_addi, /* Adding a register and an immediate. */
2102 c0opc_and, /* Bitwise "and"-ing two registers. */
2103 c0opc_sub, /* Subtracting a register from a register. */
2104 c0opc_mov, /* Moving a register to a register. */
2105 c0opc_movi, /* Moving an immediate to a register. */
2106 c0opc_l32r, /* Loading a literal. */
2107 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2108 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2109 c0opc_l32e, /* L32E instruction. */
2110 c0opc_s32e, /* S32E instruction. */
2111 c0opc_rfwo, /* RFWO instruction. */
2112 c0opc_rfwu, /* RFWU instruction. */
2113 c0opc_NrOf /* Number of opcode classifications. */
2116 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2119 rwx_special_register (const char *opcname)
2121 char ch = *opcname++;
2123 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2125 if (*opcname++ != 's')
2127 if (*opcname++ != 'r')
2129 if (*opcname++ != '.')
2135 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2137 static xtensa_insn_kind
2138 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2140 const char *opcname;
2141 xtensa_insn_kind opclass = c0opc_uninteresting;
2143 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2145 /* Get opcode name and handle special classifications. */
2147 opcname = xtensa_opcode_name (isa, opc);
2150 || strcasecmp (opcname, "ill") == 0
2151 || strcasecmp (opcname, "ill.n") == 0)
2152 opclass = c0opc_illegal;
2153 else if (strcasecmp (opcname, "break") == 0
2154 || strcasecmp (opcname, "break.n") == 0)
2155 opclass = c0opc_break;
2156 else if (strcasecmp (opcname, "entry") == 0)
2157 opclass = c0opc_entry;
2158 else if (strcasecmp (opcname, "rfwo") == 0)
2159 opclass = c0opc_rfwo;
2160 else if (strcasecmp (opcname, "rfwu") == 0)
2161 opclass = c0opc_rfwu;
2162 else if (xtensa_opcode_is_branch (isa, opc) > 0
2163 || xtensa_opcode_is_jump (isa, opc) > 0
2164 || xtensa_opcode_is_loop (isa, opc) > 0
2165 || xtensa_opcode_is_call (isa, opc) > 0
2166 || strcasecmp (opcname, "simcall") == 0
2167 || strcasecmp (opcname, "syscall") == 0)
2168 opclass = c0opc_flow;
2170 /* Also, classify specific opcodes that need to be tracked. */
2171 else if (strcasecmp (opcname, "add") == 0
2172 || strcasecmp (opcname, "add.n") == 0)
2173 opclass = c0opc_add;
2174 else if (strcasecmp (opcname, "and") == 0)
2175 opclass = c0opc_and;
2176 else if (strcasecmp (opcname, "addi") == 0
2177 || strcasecmp (opcname, "addi.n") == 0
2178 || strcasecmp (opcname, "addmi") == 0)
2179 opclass = c0opc_addi;
2180 else if (strcasecmp (opcname, "sub") == 0)
2181 opclass = c0opc_sub;
2182 else if (strcasecmp (opcname, "mov.n") == 0
2183 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2184 opclass = c0opc_mov;
2185 else if (strcasecmp (opcname, "movi") == 0
2186 || strcasecmp (opcname, "movi.n") == 0)
2187 opclass = c0opc_movi;
2188 else if (strcasecmp (opcname, "l32r") == 0)
2189 opclass = c0opc_l32r;
2190 else if (strcasecmp (opcname, "s32i") == 0
2191 || strcasecmp (opcname, "s32i.n") == 0)
2192 opclass = c0opc_s32i;
2193 else if (strcasecmp (opcname, "l32e") == 0)
2194 opclass = c0opc_l32e;
2195 else if (strcasecmp (opcname, "s32e") == 0)
2196 opclass = c0opc_s32e;
2197 else if (rwx_special_register (opcname))
2198 opclass = c0opc_rwxsr;
2203 /* Tracks register movement/mutation for a given operation, which may
2204 be within a bundle. Updates the destination register tracking info
2205 accordingly. The pc is needed only for pc-relative load instructions
2206 (eg. l32r). The SP register number is needed to identify stores to
2207 the stack frame. Returns 0, if analysis was succesfull, non-zero
2211 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2212 xtensa_insn_kind opclass, int nods, unsigned odv[],
2213 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2215 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2216 unsigned litbase, litaddr, litval;
2221 /* 3 operands: dst, src, imm. */
2222 gdb_assert (nods == 3);
2223 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2224 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2227 /* 3 operands: dst, src1, src2. */
2228 gdb_assert (nods == 3);
2229 if (src[odv[1]].fr_reg == C0_CONST)
2231 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2232 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2234 else if (src[odv[2]].fr_reg == C0_CONST)
2236 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2237 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2239 else dst[odv[0]].fr_reg = C0_INEXP;
2242 /* 3 operands: dst, src1, src2. */
2243 gdb_assert (nods == 3);
2244 if (cache->c0.c0_fpalign == 0)
2246 /* Handle dynamic stack alignment. */
2247 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2249 if (src[odv[2]].fr_reg == C0_CONST)
2250 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2253 else if ((src[odv[0]].fr_reg == spreg)
2254 && (src[odv[2]].fr_reg == spreg))
2256 if (src[odv[1]].fr_reg == C0_CONST)
2257 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2260 /* else fall through. */
2262 if (src[odv[1]].fr_reg == C0_CONST)
2264 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2265 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2267 else if (src[odv[2]].fr_reg == C0_CONST)
2269 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2270 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2272 else dst[odv[0]].fr_reg = C0_INEXP;
2275 /* 3 operands: dst, src1, src2. */
2276 gdb_assert (nods == 3);
2277 if (src[odv[2]].fr_reg == C0_CONST)
2279 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2280 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2282 else dst[odv[0]].fr_reg = C0_INEXP;
2285 /* 2 operands: dst, src [, src]. */
2286 gdb_assert (nods == 2);
2287 /* First, check if it's a special case of saving unaligned SP
2288 to a spare register in case of dynamic stack adjustment.
2289 But, only do it one time. The second time could be initializing
2290 frame pointer. We don't want to overwrite the first one. */
2291 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2292 cache->c0.c0_old_sp = odv[0];
2294 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2295 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2298 /* 2 operands: dst, imm. */
2299 gdb_assert (nods == 2);
2300 dst[odv[0]].fr_reg = C0_CONST;
2301 dst[odv[0]].fr_ofs = odv[1];
2304 /* 2 operands: dst, literal offset. */
2305 gdb_assert (nods == 2);
2306 /* litbase = xtensa_get_litbase (pc); can be also used. */
2307 litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
2308 ? 0 : xtensa_read_register
2309 (gdbarch_tdep (gdbarch)->litbase_regnum);
2310 litaddr = litbase & 1
2311 ? (litbase & ~1) + (signed)odv[1]
2312 : (pc + 3 + (signed)odv[1]) & ~3;
2313 litval = read_memory_integer (litaddr, 4, byte_order);
2314 dst[odv[0]].fr_reg = C0_CONST;
2315 dst[odv[0]].fr_ofs = litval;
2318 /* 3 operands: value, base, offset. */
2319 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2320 /* First, check if it's a spill for saved unaligned SP,
2321 when dynamic stack adjustment was applied to this frame. */
2322 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2323 && (odv[1] == spreg) /* SP usage indicates spill. */
2324 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2325 cache->c0.c0_sp_ofs = odv[2];
2327 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2328 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2329 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2330 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2331 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2333 /* ISA encoding guarantees alignment. But, check it anyway. */
2334 gdb_assert ((odv[2] & 3) == 0);
2335 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2338 /* If we end up inside Window Overflow / Underflow interrupt handler
2339 report an error because these handlers should have been handled
2340 already in a different way. */
2352 /* Analyze prologue of the function at start address to determine if it uses
2353 the Call0 ABI, and if so track register moves and linear modifications
2354 in the prologue up to the PC or just beyond the prologue, whichever is
2355 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2356 prologue. The prologue may overlap non-prologue instructions but is
2357 guaranteed to end by the first flow-control instruction (jump, branch,
2358 call or return). Since an optimized function may move information around
2359 and change the stack frame arbitrarily during the prologue, the information
2360 is guaranteed valid only at the point in the function indicated by the PC.
2361 May be used to skip the prologue or identify the ABI, w/o tracking.
2363 Returns: Address of first instruction after prologue, or PC (whichever
2364 is first), or 0, if decoding failed (in libisa).
2366 start Start address of function/prologue.
2367 pc Program counter to stop at. Use 0 to continue to end of prologue.
2368 If 0, avoids infinite run-on in corrupt code memory by bounding
2369 the scan to the end of the function if that can be determined.
2370 nregs Number of general registers to track.
2372 cache Xtensa frame cache.
2374 Note that these may produce useful results even if decoding fails
2375 because they begin with default assumptions that analysis may change. */
2378 call0_analyze_prologue (struct gdbarch *gdbarch,
2379 CORE_ADDR start, CORE_ADDR pc,
2380 int nregs, xtensa_frame_cache_t *cache)
2382 CORE_ADDR ia; /* Current insn address in prologue. */
2383 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2384 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2385 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2386 xtensa_isa isa; /* libisa ISA handle. */
2387 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2388 xtensa_format ifmt; /* libisa instruction format. */
2389 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2390 xtensa_opcode opc; /* Opcode in current slot. */
2391 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2392 int nods; /* Opcode number of operands. */
2393 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2394 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2395 int j; /* General loop counter. */
2396 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2397 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2398 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2400 struct symtab_and_line prologue_sal;
2402 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2403 (int)start, (int)pc);
2405 /* Try to limit the scan to the end of the function if a non-zero pc
2406 arg was not supplied to avoid probing beyond the end of valid memory.
2407 If memory is full of garbage that classifies as c0opc_uninteresting.
2408 If this fails (eg. if no symbols) pc ends up 0 as it was.
2409 Intialize the Call0 frame and register tracking info.
2410 Assume it's Call0 until an 'entry' instruction is encountered.
2411 Assume we may be in the prologue until we hit a flow control instr. */
2417 /* Find out, if we have an information about the prologue from DWARF. */
2418 prologue_sal = find_pc_line (start, 0);
2419 if (prologue_sal.line != 0) /* Found debug info. */
2420 body_pc = prologue_sal.end;
2422 /* If we are going to analyze the prologue in general without knowing about
2423 the current PC, make the best assumtion for the end of the prologue. */
2426 find_pc_partial_function (start, 0, NULL, &end_pc);
2427 body_pc = min (end_pc, body_pc);
2430 body_pc = min (pc, body_pc);
2433 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2435 if (!xtensa_default_isa)
2436 xtensa_default_isa = xtensa_isa_init (0, 0);
2437 isa = xtensa_default_isa;
2438 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2439 ins = xtensa_insnbuf_alloc (isa);
2440 slot = xtensa_insnbuf_alloc (isa);
2442 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2444 /* (Re)fill instruction buffer from memory if necessary, but do not
2445 read memory beyond PC to be sure we stay within text section
2446 (this protection only works if a non-zero pc is supplied). */
2448 if (ia + xtensa_isa_maxlength (isa) > bt)
2451 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2452 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2453 error (_("Unable to read target memory ..."));
2456 /* Decode format information. */
2458 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2459 ifmt = xtensa_format_decode (isa, ins);
2460 if (ifmt == XTENSA_UNDEFINED)
2465 ilen = xtensa_format_length (isa, ifmt);
2466 if (ilen == XTENSA_UNDEFINED)
2471 islots = xtensa_format_num_slots (isa, ifmt);
2472 if (islots == XTENSA_UNDEFINED)
2478 /* Analyze a bundle or a single instruction, using a snapshot of
2479 the register tracking info as input for the entire bundle so that
2480 register changes do not take effect within this bundle. */
2482 for (j = 0; j < nregs; ++j)
2483 rtmp[j] = cache->c0.c0_rt[j];
2485 for (is = 0; is < islots; ++is)
2487 /* Decode a slot and classify the opcode. */
2489 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2493 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2494 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2496 if (opc == XTENSA_UNDEFINED)
2497 opclass = c0opc_illegal;
2499 opclass = call0_classify_opcode (isa, opc);
2501 /* Decide whether to track this opcode, ignore it, or bail out. */
2510 case c0opc_uninteresting:
2513 case c0opc_flow: /* Flow control instructions stop analysis. */
2514 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2519 ia += ilen; /* Skip over 'entry' insn. */
2526 /* Only expected opcodes should get this far. */
2528 /* Extract and decode the operands. */
2529 nods = xtensa_opcode_num_operands (isa, opc);
2530 if (nods == XTENSA_UNDEFINED)
2536 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2538 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2543 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2548 /* Check operands to verify use of 'mov' assembler macro. */
2549 if (opclass == c0opc_mov && nods == 3)
2551 if (odv[2] == odv[1])
2554 if ((odv[0] == 1) && (odv[1] != 1))
2555 /* OR A1, An, An , where n != 1.
2556 This means we are inside epilogue already. */
2561 opclass = c0opc_uninteresting;
2566 /* Track register movement and modification for this operation. */
2567 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2568 opclass, nods, odv, ia, 1, cache);
2574 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2575 (unsigned)ia, fail ? "failed" : "succeeded");
2576 xtensa_insnbuf_free(isa, slot);
2577 xtensa_insnbuf_free(isa, ins);
2578 return fail ? XTENSA_ISA_BADPC : ia;
2581 /* Initialize frame cache for the current frame in CALL0 ABI. */
2584 call0_frame_cache (struct frame_info *this_frame,
2585 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2587 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2588 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2589 CORE_ADDR start_pc; /* The beginning of the function. */
2590 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2591 CORE_ADDR sp, fp, ra;
2592 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2594 sp = get_frame_register_unsigned
2595 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2596 fp = sp; /* Assume FP == SP until proven otherwise. */
2598 /* Find the beginning of the prologue of the function containing the PC
2599 and analyze it up to the PC or the end of the prologue. */
2601 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2603 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2605 if (body_pc == XTENSA_ISA_BADPC)
2609 goto finish_frame_analysis;
2613 /* Get the frame information and FP (if used) at the current PC.
2614 If PC is in the prologue, the prologue analysis is more reliable
2615 than DWARF info. We don't not know for sure, if PC is in the prologue,
2616 but we do know no calls have yet taken place, so we can almost
2617 certainly rely on the prologue analysis. */
2621 /* Prologue analysis was successful up to the PC.
2622 It includes the cases when PC == START_PC. */
2623 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2624 /* c0_hasfp == true means there is a frame pointer because
2625 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2626 was derived from SP. Otherwise, it would be C0_FP. */
2627 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2628 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2629 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2631 else /* No data from the prologue analysis. */
2634 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2639 if (cache->c0.c0_fpalign)
2641 /* This frame has a special prologue with a dynamic stack adjustment
2642 to force an alignment, which is bigger than standard 16 bytes. */
2644 CORE_ADDR unaligned_sp;
2646 if (cache->c0.c0_old_sp == C0_INEXP)
2647 /* This can't be. Prologue code should be consistent.
2648 Unaligned stack pointer should be saved in a spare register. */
2652 goto finish_frame_analysis;
2655 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2656 /* Saved unaligned value of SP is kept in a register. */
2657 unaligned_sp = get_frame_register_unsigned
2658 (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
2660 /* Get the value from stack. */
2661 unaligned_sp = (CORE_ADDR)
2662 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2664 prev_sp = unaligned_sp + c0_frmsz;
2667 prev_sp = fp + c0_frmsz;
2669 /* Frame size from debug info or prologue tracking does not account for
2670 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2673 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2675 /* Update the stack frame size. */
2676 c0_frmsz += fp - sp;
2679 /* Get the return address (RA) from the stack if saved,
2680 or try to get it from a register. */
2682 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2683 if (to_stk != C0_NOSTK)
2685 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2688 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2689 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2691 /* Special case for terminating backtrace at a function that wants to
2692 be seen as the outermost one. Such a function will clear it's RA (A0)
2693 register to 0 in the prologue instead of saving its original value. */
2698 /* RA was copied to another register or (before any function call) may
2699 still be in the original RA register. This is not always reliable:
2700 even in a leaf function, register tracking stops after prologue, and
2701 even in prologue, non-prologue instructions (not tracked) may overwrite
2702 RA or any register it was copied to. If likely in prologue or before
2703 any call, use retracking info and hope for the best (compiler should
2704 have saved RA in stack if not in a leaf function). If not in prologue,
2710 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2712 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2716 ra = get_frame_register_unsigned
2718 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2723 finish_frame_analysis:
2724 cache->pc = start_pc;
2726 /* RA == 0 marks the outermost frame. Do not go past it. */
2727 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2728 cache->c0.fp_regnum = fp_regnum;
2729 cache->c0.c0_frmsz = c0_frmsz;
2730 cache->c0.c0_hasfp = c0_hasfp;
2731 cache->c0.c0_fp = fp;
2734 static CORE_ADDR a0_saved;
2735 static CORE_ADDR a7_saved;
2736 static CORE_ADDR a11_saved;
2737 static int a0_was_saved;
2738 static int a7_was_saved;
2739 static int a11_was_saved;
2741 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2743 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2745 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2746 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2747 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2748 unsigned int spilled_value
2749 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2751 if ((at == 0) && !a0_was_saved)
2753 a0_saved = xtensa_read_register (atreg);
2756 else if ((at == 7) && !a7_was_saved)
2758 a7_saved = xtensa_read_register (atreg);
2761 else if ((at == 11) && !a11_was_saved)
2763 a11_saved = xtensa_read_register (atreg);
2767 xtensa_write_register (atreg, spilled_value);
2770 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2772 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2774 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2775 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2776 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2777 ULONGEST spilled_value = xtensa_read_register (atreg);
2779 write_memory_unsigned_integer (addr, 4,
2780 gdbarch_byte_order (gdbarch),
2784 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2790 xtNoExceptionHandler
2791 } xtensa_exception_handler_t;
2793 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2794 Return type of Xtensa Window Interrupt Handler on success. */
2795 static xtensa_exception_handler_t
2796 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2799 xtensa_insnbuf ins, slot;
2800 char ibuf[XTENSA_ISA_BSZ];
2801 CORE_ADDR ia, bt, ba;
2803 int ilen, islots, is;
2807 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2812 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2813 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2815 isa = xtensa_default_isa;
2816 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2817 ins = xtensa_insnbuf_alloc (isa);
2818 slot = xtensa_insnbuf_alloc (isa);
2827 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2829 if (ia + xtensa_isa_maxlength (isa) > bt)
2832 bt = (ba + XTENSA_ISA_BSZ);
2833 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2834 return xtNoExceptionHandler;
2836 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2837 ifmt = xtensa_format_decode (isa, ins);
2838 if (ifmt == XTENSA_UNDEFINED)
2839 return xtNoExceptionHandler;
2840 ilen = xtensa_format_length (isa, ifmt);
2841 if (ilen == XTENSA_UNDEFINED)
2842 return xtNoExceptionHandler;
2843 islots = xtensa_format_num_slots (isa, ifmt);
2844 if (islots == XTENSA_UNDEFINED)
2845 return xtNoExceptionHandler;
2846 for (is = 0; is < islots; ++is)
2848 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2849 return xtNoExceptionHandler;
2850 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2851 if (opc == XTENSA_UNDEFINED)
2852 return xtNoExceptionHandler;
2853 switch (call0_classify_opcode (isa, opc))
2859 /* We expect none of them here. */
2860 return xtNoExceptionHandler;
2862 func = execute_l32e;
2865 func = execute_s32e;
2867 case c0opc_rfwo: /* RFWO. */
2868 /* Here, we return from WindowOverflow handler and,
2869 if we stopped at the very beginning, which means
2870 A0 was saved, we have to restore it now. */
2873 int arreg = arreg_number (gdbarch,
2874 gdbarch_tdep (gdbarch)->a0_base,
2876 xtensa_write_register (arreg, a0_saved);
2878 return xtWindowOverflow;
2879 case c0opc_rfwu: /* RFWU. */
2880 /* Here, we return from WindowUnderflow handler.
2881 Let's see if either A7 or A11 has to be restored. */
2882 if (WindowUnderflow12)
2886 int arreg = arreg_number (gdbarch,
2887 gdbarch_tdep (gdbarch)->a0_base + 11,
2889 xtensa_write_register (arreg, a11_saved);
2892 else if (a7_was_saved)
2894 int arreg = arreg_number (gdbarch,
2895 gdbarch_tdep (gdbarch)->a0_base + 7,
2897 xtensa_write_register (arreg, a7_saved);
2899 return xtWindowUnderflow;
2900 default: /* Simply skip this insns. */
2904 /* Decode arguments for L32E / S32E and simulate their execution. */
2905 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2906 return xtNoExceptionHandler;
2907 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2908 return xtNoExceptionHandler;
2909 if (xtensa_operand_decode (isa, opc, 0, &at))
2910 return xtNoExceptionHandler;
2911 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2912 return xtNoExceptionHandler;
2913 if (xtensa_operand_decode (isa, opc, 1, &as))
2914 return xtNoExceptionHandler;
2915 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2916 return xtNoExceptionHandler;
2917 if (xtensa_operand_decode (isa, opc, 2, &offset))
2918 return xtNoExceptionHandler;
2920 (*func) (gdbarch, at, as, offset, wb);
2925 return xtNoExceptionHandler;
2928 /* Handle Window Overflow / Underflow exception frames. */
2931 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2932 xtensa_frame_cache_t *cache,
2935 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2936 CORE_ADDR ps, wb, ws, ra;
2937 int epc1_regnum, i, regnum;
2938 xtensa_exception_handler_t eh_type;
2940 /* Read PS, WB, and WS from the hardware. Note that PS register
2941 must be present, if Windowed ABI is supported. */
2942 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2943 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2944 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2946 /* Execute all the remaining instructions from Window Interrupt Handler
2947 by simulating them on the remote protocol level. On return, set the
2948 type of Xtensa Window Interrupt Handler, or report an error. */
2949 eh_type = execute_code (gdbarch, pc, wb);
2950 if (eh_type == xtNoExceptionHandler)
2952 Unable to decode Xtensa Window Interrupt Handler's code."));
2954 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2955 cache->call0 = 0; /* It's Windowed ABI. */
2957 /* All registers for the cached frame will be alive. */
2958 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2959 cache->wd.aregs[i] = -1;
2961 if (eh_type == xtWindowOverflow)
2962 cache->wd.ws = ws ^ (1 << wb);
2963 else /* eh_type == xtWindowUnderflow. */
2964 cache->wd.ws = ws | (1 << wb);
2966 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2967 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2969 ra = xtensa_read_register (regnum);
2970 cache->wd.callsize = WINSIZE (ra);
2971 cache->prev_sp = xtensa_read_register (regnum + 1);
2972 /* Set regnum to a frame pointer of the frame being cached. */
2973 regnum = xtensa_scan_prologue (gdbarch, pc);
2974 regnum = arreg_number (gdbarch,
2975 gdbarch_tdep (gdbarch)->a0_base + regnum,
2977 cache->base = get_frame_register_unsigned (this_frame, regnum);
2979 /* Read PC of interrupted function from EPC1 register. */
2980 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2981 if (epc1_regnum < 0)
2982 error(_("Unable to read Xtensa register EPC1"));
2983 cache->ra = xtensa_read_register (epc1_regnum);
2984 cache->pc = get_frame_func (this_frame);
2988 /* Skip function prologue.
2990 Return the pc of the first instruction after prologue. GDB calls this to
2991 find the address of the first line of the function or (if there is no line
2992 number information) to skip the prologue for planting breakpoints on
2993 function entries. Use debug info (if present) or prologue analysis to skip
2994 the prologue to achieve reliable debugging behavior. For windowed ABI,
2995 only the 'entry' instruction is skipped. It is not strictly necessary to
2996 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2997 backtrace at any point in the prologue, however certain potential hazards
2998 are avoided and a more "normal" debugging experience is ensured by
2999 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
3000 For example, if we don't skip the prologue:
3001 - Some args may not yet have been saved to the stack where the debug
3002 info expects to find them (true anyway when only 'entry' is skipped);
3003 - Software breakpoints ('break' instrs) may not have been unplanted
3004 when the prologue analysis is done on initializing the frame cache,
3005 and breaks in the prologue will throw off the analysis.
3007 If we have debug info ( line-number info, in particular ) we simply skip
3008 the code associated with the first function line effectively skipping
3009 the prologue code. It works even in cases like
3012 { int local_var = 1;
3016 because, for this source code, both Xtensa compilers will generate two
3017 separate entries ( with the same line number ) in dwarf line-number
3018 section to make sure there is a boundary between the prologue code and
3019 the rest of the function.
3021 If there is no debug info, we need to analyze the code. */
3023 /* #define DONT_SKIP_PROLOGUE */
3026 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
3028 struct symtab_and_line prologue_sal;
3031 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3033 #if DONT_SKIP_PROLOGUE
3037 /* Try to find first body line from debug info. */
3039 prologue_sal = find_pc_line (start_pc, 0);
3040 if (prologue_sal.line != 0) /* Found debug info. */
3042 /* In Call0, it is possible to have a function with only one instruction
3043 ('ret') resulting from a one-line optimized function that does nothing.
3044 In that case, prologue_sal.end may actually point to the start of the
3045 next function in the text section, causing a breakpoint to be set at
3046 the wrong place. Check, if the end address is within a different
3047 function, and if so return the start PC. We know we have symbol
3052 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
3053 && call0_ret (start_pc, prologue_sal.end))
3056 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3057 if (end_func != start_pc)
3060 return prologue_sal.end;
3063 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3064 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3065 xtensa_alloc_frame_cache (0));
3066 return body_pc != 0 ? body_pc : start_pc;
3069 /* Verify the current configuration. */
3071 xtensa_verify_config (struct gdbarch *gdbarch)
3073 struct ui_file *log;
3074 struct cleanup *cleanups;
3075 struct gdbarch_tdep *tdep;
3079 tdep = gdbarch_tdep (gdbarch);
3080 log = mem_fileopen ();
3081 cleanups = make_cleanup_ui_file_delete (log);
3083 /* Verify that we got a reasonable number of AREGS. */
3084 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3085 fprintf_unfiltered (log, _("\
3086 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3089 /* Verify that certain registers exist. */
3091 if (tdep->pc_regnum == -1)
3092 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
3093 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3094 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
3096 if (tdep->isa_use_windowed_registers)
3098 if (tdep->wb_regnum == -1)
3099 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
3100 if (tdep->ws_regnum == -1)
3101 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
3102 if (tdep->ar_base == -1)
3103 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
3106 if (tdep->a0_base == -1)
3107 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
3109 buf = ui_file_xstrdup (log, &length);
3110 make_cleanup (xfree, buf);
3112 internal_error (__FILE__, __LINE__,
3113 _("the following are invalid: %s"), buf);
3114 do_cleanups (cleanups);
3118 /* Derive specific register numbers from the array of registers. */
3121 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
3123 xtensa_register_t* rmap;
3124 int n, max_size = 4;
3127 tdep->num_nopriv_regs = 0;
3129 /* Special registers 0..255 (core). */
3130 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3132 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3134 if (rmap->target_number == 0x0020)
3135 tdep->pc_regnum = n;
3136 else if (rmap->target_number == 0x0100)
3138 else if (rmap->target_number == 0x0000)
3140 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3141 tdep->wb_regnum = n;
3142 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3143 tdep->ws_regnum = n;
3144 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3145 tdep->debugcause_regnum = n;
3146 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3147 tdep->exccause_regnum = n;
3148 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3149 tdep->excvaddr_regnum = n;
3150 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3151 tdep->lbeg_regnum = n;
3152 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3153 tdep->lend_regnum = n;
3154 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3155 tdep->lcount_regnum = n;
3156 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3157 tdep->sar_regnum = n;
3158 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3159 tdep->litbase_regnum = n;
3160 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3161 tdep->ps_regnum = n;
3163 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3164 tdep->interrupt_regnum = n;
3165 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3166 tdep->interrupt2_regnum = n;
3167 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3168 tdep->cpenable_regnum = n;
3171 if (rmap->byte_size > max_size)
3172 max_size = rmap->byte_size;
3173 if (rmap->mask != 0 && tdep->num_regs == 0)
3175 /* Find out out how to deal with priveleged registers.
3177 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3178 && tdep->num_nopriv_regs == 0)
3179 tdep->num_nopriv_regs = n;
3181 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3182 && tdep->num_regs == 0)
3186 /* Number of pseudo registers. */
3187 tdep->num_pseudo_regs = n - tdep->num_regs;
3189 /* Empirically determined maximum sizes. */
3190 tdep->max_register_raw_size = max_size;
3191 tdep->max_register_virtual_size = max_size;
3194 /* Module "constructor" function. */
3196 extern struct gdbarch_tdep xtensa_tdep;
3198 static struct gdbarch *
3199 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3201 struct gdbarch_tdep *tdep;
3202 struct gdbarch *gdbarch;
3203 struct xtensa_abi_handler *abi_handler;
3205 DEBUGTRACE ("gdbarch_init()\n");
3207 /* We have to set the byte order before we call gdbarch_alloc. */
3208 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3210 tdep = &xtensa_tdep;
3211 gdbarch = gdbarch_alloc (&info, tdep);
3212 xtensa_derive_tdep (tdep);
3214 /* Verify our configuration. */
3215 xtensa_verify_config (gdbarch);
3216 xtensa_session_once_reported = 0;
3218 /* Pseudo-Register read/write. */
3219 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3220 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3222 /* Set target information. */
3223 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3224 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3225 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3226 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3227 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3229 /* Renumber registers for known formats (stabs and dwarf2). */
3230 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3231 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3233 /* We provide our own function to get register information. */
3234 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3235 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3237 /* To call functions from GDB using dummy frame. */
3238 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3240 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3242 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3244 /* Advance PC across any prologue instructions to reach "real" code. */
3245 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3247 /* Stack grows downward. */
3248 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3250 /* Set breakpoints. */
3251 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
3253 /* After breakpoint instruction or illegal instruction, pc still
3254 points at break instruction, so don't decrement. */
3255 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3257 /* We don't skip args. */
3258 set_gdbarch_frame_args_skip (gdbarch, 0);
3260 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3262 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3264 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3266 /* Frame handling. */
3267 frame_base_set_default (gdbarch, &xtensa_frame_base);
3268 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3269 dwarf2_append_unwinders (gdbarch);
3271 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3273 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3275 xtensa_add_reggroups (gdbarch);
3276 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3278 set_gdbarch_regset_from_core_section (gdbarch,
3279 xtensa_regset_from_core_section);
3281 set_solib_svr4_fetch_link_map_offsets
3282 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3288 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3290 error (_("xtensa_dump_tdep(): not implemented"));
3293 /* Provide a prototype to silence -Wmissing-prototypes. */
3294 extern initialize_file_ftype _initialize_xtensa_tdep;
3297 _initialize_xtensa_tdep (void)
3299 struct cmd_list_element *c;
3301 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3302 xtensa_init_reggroups ();
3304 add_setshow_zinteger_cmd ("xtensa",
3306 &xtensa_debug_level,
3307 _("Set Xtensa debugging."),
3308 _("Show Xtensa debugging."), _("\
3309 When non-zero, Xtensa-specific debugging is enabled. \
3310 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3313 &setdebuglist, &showdebuglist);