1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
142 arreg = a_regnum - tdep->a0_base;
143 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
144 arreg &= tdep->num_aregs - 1;
146 return arreg + tdep->ar_base;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 areg = ar_regnum - tdep->ar_base;
158 if (areg < 0 || areg >= tdep->num_aregs)
160 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
161 return (areg > 15) ? -1 : areg;
164 /* Return the window size of the previous call to the function from which we
167 This function is used to extract the return value after a called function
168 has returned to the caller. On Xtensa, the register that holds the return
169 value (from the perspective of the caller) depends on what call
170 instruction was used. For now, we are assuming that the call instruction
171 precedes the current address, so we simply analyze the call instruction.
172 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
173 method to call the inferior function. */
176 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
178 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
183 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
185 /* Read the previous instruction (should be a call[x]{4|8|12}. */
186 read_memory (pc-3, buf, 3);
187 insn = extract_unsigned_integer (buf, 3, byte_order);
189 /* Decode call instruction:
191 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
192 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
194 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
195 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
197 if (byte_order == BFD_ENDIAN_LITTLE)
199 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
200 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
204 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
205 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
211 /* REGISTER INFORMATION */
213 /* Returns the name of a register. */
215 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
217 /* Return the name stored in the register map. */
218 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
219 + gdbarch_num_pseudo_regs (gdbarch))
220 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
222 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
226 /* Return the type of a register. Create a new type, if necessary. */
229 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233 /* Return signed integer for ARx and Ax registers. */
234 if ((regnum >= tdep->ar_base
235 && regnum < tdep->ar_base + tdep->num_aregs)
236 || (regnum >= tdep->a0_base
237 && regnum < tdep->a0_base + 16))
238 return builtin_type (gdbarch)->builtin_int;
240 if (regnum == gdbarch_pc_regnum (gdbarch)
241 || regnum == tdep->a0_base + 1)
242 return builtin_type (gdbarch)->builtin_data_ptr;
244 /* Return the stored type for all other registers. */
245 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
246 + gdbarch_num_pseudo_regs (gdbarch))
248 xtensa_register_t* reg = &tdep->regmap[regnum];
250 /* Set ctype for this register (only the first time). */
254 struct ctype_cache *tp;
255 int size = reg->byte_size;
257 /* We always use the memory representation,
258 even if the register width is smaller. */
262 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
266 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
270 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
274 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
278 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
282 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
283 if (tp->size == size)
288 char *name = xmalloc (16);
289 tp = xmalloc (sizeof (struct ctype_cache));
290 tp->next = tdep->type_entries;
291 tdep->type_entries = tp;
294 sprintf (name, "int%d", size * 8);
296 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
299 reg->ctype = tp->virtual_type;
305 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
310 /* Return the 'local' register number for stubs, dwarf2, etc.
311 The debugging information enumerates registers starting from 0 for A0
312 to n for An. So, we only have to add the base number for A0. */
315 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
319 if (regnum >= 0 && regnum < 16)
320 return gdbarch_tdep (gdbarch)->a0_base + regnum;
323 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
325 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
328 internal_error (__FILE__, __LINE__,
329 _("invalid dwarf/stabs register number %d"), regnum);
334 /* Write the bits of a masked register to the various registers.
335 Only the masked areas of these registers are modified; the other
336 fields are untouched. The size of masked registers is always less
337 than or equal to 32 bits. */
340 xtensa_register_write_masked (struct regcache *regcache,
341 xtensa_register_t *reg, const gdb_byte *buffer)
343 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
344 const xtensa_mask_t *mask = reg->mask;
346 int shift = 0; /* Shift for next mask (mod 32). */
347 int start, size; /* Start bit and size of current mask. */
349 unsigned int *ptr = value;
350 unsigned int regval, m, mem = 0;
352 int bytesize = reg->byte_size;
353 int bitsize = bytesize * 8;
356 DEBUGTRACE ("xtensa_register_write_masked ()\n");
358 /* Copy the masked register to host byte-order. */
359 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
360 for (i = 0; i < bytesize; i++)
363 mem |= (buffer[bytesize - i - 1] << 24);
368 for (i = 0; i < bytesize; i++)
371 mem |= (buffer[i] << 24);
376 /* We might have to shift the final value:
377 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
378 bytesize & 3 == x -> shift (4-x) * 8. */
380 *ptr = mem >> (((0 - bytesize) & 3) * 8);
384 /* Write the bits to the masked areas of the other registers. */
385 for (i = 0; i < mask->count; i++)
387 start = mask->mask[i].bit_start;
388 size = mask->mask[i].bit_size;
389 regval = mem >> shift;
391 if ((shift += size) > bitsize)
392 error (_("size of all masks is larger than the register"));
401 regval |= mem << (size - shift);
404 /* Make sure we have a valid register. */
405 r = mask->mask[i].reg_num;
406 if (r >= 0 && size > 0)
408 /* Don't overwrite the unmasked areas. */
410 regcache_cooked_read_unsigned (regcache, r, &old_val);
411 m = 0xffffffff >> (32 - size) << start;
413 regval = (regval & m) | (old_val & ~m);
414 regcache_cooked_write_unsigned (regcache, r, regval);
420 /* Read a tie state or mapped registers. Read the masked areas
421 of the registers and assemble them into a single value. */
424 xtensa_register_read_masked (struct regcache *regcache,
425 xtensa_register_t *reg, gdb_byte *buffer)
427 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
428 const xtensa_mask_t *mask = reg->mask;
433 unsigned int *ptr = value;
434 unsigned int regval, mem = 0;
436 int bytesize = reg->byte_size;
437 int bitsize = bytesize * 8;
440 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
441 reg->name == 0 ? "" : reg->name);
443 /* Assemble the register from the masked areas of other registers. */
444 for (i = 0; i < mask->count; i++)
446 int r = mask->mask[i].reg_num;
450 regcache_cooked_read_unsigned (regcache, r, &val);
451 regval = (unsigned int) val;
456 start = mask->mask[i].bit_start;
457 size = mask->mask[i].bit_size;
462 regval &= (0xffffffff >> (32 - size));
464 mem |= regval << shift;
466 if ((shift += size) > bitsize)
467 error (_("size of all masks is larger than the register"));
478 mem = regval >> (size - shift);
485 /* Copy value to target byte order. */
489 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
490 for (i = 0; i < bytesize; i++)
494 buffer[bytesize - i - 1] = mem & 0xff;
498 for (i = 0; i < bytesize; i++)
502 buffer[i] = mem & 0xff;
508 /* Read pseudo registers. */
511 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
512 struct regcache *regcache,
516 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
518 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
519 regnum, xtensa_register_name (gdbarch, regnum));
521 if (regnum == gdbarch_num_regs (gdbarch)
522 + gdbarch_num_pseudo_regs (gdbarch) - 1)
523 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
525 /* Read aliases a0..a15, if this is a Windowed ABI. */
526 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
527 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
528 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
530 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
532 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
533 regnum = arreg_number (gdbarch, regnum,
534 extract_unsigned_integer (buf, 4, byte_order));
537 /* We can always read non-pseudo registers. */
538 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
539 regcache_raw_read (regcache, regnum, buffer);
542 /* We have to find out how to deal with priveleged registers.
543 Let's treat them as pseudo-registers, but we cannot read/write them. */
545 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
547 buffer[0] = (gdb_byte)0;
548 buffer[1] = (gdb_byte)0;
549 buffer[2] = (gdb_byte)0;
550 buffer[3] = (gdb_byte)0;
552 /* Pseudo registers. */
554 && regnum < gdbarch_num_regs (gdbarch)
555 + gdbarch_num_pseudo_regs (gdbarch))
557 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
558 xtensa_register_type_t type = reg->type;
559 int flags = gdbarch_tdep (gdbarch)->target_flags;
561 /* We cannot read Unknown or Unmapped registers. */
562 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
564 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
566 warning (_("cannot read register %s"),
567 xtensa_register_name (gdbarch, regnum));
572 /* Some targets cannot read TIE register files. */
573 else if (type == xtRegisterTypeTieRegfile)
575 /* Use 'fetch' to get register? */
576 if (flags & xtTargetFlagsUseFetchStore)
578 warning (_("cannot read register"));
582 /* On some targets (esp. simulators), we can always read the reg. */
583 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
585 warning (_("cannot read register"));
590 /* We can always read mapped registers. */
591 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
593 xtensa_register_read_masked (regcache, reg, buffer);
597 /* Assume that we can read the register. */
598 regcache_raw_read (regcache, regnum, buffer);
601 internal_error (__FILE__, __LINE__,
602 _("invalid register number %d"), regnum);
606 /* Write pseudo registers. */
609 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
610 struct regcache *regcache,
612 const gdb_byte *buffer)
614 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
616 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
617 regnum, xtensa_register_name (gdbarch, regnum));
619 if (regnum == gdbarch_num_regs (gdbarch)
620 + gdbarch_num_pseudo_regs (gdbarch) -1)
621 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
623 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
624 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
625 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
626 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
628 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
631 regcache_raw_read (regcache,
632 gdbarch_tdep (gdbarch)->wb_regnum, buf);
633 regnum = arreg_number (gdbarch, regnum,
634 extract_unsigned_integer (buf, 4, byte_order));
637 /* We can always write 'core' registers.
638 Note: We might have converted Ax->ARy. */
639 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
640 regcache_raw_write (regcache, regnum, buffer);
642 /* We have to find out how to deal with priveleged registers.
643 Let's treat them as pseudo-registers, but we cannot read/write them. */
645 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
649 /* Pseudo registers. */
651 && regnum < gdbarch_num_regs (gdbarch)
652 + gdbarch_num_pseudo_regs (gdbarch))
654 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
655 xtensa_register_type_t type = reg->type;
656 int flags = gdbarch_tdep (gdbarch)->target_flags;
658 /* On most targets, we cannot write registers
659 of type "Unknown" or "Unmapped". */
660 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
662 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
664 warning (_("cannot write register %s"),
665 xtensa_register_name (gdbarch, regnum));
670 /* Some targets cannot read TIE register files. */
671 else if (type == xtRegisterTypeTieRegfile)
673 /* Use 'store' to get register? */
674 if (flags & xtTargetFlagsUseFetchStore)
676 warning (_("cannot write register"));
680 /* On some targets (esp. simulators), we can always write
682 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
684 warning (_("cannot write register"));
689 /* We can always write mapped registers. */
690 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
692 xtensa_register_write_masked (regcache, reg, buffer);
696 /* Assume that we can write the register. */
697 regcache_raw_write (regcache, regnum, buffer);
700 internal_error (__FILE__, __LINE__,
701 _("invalid register number %d"), regnum);
704 static inline char xtensa_hextochar (int xdigit)
706 static char hex[]="0123456789abcdef";
708 return hex[xdigit & 0x0f];
711 static struct reggroup *xtensa_ar_reggroup;
712 static struct reggroup *xtensa_user_reggroup;
713 static struct reggroup *xtensa_vectra_reggroup;
714 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
717 xtensa_init_reggroups (void)
720 char cpname[] = "cp0";
722 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
723 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
724 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
726 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
728 cpname[2] = xtensa_hextochar (i);
729 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
734 xtensa_add_reggroups (struct gdbarch *gdbarch)
738 /* Predefined groups. */
739 reggroup_add (gdbarch, all_reggroup);
740 reggroup_add (gdbarch, save_reggroup);
741 reggroup_add (gdbarch, restore_reggroup);
742 reggroup_add (gdbarch, system_reggroup);
743 reggroup_add (gdbarch, vector_reggroup);
744 reggroup_add (gdbarch, general_reggroup);
745 reggroup_add (gdbarch, float_reggroup);
747 /* Xtensa-specific groups. */
748 reggroup_add (gdbarch, xtensa_ar_reggroup);
749 reggroup_add (gdbarch, xtensa_user_reggroup);
750 reggroup_add (gdbarch, xtensa_vectra_reggroup);
752 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
753 reggroup_add (gdbarch, xtensa_cp[i]);
757 xtensa_coprocessor_register_group (struct reggroup *group)
761 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
762 if (group == xtensa_cp[i])
768 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
769 | XTENSA_REGISTER_FLAGS_WRITABLE \
770 | XTENSA_REGISTER_FLAGS_VOLATILE)
772 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
773 | XTENSA_REGISTER_FLAGS_WRITABLE)
776 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
778 struct reggroup *group)
780 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
781 xtensa_register_type_t type = reg->type;
782 xtensa_register_group_t rg = reg->group;
785 /* First, skip registers that are not visible to this target
786 (unknown and unmapped registers when not using ISS). */
788 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
790 if (group == all_reggroup)
792 if (group == xtensa_ar_reggroup)
793 return rg & xtRegisterGroupAddrReg;
794 if (group == xtensa_user_reggroup)
795 return rg & xtRegisterGroupUser;
796 if (group == float_reggroup)
797 return rg & xtRegisterGroupFloat;
798 if (group == general_reggroup)
799 return rg & xtRegisterGroupGeneral;
800 if (group == float_reggroup)
801 return rg & xtRegisterGroupFloat;
802 if (group == system_reggroup)
803 return rg & xtRegisterGroupState;
804 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
805 return rg & xtRegisterGroupVectra;
806 if (group == save_reggroup || group == restore_reggroup)
807 return (regnum < gdbarch_num_regs (gdbarch)
808 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
809 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
810 return rg & (xtRegisterGroupCP0 << cp_number);
816 /* Supply register REGNUM from the buffer specified by GREGS and LEN
817 in the general-purpose register set REGSET to register cache
818 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
821 xtensa_supply_gregset (const struct regset *regset,
827 const xtensa_elf_gregset_t *regs = gregs;
828 struct gdbarch *gdbarch = get_regcache_arch (rc);
831 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
833 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
834 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
835 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
836 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
837 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
838 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
839 (char *) ®s->windowbase);
840 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
841 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
842 (char *) ®s->windowstart);
843 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
844 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
845 (char *) ®s->lbeg);
846 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
847 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
848 (char *) ®s->lend);
849 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
850 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
851 (char *) ®s->lcount);
852 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
853 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
854 (char *) ®s->sar);
855 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
856 && regnum < gdbarch_tdep (gdbarch)->ar_base
857 + gdbarch_tdep (gdbarch)->num_aregs)
858 regcache_raw_supply (rc, regnum,
859 (char *) ®s->ar[regnum - gdbarch_tdep
860 (gdbarch)->ar_base]);
861 else if (regnum == -1)
863 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
864 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
865 (char *) ®s->ar[i]);
870 /* Xtensa register set. */
876 xtensa_supply_gregset
880 /* Return the appropriate register set for the core
881 section identified by SECT_NAME and SECT_SIZE. */
883 static const struct regset *
884 xtensa_regset_from_core_section (struct gdbarch *core_arch,
885 const char *sect_name,
888 DEBUGTRACE ("xtensa_regset_from_core_section "
889 "(..., sect_name==\"%s\", sect_size==%x)\n",
890 sect_name, (unsigned int) sect_size);
892 if (strcmp (sect_name, ".reg") == 0
893 && sect_size >= sizeof(xtensa_elf_gregset_t))
894 return &xtensa_gregset;
900 /* Handling frames. */
902 /* Number of registers to save in case of Windowed ABI. */
903 #define XTENSA_NUM_SAVED_AREGS 12
905 /* Frame cache part for Windowed ABI. */
906 typedef struct xtensa_windowed_frame_cache
908 int wb; /* WINDOWBASE of the previous frame. */
909 int callsize; /* Call size of this frame. */
910 int ws; /* WINDOWSTART of the previous frame. It
911 keeps track of life windows only. If there
912 is no bit set for the window, that means it
913 had been already spilled because of window
916 /* Spilled A-registers from the previous frame.
917 AREGS[i] == -1, if corresponding AR is alive. */
918 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
919 } xtensa_windowed_frame_cache_t;
921 /* Call0 ABI Definitions. */
923 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
925 #define C0_NREGS 16 /* Number of A-registers to track. */
926 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
927 #define C0_SP 1 /* Register used as SP. */
928 #define C0_FP 15 /* Register used as FP. */
929 #define C0_RA 0 /* Register used as return address. */
930 #define C0_ARGS 2 /* Register used as first arg/retval. */
931 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
933 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
934 A-register where the current content of the reg came from (in terms
935 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
936 mean that the orignal content of the register was saved to the stack.
937 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
938 know where SP will end up until the entire prologue has been analyzed. */
940 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
941 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
942 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
944 extern xtensa_isa xtensa_default_isa;
946 typedef struct xtensa_c0reg
948 int fr_reg; /* original register from which register content
949 is derived, or C0_CONST, or C0_INEXP. */
950 int fr_ofs; /* constant offset from reg, or immediate value. */
951 int to_stk; /* offset from original SP to register (4-byte
952 aligned), or C0_NOSTK if register has not
957 /* Frame cache part for Call0 ABI. */
958 typedef struct xtensa_call0_frame_cache
960 int c0_frmsz; /* Stack frame size. */
961 int c0_hasfp; /* Current frame uses frame
963 int fp_regnum; /* A-register used as FP. */
964 int c0_fp; /* Actual value of frame pointer. */
965 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
966 } xtensa_call0_frame_cache_t;
968 typedef struct xtensa_frame_cache
970 CORE_ADDR base; /* Stack pointer of this frame. */
971 CORE_ADDR pc; /* PC at the entry point to the function. */
972 CORE_ADDR ra; /* The raw return address (without CALLINC). */
973 CORE_ADDR ps; /* The PS register of this frame. */
974 CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
975 int call0; /* It's a call0 framework (else windowed). */
978 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
979 xtensa_call0_frame_cache_t c0; /* call0 == true. */
981 } xtensa_frame_cache_t;
984 static struct xtensa_frame_cache *
985 xtensa_alloc_frame_cache (int windowed)
987 xtensa_frame_cache_t *cache;
990 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
992 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
999 cache->call0 = !windowed;
1002 cache->c0.c0_frmsz = -1;
1003 cache->c0.c0_hasfp = 0;
1004 cache->c0.fp_regnum = -1;
1005 cache->c0.c0_fp = -1;
1007 for (i = 0; i < C0_NREGS; i++)
1009 cache->c0.c0_rt[i].fr_reg = i;
1010 cache->c0.c0_rt[i].fr_ofs = 0;
1011 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1018 cache->wd.callsize = -1;
1020 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1021 cache->wd.aregs[i] = -1;
1028 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1030 return address & ~15;
1035 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1040 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1041 host_address_to_string (next_frame));
1043 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1044 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1046 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1052 static struct frame_id
1053 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1057 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1059 pc = get_frame_pc (this_frame);
1060 fp = get_frame_register_unsigned
1061 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1063 /* Make dummy frame ID unique by adding a constant. */
1064 return frame_id_build (fp + SP_ALIGNMENT, pc);
1067 /* Returns the best guess about which register is a frame pointer
1068 for the function containing CURRENT_PC. */
1070 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1071 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1074 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1076 #define RETURN_FP goto done
1078 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1079 CORE_ADDR start_addr;
1081 xtensa_insnbuf ins, slot;
1082 char ibuf[XTENSA_ISA_BSZ];
1083 CORE_ADDR ia, bt, ba;
1085 int ilen, islots, is;
1087 const char *opcname;
1089 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1090 if (start_addr == 0)
1093 if (!xtensa_default_isa)
1094 xtensa_default_isa = xtensa_isa_init (0, 0);
1095 isa = xtensa_default_isa;
1096 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1097 ins = xtensa_insnbuf_alloc (isa);
1098 slot = xtensa_insnbuf_alloc (isa);
1101 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1103 if (ia + xtensa_isa_maxlength (isa) > bt)
1106 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1107 ? ba + XTENSA_ISA_BSZ : current_pc;
1108 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1112 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1113 ifmt = xtensa_format_decode (isa, ins);
1114 if (ifmt == XTENSA_UNDEFINED)
1116 ilen = xtensa_format_length (isa, ifmt);
1117 if (ilen == XTENSA_UNDEFINED)
1119 islots = xtensa_format_num_slots (isa, ifmt);
1120 if (islots == XTENSA_UNDEFINED)
1123 for (is = 0; is < islots; ++is)
1125 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1128 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1129 if (opc == XTENSA_UNDEFINED)
1132 opcname = xtensa_opcode_name (isa, opc);
1134 if (strcasecmp (opcname, "mov.n") == 0
1135 || strcasecmp (opcname, "or") == 0)
1137 unsigned int register_operand;
1139 /* Possible candidate for setting frame pointer
1140 from A1. This is what we are looking for. */
1142 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1143 is, slot, ®ister_operand) != 0)
1145 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1147 if (register_operand == 1) /* Mov{.n} FP A1. */
1149 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1150 ®ister_operand) != 0)
1152 if (xtensa_operand_decode (isa, opc, 0,
1153 ®ister_operand) != 0)
1157 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1163 /* We have problems decoding the memory. */
1165 || strcasecmp (opcname, "ill") == 0
1166 || strcasecmp (opcname, "ill.n") == 0
1167 /* Hit planted breakpoint. */
1168 || strcasecmp (opcname, "break") == 0
1169 || strcasecmp (opcname, "break.n") == 0
1170 /* Flow control instructions finish prologue. */
1171 || xtensa_opcode_is_branch (isa, opc) > 0
1172 || xtensa_opcode_is_jump (isa, opc) > 0
1173 || xtensa_opcode_is_loop (isa, opc) > 0
1174 || xtensa_opcode_is_call (isa, opc) > 0
1175 || strcasecmp (opcname, "simcall") == 0
1176 || strcasecmp (opcname, "syscall") == 0)
1177 /* Can not continue analysis. */
1182 xtensa_insnbuf_free(isa, slot);
1183 xtensa_insnbuf_free(isa, ins);
1187 /* The key values to identify the frame using "cache" are
1189 cache->base = SP (or best guess about FP) of this frame;
1190 cache->pc = entry-PC (entry point of the frame function);
1191 cache->prev_sp = SP of the previous frame. */
1194 call0_frame_cache (struct frame_info *this_frame,
1195 xtensa_frame_cache_t *cache,
1196 CORE_ADDR pc, CORE_ADDR litbase);
1198 static struct xtensa_frame_cache *
1199 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1201 xtensa_frame_cache_t *cache;
1202 CORE_ADDR ra, wb, ws, pc, sp, ps;
1203 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1204 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1205 unsigned int fp_regnum;
1206 int windowed, ps_regnum;
1211 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1212 ps_regnum = gdbarch_ps_regnum (gdbarch);
1213 ps = (ps_regnum >= 0)
1214 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS;
1216 windowed = windowing_enabled (gdbarch, ps);
1218 /* Get pristine xtensa-frame. */
1219 cache = xtensa_alloc_frame_cache (windowed);
1220 *this_cache = cache;
1226 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1227 wb = get_frame_register_unsigned (this_frame,
1228 gdbarch_tdep (gdbarch)->wb_regnum);
1229 ws = get_frame_register_unsigned (this_frame,
1230 gdbarch_tdep (gdbarch)->ws_regnum);
1232 op1 = read_memory_integer (pc, 1, byte_order);
1233 if (XTENSA_IS_ENTRY (gdbarch, op1))
1235 int callinc = CALLINC (ps);
1236 ra = get_frame_register_unsigned
1237 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1239 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1240 cache->wd.callsize = 0;
1243 cache->prev_sp = get_frame_register_unsigned
1244 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1246 /* This only can be the outermost frame since we are
1247 just about to execute ENTRY. SP hasn't been set yet.
1248 We can assume any frame size, because it does not
1249 matter, and, let's fake frame base in cache. */
1250 cache->base = cache->prev_sp - 16;
1253 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1254 cache->ps = (ps & ~PS_CALLINC_MASK)
1255 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1261 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1262 ra = get_frame_register_unsigned (this_frame,
1263 gdbarch_tdep (gdbarch)->a0_base);
1264 cache->wd.callsize = WINSIZE (ra);
1265 cache->wd.wb = (wb - cache->wd.callsize / 4)
1266 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1267 cache->wd.ws = ws & ~(1 << wb);
1269 cache->pc = get_frame_func (this_frame);
1270 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1271 cache->ps = (ps & ~PS_CALLINC_MASK)
1272 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1275 if (cache->wd.ws == 0)
1280 sp = get_frame_register_unsigned
1281 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1283 for (i = 0; i < 4; i++, sp += 4)
1285 cache->wd.aregs[i] = sp;
1288 if (cache->wd.callsize > 4)
1290 /* Set A4...A7/A11. */
1291 /* Get the SP of the frame previous to the previous one.
1292 To achieve this, we have to dereference SP twice. */
1293 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1294 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1295 sp -= cache->wd.callsize * 4;
1297 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1299 cache->wd.aregs[i] = sp;
1304 if ((cache->prev_sp == 0) && ( ra != 0 ))
1305 /* If RA is equal to 0 this frame is an outermost frame.
1306 Leave cache->prev_sp unchanged marking the boundary of the
1309 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1311 /* Register window overflow already happened.
1312 We can read caller's SP from the proper spill loction. */
1313 sp = get_frame_register_unsigned
1314 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1315 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1319 /* Read caller's frame SP directly from the previous window. */
1320 int regnum = arreg_number
1321 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1324 cache->prev_sp = get_frame_register_unsigned (this_frame,
1329 else /* Call0 framework. */
1331 unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
1332 CORE_ADDR litbase = (litbase_regnum == -1)
1333 ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
1335 call0_frame_cache (this_frame, cache, pc, litbase);
1336 fp_regnum = cache->c0.fp_regnum;
1339 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1345 xtensa_frame_this_id (struct frame_info *this_frame,
1347 struct frame_id *this_id)
1349 struct xtensa_frame_cache *cache =
1350 xtensa_frame_cache (this_frame, this_cache);
1352 if (cache->prev_sp == 0)
1355 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1358 static struct value *
1359 xtensa_frame_prev_register (struct frame_info *this_frame,
1363 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1364 struct xtensa_frame_cache *cache;
1365 ULONGEST saved_reg = 0;
1368 if (*this_cache == NULL)
1369 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1370 cache = *this_cache;
1372 if (regnum ==gdbarch_pc_regnum (gdbarch))
1373 saved_reg = cache->ra;
1374 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1375 saved_reg = cache->prev_sp;
1376 else if (!cache->call0)
1378 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1379 saved_reg = cache->wd.ws;
1380 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1381 saved_reg = cache->wd.wb;
1382 else if (regnum == gdbarch_ps_regnum (gdbarch))
1383 saved_reg = cache->ps;
1391 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1393 if (!cache->call0) /* Windowed ABI. */
1395 /* Convert A-register numbers to AR-register numbers,
1396 if we deal with A-register. */
1397 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1398 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1399 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1401 /* Check, if we deal with AR-register saved on stack. */
1402 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1403 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1404 + gdbarch_tdep (gdbarch)->num_aregs))
1406 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1409 && areg < XTENSA_NUM_SAVED_AREGS
1410 && cache->wd.aregs[areg] != -1)
1411 return frame_unwind_got_memory (this_frame, regnum,
1412 cache->wd.aregs[areg]);
1415 else /* Call0 ABI. */
1417 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1418 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1420 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1427 /* If register was saved in the prologue, retrieve it. */
1428 stkofs = cache->c0.c0_rt[reg].to_stk;
1429 if (stkofs != C0_NOSTK)
1431 /* Determine SP on entry based on FP. */
1432 spe = cache->c0.c0_fp
1433 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1435 return frame_unwind_got_memory (this_frame, regnum,
1441 /* All other registers have been either saved to
1442 the stack or are still alive in the processor. */
1444 return frame_unwind_got_register (this_frame, regnum, regnum);
1448 static const struct frame_unwind
1452 xtensa_frame_this_id,
1453 xtensa_frame_prev_register,
1455 default_frame_sniffer
1459 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1461 struct xtensa_frame_cache *cache =
1462 xtensa_frame_cache (this_frame, this_cache);
1467 static const struct frame_base
1471 xtensa_frame_base_address,
1472 xtensa_frame_base_address,
1473 xtensa_frame_base_address
1478 xtensa_extract_return_value (struct type *type,
1479 struct regcache *regcache,
1482 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1483 bfd_byte *valbuf = dst;
1484 int len = TYPE_LENGTH (type);
1489 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1491 gdb_assert(len > 0);
1493 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1495 /* First, we have to find the caller window in the register file. */
1496 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1497 callsize = extract_call_winsize (gdbarch, pc);
1499 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1500 if (len > (callsize > 8 ? 8 : 16))
1501 internal_error (__FILE__, __LINE__,
1502 _("cannot extract return value of %d bytes long"),
1505 /* Get the register offset of the return
1506 register (A2) in the caller window. */
1507 regcache_raw_read_unsigned
1508 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1509 areg = arreg_number (gdbarch,
1510 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1514 /* No windowing hardware - Call0 ABI. */
1515 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1518 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1520 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1523 for (; len > 0; len -= 4, areg++, valbuf += 4)
1526 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1528 regcache_raw_read (regcache, areg, valbuf);
1534 xtensa_store_return_value (struct type *type,
1535 struct regcache *regcache,
1538 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1539 const bfd_byte *valbuf = dst;
1543 int len = TYPE_LENGTH (type);
1546 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1548 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1550 regcache_raw_read_unsigned
1551 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1552 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1553 callsize = extract_call_winsize (gdbarch, pc);
1555 if (len > (callsize > 8 ? 8 : 16))
1556 internal_error (__FILE__, __LINE__,
1557 _("unimplemented for this length: %d"),
1558 TYPE_LENGTH (type));
1559 areg = arreg_number (gdbarch,
1560 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1562 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1563 callsize, (int) wb);
1567 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1570 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1573 for (; len > 0; len -= 4, areg++, valbuf += 4)
1576 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1578 regcache_raw_write (regcache, areg, valbuf);
1583 static enum return_value_convention
1584 xtensa_return_value (struct gdbarch *gdbarch,
1585 struct type *func_type,
1586 struct type *valtype,
1587 struct regcache *regcache,
1589 const gdb_byte *writebuf)
1591 /* Structures up to 16 bytes are returned in registers. */
1593 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1594 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1595 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1596 && TYPE_LENGTH (valtype) > 16);
1599 return RETURN_VALUE_STRUCT_CONVENTION;
1601 DEBUGTRACE ("xtensa_return_value(...)\n");
1603 if (writebuf != NULL)
1605 xtensa_store_return_value (valtype, regcache, writebuf);
1608 if (readbuf != NULL)
1610 gdb_assert (!struct_return);
1611 xtensa_extract_return_value (valtype, regcache, readbuf);
1613 return RETURN_VALUE_REGISTER_CONVENTION;
1620 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1621 struct value *function,
1622 struct regcache *regcache,
1625 struct value **args,
1628 CORE_ADDR struct_addr)
1630 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1632 int size, onstack_size;
1633 gdb_byte *buf = (gdb_byte *) alloca (16);
1635 struct argument_info
1637 const bfd_byte *contents;
1639 int onstack; /* onstack == 0 => in reg */
1640 int align; /* alignment */
1643 int offset; /* stack offset if on stack. */
1644 int regno; /* regno if in register. */
1648 struct argument_info *arg_info =
1649 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1653 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1655 if (xtensa_debug_level > 3)
1658 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1659 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1660 "struct_addr=0x%x\n",
1661 (int) sp, (int) struct_return, (int) struct_addr);
1663 for (i = 0; i < nargs; i++)
1665 struct value *arg = args[i];
1666 struct type *arg_type = check_typedef (value_type (arg));
1667 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1668 host_address_to_string (arg),
1669 TYPE_LENGTH (arg_type));
1670 switch (TYPE_CODE (arg_type))
1673 fprintf_unfiltered (gdb_stdlog, "int");
1675 case TYPE_CODE_STRUCT:
1676 fprintf_unfiltered (gdb_stdlog, "struct");
1679 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1682 fprintf_unfiltered (gdb_stdlog, " %s\n",
1683 host_address_to_string (value_contents (arg)));
1687 /* First loop: collect information.
1688 Cast into type_long. (This shouldn't happen often for C because
1689 GDB already does this earlier.) It's possible that GDB could
1690 do it all the time but it's harmless to leave this code here. */
1697 size = REGISTER_SIZE;
1699 for (i = 0; i < nargs; i++)
1701 struct argument_info *info = &arg_info[i];
1702 struct value *arg = args[i];
1703 struct type *arg_type = check_typedef (value_type (arg));
1705 switch (TYPE_CODE (arg_type))
1708 case TYPE_CODE_BOOL:
1709 case TYPE_CODE_CHAR:
1710 case TYPE_CODE_RANGE:
1711 case TYPE_CODE_ENUM:
1713 /* Cast argument to long if necessary as the mask does it too. */
1714 if (TYPE_LENGTH (arg_type)
1715 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1717 arg_type = builtin_type (gdbarch)->builtin_long;
1718 arg = value_cast (arg_type, arg);
1720 /* Aligment is equal to the type length for the basic types. */
1721 info->align = TYPE_LENGTH (arg_type);
1726 /* Align doubles correctly. */
1727 if (TYPE_LENGTH (arg_type)
1728 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1729 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1731 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1734 case TYPE_CODE_STRUCT:
1736 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1739 info->length = TYPE_LENGTH (arg_type);
1740 info->contents = value_contents (arg);
1742 /* Align size and onstack_size. */
1743 size = (size + info->align - 1) & ~(info->align - 1);
1744 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1746 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1749 info->u.offset = onstack_size;
1750 onstack_size += info->length;
1755 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1757 size += info->length;
1760 /* Adjust the stack pointer and align it. */
1761 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1763 /* Simulate MOVSP, if Windowed ABI. */
1764 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1767 read_memory (osp - 16, buf, 16);
1768 write_memory (sp - 16, buf, 16);
1771 /* Second Loop: Load arguments. */
1775 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1776 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1779 for (i = 0; i < nargs; i++)
1781 struct argument_info *info = &arg_info[i];
1785 int n = info->length;
1786 CORE_ADDR offset = sp + info->u.offset;
1788 /* Odd-sized structs are aligned to the lower side of a memory
1789 word in big-endian mode and require a shift. This only
1790 applies for structures smaller than one word. */
1792 if (n < REGISTER_SIZE
1793 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1794 offset += (REGISTER_SIZE - n);
1796 write_memory (offset, info->contents, info->length);
1801 int n = info->length;
1802 const bfd_byte *cp = info->contents;
1803 int r = info->u.regno;
1805 /* Odd-sized structs are aligned to the lower side of registers in
1806 big-endian mode and require a shift. The odd-sized leftover will
1807 be at the end. Note that this is only true for structures smaller
1808 than REGISTER_SIZE; for larger odd-sized structures the excess
1809 will be left-aligned in the register on both endiannesses. */
1811 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1814 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1815 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1817 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1818 regcache_cooked_write (regcache, r, buf);
1820 cp += REGISTER_SIZE;
1827 regcache_cooked_write (regcache, r, cp);
1829 cp += REGISTER_SIZE;
1836 /* Set the return address of dummy frame to the dummy address.
1837 The return address for the current function (in A0) is
1838 saved in the dummy frame, so we can savely overwrite A0 here. */
1840 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1843 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1844 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1845 ps = (unsigned long) val & ~0x00030000;
1846 regcache_cooked_write_unsigned
1847 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1848 regcache_cooked_write_unsigned (regcache,
1849 gdbarch_ps_regnum (gdbarch),
1852 /* All the registers have been saved. After executing
1853 dummy call, they all will be restored. So it's safe
1854 to modify WINDOWSTART register to make it look like there
1855 is only one register window corresponding to WINDOWEBASE. */
1857 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1858 regcache_cooked_write_unsigned
1859 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1860 1 << extract_unsigned_integer (buf, 4, byte_order));
1864 /* Simulate CALL0: write RA into A0 register. */
1865 regcache_cooked_write_unsigned
1866 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1869 /* Set new stack pointer and return it. */
1870 regcache_cooked_write_unsigned (regcache,
1871 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1872 /* Make dummy frame ID unique by adding a constant. */
1873 return sp + SP_ALIGNMENT;
1877 /* Return a breakpoint for the current location of PC. We always use
1878 the density version if we have density instructions (regardless of the
1879 current instruction at PC), and use regular instructions otherwise. */
1881 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1882 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1883 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1884 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1886 static const unsigned char *
1887 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1890 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1891 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1892 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1893 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1895 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1897 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1899 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1901 *lenptr = sizeof (density_big_breakpoint);
1902 return density_big_breakpoint;
1906 *lenptr = sizeof (density_little_breakpoint);
1907 return density_little_breakpoint;
1912 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1914 *lenptr = sizeof (big_breakpoint);
1915 return big_breakpoint;
1919 *lenptr = sizeof (little_breakpoint);
1920 return little_breakpoint;
1925 /* Call0 ABI support routines. */
1927 /* Call0 opcode class. Opcodes are preclassified according to what they
1928 mean for Call0 prologue analysis, and their number of significant operands.
1929 The purpose of this is to simplify prologue analysis by separating
1930 instruction decoding (libisa) from the semantics of prologue analysis. */
1933 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1934 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1935 c0opc_flow, /* Flow control insn. */
1936 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1937 c0opc_break, /* Debugger software breakpoints. */
1938 c0opc_add, /* Adding two registers. */
1939 c0opc_addi, /* Adding a register and an immediate. */
1940 c0opc_sub, /* Subtracting a register from a register. */
1941 c0opc_mov, /* Moving a register to a register. */
1942 c0opc_movi, /* Moving an immediate to a register. */
1943 c0opc_l32r, /* Loading a literal. */
1944 c0opc_s32i, /* Storing word at fixed offset from a base
1946 c0opc_NrOf /* Number of opcode classifications. */
1950 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1952 static xtensa_insn_kind
1953 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1955 const char *opcname;
1956 xtensa_insn_kind opclass = c0opc_uninteresting;
1958 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1960 /* Get opcode name and handle special classifications. */
1962 opcname = xtensa_opcode_name (isa, opc);
1965 || strcasecmp (opcname, "ill") == 0
1966 || strcasecmp (opcname, "ill.n") == 0)
1967 opclass = c0opc_illegal;
1968 else if (strcasecmp (opcname, "break") == 0
1969 || strcasecmp (opcname, "break.n") == 0)
1970 opclass = c0opc_break;
1971 else if (strcasecmp (opcname, "entry") == 0)
1972 opclass = c0opc_entry;
1973 else if (xtensa_opcode_is_branch (isa, opc) > 0
1974 || xtensa_opcode_is_jump (isa, opc) > 0
1975 || xtensa_opcode_is_loop (isa, opc) > 0
1976 || xtensa_opcode_is_call (isa, opc) > 0
1977 || strcasecmp (opcname, "simcall") == 0
1978 || strcasecmp (opcname, "syscall") == 0)
1979 opclass = c0opc_flow;
1981 /* Also, classify specific opcodes that need to be tracked. */
1982 else if (strcasecmp (opcname, "add") == 0
1983 || strcasecmp (opcname, "add.n") == 0)
1984 opclass = c0opc_add;
1985 else if (strcasecmp (opcname, "addi") == 0
1986 || strcasecmp (opcname, "addi.n") == 0
1987 || strcasecmp (opcname, "addmi") == 0)
1988 opclass = c0opc_addi;
1989 else if (strcasecmp (opcname, "sub") == 0)
1990 opclass = c0opc_sub;
1991 else if (strcasecmp (opcname, "mov.n") == 0
1992 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1993 opclass = c0opc_mov;
1994 else if (strcasecmp (opcname, "movi") == 0
1995 || strcasecmp (opcname, "movi.n") == 0)
1996 opclass = c0opc_movi;
1997 else if (strcasecmp (opcname, "l32r") == 0)
1998 opclass = c0opc_l32r;
1999 else if (strcasecmp (opcname, "s32i") == 0
2000 || strcasecmp (opcname, "s32i.n") == 0)
2001 opclass = c0opc_s32i;
2006 /* Tracks register movement/mutation for a given operation, which may
2007 be within a bundle. Updates the destination register tracking info
2008 accordingly. The pc is needed only for pc-relative load instructions
2009 (eg. l32r). The SP register number is needed to identify stores to
2013 call0_track_op (struct gdbarch *gdbarch,
2014 xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2015 xtensa_insn_kind opclass, int nods, unsigned odv[],
2016 CORE_ADDR pc, CORE_ADDR litbase, int spreg)
2018 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2019 unsigned litaddr, litval;
2024 /* 3 operands: dst, src, imm. */
2025 gdb_assert (nods == 3);
2026 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2027 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2030 /* 3 operands: dst, src1, src2. */
2031 gdb_assert (nods == 3);
2032 if (src[odv[1]].fr_reg == C0_CONST)
2034 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2035 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2037 else if (src[odv[2]].fr_reg == C0_CONST)
2039 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2040 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2042 else dst[odv[0]].fr_reg = C0_INEXP;
2045 /* 3 operands: dst, src1, src2. */
2046 gdb_assert (nods == 3);
2047 if (src[odv[2]].fr_reg == C0_CONST)
2049 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2050 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2052 else dst[odv[0]].fr_reg = C0_INEXP;
2055 /* 2 operands: dst, src [, src]. */
2056 gdb_assert (nods == 2);
2057 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2058 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2061 /* 2 operands: dst, imm. */
2062 gdb_assert (nods == 2);
2063 dst[odv[0]].fr_reg = C0_CONST;
2064 dst[odv[0]].fr_ofs = odv[1];
2067 /* 2 operands: dst, literal offset. */
2068 gdb_assert (nods == 2);
2069 litaddr = litbase & 1
2070 ? (litbase & ~1) + (signed)odv[1]
2071 : (pc + 3 + (signed)odv[1]) & ~3;
2072 litval = read_memory_integer (litaddr, 4, byte_order);
2073 dst[odv[0]].fr_reg = C0_CONST;
2074 dst[odv[0]].fr_ofs = litval;
2077 /* 3 operands: value, base, offset. */
2078 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2079 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2080 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2081 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2082 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2083 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2085 /* ISA encoding guarantees alignment. But, check it anyway. */
2086 gdb_assert ((odv[2] & 3) == 0);
2087 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2091 gdb_assert_not_reached ("unexpected instruction kind");
2095 /* Analyze prologue of the function at start address to determine if it uses
2096 the Call0 ABI, and if so track register moves and linear modifications
2097 in the prologue up to the PC or just beyond the prologue, whichever is first.
2098 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2099 The prologue may overlap non-prologue instructions but is guaranteed to end
2100 by the first flow-control instruction (jump, branch, call or return).
2101 Since an optimized function may move information around and change the
2102 stack frame arbitrarily during the prologue, the information is guaranteed
2103 valid only at the point in the function indicated by the PC.
2104 May be used to skip the prologue or identify the ABI, w/o tracking.
2106 Returns: Address of first instruction after prologue, or PC (whichever
2107 is first), or 0, if decoding failed (in libisa).
2109 start Start address of function/prologue.
2110 pc Program counter to stop at. Use 0 to continue to end of prologue.
2111 If 0, avoids infinite run-on in corrupt code memory by bounding
2112 the scan to the end of the function if that can be determined.
2113 nregs Number of general registers to track (size of rt[] array).
2115 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2116 If NULL, registers are not tracked.
2118 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2119 (more accurately, non-zero until 'entry' insn is encountered).
2121 Note that these may produce useful results even if decoding fails
2122 because they begin with default assumptions that analysis may change. */
2125 call0_analyze_prologue (struct gdbarch *gdbarch,
2126 CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
2127 int nregs, xtensa_c0reg_t rt[], int *call0)
2129 CORE_ADDR ia; /* Current insn address in prologue. */
2130 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2131 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2132 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2133 xtensa_isa isa; /* libisa ISA handle. */
2134 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2135 xtensa_format ifmt; /* libisa instruction format. */
2136 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2137 xtensa_opcode opc; /* Opcode in current slot. */
2138 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2139 int nods; /* Opcode number of operands. */
2140 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2141 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2142 int j; /* General loop counter. */
2143 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2144 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2145 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2147 struct symtab_and_line prologue_sal;
2149 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2150 (int)start, (int)pc);
2152 /* Try to limit the scan to the end of the function if a non-zero pc
2153 arg was not supplied to avoid probing beyond the end of valid memory.
2154 If memory is full of garbage that classifies as c0opc_uninteresting.
2155 If this fails (eg. if no symbols) pc ends up 0 as it was.
2156 Intialize the Call0 frame and register tracking info.
2157 Assume it's Call0 until an 'entry' instruction is encountered.
2158 Assume we may be in the prologue until we hit a flow control instr. */
2164 /* Find out, if we have an information about the prologue from DWARF. */
2165 prologue_sal = find_pc_line (start, 0);
2166 if (prologue_sal.line != 0) /* Found debug info. */
2167 body_pc = prologue_sal.end;
2169 /* If we are going to analyze the prologue in general without knowing about
2170 the current PC, make the best assumtion for the end of the prologue. */
2173 find_pc_partial_function (start, 0, NULL, &end_pc);
2174 body_pc = min (end_pc, body_pc);
2177 body_pc = min (pc, body_pc);
2184 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2185 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2189 if (!xtensa_default_isa)
2190 xtensa_default_isa = xtensa_isa_init (0, 0);
2191 isa = xtensa_default_isa;
2192 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2193 ins = xtensa_insnbuf_alloc (isa);
2194 slot = xtensa_insnbuf_alloc (isa);
2196 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2198 /* (Re)fill instruction buffer from memory if necessary, but do not
2199 read memory beyond PC to be sure we stay within text section
2200 (this protection only works if a non-zero pc is supplied). */
2202 if (ia + xtensa_isa_maxlength (isa) > bt)
2205 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2206 read_memory (ba, ibuf, bt - ba);
2207 /* If there is a memory reading error read_memory () will report it
2208 and then throw an exception, stopping command execution. */
2211 /* Decode format information. */
2213 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2214 ifmt = xtensa_format_decode (isa, ins);
2215 if (ifmt == XTENSA_UNDEFINED)
2220 ilen = xtensa_format_length (isa, ifmt);
2221 if (ilen == XTENSA_UNDEFINED)
2226 islots = xtensa_format_num_slots (isa, ifmt);
2227 if (islots == XTENSA_UNDEFINED)
2233 /* Analyze a bundle or a single instruction, using a snapshot of
2234 the register tracking info as input for the entire bundle so that
2235 register changes do not take effect within this bundle. */
2237 for (j = 0; j < nregs; ++j)
2240 for (is = 0; is < islots; ++is)
2242 /* Decode a slot and classify the opcode. */
2244 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2248 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2249 DEBUGVERB ("[call0_analyze_prologue] instr "
2250 "addr = 0x%08x, opc = %d\n",
2252 if (opc == XTENSA_UNDEFINED)
2253 opclass = c0opc_illegal;
2255 opclass = call0_classify_opcode (isa, opc);
2257 /* Decide whether to track this opcode, ignore it, or bail out. */
2266 case c0opc_uninteresting:
2275 ia += ilen; /* Skip over 'entry' insn. */
2283 /* Only expected opcodes should get this far. */
2287 /* Extract and decode the operands. */
2288 nods = xtensa_opcode_num_operands (isa, opc);
2289 if (nods == XTENSA_UNDEFINED)
2295 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2297 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2302 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2307 /* Check operands to verify use of 'mov' assembler macro. */
2308 if (opclass == c0opc_mov && nods == 3)
2310 if (odv[2] == odv[1])
2314 opclass = c0opc_uninteresting;
2319 /* Track register movement and modification for this operation. */
2320 call0_track_op (gdbarch, rt, rtmp, opclass,
2321 nods, odv, ia, litbase, 1);
2325 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2326 (unsigned)ia, fail ? "failed" : "succeeded");
2327 xtensa_insnbuf_free(isa, slot);
2328 xtensa_insnbuf_free(isa, ins);
2329 return fail ? XTENSA_ISA_BADPC : ia;
2332 /* Initialize frame cache for the current frame in CALL0 ABI. */
2335 call0_frame_cache (struct frame_info *this_frame,
2336 xtensa_frame_cache_t *cache,
2337 CORE_ADDR pc, CORE_ADDR litbase)
2339 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2340 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2341 CORE_ADDR start_pc; /* The beginning of the function. */
2342 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2343 CORE_ADDR sp, fp, ra;
2344 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2346 /* Find the beginning of the prologue of the function containing the PC
2347 and analyze it up to the PC or the end of the prologue. */
2349 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2351 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
2353 &cache->c0.c0_rt[0],
2356 if (body_pc == XTENSA_ISA_BADPC)
2357 error (_("Xtensa-specific internal error: CALL0 prologue \
2358 analysis failed in this frame. GDB command execution stopped."));
2361 sp = get_frame_register_unsigned
2362 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2363 fp = sp; /* Assume FP == SP until proven otherwise. */
2365 /* Get the frame information and FP (if used) at the current PC.
2366 If PC is in the prologue, the prologue analysis is more reliable
2367 than DWARF info. We don't not know for sure if PC is in the prologue,
2368 but we know no calls have yet taken place, so we can almost
2369 certainly rely on the prologue analysis. */
2373 /* Prologue analysis was successful up to the PC.
2374 It includes the cases when PC == START_PC. */
2375 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2376 /* c0_hasfp == true means there is a frame pointer because
2377 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2378 was derived from SP. Otherwise, it would be C0_FP. */
2379 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2380 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2381 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2383 else /* No data from the prologue analysis. */
2386 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2391 prev_sp = fp + c0_frmsz;
2393 /* Frame size from debug info or prologue tracking does not account for
2394 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2397 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2399 /* Recalculate previous SP. */
2400 prev_sp = fp + c0_frmsz;
2401 /* Update the stack frame size. */
2402 c0_frmsz += fp - sp;
2405 /* Get the return address (RA) from the stack if saved,
2406 or try to get it from a register. */
2408 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2409 if (to_stk != C0_NOSTK)
2411 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2414 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2415 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2417 /* Special case for terminating backtrace at a function that
2418 wants to be seen as the outermost. Such a function will
2419 clear it's RA (A0) register to 0 in the prologue instead of
2420 saving its original value. */
2425 /* RA was copied to another register or (before any function
2426 call) may still be in the original RA register. This is not
2427 always reliable: even in a leaf function, register tracking
2428 stops after prologue, and even in prologue, non-prologue
2429 instructions (not tracked) may overwrite RA or any register
2430 it was copied to. If likely in prologue or before any call,
2431 use retracking info and hope for the best (compiler should
2432 have saved RA in stack if not in a leaf function). If not in
2433 prologue, too bad. */
2438 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2440 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2444 ra = get_frame_register_unsigned
2446 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2451 cache->pc = start_pc;
2453 /* RA == 0 marks the outermost frame. Do not go past it. */
2454 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2455 cache->c0.fp_regnum = fp_regnum;
2456 cache->c0.c0_frmsz = c0_frmsz;
2457 cache->c0.c0_hasfp = c0_hasfp;
2458 cache->c0.c0_fp = fp;
2462 /* Skip function prologue.
2464 Return the pc of the first instruction after prologue. GDB calls this to
2465 find the address of the first line of the function or (if there is no line
2466 number information) to skip the prologue for planting breakpoints on
2467 function entries. Use debug info (if present) or prologue analysis to skip
2468 the prologue to achieve reliable debugging behavior. For windowed ABI,
2469 only the 'entry' instruction is skipped. It is not strictly necessary to
2470 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2471 backtrace at any point in the prologue, however certain potential hazards
2472 are avoided and a more "normal" debugging experience is ensured by
2473 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2474 For example, if we don't skip the prologue:
2475 - Some args may not yet have been saved to the stack where the debug
2476 info expects to find them (true anyway when only 'entry' is skipped);
2477 - Software breakpoints ('break' instrs) may not have been unplanted
2478 when the prologue analysis is done on initializing the frame cache,
2479 and breaks in the prologue will throw off the analysis.
2481 If we have debug info ( line-number info, in particular ) we simply skip
2482 the code associated with the first function line effectively skipping
2483 the prologue code. It works even in cases like
2486 { int local_var = 1;
2490 because, for this source code, both Xtensa compilers will generate two
2491 separate entries ( with the same line number ) in dwarf line-number
2492 section to make sure there is a boundary between the prologue code and
2493 the rest of the function.
2495 If there is no debug info, we need to analyze the code. */
2497 /* #define DONT_SKIP_PROLOGUE */
2500 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2502 struct symtab_and_line prologue_sal;
2505 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2507 #if DONT_SKIP_PROLOGUE
2511 /* Try to find first body line from debug info. */
2513 prologue_sal = find_pc_line (start_pc, 0);
2514 if (prologue_sal.line != 0) /* Found debug info. */
2516 /* In Call0, it is possible to have a function with only one instruction
2517 ('ret') resulting from a 1-line optimized function that does nothing.
2518 In that case, prologue_sal.end may actually point to the start of the
2519 next function in the text section, causing a breakpoint to be set at
2520 the wrong place. Check if the end address is in a different function,
2521 and if so return the start PC. We know we have symbol info. */
2525 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2526 if (end_func != start_pc)
2529 return prologue_sal.end;
2532 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2533 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
2534 return body_pc != 0 ? body_pc : start_pc;
2537 /* Verify the current configuration. */
2539 xtensa_verify_config (struct gdbarch *gdbarch)
2541 struct ui_file *log;
2542 struct cleanup *cleanups;
2543 struct gdbarch_tdep *tdep;
2547 tdep = gdbarch_tdep (gdbarch);
2548 log = mem_fileopen ();
2549 cleanups = make_cleanup_ui_file_delete (log);
2551 /* Verify that we got a reasonable number of AREGS. */
2552 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2553 fprintf_unfiltered (log, _("\
2554 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2557 /* Verify that certain registers exist. */
2559 if (tdep->pc_regnum == -1)
2560 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2561 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2562 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2564 if (tdep->isa_use_windowed_registers)
2566 if (tdep->wb_regnum == -1)
2567 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2568 if (tdep->ws_regnum == -1)
2569 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2570 if (tdep->ar_base == -1)
2571 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2574 if (tdep->a0_base == -1)
2575 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2577 buf = ui_file_xstrdup (log, &length);
2578 make_cleanup (xfree, buf);
2580 internal_error (__FILE__, __LINE__,
2581 _("the following are invalid: %s"), buf);
2582 do_cleanups (cleanups);
2586 /* Derive specific register numbers from the array of registers. */
2589 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2591 xtensa_register_t* rmap;
2592 int n, max_size = 4;
2595 tdep->num_nopriv_regs = 0;
2597 /* Special registers 0..255 (core). */
2598 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2600 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2602 if (rmap->target_number == 0x0020)
2603 tdep->pc_regnum = n;
2604 else if (rmap->target_number == 0x0100)
2606 else if (rmap->target_number == 0x0000)
2608 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2609 tdep->wb_regnum = n;
2610 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2611 tdep->ws_regnum = n;
2612 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2613 tdep->debugcause_regnum = n;
2614 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2615 tdep->exccause_regnum = n;
2616 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2617 tdep->excvaddr_regnum = n;
2618 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2619 tdep->lbeg_regnum = n;
2620 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2621 tdep->lend_regnum = n;
2622 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2623 tdep->lcount_regnum = n;
2624 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2625 tdep->sar_regnum = n;
2626 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2627 tdep->litbase_regnum = n;
2628 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2629 tdep->ps_regnum = n;
2631 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2632 tdep->interrupt_regnum = n;
2633 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2634 tdep->interrupt2_regnum = n;
2635 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2636 tdep->cpenable_regnum = n;
2639 if (rmap->byte_size > max_size)
2640 max_size = rmap->byte_size;
2641 if (rmap->mask != 0 && tdep->num_regs == 0)
2643 /* Find out out how to deal with priveleged registers.
2645 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2646 && tdep->num_nopriv_regs == 0)
2647 tdep->num_nopriv_regs = n;
2649 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2650 && tdep->num_regs == 0)
2654 /* Number of pseudo registers. */
2655 tdep->num_pseudo_regs = n - tdep->num_regs;
2657 /* Empirically determined maximum sizes. */
2658 tdep->max_register_raw_size = max_size;
2659 tdep->max_register_virtual_size = max_size;
2662 /* Module "constructor" function. */
2664 extern struct gdbarch_tdep xtensa_tdep;
2666 static struct gdbarch *
2667 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2669 struct gdbarch_tdep *tdep;
2670 struct gdbarch *gdbarch;
2671 struct xtensa_abi_handler *abi_handler;
2673 DEBUGTRACE ("gdbarch_init()\n");
2675 /* We have to set the byte order before we call gdbarch_alloc. */
2676 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
2678 tdep = &xtensa_tdep;
2679 gdbarch = gdbarch_alloc (&info, tdep);
2680 xtensa_derive_tdep (tdep);
2682 /* Verify our configuration. */
2683 xtensa_verify_config (gdbarch);
2685 /* Pseudo-Register read/write. */
2686 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2687 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2689 /* Set target information. */
2690 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2691 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2692 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2693 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2694 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2696 /* Renumber registers for known formats (stabs and dwarf2). */
2697 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2698 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2700 /* We provide our own function to get register information. */
2701 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2702 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2704 /* To call functions from GDB using dummy frame. */
2705 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2707 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2709 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2711 /* Advance PC across any prologue instructions to reach "real" code. */
2712 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2714 /* Stack grows downward. */
2715 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2717 /* Set breakpoints. */
2718 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2720 /* After breakpoint instruction or illegal instruction, pc still
2721 points at break instruction, so don't decrement. */
2722 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2724 /* We don't skip args. */
2725 set_gdbarch_frame_args_skip (gdbarch, 0);
2727 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2729 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2731 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
2733 /* Frame handling. */
2734 frame_base_set_default (gdbarch, &xtensa_frame_base);
2735 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
2736 dwarf2_append_unwinders (gdbarch);
2738 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2740 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2742 xtensa_add_reggroups (gdbarch);
2743 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2745 set_gdbarch_regset_from_core_section (gdbarch,
2746 xtensa_regset_from_core_section);
2748 set_solib_svr4_fetch_link_map_offsets
2749 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
2755 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2757 error (_("xtensa_dump_tdep(): not implemented"));
2760 /* Provide a prototype to silence -Wmissing-prototypes. */
2761 extern initialize_file_ftype _initialize_xtensa_tdep;
2764 _initialize_xtensa_tdep (void)
2766 struct cmd_list_element *c;
2768 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2769 xtensa_init_reggroups ();
2771 add_setshow_zinteger_cmd ("xtensa",
2773 &xtensa_debug_level,
2774 _("Set Xtensa debugging."),
2775 _("Show Xtensa debugging."), _("\
2776 When non-zero, Xtensa-specific debugging is enabled. \
2777 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2780 &setdebuglist, &showdebuglist);