1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
41 #include "frame-base.h"
42 #include "frame-unwind.h"
44 #include "arch-utils.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
54 #include "xtensa-config.h"
57 static unsigned int xtensa_debug_level = 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
77 #define SP_ALIGNMENT 16
80 /* On Windowed ABI, we use a6 through a11 for passing arguments
81 to a function called by GDB because CALL4 is used. */
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
92 /* On TX, hardware can be configured without Exception Option.
93 There is no PS register in this case. Inside XT-GDB, let us treat
94 it as a virtual read-only register always holding the same value. */
97 /* ABI-independent macros. */
98 #define ARG_NOF(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi \
100 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
101 #define ARG_1ST(gdbarch) \
102 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
103 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
104 : (gdbarch_tdep (gdbarch)->a0_base + 6))
106 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
107 indicates that the instruction is an ENTRY instruction. */
109 #define XTENSA_IS_ENTRY(gdbarch, op1) \
110 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
111 ? ((op1) == 0x6c) : ((op1) == 0x36))
113 #define XTENSA_ENTRY_LENGTH 3
115 /* windowing_enabled() returns true, if windowing is enabled.
116 WOE must be set to 1; EXCM to 0.
117 Note: We assume that EXCM is always 0 for XEA1. */
119 #define PS_WOE (1<<18)
120 #define PS_EXC (1<<4)
123 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
125 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
126 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
129 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
132 /* Convert a live A-register number to the corresponding AR-register
135 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
137 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
140 arreg = a_regnum - tdep->a0_base;
141 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
142 arreg &= tdep->num_aregs - 1;
144 return arreg + tdep->ar_base;
147 /* Convert a live AR-register number to the corresponding A-register order
148 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
150 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
152 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
155 areg = ar_regnum - tdep->ar_base;
156 if (areg < 0 || areg >= tdep->num_aregs)
158 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
159 return (areg > 15) ? -1 : areg;
162 /* Read Xtensa register directly from the hardware. */
164 xtensa_read_register (int regnum)
168 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
169 return (unsigned long) value;
172 /* Write Xtensa register directly to the hardware. */
174 xtensa_write_register (int regnum, ULONGEST value)
176 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
179 /* Return the window size of the previous call to the function from which we
182 This function is used to extract the return value after a called function
183 has returned to the caller. On Xtensa, the register that holds the return
184 value (from the perspective of the caller) depends on what call
185 instruction was used. For now, we are assuming that the call instruction
186 precedes the current address, so we simply analyze the call instruction.
187 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
188 method to call the inferior function. */
191 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
193 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
198 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
200 /* Read the previous instruction (should be a call[x]{4|8|12}. */
201 read_memory (pc-3, buf, 3);
202 insn = extract_unsigned_integer (buf, 3, byte_order);
204 /* Decode call instruction:
206 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
207 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
209 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
210 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
212 if (byte_order == BFD_ENDIAN_LITTLE)
214 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
215 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
219 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
220 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
226 /* REGISTER INFORMATION */
228 /* Find register by name. */
230 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
234 for (i = 0; i < gdbarch_num_regs (gdbarch)
235 + gdbarch_num_pseudo_regs (gdbarch);
238 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
244 /* Returns the name of a register. */
246 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
248 /* Return the name stored in the register map. */
249 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
250 + gdbarch_num_pseudo_regs (gdbarch))
251 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
253 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
257 /* Return the type of a register. Create a new type, if necessary. */
260 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
264 /* Return signed integer for ARx and Ax registers. */
265 if ((regnum >= tdep->ar_base
266 && regnum < tdep->ar_base + tdep->num_aregs)
267 || (regnum >= tdep->a0_base
268 && regnum < tdep->a0_base + 16))
269 return builtin_type (gdbarch)->builtin_int;
271 if (regnum == gdbarch_pc_regnum (gdbarch)
272 || regnum == tdep->a0_base + 1)
273 return builtin_type (gdbarch)->builtin_data_ptr;
275 /* Return the stored type for all other registers. */
276 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
277 + gdbarch_num_pseudo_regs (gdbarch))
279 xtensa_register_t* reg = &tdep->regmap[regnum];
281 /* Set ctype for this register (only the first time). */
285 struct ctype_cache *tp;
286 int size = reg->byte_size;
288 /* We always use the memory representation,
289 even if the register width is smaller. */
293 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
297 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
301 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
305 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
309 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
313 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
314 if (tp->size == size)
319 char *name = xstrprintf ("int%d", size * 8);
321 tp = XNEW (struct ctype_cache);
322 tp->next = tdep->type_entries;
323 tdep->type_entries = tp;
326 = arch_integer_type (gdbarch, size * 8, 1, name);
330 reg->ctype = tp->virtual_type;
336 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
341 /* Return the 'local' register number for stubs, dwarf2, etc.
342 The debugging information enumerates registers starting from 0 for A0
343 to n for An. So, we only have to add the base number for A0. */
346 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
350 if (regnum >= 0 && regnum < 16)
351 return gdbarch_tdep (gdbarch)->a0_base + regnum;
354 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
356 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
359 internal_error (__FILE__, __LINE__,
360 _("invalid dwarf/stabs register number %d"), regnum);
365 /* Write the bits of a masked register to the various registers.
366 Only the masked areas of these registers are modified; the other
367 fields are untouched. The size of masked registers is always less
368 than or equal to 32 bits. */
371 xtensa_register_write_masked (struct regcache *regcache,
372 xtensa_register_t *reg, const gdb_byte *buffer)
374 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
375 const xtensa_mask_t *mask = reg->mask;
377 int shift = 0; /* Shift for next mask (mod 32). */
378 int start, size; /* Start bit and size of current mask. */
380 unsigned int *ptr = value;
381 unsigned int regval, m, mem = 0;
383 int bytesize = reg->byte_size;
384 int bitsize = bytesize * 8;
387 DEBUGTRACE ("xtensa_register_write_masked ()\n");
389 /* Copy the masked register to host byte-order. */
390 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
391 for (i = 0; i < bytesize; i++)
394 mem |= (buffer[bytesize - i - 1] << 24);
399 for (i = 0; i < bytesize; i++)
402 mem |= (buffer[i] << 24);
407 /* We might have to shift the final value:
408 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
409 bytesize & 3 == x -> shift (4-x) * 8. */
411 *ptr = mem >> (((0 - bytesize) & 3) * 8);
415 /* Write the bits to the masked areas of the other registers. */
416 for (i = 0; i < mask->count; i++)
418 start = mask->mask[i].bit_start;
419 size = mask->mask[i].bit_size;
420 regval = mem >> shift;
422 if ((shift += size) > bitsize)
423 error (_("size of all masks is larger than the register"));
432 regval |= mem << (size - shift);
435 /* Make sure we have a valid register. */
436 r = mask->mask[i].reg_num;
437 if (r >= 0 && size > 0)
439 /* Don't overwrite the unmasked areas. */
441 regcache_cooked_read_unsigned (regcache, r, &old_val);
442 m = 0xffffffff >> (32 - size) << start;
444 regval = (regval & m) | (old_val & ~m);
445 regcache_cooked_write_unsigned (regcache, r, regval);
451 /* Read a tie state or mapped registers. Read the masked areas
452 of the registers and assemble them into a single value. */
454 static enum register_status
455 xtensa_register_read_masked (struct regcache *regcache,
456 xtensa_register_t *reg, gdb_byte *buffer)
458 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
459 const xtensa_mask_t *mask = reg->mask;
464 unsigned int *ptr = value;
465 unsigned int regval, mem = 0;
467 int bytesize = reg->byte_size;
468 int bitsize = bytesize * 8;
471 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
472 reg->name == 0 ? "" : reg->name);
474 /* Assemble the register from the masked areas of other registers. */
475 for (i = 0; i < mask->count; i++)
477 int r = mask->mask[i].reg_num;
480 enum register_status status;
483 status = regcache_cooked_read_unsigned (regcache, r, &val);
484 if (status != REG_VALID)
486 regval = (unsigned int) val;
491 start = mask->mask[i].bit_start;
492 size = mask->mask[i].bit_size;
497 regval &= (0xffffffff >> (32 - size));
499 mem |= regval << shift;
501 if ((shift += size) > bitsize)
502 error (_("size of all masks is larger than the register"));
513 mem = regval >> (size - shift);
520 /* Copy value to target byte order. */
524 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
525 for (i = 0; i < bytesize; i++)
529 buffer[bytesize - i - 1] = mem & 0xff;
533 for (i = 0; i < bytesize; i++)
537 buffer[i] = mem & 0xff;
545 /* Read pseudo registers. */
547 static enum register_status
548 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
549 struct regcache *regcache,
553 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
555 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
556 regnum, xtensa_register_name (gdbarch, regnum));
558 /* Read aliases a0..a15, if this is a Windowed ABI. */
559 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
560 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
561 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
563 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
564 enum register_status status;
566 status = regcache_raw_read (regcache,
567 gdbarch_tdep (gdbarch)->wb_regnum,
569 if (status != REG_VALID)
571 regnum = arreg_number (gdbarch, regnum,
572 extract_unsigned_integer (buf, 4, byte_order));
575 /* We can always read non-pseudo registers. */
576 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
577 return regcache_raw_read (regcache, regnum, buffer);
579 /* We have to find out how to deal with priveleged registers.
580 Let's treat them as pseudo-registers, but we cannot read/write them. */
582 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
584 buffer[0] = (gdb_byte)0;
585 buffer[1] = (gdb_byte)0;
586 buffer[2] = (gdb_byte)0;
587 buffer[3] = (gdb_byte)0;
590 /* Pseudo registers. */
592 && regnum < gdbarch_num_regs (gdbarch)
593 + gdbarch_num_pseudo_regs (gdbarch))
595 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
596 xtensa_register_type_t type = reg->type;
597 int flags = gdbarch_tdep (gdbarch)->target_flags;
599 /* We cannot read Unknown or Unmapped registers. */
600 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
602 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
604 warning (_("cannot read register %s"),
605 xtensa_register_name (gdbarch, regnum));
610 /* Some targets cannot read TIE register files. */
611 else if (type == xtRegisterTypeTieRegfile)
613 /* Use 'fetch' to get register? */
614 if (flags & xtTargetFlagsUseFetchStore)
616 warning (_("cannot read register"));
620 /* On some targets (esp. simulators), we can always read the reg. */
621 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
623 warning (_("cannot read register"));
628 /* We can always read mapped registers. */
629 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
630 return xtensa_register_read_masked (regcache, reg, buffer);
632 /* Assume that we can read the register. */
633 return regcache_raw_read (regcache, regnum, buffer);
636 internal_error (__FILE__, __LINE__,
637 _("invalid register number %d"), regnum);
641 /* Write pseudo registers. */
644 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
645 struct regcache *regcache,
647 const gdb_byte *buffer)
649 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
651 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
652 regnum, xtensa_register_name (gdbarch, regnum));
654 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
655 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
656 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
657 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
659 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
661 regcache_raw_read (regcache,
662 gdbarch_tdep (gdbarch)->wb_regnum, buf);
663 regnum = arreg_number (gdbarch, regnum,
664 extract_unsigned_integer (buf, 4, byte_order));
667 /* We can always write 'core' registers.
668 Note: We might have converted Ax->ARy. */
669 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
670 regcache_raw_write (regcache, regnum, buffer);
672 /* We have to find out how to deal with priveleged registers.
673 Let's treat them as pseudo-registers, but we cannot read/write them. */
675 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
679 /* Pseudo registers. */
681 && regnum < gdbarch_num_regs (gdbarch)
682 + gdbarch_num_pseudo_regs (gdbarch))
684 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
685 xtensa_register_type_t type = reg->type;
686 int flags = gdbarch_tdep (gdbarch)->target_flags;
688 /* On most targets, we cannot write registers
689 of type "Unknown" or "Unmapped". */
690 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
692 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
694 warning (_("cannot write register %s"),
695 xtensa_register_name (gdbarch, regnum));
700 /* Some targets cannot read TIE register files. */
701 else if (type == xtRegisterTypeTieRegfile)
703 /* Use 'store' to get register? */
704 if (flags & xtTargetFlagsUseFetchStore)
706 warning (_("cannot write register"));
710 /* On some targets (esp. simulators), we can always write
712 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
714 warning (_("cannot write register"));
719 /* We can always write mapped registers. */
720 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
722 xtensa_register_write_masked (regcache, reg, buffer);
726 /* Assume that we can write the register. */
727 regcache_raw_write (regcache, regnum, buffer);
730 internal_error (__FILE__, __LINE__,
731 _("invalid register number %d"), regnum);
734 static struct reggroup *xtensa_ar_reggroup;
735 static struct reggroup *xtensa_user_reggroup;
736 static struct reggroup *xtensa_vectra_reggroup;
737 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
740 xtensa_init_reggroups (void)
743 char cpname[] = "cp0";
745 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
746 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
747 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
749 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
752 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
757 xtensa_add_reggroups (struct gdbarch *gdbarch)
761 /* Predefined groups. */
762 reggroup_add (gdbarch, all_reggroup);
763 reggroup_add (gdbarch, save_reggroup);
764 reggroup_add (gdbarch, restore_reggroup);
765 reggroup_add (gdbarch, system_reggroup);
766 reggroup_add (gdbarch, vector_reggroup);
767 reggroup_add (gdbarch, general_reggroup);
768 reggroup_add (gdbarch, float_reggroup);
770 /* Xtensa-specific groups. */
771 reggroup_add (gdbarch, xtensa_ar_reggroup);
772 reggroup_add (gdbarch, xtensa_user_reggroup);
773 reggroup_add (gdbarch, xtensa_vectra_reggroup);
775 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
776 reggroup_add (gdbarch, xtensa_cp[i]);
780 xtensa_coprocessor_register_group (struct reggroup *group)
784 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
785 if (group == xtensa_cp[i])
791 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
792 | XTENSA_REGISTER_FLAGS_WRITABLE \
793 | XTENSA_REGISTER_FLAGS_VOLATILE)
795 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
796 | XTENSA_REGISTER_FLAGS_WRITABLE)
799 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
801 struct reggroup *group)
803 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
804 xtensa_register_type_t type = reg->type;
805 xtensa_register_group_t rg = reg->group;
808 if (group == save_reggroup)
809 /* Every single register should be included into the list of registers
810 to be watched for changes while using -data-list-changed-registers. */
813 /* First, skip registers that are not visible to this target
814 (unknown and unmapped registers when not using ISS). */
816 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
818 if (group == all_reggroup)
820 if (group == xtensa_ar_reggroup)
821 return rg & xtRegisterGroupAddrReg;
822 if (group == xtensa_user_reggroup)
823 return rg & xtRegisterGroupUser;
824 if (group == float_reggroup)
825 return rg & xtRegisterGroupFloat;
826 if (group == general_reggroup)
827 return rg & xtRegisterGroupGeneral;
828 if (group == system_reggroup)
829 return rg & xtRegisterGroupState;
830 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
831 return rg & xtRegisterGroupVectra;
832 if (group == restore_reggroup)
833 return (regnum < gdbarch_num_regs (gdbarch)
834 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
835 cp_number = xtensa_coprocessor_register_group (group);
837 return rg & (xtRegisterGroupCP0 << cp_number);
843 /* Supply register REGNUM from the buffer specified by GREGS and LEN
844 in the general-purpose register set REGSET to register cache
845 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
848 xtensa_supply_gregset (const struct regset *regset,
854 const xtensa_elf_gregset_t *regs = gregs;
855 struct gdbarch *gdbarch = get_regcache_arch (rc);
858 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
860 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
861 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
862 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
863 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
864 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
865 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
866 (char *) ®s->windowbase);
867 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
868 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
869 (char *) ®s->windowstart);
870 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
871 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
872 (char *) ®s->lbeg);
873 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
874 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
875 (char *) ®s->lend);
876 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
877 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
878 (char *) ®s->lcount);
879 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
880 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
881 (char *) ®s->sar);
882 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
883 && regnum < gdbarch_tdep (gdbarch)->ar_base
884 + gdbarch_tdep (gdbarch)->num_aregs)
885 regcache_raw_supply (rc, regnum,
886 (char *) ®s->ar[regnum - gdbarch_tdep
887 (gdbarch)->ar_base]);
888 else if (regnum == -1)
890 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
891 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
892 (char *) ®s->ar[i]);
897 /* Xtensa register set. */
903 xtensa_supply_gregset
907 /* Iterate over supported core file register note sections. */
910 xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch,
911 iterate_over_regset_sections_cb *cb,
913 const struct regcache *regcache)
915 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
917 cb (".reg", sizeof (xtensa_elf_gregset_t), &xtensa_gregset,
922 /* Handling frames. */
924 /* Number of registers to save in case of Windowed ABI. */
925 #define XTENSA_NUM_SAVED_AREGS 12
927 /* Frame cache part for Windowed ABI. */
928 typedef struct xtensa_windowed_frame_cache
930 int wb; /* WINDOWBASE of the previous frame. */
931 int callsize; /* Call size of this frame. */
932 int ws; /* WINDOWSTART of the previous frame. It keeps track of
933 life windows only. If there is no bit set for the
934 window, that means it had been already spilled
935 because of window overflow. */
937 /* Addresses of spilled A-registers.
938 AREGS[i] == -1, if corresponding AR is alive. */
939 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
940 } xtensa_windowed_frame_cache_t;
942 /* Call0 ABI Definitions. */
944 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
946 #define C0_NREGS 16 /* Number of A-registers to track. */
947 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
948 #define C0_SP 1 /* Register used as SP. */
949 #define C0_FP 15 /* Register used as FP. */
950 #define C0_RA 0 /* Register used as return address. */
951 #define C0_ARGS 2 /* Register used as first arg/retval. */
952 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
954 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
955 A-register where the current content of the reg came from (in terms
956 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
957 mean that the orignal content of the register was saved to the stack.
958 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
959 know where SP will end up until the entire prologue has been analyzed. */
961 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
962 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
963 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
965 extern xtensa_isa xtensa_default_isa;
967 typedef struct xtensa_c0reg
969 int fr_reg; /* original register from which register content
970 is derived, or C0_CONST, or C0_INEXP. */
971 int fr_ofs; /* constant offset from reg, or immediate value. */
972 int to_stk; /* offset from original SP to register (4-byte aligned),
973 or C0_NOSTK if register has not been saved. */
976 /* Frame cache part for Call0 ABI. */
977 typedef struct xtensa_call0_frame_cache
979 int c0_frmsz; /* Stack frame size. */
980 int c0_hasfp; /* Current frame uses frame pointer. */
981 int fp_regnum; /* A-register used as FP. */
982 int c0_fp; /* Actual value of frame pointer. */
983 int c0_fpalign; /* Dinamic adjustment for the stack
984 pointer. It's an AND mask. Zero,
985 if alignment was not adjusted. */
986 int c0_old_sp; /* In case of dynamic adjustment, it is
987 a register holding unaligned sp.
988 C0_INEXP, when undefined. */
989 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
990 stack offset. C0_NOSTK otherwise. */
992 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
993 } xtensa_call0_frame_cache_t;
995 typedef struct xtensa_frame_cache
997 CORE_ADDR base; /* Stack pointer of this frame. */
998 CORE_ADDR pc; /* PC of this frame at the function entry point. */
999 CORE_ADDR ra; /* The raw return address of this frame. */
1000 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1001 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1002 int call0; /* It's a call0 framework (else windowed). */
1005 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1006 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1008 } xtensa_frame_cache_t;
1011 static struct xtensa_frame_cache *
1012 xtensa_alloc_frame_cache (int windowed)
1014 xtensa_frame_cache_t *cache;
1017 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1019 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1026 cache->call0 = !windowed;
1029 cache->c0.c0_frmsz = -1;
1030 cache->c0.c0_hasfp = 0;
1031 cache->c0.fp_regnum = -1;
1032 cache->c0.c0_fp = -1;
1033 cache->c0.c0_fpalign = 0;
1034 cache->c0.c0_old_sp = C0_INEXP;
1035 cache->c0.c0_sp_ofs = C0_NOSTK;
1037 for (i = 0; i < C0_NREGS; i++)
1039 cache->c0.c0_rt[i].fr_reg = i;
1040 cache->c0.c0_rt[i].fr_ofs = 0;
1041 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1048 cache->wd.callsize = -1;
1050 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1051 cache->wd.aregs[i] = -1;
1058 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1060 return address & ~15;
1065 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1070 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1071 host_address_to_string (next_frame));
1073 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1074 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1076 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1082 static struct frame_id
1083 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1087 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1089 pc = get_frame_pc (this_frame);
1090 fp = get_frame_register_unsigned
1091 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1093 /* Make dummy frame ID unique by adding a constant. */
1094 return frame_id_build (fp + SP_ALIGNMENT, pc);
1097 /* Returns true, if instruction to execute next is unique to Xtensa Window
1098 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1101 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1103 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1104 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1107 if (byte_order == BFD_ENDIAN_BIG)
1109 /* Check, if this is L32E or S32E. */
1110 code = insn & 0xf000ff00;
1111 if ((code == 0x00009000) || (code == 0x00009400))
1113 /* Check, if this is RFWU or RFWO. */
1114 code = insn & 0xffffff00;
1115 return ((code == 0x00430000) || (code == 0x00530000));
1119 /* Check, if this is L32E or S32E. */
1120 code = insn & 0x00ff000f;
1121 if ((code == 0x090000) || (code == 0x490000))
1123 /* Check, if this is RFWU or RFWO. */
1124 code = insn & 0x00ffffff;
1125 return ((code == 0x00003400) || (code == 0x00003500));
1129 /* Returns the best guess about which register is a frame pointer
1130 for the function containing CURRENT_PC. */
1132 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1133 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1136 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1138 #define RETURN_FP goto done
1140 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1141 CORE_ADDR start_addr;
1143 xtensa_insnbuf ins, slot;
1144 gdb_byte ibuf[XTENSA_ISA_BSZ];
1145 CORE_ADDR ia, bt, ba;
1147 int ilen, islots, is;
1149 const char *opcname;
1151 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1152 if (start_addr == 0)
1155 if (!xtensa_default_isa)
1156 xtensa_default_isa = xtensa_isa_init (0, 0);
1157 isa = xtensa_default_isa;
1158 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1159 ins = xtensa_insnbuf_alloc (isa);
1160 slot = xtensa_insnbuf_alloc (isa);
1163 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1165 if (ia + xtensa_isa_maxlength (isa) > bt)
1168 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1169 ? ba + XTENSA_ISA_BSZ : current_pc;
1170 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1174 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1175 ifmt = xtensa_format_decode (isa, ins);
1176 if (ifmt == XTENSA_UNDEFINED)
1178 ilen = xtensa_format_length (isa, ifmt);
1179 if (ilen == XTENSA_UNDEFINED)
1181 islots = xtensa_format_num_slots (isa, ifmt);
1182 if (islots == XTENSA_UNDEFINED)
1185 for (is = 0; is < islots; ++is)
1187 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1190 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1191 if (opc == XTENSA_UNDEFINED)
1194 opcname = xtensa_opcode_name (isa, opc);
1196 if (strcasecmp (opcname, "mov.n") == 0
1197 || strcasecmp (opcname, "or") == 0)
1199 unsigned int register_operand;
1201 /* Possible candidate for setting frame pointer
1202 from A1. This is what we are looking for. */
1204 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1205 is, slot, ®ister_operand) != 0)
1207 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1209 if (register_operand == 1) /* Mov{.n} FP A1. */
1211 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1212 ®ister_operand) != 0)
1214 if (xtensa_operand_decode (isa, opc, 0,
1215 ®ister_operand) != 0)
1219 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1225 /* We have problems decoding the memory. */
1227 || strcasecmp (opcname, "ill") == 0
1228 || strcasecmp (opcname, "ill.n") == 0
1229 /* Hit planted breakpoint. */
1230 || strcasecmp (opcname, "break") == 0
1231 || strcasecmp (opcname, "break.n") == 0
1232 /* Flow control instructions finish prologue. */
1233 || xtensa_opcode_is_branch (isa, opc) > 0
1234 || xtensa_opcode_is_jump (isa, opc) > 0
1235 || xtensa_opcode_is_loop (isa, opc) > 0
1236 || xtensa_opcode_is_call (isa, opc) > 0
1237 || strcasecmp (opcname, "simcall") == 0
1238 || strcasecmp (opcname, "syscall") == 0)
1239 /* Can not continue analysis. */
1244 xtensa_insnbuf_free(isa, slot);
1245 xtensa_insnbuf_free(isa, ins);
1249 /* The key values to identify the frame using "cache" are
1251 cache->base = SP (or best guess about FP) of this frame;
1252 cache->pc = entry-PC (entry point of the frame function);
1253 cache->prev_sp = SP of the previous frame. */
1256 call0_frame_cache (struct frame_info *this_frame,
1257 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1260 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1261 xtensa_frame_cache_t *cache,
1264 static struct xtensa_frame_cache *
1265 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1267 xtensa_frame_cache_t *cache;
1268 CORE_ADDR ra, wb, ws, pc, sp, ps;
1269 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1270 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1271 unsigned int fp_regnum;
1272 int windowed, ps_regnum;
1277 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1278 ps_regnum = gdbarch_ps_regnum (gdbarch);
1279 ps = (ps_regnum >= 0
1280 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1282 windowed = windowing_enabled (gdbarch, ps);
1284 /* Get pristine xtensa-frame. */
1285 cache = xtensa_alloc_frame_cache (windowed);
1286 *this_cache = cache;
1292 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1293 wb = get_frame_register_unsigned (this_frame,
1294 gdbarch_tdep (gdbarch)->wb_regnum);
1295 ws = get_frame_register_unsigned (this_frame,
1296 gdbarch_tdep (gdbarch)->ws_regnum);
1298 op1 = read_memory_integer (pc, 1, byte_order);
1299 if (XTENSA_IS_ENTRY (gdbarch, op1))
1301 int callinc = CALLINC (ps);
1302 ra = get_frame_register_unsigned
1303 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1305 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1306 cache->wd.callsize = 0;
1309 cache->prev_sp = get_frame_register_unsigned
1310 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1312 /* This only can be the outermost frame since we are
1313 just about to execute ENTRY. SP hasn't been set yet.
1314 We can assume any frame size, because it does not
1315 matter, and, let's fake frame base in cache. */
1316 cache->base = cache->prev_sp - 16;
1319 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1320 cache->ps = (ps & ~PS_CALLINC_MASK)
1321 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1327 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1328 ra = get_frame_register_unsigned (this_frame,
1329 gdbarch_tdep (gdbarch)->a0_base);
1330 cache->wd.callsize = WINSIZE (ra);
1331 cache->wd.wb = (wb - cache->wd.callsize / 4)
1332 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1333 cache->wd.ws = ws & ~(1 << wb);
1335 cache->pc = get_frame_func (this_frame);
1336 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1337 cache->ps = (ps & ~PS_CALLINC_MASK)
1338 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1341 if (cache->wd.ws == 0)
1346 sp = get_frame_register_unsigned
1347 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1349 for (i = 0; i < 4; i++, sp += 4)
1351 cache->wd.aregs[i] = sp;
1354 if (cache->wd.callsize > 4)
1356 /* Set A4...A7/A11. */
1357 /* Get the SP of the frame previous to the previous one.
1358 To achieve this, we have to dereference SP twice. */
1359 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1360 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1361 sp -= cache->wd.callsize * 4;
1363 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1365 cache->wd.aregs[i] = sp;
1370 if ((cache->prev_sp == 0) && ( ra != 0 ))
1371 /* If RA is equal to 0 this frame is an outermost frame. Leave
1372 cache->prev_sp unchanged marking the boundary of the frame stack. */
1374 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1376 /* Register window overflow already happened.
1377 We can read caller's SP from the proper spill loction. */
1378 sp = get_frame_register_unsigned
1379 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1380 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1384 /* Read caller's frame SP directly from the previous window. */
1385 int regnum = arreg_number
1386 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1389 cache->prev_sp = xtensa_read_register (regnum);
1393 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1395 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1397 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1398 /* Everything was set already, including cache->base. */
1401 else /* Call0 framework. */
1403 call0_frame_cache (this_frame, cache, pc);
1404 fp_regnum = cache->c0.fp_regnum;
1407 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1412 static int xtensa_session_once_reported = 1;
1414 /* Report a problem with prologue analysis while doing backtracing.
1415 But, do it only once to avoid annoyng repeated messages. */
1420 if (xtensa_session_once_reported == 0)
1422 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1423 This message will not be repeated in this session.\n"));
1425 xtensa_session_once_reported = 1;
1430 xtensa_frame_this_id (struct frame_info *this_frame,
1432 struct frame_id *this_id)
1434 struct xtensa_frame_cache *cache =
1435 xtensa_frame_cache (this_frame, this_cache);
1437 if (cache->prev_sp == 0)
1440 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1443 static struct value *
1444 xtensa_frame_prev_register (struct frame_info *this_frame,
1448 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1449 struct xtensa_frame_cache *cache;
1450 ULONGEST saved_reg = 0;
1453 if (*this_cache == NULL)
1454 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1455 cache = *this_cache;
1457 if (regnum ==gdbarch_pc_regnum (gdbarch))
1458 saved_reg = cache->ra;
1459 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1460 saved_reg = cache->prev_sp;
1461 else if (!cache->call0)
1463 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1464 saved_reg = cache->wd.ws;
1465 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1466 saved_reg = cache->wd.wb;
1467 else if (regnum == gdbarch_ps_regnum (gdbarch))
1468 saved_reg = cache->ps;
1476 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1478 if (!cache->call0) /* Windowed ABI. */
1480 /* Convert A-register numbers to AR-register numbers,
1481 if we deal with A-register. */
1482 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1483 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1484 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1486 /* Check, if we deal with AR-register saved on stack. */
1487 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1488 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1489 + gdbarch_tdep (gdbarch)->num_aregs))
1491 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1494 && areg < XTENSA_NUM_SAVED_AREGS
1495 && cache->wd.aregs[areg] != -1)
1496 return frame_unwind_got_memory (this_frame, regnum,
1497 cache->wd.aregs[areg]);
1500 else /* Call0 ABI. */
1502 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1503 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1505 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1512 /* If register was saved in the prologue, retrieve it. */
1513 stkofs = cache->c0.c0_rt[reg].to_stk;
1514 if (stkofs != C0_NOSTK)
1516 /* Determine SP on entry based on FP. */
1517 spe = cache->c0.c0_fp
1518 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1520 return frame_unwind_got_memory (this_frame, regnum,
1526 /* All other registers have been either saved to
1527 the stack or are still alive in the processor. */
1529 return frame_unwind_got_register (this_frame, regnum, regnum);
1533 static const struct frame_unwind
1537 default_frame_unwind_stop_reason,
1538 xtensa_frame_this_id,
1539 xtensa_frame_prev_register,
1541 default_frame_sniffer
1545 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1547 struct xtensa_frame_cache *cache =
1548 xtensa_frame_cache (this_frame, this_cache);
1553 static const struct frame_base
1557 xtensa_frame_base_address,
1558 xtensa_frame_base_address,
1559 xtensa_frame_base_address
1564 xtensa_extract_return_value (struct type *type,
1565 struct regcache *regcache,
1568 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1569 bfd_byte *valbuf = dst;
1570 int len = TYPE_LENGTH (type);
1575 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1577 gdb_assert(len > 0);
1579 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1581 /* First, we have to find the caller window in the register file. */
1582 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1583 callsize = extract_call_winsize (gdbarch, pc);
1585 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1586 if (len > (callsize > 8 ? 8 : 16))
1587 internal_error (__FILE__, __LINE__,
1588 _("cannot extract return value of %d bytes long"),
1591 /* Get the register offset of the return
1592 register (A2) in the caller window. */
1593 regcache_raw_read_unsigned
1594 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1595 areg = arreg_number (gdbarch,
1596 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1600 /* No windowing hardware - Call0 ABI. */
1601 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1604 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1606 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1609 for (; len > 0; len -= 4, areg++, valbuf += 4)
1612 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1614 regcache_raw_read (regcache, areg, valbuf);
1620 xtensa_store_return_value (struct type *type,
1621 struct regcache *regcache,
1624 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1625 const bfd_byte *valbuf = dst;
1629 int len = TYPE_LENGTH (type);
1632 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1634 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1636 regcache_raw_read_unsigned
1637 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1638 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1639 callsize = extract_call_winsize (gdbarch, pc);
1641 if (len > (callsize > 8 ? 8 : 16))
1642 internal_error (__FILE__, __LINE__,
1643 _("unimplemented for this length: %d"),
1644 TYPE_LENGTH (type));
1645 areg = arreg_number (gdbarch,
1646 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1648 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1649 callsize, (int) wb);
1653 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1656 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1659 for (; len > 0; len -= 4, areg++, valbuf += 4)
1662 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1664 regcache_raw_write (regcache, areg, valbuf);
1669 static enum return_value_convention
1670 xtensa_return_value (struct gdbarch *gdbarch,
1671 struct value *function,
1672 struct type *valtype,
1673 struct regcache *regcache,
1675 const gdb_byte *writebuf)
1677 /* Structures up to 16 bytes are returned in registers. */
1679 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1680 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1681 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1682 && TYPE_LENGTH (valtype) > 16);
1685 return RETURN_VALUE_STRUCT_CONVENTION;
1687 DEBUGTRACE ("xtensa_return_value(...)\n");
1689 if (writebuf != NULL)
1691 xtensa_store_return_value (valtype, regcache, writebuf);
1694 if (readbuf != NULL)
1696 gdb_assert (!struct_return);
1697 xtensa_extract_return_value (valtype, regcache, readbuf);
1699 return RETURN_VALUE_REGISTER_CONVENTION;
1706 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1707 struct value *function,
1708 struct regcache *regcache,
1711 struct value **args,
1714 CORE_ADDR struct_addr)
1716 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1718 int size, onstack_size;
1719 gdb_byte *buf = (gdb_byte *) alloca (16);
1721 struct argument_info
1723 const bfd_byte *contents;
1725 int onstack; /* onstack == 0 => in reg */
1726 int align; /* alignment */
1729 int offset; /* stack offset if on stack. */
1730 int regno; /* regno if in register. */
1734 struct argument_info *arg_info =
1735 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1739 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1741 if (xtensa_debug_level > 3)
1744 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1745 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1746 "struct_addr=0x%x\n",
1747 (int) sp, (int) struct_return, (int) struct_addr);
1749 for (i = 0; i < nargs; i++)
1751 struct value *arg = args[i];
1752 struct type *arg_type = check_typedef (value_type (arg));
1753 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1754 host_address_to_string (arg),
1755 TYPE_LENGTH (arg_type));
1756 switch (TYPE_CODE (arg_type))
1759 fprintf_unfiltered (gdb_stdlog, "int");
1761 case TYPE_CODE_STRUCT:
1762 fprintf_unfiltered (gdb_stdlog, "struct");
1765 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1768 fprintf_unfiltered (gdb_stdlog, " %s\n",
1769 host_address_to_string (value_contents (arg)));
1773 /* First loop: collect information.
1774 Cast into type_long. (This shouldn't happen often for C because
1775 GDB already does this earlier.) It's possible that GDB could
1776 do it all the time but it's harmless to leave this code here. */
1783 size = REGISTER_SIZE;
1785 for (i = 0; i < nargs; i++)
1787 struct argument_info *info = &arg_info[i];
1788 struct value *arg = args[i];
1789 struct type *arg_type = check_typedef (value_type (arg));
1791 switch (TYPE_CODE (arg_type))
1794 case TYPE_CODE_BOOL:
1795 case TYPE_CODE_CHAR:
1796 case TYPE_CODE_RANGE:
1797 case TYPE_CODE_ENUM:
1799 /* Cast argument to long if necessary as the mask does it too. */
1800 if (TYPE_LENGTH (arg_type)
1801 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1803 arg_type = builtin_type (gdbarch)->builtin_long;
1804 arg = value_cast (arg_type, arg);
1806 /* Aligment is equal to the type length for the basic types. */
1807 info->align = TYPE_LENGTH (arg_type);
1812 /* Align doubles correctly. */
1813 if (TYPE_LENGTH (arg_type)
1814 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1815 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1817 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1820 case TYPE_CODE_STRUCT:
1822 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1825 info->length = TYPE_LENGTH (arg_type);
1826 info->contents = value_contents (arg);
1828 /* Align size and onstack_size. */
1829 size = (size + info->align - 1) & ~(info->align - 1);
1830 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1832 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1835 info->u.offset = onstack_size;
1836 onstack_size += info->length;
1841 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1843 size += info->length;
1846 /* Adjust the stack pointer and align it. */
1847 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1849 /* Simulate MOVSP, if Windowed ABI. */
1850 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1853 read_memory (osp - 16, buf, 16);
1854 write_memory (sp - 16, buf, 16);
1857 /* Second Loop: Load arguments. */
1861 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1862 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1865 for (i = 0; i < nargs; i++)
1867 struct argument_info *info = &arg_info[i];
1871 int n = info->length;
1872 CORE_ADDR offset = sp + info->u.offset;
1874 /* Odd-sized structs are aligned to the lower side of a memory
1875 word in big-endian mode and require a shift. This only
1876 applies for structures smaller than one word. */
1878 if (n < REGISTER_SIZE
1879 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1880 offset += (REGISTER_SIZE - n);
1882 write_memory (offset, info->contents, info->length);
1887 int n = info->length;
1888 const bfd_byte *cp = info->contents;
1889 int r = info->u.regno;
1891 /* Odd-sized structs are aligned to the lower side of registers in
1892 big-endian mode and require a shift. The odd-sized leftover will
1893 be at the end. Note that this is only true for structures smaller
1894 than REGISTER_SIZE; for larger odd-sized structures the excess
1895 will be left-aligned in the register on both endiannesses. */
1897 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1900 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1901 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1903 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1904 regcache_cooked_write (regcache, r, buf);
1906 cp += REGISTER_SIZE;
1913 regcache_cooked_write (regcache, r, cp);
1915 cp += REGISTER_SIZE;
1922 /* Set the return address of dummy frame to the dummy address.
1923 The return address for the current function (in A0) is
1924 saved in the dummy frame, so we can savely overwrite A0 here. */
1926 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1930 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1931 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1932 ps = (unsigned long) val & ~0x00030000;
1933 regcache_cooked_write_unsigned
1934 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1935 regcache_cooked_write_unsigned (regcache,
1936 gdbarch_ps_regnum (gdbarch),
1939 /* All the registers have been saved. After executing
1940 dummy call, they all will be restored. So it's safe
1941 to modify WINDOWSTART register to make it look like there
1942 is only one register window corresponding to WINDOWEBASE. */
1944 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1945 regcache_cooked_write_unsigned
1946 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1947 1 << extract_unsigned_integer (buf, 4, byte_order));
1951 /* Simulate CALL0: write RA into A0 register. */
1952 regcache_cooked_write_unsigned
1953 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1956 /* Set new stack pointer and return it. */
1957 regcache_cooked_write_unsigned (regcache,
1958 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1959 /* Make dummy frame ID unique by adding a constant. */
1960 return sp + SP_ALIGNMENT;
1964 /* Return a breakpoint for the current location of PC. We always use
1965 the density version if we have density instructions (regardless of the
1966 current instruction at PC), and use regular instructions otherwise. */
1968 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1969 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1970 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1971 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1973 static const unsigned char *
1974 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1977 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1978 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1979 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1980 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1982 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1984 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1986 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1988 *lenptr = sizeof (density_big_breakpoint);
1989 return density_big_breakpoint;
1993 *lenptr = sizeof (density_little_breakpoint);
1994 return density_little_breakpoint;
1999 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2001 *lenptr = sizeof (big_breakpoint);
2002 return big_breakpoint;
2006 *lenptr = sizeof (little_breakpoint);
2007 return little_breakpoint;
2012 /* Call0 ABI support routines. */
2014 /* Return true, if PC points to "ret" or "ret.n". */
2017 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2019 #define RETURN_RET goto done
2021 xtensa_insnbuf ins, slot;
2022 gdb_byte ibuf[XTENSA_ISA_BSZ];
2023 CORE_ADDR ia, bt, ba;
2025 int ilen, islots, is;
2027 const char *opcname;
2030 isa = xtensa_default_isa;
2031 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2032 ins = xtensa_insnbuf_alloc (isa);
2033 slot = xtensa_insnbuf_alloc (isa);
2036 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2038 if (ia + xtensa_isa_maxlength (isa) > bt)
2041 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2042 ? ba + XTENSA_ISA_BSZ : finish_pc;
2043 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2047 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2048 ifmt = xtensa_format_decode (isa, ins);
2049 if (ifmt == XTENSA_UNDEFINED)
2051 ilen = xtensa_format_length (isa, ifmt);
2052 if (ilen == XTENSA_UNDEFINED)
2054 islots = xtensa_format_num_slots (isa, ifmt);
2055 if (islots == XTENSA_UNDEFINED)
2058 for (is = 0; is < islots; ++is)
2060 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2063 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2064 if (opc == XTENSA_UNDEFINED)
2067 opcname = xtensa_opcode_name (isa, opc);
2069 if ((strcasecmp (opcname, "ret.n") == 0)
2070 || (strcasecmp (opcname, "ret") == 0))
2078 xtensa_insnbuf_free(isa, slot);
2079 xtensa_insnbuf_free(isa, ins);
2083 /* Call0 opcode class. Opcodes are preclassified according to what they
2084 mean for Call0 prologue analysis, and their number of significant operands.
2085 The purpose of this is to simplify prologue analysis by separating
2086 instruction decoding (libisa) from the semantics of prologue analysis. */
2090 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2091 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2092 c0opc_flow, /* Flow control insn. */
2093 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2094 c0opc_break, /* Debugger software breakpoints. */
2095 c0opc_add, /* Adding two registers. */
2096 c0opc_addi, /* Adding a register and an immediate. */
2097 c0opc_and, /* Bitwise "and"-ing two registers. */
2098 c0opc_sub, /* Subtracting a register from a register. */
2099 c0opc_mov, /* Moving a register to a register. */
2100 c0opc_movi, /* Moving an immediate to a register. */
2101 c0opc_l32r, /* Loading a literal. */
2102 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2103 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2104 c0opc_l32e, /* L32E instruction. */
2105 c0opc_s32e, /* S32E instruction. */
2106 c0opc_rfwo, /* RFWO instruction. */
2107 c0opc_rfwu, /* RFWU instruction. */
2108 c0opc_NrOf /* Number of opcode classifications. */
2111 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2114 rwx_special_register (const char *opcname)
2116 char ch = *opcname++;
2118 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2120 if (*opcname++ != 's')
2122 if (*opcname++ != 'r')
2124 if (*opcname++ != '.')
2130 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2132 static xtensa_insn_kind
2133 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2135 const char *opcname;
2136 xtensa_insn_kind opclass = c0opc_uninteresting;
2138 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2140 /* Get opcode name and handle special classifications. */
2142 opcname = xtensa_opcode_name (isa, opc);
2145 || strcasecmp (opcname, "ill") == 0
2146 || strcasecmp (opcname, "ill.n") == 0)
2147 opclass = c0opc_illegal;
2148 else if (strcasecmp (opcname, "break") == 0
2149 || strcasecmp (opcname, "break.n") == 0)
2150 opclass = c0opc_break;
2151 else if (strcasecmp (opcname, "entry") == 0)
2152 opclass = c0opc_entry;
2153 else if (strcasecmp (opcname, "rfwo") == 0)
2154 opclass = c0opc_rfwo;
2155 else if (strcasecmp (opcname, "rfwu") == 0)
2156 opclass = c0opc_rfwu;
2157 else if (xtensa_opcode_is_branch (isa, opc) > 0
2158 || xtensa_opcode_is_jump (isa, opc) > 0
2159 || xtensa_opcode_is_loop (isa, opc) > 0
2160 || xtensa_opcode_is_call (isa, opc) > 0
2161 || strcasecmp (opcname, "simcall") == 0
2162 || strcasecmp (opcname, "syscall") == 0)
2163 opclass = c0opc_flow;
2165 /* Also, classify specific opcodes that need to be tracked. */
2166 else if (strcasecmp (opcname, "add") == 0
2167 || strcasecmp (opcname, "add.n") == 0)
2168 opclass = c0opc_add;
2169 else if (strcasecmp (opcname, "and") == 0)
2170 opclass = c0opc_and;
2171 else if (strcasecmp (opcname, "addi") == 0
2172 || strcasecmp (opcname, "addi.n") == 0
2173 || strcasecmp (opcname, "addmi") == 0)
2174 opclass = c0opc_addi;
2175 else if (strcasecmp (opcname, "sub") == 0)
2176 opclass = c0opc_sub;
2177 else if (strcasecmp (opcname, "mov.n") == 0
2178 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2179 opclass = c0opc_mov;
2180 else if (strcasecmp (opcname, "movi") == 0
2181 || strcasecmp (opcname, "movi.n") == 0)
2182 opclass = c0opc_movi;
2183 else if (strcasecmp (opcname, "l32r") == 0)
2184 opclass = c0opc_l32r;
2185 else if (strcasecmp (opcname, "s32i") == 0
2186 || strcasecmp (opcname, "s32i.n") == 0)
2187 opclass = c0opc_s32i;
2188 else if (strcasecmp (opcname, "l32e") == 0)
2189 opclass = c0opc_l32e;
2190 else if (strcasecmp (opcname, "s32e") == 0)
2191 opclass = c0opc_s32e;
2192 else if (rwx_special_register (opcname))
2193 opclass = c0opc_rwxsr;
2198 /* Tracks register movement/mutation for a given operation, which may
2199 be within a bundle. Updates the destination register tracking info
2200 accordingly. The pc is needed only for pc-relative load instructions
2201 (eg. l32r). The SP register number is needed to identify stores to
2202 the stack frame. Returns 0, if analysis was succesfull, non-zero
2206 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2207 xtensa_insn_kind opclass, int nods, unsigned odv[],
2208 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2210 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2211 unsigned litbase, litaddr, litval;
2216 /* 3 operands: dst, src, imm. */
2217 gdb_assert (nods == 3);
2218 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2219 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2222 /* 3 operands: dst, src1, src2. */
2223 gdb_assert (nods == 3);
2224 if (src[odv[1]].fr_reg == C0_CONST)
2226 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2227 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2229 else if (src[odv[2]].fr_reg == C0_CONST)
2231 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2232 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2234 else dst[odv[0]].fr_reg = C0_INEXP;
2237 /* 3 operands: dst, src1, src2. */
2238 gdb_assert (nods == 3);
2239 if (cache->c0.c0_fpalign == 0)
2241 /* Handle dynamic stack alignment. */
2242 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2244 if (src[odv[2]].fr_reg == C0_CONST)
2245 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2248 else if ((src[odv[0]].fr_reg == spreg)
2249 && (src[odv[2]].fr_reg == spreg))
2251 if (src[odv[1]].fr_reg == C0_CONST)
2252 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2255 /* else fall through. */
2257 if (src[odv[1]].fr_reg == C0_CONST)
2259 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2260 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2262 else if (src[odv[2]].fr_reg == C0_CONST)
2264 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2265 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2267 else dst[odv[0]].fr_reg = C0_INEXP;
2270 /* 3 operands: dst, src1, src2. */
2271 gdb_assert (nods == 3);
2272 if (src[odv[2]].fr_reg == C0_CONST)
2274 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2275 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2277 else dst[odv[0]].fr_reg = C0_INEXP;
2280 /* 2 operands: dst, src [, src]. */
2281 gdb_assert (nods == 2);
2282 /* First, check if it's a special case of saving unaligned SP
2283 to a spare register in case of dynamic stack adjustment.
2284 But, only do it one time. The second time could be initializing
2285 frame pointer. We don't want to overwrite the first one. */
2286 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2287 cache->c0.c0_old_sp = odv[0];
2289 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2290 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2293 /* 2 operands: dst, imm. */
2294 gdb_assert (nods == 2);
2295 dst[odv[0]].fr_reg = C0_CONST;
2296 dst[odv[0]].fr_ofs = odv[1];
2299 /* 2 operands: dst, literal offset. */
2300 gdb_assert (nods == 2);
2301 /* litbase = xtensa_get_litbase (pc); can be also used. */
2302 litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
2303 ? 0 : xtensa_read_register
2304 (gdbarch_tdep (gdbarch)->litbase_regnum);
2305 litaddr = litbase & 1
2306 ? (litbase & ~1) + (signed)odv[1]
2307 : (pc + 3 + (signed)odv[1]) & ~3;
2308 litval = read_memory_integer (litaddr, 4, byte_order);
2309 dst[odv[0]].fr_reg = C0_CONST;
2310 dst[odv[0]].fr_ofs = litval;
2313 /* 3 operands: value, base, offset. */
2314 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2315 /* First, check if it's a spill for saved unaligned SP,
2316 when dynamic stack adjustment was applied to this frame. */
2317 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2318 && (odv[1] == spreg) /* SP usage indicates spill. */
2319 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2320 cache->c0.c0_sp_ofs = odv[2];
2322 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2323 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2324 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2325 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2326 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2328 /* ISA encoding guarantees alignment. But, check it anyway. */
2329 gdb_assert ((odv[2] & 3) == 0);
2330 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2333 /* If we end up inside Window Overflow / Underflow interrupt handler
2334 report an error because these handlers should have been handled
2335 already in a different way. */
2347 /* Analyze prologue of the function at start address to determine if it uses
2348 the Call0 ABI, and if so track register moves and linear modifications
2349 in the prologue up to the PC or just beyond the prologue, whichever is
2350 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2351 prologue. The prologue may overlap non-prologue instructions but is
2352 guaranteed to end by the first flow-control instruction (jump, branch,
2353 call or return). Since an optimized function may move information around
2354 and change the stack frame arbitrarily during the prologue, the information
2355 is guaranteed valid only at the point in the function indicated by the PC.
2356 May be used to skip the prologue or identify the ABI, w/o tracking.
2358 Returns: Address of first instruction after prologue, or PC (whichever
2359 is first), or 0, if decoding failed (in libisa).
2361 start Start address of function/prologue.
2362 pc Program counter to stop at. Use 0 to continue to end of prologue.
2363 If 0, avoids infinite run-on in corrupt code memory by bounding
2364 the scan to the end of the function if that can be determined.
2365 nregs Number of general registers to track.
2367 cache Xtensa frame cache.
2369 Note that these may produce useful results even if decoding fails
2370 because they begin with default assumptions that analysis may change. */
2373 call0_analyze_prologue (struct gdbarch *gdbarch,
2374 CORE_ADDR start, CORE_ADDR pc,
2375 int nregs, xtensa_frame_cache_t *cache)
2377 CORE_ADDR ia; /* Current insn address in prologue. */
2378 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2379 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2380 gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2381 xtensa_isa isa; /* libisa ISA handle. */
2382 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2383 xtensa_format ifmt; /* libisa instruction format. */
2384 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2385 xtensa_opcode opc; /* Opcode in current slot. */
2386 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2387 int nods; /* Opcode number of operands. */
2388 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2389 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2390 int j; /* General loop counter. */
2391 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2392 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2393 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2395 struct symtab_and_line prologue_sal;
2397 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2398 (int)start, (int)pc);
2400 /* Try to limit the scan to the end of the function if a non-zero pc
2401 arg was not supplied to avoid probing beyond the end of valid memory.
2402 If memory is full of garbage that classifies as c0opc_uninteresting.
2403 If this fails (eg. if no symbols) pc ends up 0 as it was.
2404 Intialize the Call0 frame and register tracking info.
2405 Assume it's Call0 until an 'entry' instruction is encountered.
2406 Assume we may be in the prologue until we hit a flow control instr. */
2412 /* Find out, if we have an information about the prologue from DWARF. */
2413 prologue_sal = find_pc_line (start, 0);
2414 if (prologue_sal.line != 0) /* Found debug info. */
2415 body_pc = prologue_sal.end;
2417 /* If we are going to analyze the prologue in general without knowing about
2418 the current PC, make the best assumtion for the end of the prologue. */
2421 find_pc_partial_function (start, 0, NULL, &end_pc);
2422 body_pc = min (end_pc, body_pc);
2425 body_pc = min (pc, body_pc);
2428 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2430 if (!xtensa_default_isa)
2431 xtensa_default_isa = xtensa_isa_init (0, 0);
2432 isa = xtensa_default_isa;
2433 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2434 ins = xtensa_insnbuf_alloc (isa);
2435 slot = xtensa_insnbuf_alloc (isa);
2437 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2439 /* (Re)fill instruction buffer from memory if necessary, but do not
2440 read memory beyond PC to be sure we stay within text section
2441 (this protection only works if a non-zero pc is supplied). */
2443 if (ia + xtensa_isa_maxlength (isa) > bt)
2446 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2447 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2448 error (_("Unable to read target memory ..."));
2451 /* Decode format information. */
2453 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2454 ifmt = xtensa_format_decode (isa, ins);
2455 if (ifmt == XTENSA_UNDEFINED)
2460 ilen = xtensa_format_length (isa, ifmt);
2461 if (ilen == XTENSA_UNDEFINED)
2466 islots = xtensa_format_num_slots (isa, ifmt);
2467 if (islots == XTENSA_UNDEFINED)
2473 /* Analyze a bundle or a single instruction, using a snapshot of
2474 the register tracking info as input for the entire bundle so that
2475 register changes do not take effect within this bundle. */
2477 for (j = 0; j < nregs; ++j)
2478 rtmp[j] = cache->c0.c0_rt[j];
2480 for (is = 0; is < islots; ++is)
2482 /* Decode a slot and classify the opcode. */
2484 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2488 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2489 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2491 if (opc == XTENSA_UNDEFINED)
2492 opclass = c0opc_illegal;
2494 opclass = call0_classify_opcode (isa, opc);
2496 /* Decide whether to track this opcode, ignore it, or bail out. */
2505 case c0opc_uninteresting:
2508 case c0opc_flow: /* Flow control instructions stop analysis. */
2509 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2514 ia += ilen; /* Skip over 'entry' insn. */
2521 /* Only expected opcodes should get this far. */
2523 /* Extract and decode the operands. */
2524 nods = xtensa_opcode_num_operands (isa, opc);
2525 if (nods == XTENSA_UNDEFINED)
2531 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2533 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2538 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2543 /* Check operands to verify use of 'mov' assembler macro. */
2544 if (opclass == c0opc_mov && nods == 3)
2546 if (odv[2] == odv[1])
2549 if ((odv[0] == 1) && (odv[1] != 1))
2550 /* OR A1, An, An , where n != 1.
2551 This means we are inside epilogue already. */
2556 opclass = c0opc_uninteresting;
2561 /* Track register movement and modification for this operation. */
2562 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2563 opclass, nods, odv, ia, 1, cache);
2569 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2570 (unsigned)ia, fail ? "failed" : "succeeded");
2571 xtensa_insnbuf_free(isa, slot);
2572 xtensa_insnbuf_free(isa, ins);
2573 return fail ? XTENSA_ISA_BADPC : ia;
2576 /* Initialize frame cache for the current frame in CALL0 ABI. */
2579 call0_frame_cache (struct frame_info *this_frame,
2580 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2582 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2583 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2584 CORE_ADDR start_pc; /* The beginning of the function. */
2585 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2586 CORE_ADDR sp, fp, ra;
2587 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2589 sp = get_frame_register_unsigned
2590 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2591 fp = sp; /* Assume FP == SP until proven otherwise. */
2593 /* Find the beginning of the prologue of the function containing the PC
2594 and analyze it up to the PC or the end of the prologue. */
2596 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2598 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2600 if (body_pc == XTENSA_ISA_BADPC)
2604 goto finish_frame_analysis;
2608 /* Get the frame information and FP (if used) at the current PC.
2609 If PC is in the prologue, the prologue analysis is more reliable
2610 than DWARF info. We don't not know for sure, if PC is in the prologue,
2611 but we do know no calls have yet taken place, so we can almost
2612 certainly rely on the prologue analysis. */
2616 /* Prologue analysis was successful up to the PC.
2617 It includes the cases when PC == START_PC. */
2618 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2619 /* c0_hasfp == true means there is a frame pointer because
2620 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2621 was derived from SP. Otherwise, it would be C0_FP. */
2622 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2623 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2624 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2626 else /* No data from the prologue analysis. */
2629 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2634 if (cache->c0.c0_fpalign)
2636 /* This frame has a special prologue with a dynamic stack adjustment
2637 to force an alignment, which is bigger than standard 16 bytes. */
2639 CORE_ADDR unaligned_sp;
2641 if (cache->c0.c0_old_sp == C0_INEXP)
2642 /* This can't be. Prologue code should be consistent.
2643 Unaligned stack pointer should be saved in a spare register. */
2647 goto finish_frame_analysis;
2650 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2651 /* Saved unaligned value of SP is kept in a register. */
2652 unaligned_sp = get_frame_register_unsigned
2653 (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
2655 /* Get the value from stack. */
2656 unaligned_sp = (CORE_ADDR)
2657 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2659 prev_sp = unaligned_sp + c0_frmsz;
2662 prev_sp = fp + c0_frmsz;
2664 /* Frame size from debug info or prologue tracking does not account for
2665 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2668 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2670 /* Update the stack frame size. */
2671 c0_frmsz += fp - sp;
2674 /* Get the return address (RA) from the stack if saved,
2675 or try to get it from a register. */
2677 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2678 if (to_stk != C0_NOSTK)
2680 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2683 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2684 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2686 /* Special case for terminating backtrace at a function that wants to
2687 be seen as the outermost one. Such a function will clear it's RA (A0)
2688 register to 0 in the prologue instead of saving its original value. */
2693 /* RA was copied to another register or (before any function call) may
2694 still be in the original RA register. This is not always reliable:
2695 even in a leaf function, register tracking stops after prologue, and
2696 even in prologue, non-prologue instructions (not tracked) may overwrite
2697 RA or any register it was copied to. If likely in prologue or before
2698 any call, use retracking info and hope for the best (compiler should
2699 have saved RA in stack if not in a leaf function). If not in prologue,
2705 && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2707 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2711 ra = get_frame_register_unsigned
2713 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2718 finish_frame_analysis:
2719 cache->pc = start_pc;
2721 /* RA == 0 marks the outermost frame. Do not go past it. */
2722 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2723 cache->c0.fp_regnum = fp_regnum;
2724 cache->c0.c0_frmsz = c0_frmsz;
2725 cache->c0.c0_hasfp = c0_hasfp;
2726 cache->c0.c0_fp = fp;
2729 static CORE_ADDR a0_saved;
2730 static CORE_ADDR a7_saved;
2731 static CORE_ADDR a11_saved;
2732 static int a0_was_saved;
2733 static int a7_was_saved;
2734 static int a11_was_saved;
2736 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2738 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2740 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2741 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2742 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2743 unsigned int spilled_value
2744 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2746 if ((at == 0) && !a0_was_saved)
2748 a0_saved = xtensa_read_register (atreg);
2751 else if ((at == 7) && !a7_was_saved)
2753 a7_saved = xtensa_read_register (atreg);
2756 else if ((at == 11) && !a11_was_saved)
2758 a11_saved = xtensa_read_register (atreg);
2762 xtensa_write_register (atreg, spilled_value);
2765 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2767 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2769 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2770 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2771 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2772 ULONGEST spilled_value = xtensa_read_register (atreg);
2774 write_memory_unsigned_integer (addr, 4,
2775 gdbarch_byte_order (gdbarch),
2779 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2785 xtNoExceptionHandler
2786 } xtensa_exception_handler_t;
2788 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2789 Return type of Xtensa Window Interrupt Handler on success. */
2790 static xtensa_exception_handler_t
2791 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2794 xtensa_insnbuf ins, slot;
2795 gdb_byte ibuf[XTENSA_ISA_BSZ];
2796 CORE_ADDR ia, bt, ba;
2798 int ilen, islots, is;
2802 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2804 uint32_t at, as, offset;
2806 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2807 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2809 isa = xtensa_default_isa;
2810 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2811 ins = xtensa_insnbuf_alloc (isa);
2812 slot = xtensa_insnbuf_alloc (isa);
2821 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2823 if (ia + xtensa_isa_maxlength (isa) > bt)
2826 bt = (ba + XTENSA_ISA_BSZ);
2827 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2828 return xtNoExceptionHandler;
2830 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2831 ifmt = xtensa_format_decode (isa, ins);
2832 if (ifmt == XTENSA_UNDEFINED)
2833 return xtNoExceptionHandler;
2834 ilen = xtensa_format_length (isa, ifmt);
2835 if (ilen == XTENSA_UNDEFINED)
2836 return xtNoExceptionHandler;
2837 islots = xtensa_format_num_slots (isa, ifmt);
2838 if (islots == XTENSA_UNDEFINED)
2839 return xtNoExceptionHandler;
2840 for (is = 0; is < islots; ++is)
2842 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2843 return xtNoExceptionHandler;
2844 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2845 if (opc == XTENSA_UNDEFINED)
2846 return xtNoExceptionHandler;
2847 switch (call0_classify_opcode (isa, opc))
2853 /* We expect none of them here. */
2854 return xtNoExceptionHandler;
2856 func = execute_l32e;
2859 func = execute_s32e;
2861 case c0opc_rfwo: /* RFWO. */
2862 /* Here, we return from WindowOverflow handler and,
2863 if we stopped at the very beginning, which means
2864 A0 was saved, we have to restore it now. */
2867 int arreg = arreg_number (gdbarch,
2868 gdbarch_tdep (gdbarch)->a0_base,
2870 xtensa_write_register (arreg, a0_saved);
2872 return xtWindowOverflow;
2873 case c0opc_rfwu: /* RFWU. */
2874 /* Here, we return from WindowUnderflow handler.
2875 Let's see if either A7 or A11 has to be restored. */
2876 if (WindowUnderflow12)
2880 int arreg = arreg_number (gdbarch,
2881 gdbarch_tdep (gdbarch)->a0_base + 11,
2883 xtensa_write_register (arreg, a11_saved);
2886 else if (a7_was_saved)
2888 int arreg = arreg_number (gdbarch,
2889 gdbarch_tdep (gdbarch)->a0_base + 7,
2891 xtensa_write_register (arreg, a7_saved);
2893 return xtWindowUnderflow;
2894 default: /* Simply skip this insns. */
2898 /* Decode arguments for L32E / S32E and simulate their execution. */
2899 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2900 return xtNoExceptionHandler;
2901 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2902 return xtNoExceptionHandler;
2903 if (xtensa_operand_decode (isa, opc, 0, &at))
2904 return xtNoExceptionHandler;
2905 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2906 return xtNoExceptionHandler;
2907 if (xtensa_operand_decode (isa, opc, 1, &as))
2908 return xtNoExceptionHandler;
2909 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2910 return xtNoExceptionHandler;
2911 if (xtensa_operand_decode (isa, opc, 2, &offset))
2912 return xtNoExceptionHandler;
2914 (*func) (gdbarch, at, as, offset, wb);
2919 return xtNoExceptionHandler;
2922 /* Handle Window Overflow / Underflow exception frames. */
2925 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2926 xtensa_frame_cache_t *cache,
2929 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2930 CORE_ADDR ps, wb, ws, ra;
2931 int epc1_regnum, i, regnum;
2932 xtensa_exception_handler_t eh_type;
2934 /* Read PS, WB, and WS from the hardware. Note that PS register
2935 must be present, if Windowed ABI is supported. */
2936 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2937 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2938 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2940 /* Execute all the remaining instructions from Window Interrupt Handler
2941 by simulating them on the remote protocol level. On return, set the
2942 type of Xtensa Window Interrupt Handler, or report an error. */
2943 eh_type = execute_code (gdbarch, pc, wb);
2944 if (eh_type == xtNoExceptionHandler)
2946 Unable to decode Xtensa Window Interrupt Handler's code."));
2948 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2949 cache->call0 = 0; /* It's Windowed ABI. */
2951 /* All registers for the cached frame will be alive. */
2952 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2953 cache->wd.aregs[i] = -1;
2955 if (eh_type == xtWindowOverflow)
2956 cache->wd.ws = ws ^ (1 << wb);
2957 else /* eh_type == xtWindowUnderflow. */
2958 cache->wd.ws = ws | (1 << wb);
2960 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2961 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2963 ra = xtensa_read_register (regnum);
2964 cache->wd.callsize = WINSIZE (ra);
2965 cache->prev_sp = xtensa_read_register (regnum + 1);
2966 /* Set regnum to a frame pointer of the frame being cached. */
2967 regnum = xtensa_scan_prologue (gdbarch, pc);
2968 regnum = arreg_number (gdbarch,
2969 gdbarch_tdep (gdbarch)->a0_base + regnum,
2971 cache->base = get_frame_register_unsigned (this_frame, regnum);
2973 /* Read PC of interrupted function from EPC1 register. */
2974 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2975 if (epc1_regnum < 0)
2976 error(_("Unable to read Xtensa register EPC1"));
2977 cache->ra = xtensa_read_register (epc1_regnum);
2978 cache->pc = get_frame_func (this_frame);
2982 /* Skip function prologue.
2984 Return the pc of the first instruction after prologue. GDB calls this to
2985 find the address of the first line of the function or (if there is no line
2986 number information) to skip the prologue for planting breakpoints on
2987 function entries. Use debug info (if present) or prologue analysis to skip
2988 the prologue to achieve reliable debugging behavior. For windowed ABI,
2989 only the 'entry' instruction is skipped. It is not strictly necessary to
2990 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2991 backtrace at any point in the prologue, however certain potential hazards
2992 are avoided and a more "normal" debugging experience is ensured by
2993 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2994 For example, if we don't skip the prologue:
2995 - Some args may not yet have been saved to the stack where the debug
2996 info expects to find them (true anyway when only 'entry' is skipped);
2997 - Software breakpoints ('break' instrs) may not have been unplanted
2998 when the prologue analysis is done on initializing the frame cache,
2999 and breaks in the prologue will throw off the analysis.
3001 If we have debug info ( line-number info, in particular ) we simply skip
3002 the code associated with the first function line effectively skipping
3003 the prologue code. It works even in cases like
3006 { int local_var = 1;
3010 because, for this source code, both Xtensa compilers will generate two
3011 separate entries ( with the same line number ) in dwarf line-number
3012 section to make sure there is a boundary between the prologue code and
3013 the rest of the function.
3015 If there is no debug info, we need to analyze the code. */
3017 /* #define DONT_SKIP_PROLOGUE */
3020 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
3022 struct symtab_and_line prologue_sal;
3025 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3027 #if DONT_SKIP_PROLOGUE
3031 /* Try to find first body line from debug info. */
3033 prologue_sal = find_pc_line (start_pc, 0);
3034 if (prologue_sal.line != 0) /* Found debug info. */
3036 /* In Call0, it is possible to have a function with only one instruction
3037 ('ret') resulting from a one-line optimized function that does nothing.
3038 In that case, prologue_sal.end may actually point to the start of the
3039 next function in the text section, causing a breakpoint to be set at
3040 the wrong place. Check, if the end address is within a different
3041 function, and if so return the start PC. We know we have symbol
3046 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
3047 && call0_ret (start_pc, prologue_sal.end))
3050 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3051 if (end_func != start_pc)
3054 return prologue_sal.end;
3057 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3058 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3059 xtensa_alloc_frame_cache (0));
3060 return body_pc != 0 ? body_pc : start_pc;
3063 /* Verify the current configuration. */
3065 xtensa_verify_config (struct gdbarch *gdbarch)
3067 struct ui_file *log;
3068 struct cleanup *cleanups;
3069 struct gdbarch_tdep *tdep;
3073 tdep = gdbarch_tdep (gdbarch);
3074 log = mem_fileopen ();
3075 cleanups = make_cleanup_ui_file_delete (log);
3077 /* Verify that we got a reasonable number of AREGS. */
3078 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3079 fprintf_unfiltered (log, _("\
3080 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3083 /* Verify that certain registers exist. */
3085 if (tdep->pc_regnum == -1)
3086 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
3087 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3088 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
3090 if (tdep->isa_use_windowed_registers)
3092 if (tdep->wb_regnum == -1)
3093 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
3094 if (tdep->ws_regnum == -1)
3095 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
3096 if (tdep->ar_base == -1)
3097 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
3100 if (tdep->a0_base == -1)
3101 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
3103 buf = ui_file_xstrdup (log, &length);
3104 make_cleanup (xfree, buf);
3106 internal_error (__FILE__, __LINE__,
3107 _("the following are invalid: %s"), buf);
3108 do_cleanups (cleanups);
3112 /* Derive specific register numbers from the array of registers. */
3115 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
3117 xtensa_register_t* rmap;
3118 int n, max_size = 4;
3121 tdep->num_nopriv_regs = 0;
3123 /* Special registers 0..255 (core). */
3124 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3126 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3128 if (rmap->target_number == 0x0020)
3129 tdep->pc_regnum = n;
3130 else if (rmap->target_number == 0x0100)
3132 else if (rmap->target_number == 0x0000)
3134 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3135 tdep->wb_regnum = n;
3136 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3137 tdep->ws_regnum = n;
3138 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3139 tdep->debugcause_regnum = n;
3140 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3141 tdep->exccause_regnum = n;
3142 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3143 tdep->excvaddr_regnum = n;
3144 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3145 tdep->lbeg_regnum = n;
3146 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3147 tdep->lend_regnum = n;
3148 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3149 tdep->lcount_regnum = n;
3150 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3151 tdep->sar_regnum = n;
3152 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3153 tdep->litbase_regnum = n;
3154 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3155 tdep->ps_regnum = n;
3157 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3158 tdep->interrupt_regnum = n;
3159 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3160 tdep->interrupt2_regnum = n;
3161 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3162 tdep->cpenable_regnum = n;
3165 if (rmap->byte_size > max_size)
3166 max_size = rmap->byte_size;
3167 if (rmap->mask != 0 && tdep->num_regs == 0)
3169 /* Find out out how to deal with priveleged registers.
3171 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3172 && tdep->num_nopriv_regs == 0)
3173 tdep->num_nopriv_regs = n;
3175 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3176 && tdep->num_regs == 0)
3180 /* Number of pseudo registers. */
3181 tdep->num_pseudo_regs = n - tdep->num_regs;
3183 /* Empirically determined maximum sizes. */
3184 tdep->max_register_raw_size = max_size;
3185 tdep->max_register_virtual_size = max_size;
3188 /* Module "constructor" function. */
3190 extern struct gdbarch_tdep xtensa_tdep;
3192 static struct gdbarch *
3193 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3195 struct gdbarch_tdep *tdep;
3196 struct gdbarch *gdbarch;
3197 struct xtensa_abi_handler *abi_handler;
3199 DEBUGTRACE ("gdbarch_init()\n");
3201 /* We have to set the byte order before we call gdbarch_alloc. */
3202 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3204 tdep = &xtensa_tdep;
3205 gdbarch = gdbarch_alloc (&info, tdep);
3206 xtensa_derive_tdep (tdep);
3208 /* Verify our configuration. */
3209 xtensa_verify_config (gdbarch);
3210 xtensa_session_once_reported = 0;
3212 /* Pseudo-Register read/write. */
3213 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3214 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3216 /* Set target information. */
3217 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3218 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3219 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3220 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3221 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3223 /* Renumber registers for known formats (stabs and dwarf2). */
3224 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3225 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3227 /* We provide our own function to get register information. */
3228 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3229 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3231 /* To call functions from GDB using dummy frame. */
3232 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3234 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3236 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3238 /* Advance PC across any prologue instructions to reach "real" code. */
3239 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3241 /* Stack grows downward. */
3242 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3244 /* Set breakpoints. */
3245 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
3247 /* After breakpoint instruction or illegal instruction, pc still
3248 points at break instruction, so don't decrement. */
3249 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3251 /* We don't skip args. */
3252 set_gdbarch_frame_args_skip (gdbarch, 0);
3254 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3256 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3258 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3260 /* Frame handling. */
3261 frame_base_set_default (gdbarch, &xtensa_frame_base);
3262 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3263 dwarf2_append_unwinders (gdbarch);
3265 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3267 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3269 xtensa_add_reggroups (gdbarch);
3270 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3272 set_gdbarch_iterate_over_regset_sections
3273 (gdbarch, xtensa_iterate_over_regset_sections);
3275 set_solib_svr4_fetch_link_map_offsets
3276 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3278 /* Hook in the ABI-specific overrides, if they have been registered. */
3279 gdbarch_init_osabi (info, gdbarch);
3285 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3287 error (_("xtensa_dump_tdep(): not implemented"));
3290 /* Provide a prototype to silence -Wmissing-prototypes. */
3291 extern initialize_file_ftype _initialize_xtensa_tdep;
3294 _initialize_xtensa_tdep (void)
3296 struct cmd_list_element *c;
3298 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3299 xtensa_init_reggroups ();
3301 add_setshow_zuinteger_cmd ("xtensa",
3303 &xtensa_debug_level,
3304 _("Set Xtensa debugging."),
3305 _("Show Xtensa debugging."), _("\
3306 When non-zero, Xtensa-specific debugging is enabled. \
3307 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3310 &setdebuglist, &showdebuglist);