1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "floatformat.h"
32 #include "reggroups.h"
35 #include "dummy-frame.h"
36 #include "elf/dwarf2.h"
37 #include "dwarf2-frame.h"
38 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
50 #include "gdb_assert.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
56 static int xtensa_debug_level = 0;
58 #define DEBUGWARN(args...) \
59 if (xtensa_debug_level > 0) \
60 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
62 #define DEBUGINFO(args...) \
63 if (xtensa_debug_level > 1) \
64 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
66 #define DEBUGTRACE(args...) \
67 if (xtensa_debug_level > 2) \
68 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
70 #define DEBUGVERB(args...) \
71 if (xtensa_debug_level > 3) \
72 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
75 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
76 #define SP_ALIGNMENT 16
79 /* On Windowed ABI, we use a6 through a11 for passing arguments
80 to a function called by GDB because CALL4 is used. */
81 #define ARGS_FIRST_REG gdbarch_tdep (current_gdbarch)->a0_base + 6
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
93 /* Convert a live Ax register number to the corresponding Areg number. */
94 #define AREG_NUMBER(r, wb) \
95 ((((r) - (gdbarch_tdep (current_gdbarch)->a0_base + 0) + (((wb) \
96 & ((gdbarch_tdep (current_gdbarch)->num_aregs - 1) >> 2)) << WB_SHIFT)) & \
97 (gdbarch_tdep (current_gdbarch)->num_aregs - 1)) \
98 + gdbarch_tdep (current_gdbarch)->ar_base)
100 /* ABI-independent macros. */
101 #define ARG_NOF (gdbarch_tdep (current_gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST (gdbarch_tdep (current_gdbarch)->call_abi \
104 == CallAbiCall0Only \
105 ? (gdbarch_tdep (current_gdbarch)->a0_base + 0) + C0_ARGS \
108 extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *);
109 extern int xtensa_config_byte_order (struct gdbarch_info *);
112 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
113 indicates that the instruction is an ENTRY instruction. */
115 #define XTENSA_IS_ENTRY(op1) \
116 ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \
117 ? ((op1) == 0x6c) : ((op1) == 0x36))
119 #define XTENSA_ENTRY_LENGTH 3
121 /* windowing_enabled() returns true, if windowing is enabled.
122 WOE must be set to 1; EXCM to 0.
123 Note: We assume that EXCM is always 0 for XEA1. */
125 #define PS_WOE (1<<18)
126 #define PS_EXC (1<<4)
129 windowing_enabled (CORE_ADDR ps)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Return the window size of the previous call to the function from which we
137 This function is used to extract the return value after a called function
138 has returned to the caller. On Xtensa, the register that holds the return
139 value (from the perspective of the caller) depends on what call
140 instruction was used. For now, we are assuming that the call instruction
141 precedes the current address, so we simply analyze the call instruction.
142 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
143 method to call the inferior function. */
146 extract_call_winsize (CORE_ADDR pc)
152 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
154 /* Read the previous instruction (should be a call[x]{4|8|12}. */
155 read_memory (pc-3, buf, 3);
156 insn = extract_unsigned_integer (buf, 3);
158 /* Decode call instruction:
160 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
161 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
163 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
164 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
166 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
168 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
169 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
173 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
174 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
180 /* REGISTER INFORMATION */
182 /* Returns the name of a register. */
184 xtensa_register_name (int regnum)
186 /* Return the name stored in the register map. */
187 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
188 + gdbarch_num_pseudo_regs (current_gdbarch))
189 return gdbarch_tdep (current_gdbarch)->regmap[regnum].name;
191 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
196 xtensa_read_register (int regnum)
200 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
201 return (unsigned long) value;
204 /* Return the type of a register. Create a new type, if necessary. */
206 static struct ctype_cache
208 struct ctype_cache *next;
210 struct type *virtual_type;
211 } *type_entries = NULL;
214 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
216 /* Return signed integer for ARx and Ax registers. */
217 if ((regnum >= gdbarch_tdep (gdbarch)->ar_base
218 && regnum < gdbarch_tdep (gdbarch)->ar_base
219 + gdbarch_tdep (gdbarch)->num_aregs)
220 || (regnum >= gdbarch_tdep (gdbarch)->a0_base
221 && regnum < gdbarch_tdep (gdbarch)->a0_base + 16))
222 return builtin_type_int;
224 if (regnum == gdbarch_pc_regnum (gdbarch)
225 || regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
226 return lookup_pointer_type (builtin_type_void);
228 /* Return the stored type for all other registers. */
229 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
230 + gdbarch_num_pseudo_regs (gdbarch))
232 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
234 /* Set ctype for this register (only the first time). */
238 struct ctype_cache *tp;
239 int size = reg->byte_size;
241 /* We always use the memory representation,
242 even if the register width is smaller. */
246 reg->ctype = builtin_type_uint8;
250 reg->ctype = builtin_type_uint16;
254 reg->ctype = builtin_type_uint32;
258 reg->ctype = builtin_type_uint64;
262 reg->ctype = builtin_type_uint128;
266 for (tp = type_entries; tp != NULL; tp = tp->next)
267 if (tp->size == size)
272 char *name = xmalloc (16);
273 tp = xmalloc (sizeof (struct ctype_cache));
274 tp->next = type_entries;
278 sprintf (name, "int%d", size * 8);
279 tp->virtual_type = init_type (TYPE_CODE_INT, size,
280 TYPE_FLAG_UNSIGNED, name,
284 reg->ctype = tp->virtual_type;
290 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
295 /* Return the 'local' register number for stubs, dwarf2, etc.
296 The debugging information enumerates registers starting from 0 for A0
297 to n for An. So, we only have to add the base number for A0. */
300 xtensa_reg_to_regnum (int regnum)
304 if (regnum >= 0 && regnum < 16)
305 return gdbarch_tdep (current_gdbarch)->a0_base + regnum;
308 i < gdbarch_num_regs (current_gdbarch)
309 + gdbarch_num_pseudo_regs (current_gdbarch);
311 if (regnum == gdbarch_tdep (current_gdbarch)->regmap[i].target_number)
314 internal_error (__FILE__, __LINE__,
315 _("invalid dwarf/stabs register number %d"), regnum);
320 /* Write the bits of a masked register to the various registers.
321 Only the masked areas of these registers are modified; the other
322 fields are untouched. The size of masked registers is always less
323 than or equal to 32 bits. */
326 xtensa_register_write_masked (struct regcache *regcache,
327 xtensa_register_t *reg, const gdb_byte *buffer)
329 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
330 const xtensa_mask_t *mask = reg->mask;
332 int shift = 0; /* Shift for next mask (mod 32). */
333 int start, size; /* Start bit and size of current mask. */
335 unsigned int *ptr = value;
336 unsigned int regval, m, mem = 0;
338 int bytesize = reg->byte_size;
339 int bitsize = bytesize * 8;
342 DEBUGTRACE ("xtensa_register_write_masked ()\n");
344 /* Copy the masked register to host byte-order. */
345 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
346 for (i = 0; i < bytesize; i++)
349 mem |= (buffer[bytesize - i - 1] << 24);
354 for (i = 0; i < bytesize; i++)
357 mem |= (buffer[i] << 24);
362 /* We might have to shift the final value:
363 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
364 bytesize & 3 == x -> shift (4-x) * 8. */
366 *ptr = mem >> (((0 - bytesize) & 3) * 8);
370 /* Write the bits to the masked areas of the other registers. */
371 for (i = 0; i < mask->count; i++)
373 start = mask->mask[i].bit_start;
374 size = mask->mask[i].bit_size;
375 regval = mem >> shift;
377 if ((shift += size) > bitsize)
378 error (_("size of all masks is larger than the register"));
387 regval |= mem << (size - shift);
390 /* Make sure we have a valid register. */
391 r = mask->mask[i].reg_num;
392 if (r >= 0 && size > 0)
394 /* Don't overwrite the unmasked areas. */
396 regcache_cooked_read_unsigned (regcache, r, &old_val);
397 m = 0xffffffff >> (32 - size) << start;
399 regval = (regval & m) | (old_val & ~m);
400 regcache_cooked_write_unsigned (regcache, r, regval);
406 /* Read a tie state or mapped registers. Read the masked areas
407 of the registers and assemble them into a single value. */
410 xtensa_register_read_masked (struct regcache *regcache,
411 xtensa_register_t *reg, gdb_byte *buffer)
413 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
414 const xtensa_mask_t *mask = reg->mask;
419 unsigned int *ptr = value;
420 unsigned int regval, mem = 0;
422 int bytesize = reg->byte_size;
423 int bitsize = bytesize * 8;
426 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
427 reg->name == 0 ? "" : reg->name);
429 /* Assemble the register from the masked areas of other registers. */
430 for (i = 0; i < mask->count; i++)
432 int r = mask->mask[i].reg_num;
436 regcache_cooked_read_unsigned (regcache, r, &val);
437 regval = (unsigned int) val;
442 start = mask->mask[i].bit_start;
443 size = mask->mask[i].bit_size;
448 regval &= (0xffffffff >> (32 - size));
450 mem |= regval << shift;
452 if ((shift += size) > bitsize)
453 error (_("size of all masks is larger than the register"));
464 mem = regval >> (size - shift);
471 /* Copy value to target byte order. */
475 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
476 for (i = 0; i < bytesize; i++)
480 buffer[bytesize - i - 1] = mem & 0xff;
484 for (i = 0; i < bytesize; i++)
488 buffer[i] = mem & 0xff;
494 /* Read pseudo registers. */
497 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
498 struct regcache *regcache,
502 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
503 regnum, xtensa_register_name (regnum));
505 if (regnum == gdbarch_num_regs (gdbarch)
506 + gdbarch_num_pseudo_regs (gdbarch))
507 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
509 /* Read aliases a0..a15, if this is a Windowed ABI. */
510 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
511 && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0)
512 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
514 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
516 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
517 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
520 /* We can always read non-pseudo registers. */
521 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
522 regcache_raw_read (regcache, regnum, buffer);
524 /* Pseudo registers. */
526 && regnum < gdbarch_num_regs (gdbarch)
527 + gdbarch_num_pseudo_regs (gdbarch))
529 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
530 xtensa_register_type_t type = reg->type;
531 int flags = gdbarch_tdep (gdbarch)->target_flags;
533 /* We cannot read Unknown or Unmapped registers. */
534 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
536 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
538 warning (_("cannot read register %s"),
539 xtensa_register_name (regnum));
544 /* Some targets cannot read TIE register files. */
545 else if (type == xtRegisterTypeTieRegfile)
547 /* Use 'fetch' to get register? */
548 if (flags & xtTargetFlagsUseFetchStore)
550 warning (_("cannot read register"));
554 /* On some targets (esp. simulators), we can always read the reg. */
555 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
557 warning (_("cannot read register"));
562 /* We can always read mapped registers. */
563 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
565 xtensa_register_read_masked (regcache, reg, buffer);
569 /* Assume that we can read the register. */
570 regcache_raw_read (regcache, regnum, buffer);
573 internal_error (__FILE__, __LINE__,
574 _("invalid register number %d"), regnum);
578 /* Write pseudo registers. */
581 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
582 struct regcache *regcache,
584 const gdb_byte *buffer)
586 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
587 regnum, xtensa_register_name (regnum));
589 if (regnum == gdbarch_num_regs (gdbarch)
590 + gdbarch_num_pseudo_regs (gdbarch))
591 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
593 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
594 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
595 && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0)
596 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
598 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
601 regcache_raw_read (regcache,
602 gdbarch_tdep (gdbarch)->wb_regnum, buf);
603 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
606 /* We can always write 'core' registers.
607 Note: We might have converted Ax->ARy. */
608 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
609 regcache_raw_write (regcache, regnum, buffer);
611 /* Pseudo registers. */
613 && regnum < gdbarch_num_regs (gdbarch)
614 + gdbarch_num_pseudo_regs (gdbarch))
616 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
617 xtensa_register_type_t type = reg->type;
618 int flags = gdbarch_tdep (gdbarch)->target_flags;
620 /* On most targets, we cannot write registers
621 of type "Unknown" or "Unmapped". */
622 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
624 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
626 warning (_("cannot write register %s"),
627 xtensa_register_name (regnum));
632 /* Some targets cannot read TIE register files. */
633 else if (type == xtRegisterTypeTieRegfile)
635 /* Use 'store' to get register? */
636 if (flags & xtTargetFlagsUseFetchStore)
638 warning (_("cannot write register"));
642 /* On some targets (esp. simulators), we can always write
644 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
646 warning (_("cannot write register"));
651 /* We can always write mapped registers. */
652 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
654 xtensa_register_write_masked (regcache, reg, buffer);
658 /* Assume that we can write the register. */
659 regcache_raw_write (regcache, regnum, buffer);
662 internal_error (__FILE__, __LINE__,
663 _("invalid register number %d"), regnum);
666 static struct reggroup *xtensa_ar_reggroup;
667 static struct reggroup *xtensa_user_reggroup;
668 static struct reggroup *xtensa_vectra_reggroup;
669 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
672 xtensa_init_reggroups (void)
674 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
675 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
676 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
678 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
679 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
680 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
681 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
682 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
683 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
684 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
685 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
689 xtensa_add_reggroups (struct gdbarch *gdbarch)
693 /* Predefined groups. */
694 reggroup_add (gdbarch, all_reggroup);
695 reggroup_add (gdbarch, save_reggroup);
696 reggroup_add (gdbarch, restore_reggroup);
697 reggroup_add (gdbarch, system_reggroup);
698 reggroup_add (gdbarch, vector_reggroup);
699 reggroup_add (gdbarch, general_reggroup);
700 reggroup_add (gdbarch, float_reggroup);
702 /* Xtensa-specific groups. */
703 reggroup_add (gdbarch, xtensa_ar_reggroup);
704 reggroup_add (gdbarch, xtensa_user_reggroup);
705 reggroup_add (gdbarch, xtensa_vectra_reggroup);
707 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
708 reggroup_add (gdbarch, xtensa_cp[i]);
712 xtensa_coprocessor_register_group (struct reggroup *group)
716 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
717 if (group == xtensa_cp[i])
723 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
724 | XTENSA_REGISTER_FLAGS_WRITABLE \
725 | XTENSA_REGISTER_FLAGS_VOLATILE)
727 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
728 | XTENSA_REGISTER_FLAGS_WRITABLE)
731 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
733 struct reggroup *group)
735 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
736 xtensa_register_type_t type = reg->type;
737 xtensa_register_group_t rg = reg->group;
740 /* First, skip registers that are not visible to this target
741 (unknown and unmapped registers when not using ISS). */
743 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
745 if (group == all_reggroup)
747 if (group == xtensa_ar_reggroup)
748 return rg & xtRegisterGroupAddrReg;
749 if (group == xtensa_user_reggroup)
750 return rg & xtRegisterGroupUser;
751 if (group == float_reggroup)
752 return rg & xtRegisterGroupFloat;
753 if (group == general_reggroup)
754 return rg & xtRegisterGroupGeneral;
755 if (group == float_reggroup)
756 return rg & xtRegisterGroupFloat;
757 if (group == system_reggroup)
758 return rg & xtRegisterGroupState;
759 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
760 return rg & xtRegisterGroupVectra;
761 if (group == save_reggroup || group == restore_reggroup)
762 return (regnum < gdbarch_num_regs (gdbarch)
763 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
764 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
765 return rg & (xtRegisterGroupCP0 << cp_number);
771 /* Supply register REGNUM from the buffer specified by GREGS and LEN
772 in the general-purpose register set REGSET to register cache
773 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
776 xtensa_supply_gregset (const struct regset *regset,
782 const xtensa_elf_gregset_t *regs = gregs;
783 struct gdbarch *gdbarch = get_regcache_arch (rc);
786 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
788 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
789 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
790 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
791 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
792 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
793 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
794 (char *) ®s->windowbase);
795 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
796 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
797 (char *) ®s->windowstart);
798 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
799 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
800 (char *) ®s->lbeg);
801 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
802 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
803 (char *) ®s->lend);
804 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
805 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
806 (char *) ®s->lcount);
807 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
808 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
809 (char *) ®s->sar);
810 if (regnum == gdbarch_tdep (gdbarch)->exccause_regnum || regnum == -1)
811 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->exccause_regnum,
812 (char *) ®s->exccause);
813 if (regnum == gdbarch_tdep (gdbarch)->excvaddr_regnum || regnum == -1)
814 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->excvaddr_regnum,
815 (char *) ®s->excvaddr);
816 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
817 && regnum < gdbarch_tdep (gdbarch)->ar_base
818 + gdbarch_tdep (gdbarch)->num_aregs)
819 regcache_raw_supply (rc, regnum,
820 (char *) ®s->ar[regnum - gdbarch_tdep
821 (gdbarch)->ar_base]);
822 else if (regnum == -1)
824 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
825 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
826 (char *) ®s->ar[i]);
831 /* Xtensa register set. */
837 xtensa_supply_gregset
841 /* Return the appropriate register set for the core
842 section identified by SECT_NAME and SECT_SIZE. */
844 static const struct regset *
845 xtensa_regset_from_core_section (struct gdbarch *core_arch,
846 const char *sect_name,
849 DEBUGTRACE ("xtensa_regset_from_core_section "
850 "(..., sect_name==\"%s\", sect_size==%x) \n",
851 sect_name, sect_size);
853 if (strcmp (sect_name, ".reg") == 0
854 && sect_size >= sizeof(xtensa_elf_gregset_t))
855 return &xtensa_gregset;
861 /* Handling frames. */
863 /* Number of registers to save in case of Windowed ABI. */
864 #define XTENSA_NUM_SAVED_AREGS 12
866 /* Frame cache part for Windowed ABI. */
867 typedef struct xtensa_windowed_frame_cache
869 int wb; /* Base for this frame; -1 if not in regfile. */
870 int callsize; /* Call size to next frame. */
872 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
873 } xtensa_windowed_frame_cache_t;
875 /* Call0 ABI Definitions. */
877 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
878 #define C0_NREGS 16 /* Number of A-registers to track. */
879 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
880 #define C0_SP 1 /* Register used as SP. */
881 #define C0_FP 15 /* Register used as FP. */
882 #define C0_RA 0 /* Register used as return address. */
883 #define C0_ARGS 2 /* Register used as first arg/retval. */
884 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
886 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
887 A-register where the current content of the reg came from (in terms
888 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
889 mean that the orignal content of the register was saved to the stack.
890 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
891 know where SP will end up until the entire prologue has been analyzed. */
893 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
894 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
895 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
897 extern xtensa_isa xtensa_default_isa;
899 typedef struct xtensa_c0reg
901 int fr_reg; /* original register from which register content
902 is derived, or C0_CONST, or C0_INEXP. */
903 int fr_ofs; /* constant offset from reg, or immediate value. */
904 int to_stk; /* offset from original SP to register (4-byte aligned),
905 or C0_NOSTK if register has not been saved. */
909 /* Frame cache part for Call0 ABI. */
910 typedef struct xtensa_call0_frame_cache
912 int c0_frmsz; /* Stack frame size. */
913 int c0_hasfp; /* Current frame uses frame pointer. */
914 int fp_regnum; /* A-register used as FP. */
915 int c0_fp; /* Actual value of frame pointer. */
916 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
917 } xtensa_call0_frame_cache_t;
919 typedef struct xtensa_frame_cache
921 CORE_ADDR base; /* Stack pointer of the next frame. */
922 CORE_ADDR pc; /* PC at the entry point to the function. */
923 CORE_ADDR ra; /* The raw return address. */
924 CORE_ADDR ps; /* The PS register of the frame. */
925 CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
926 int call0; /* It's a call0 framework (else windowed). */
929 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
930 xtensa_call0_frame_cache_t c0; /* call0 == true. */
932 } xtensa_frame_cache_t;
935 static struct xtensa_frame_cache *
936 xtensa_alloc_frame_cache (int windowed)
938 xtensa_frame_cache_t *cache;
941 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
943 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
950 cache->call0 = !windowed;
953 cache->c0.c0_frmsz = -1;
954 cache->c0.c0_hasfp = 0;
955 cache->c0.fp_regnum = -1;
956 cache->c0.c0_fp = -1;
958 for (i = 0; i < C0_NREGS; i++)
960 cache->c0.c0_rt[i].fr_reg = i;
961 cache->c0.c0_rt[i].fr_ofs = 0;
962 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
968 cache->wd.callsize = -1;
970 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
971 cache->wd.aregs[i] = -1;
978 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
980 return address & ~15;
985 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
989 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
991 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
993 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
994 extract_typed_address (buf, builtin_type_void_func_ptr));
996 return extract_typed_address (buf, builtin_type_void_func_ptr);
1000 static struct frame_id
1001 xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1005 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
1007 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
1009 pc = frame_pc_unwind (next_frame);
1010 fp = frame_unwind_register_unsigned
1011 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1013 /* Make dummy frame ID unique by adding a constant. */
1014 return frame_id_build (fp + SP_ALIGNMENT, pc);
1017 /* The key values to identify the frame using "cache" are
1019 cache->base = SP of this frame;
1020 cache->pc = entry-PC (entry point of the frame function);
1021 cache->prev_sp = SP of the previous frame.
1025 call0_frame_cache (struct frame_info *next_frame,
1026 xtensa_frame_cache_t *cache,
1029 static struct xtensa_frame_cache *
1030 xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
1032 xtensa_frame_cache_t *cache;
1033 CORE_ADDR ra, wb, ws, pc, sp, ps;
1034 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1035 unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch);
1039 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
1040 next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
1045 windowed = windowing_enabled (xtensa_read_register (ps_regnum));
1047 /* Get pristine xtensa-frame. */
1048 cache = xtensa_alloc_frame_cache (windowed);
1049 *this_cache = cache;
1051 pc = frame_unwind_register_unsigned (next_frame,
1052 gdbarch_pc_regnum (gdbarch));
1056 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1057 wb = frame_unwind_register_unsigned
1058 (next_frame, gdbarch_tdep (gdbarch)->wb_regnum);
1059 ws = frame_unwind_register_unsigned
1060 (next_frame, gdbarch_tdep (gdbarch)->ws_regnum);
1061 ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
1063 op1 = read_memory_integer (pc, 1);
1064 if (XTENSA_IS_ENTRY (op1))
1066 int callinc = CALLINC (ps);
1067 ra = frame_unwind_register_unsigned
1068 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0 + callinc * 4);
1070 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
1073 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1074 cache->wd.callsize = 0;
1077 cache->prev_sp = frame_unwind_register_unsigned
1078 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1082 ra = frame_unwind_register_unsigned
1083 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0);
1084 cache->wd.callsize = WINSIZE (ra);
1085 cache->wd.wb = (wb - cache->wd.callsize / 4)
1086 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1087 cache->wd.ws = ws & ~(1 << wb);
1090 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
1091 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1092 cache->ps = (ps & ~PS_CALLINC_MASK)
1093 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1095 if (cache->wd.ws == 0)
1100 sp = frame_unwind_register_unsigned
1101 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1103 for (i = 0; i < 4; i++, sp += 4)
1105 cache->wd.aregs[i] = sp;
1108 if (cache->wd.callsize > 4)
1110 /* Set A4...A7/A11. */
1111 /* Read an SP of the previous frame. */
1112 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1113 sp -= cache->wd.callsize * 4;
1115 for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
1117 cache->wd.aregs[i] = sp;
1122 if ((cache->prev_sp == 0) && ( ra != 0 ))
1123 /* If RA is equal to 0 this frame is an outermost frame. Leave
1124 cache->prev_sp unchanged marking the boundary of the frame stack. */
1126 if (cache->wd.ws == 0)
1128 /* Register window overflow already happened.
1129 We can read caller's SP from the proper spill loction. */
1131 read_memory_integer (cache->wd.aregs[1],
1132 register_size (gdbarch,
1133 gdbarch_tdep (gdbarch)->a0_base + 1));
1137 /* Read caller's frame SP directly from the previous window. */
1138 int regnum = AREG_NUMBER
1139 (gdbarch_tdep (gdbarch)->a0_base + 1,
1142 cache->prev_sp = xtensa_read_register (regnum);
1146 else /* Call0 framework. */
1148 call0_frame_cache (next_frame, cache, pc);
1151 cache->base = frame_unwind_register_unsigned
1152 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1158 xtensa_frame_this_id (struct frame_info *next_frame,
1160 struct frame_id *this_id)
1162 struct xtensa_frame_cache *cache =
1163 xtensa_frame_cache (next_frame, this_cache);
1166 DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n",
1167 (unsigned int) next_frame, (unsigned int) *this_cache);
1169 if (cache->prev_sp == 0)
1172 id = frame_id_build (cache->prev_sp, cache->pc);
1173 if (frame_id_eq (id, get_frame_id(next_frame)))
1176 Frame stack is corrupted. That could happen because of \
1177 setting register(s) from GDB or stopping execution \
1178 inside exception handler. Frame backtracing has stopped. \
1179 It can make some GDB commands work inappropriately.\n"));
1187 call0_frame_get_reg_at_entry (struct frame_info *next_frame,
1188 struct xtensa_frame_cache *cache,
1191 enum lval_type *lval,
1196 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1197 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1198 && regnum <= (gdbarch_tdep (gdbarch)->ar_base + C0_NREGS))
1199 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1201 /* Determine stack pointer on entry to this function, based on FP. */
1202 spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1204 /* If register was saved to the stack frame in the prologue, retrieve it. */
1205 stkofs = cache->c0.c0_rt[reg].to_stk;
1206 if (stkofs != C0_NOSTK)
1208 *lval = lval_memory;
1209 *addrp = spe + stkofs;
1212 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1217 /* If not callee-saved or if known to have been overwritten, give up. */
1219 || cache->c0.c0_rt[reg].fr_reg != reg
1220 || cache->c0.c0_rt[reg].fr_ofs != 0)
1223 if (get_frame_type (next_frame) != NORMAL_FRAME)
1224 /* TODO: Do we need a special case for DUMMY_FRAME here? */
1227 return call0_frame_get_reg_at_entry (get_next_frame(next_frame),
1228 cache, regnum, addrp, lval, valuep);
1232 xtensa_frame_prev_register (struct frame_info *next_frame,
1236 enum lval_type *lvalp,
1241 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1242 struct xtensa_frame_cache *cache =
1243 xtensa_frame_cache (next_frame, this_cache);
1244 CORE_ADDR saved_reg = 0;
1247 DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, "
1248 "*this 0x%08x, regnum %d (%s), ...)\n",
1249 (unsigned int) next_frame,
1250 *this_cache ? (unsigned int) *this_cache : 0, regnum,
1251 xtensa_register_name (regnum));
1253 if (regnum ==gdbarch_pc_regnum (gdbarch))
1254 saved_reg = cache->ra;
1255 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1256 saved_reg = cache->prev_sp;
1257 else if (!cache->call0)
1259 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1261 if (cache->wd.ws != 0)
1262 saved_reg = cache->wd.ws;
1264 saved_reg = 1 << cache->wd.wb;
1266 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1267 saved_reg = cache->wd.wb;
1268 else if (regnum == gdbarch_ps_regnum (gdbarch))
1269 saved_reg = cache->ps;
1283 store_unsigned_integer (valuep, 4, saved_reg);
1288 if (!cache->call0) /* Windowed ABI. */
1290 /* Convert A-register numbers to AR-register numbers. */
1291 if (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0
1292 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1293 regnum = AREG_NUMBER (regnum, cache->wd.wb);
1295 /* Check if AR-register has been saved to stack. */
1296 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1297 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1298 + gdbarch_tdep (gdbarch)->num_aregs))
1300 int areg = regnum - gdbarch_tdep (gdbarch)->ar_base
1301 - (cache->wd.wb * 4);
1304 && areg < XTENSA_NUM_SAVED_AREGS
1305 && cache->wd.aregs[areg] != -1)
1308 *lvalp = lval_memory;
1309 *addrp = cache->wd.aregs[areg];
1313 read_memory (*addrp, valuep,
1314 register_size (gdbarch, regnum));
1316 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1321 else /* Call0 ABI. */
1323 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1324 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1326 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1333 /* If register was saved in the prologue, retrieve it. */
1334 stkofs = cache->c0.c0_rt[reg].to_stk;
1335 if (stkofs != C0_NOSTK)
1337 /* Determine SP on entry based on FP. */
1338 spe = cache->c0.c0_fp
1339 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1341 *lvalp = lval_memory;
1342 *addrp = spe + stkofs;
1346 read_memory (*addrp, valuep,
1347 register_size (gdbarch, regnum));
1349 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1355 /* All other registers have been either saved to
1356 the stack or are still alive in the processor. */
1359 *lvalp = lval_register;
1363 frame_unwind_register (next_frame, (*realnump), valuep);
1367 static const struct frame_unwind
1368 xtensa_frame_unwind =
1371 xtensa_frame_this_id,
1372 xtensa_frame_prev_register
1375 static const struct frame_unwind *
1376 xtensa_frame_sniffer (struct frame_info *next_frame)
1378 return &xtensa_frame_unwind;
1382 xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache)
1384 struct xtensa_frame_cache *cache =
1385 xtensa_frame_cache (next_frame, this_cache);
1390 static const struct frame_base
1393 &xtensa_frame_unwind,
1394 xtensa_frame_base_address,
1395 xtensa_frame_base_address,
1396 xtensa_frame_base_address
1401 xtensa_extract_return_value (struct type *type,
1402 struct regcache *regcache,
1405 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1406 bfd_byte *valbuf = dst;
1407 int len = TYPE_LENGTH (type);
1412 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1414 gdb_assert(len > 0);
1416 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1418 /* First, we have to find the caller window in the register file. */
1419 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1420 callsize = extract_call_winsize (pc);
1422 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1423 if (len > (callsize > 8 ? 8 : 16))
1424 internal_error (__FILE__, __LINE__,
1425 _("cannot extract return value of %d bytes long"), len);
1427 /* Get the register offset of the return
1428 register (A2) in the caller window. */
1429 regcache_raw_read_unsigned
1430 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1431 areg = AREG_NUMBER(gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1435 /* No windowing hardware - Call0 ABI. */
1436 areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS;
1439 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1441 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1444 for (; len > 0; len -= 4, areg++, valbuf += 4)
1447 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1449 regcache_raw_read (regcache, areg, valbuf);
1455 xtensa_store_return_value (struct type *type,
1456 struct regcache *regcache,
1459 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1460 const bfd_byte *valbuf = dst;
1464 int len = TYPE_LENGTH (type);
1467 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1469 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1471 regcache_raw_read_unsigned
1472 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1473 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1474 callsize = extract_call_winsize (pc);
1476 if (len > (callsize > 8 ? 8 : 16))
1477 internal_error (__FILE__, __LINE__,
1478 _("unimplemented for this length: %d"),
1479 TYPE_LENGTH (type));
1480 areg = AREG_NUMBER (gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1482 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1483 callsize, (int) wb);
1487 areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS;
1490 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1493 for (; len > 0; len -= 4, areg++, valbuf += 4)
1496 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1498 regcache_raw_write (regcache, areg, valbuf);
1503 static enum return_value_convention
1504 xtensa_return_value (struct gdbarch *gdbarch,
1505 struct type *valtype,
1506 struct regcache *regcache,
1508 const gdb_byte *writebuf)
1510 /* Structures up to 16 bytes are returned in registers. */
1512 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1513 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1514 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1515 && TYPE_LENGTH (valtype) > 16);
1518 return RETURN_VALUE_STRUCT_CONVENTION;
1520 DEBUGTRACE ("xtensa_return_value(...)\n");
1522 if (writebuf != NULL)
1524 xtensa_store_return_value (valtype, regcache, writebuf);
1527 if (readbuf != NULL)
1529 gdb_assert (!struct_return);
1530 xtensa_extract_return_value (valtype, regcache, readbuf);
1532 return RETURN_VALUE_REGISTER_CONVENTION;
1539 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1540 struct value *function,
1541 struct regcache *regcache,
1544 struct value **args,
1547 CORE_ADDR struct_addr)
1550 int size, onstack_size;
1551 gdb_byte *buf = (gdb_byte *) alloca (16);
1553 struct argument_info
1555 const bfd_byte *contents;
1557 int onstack; /* onstack == 0 => in reg */
1558 int align; /* alignment */
1561 int offset; /* stack offset if on stack */
1562 int regno; /* regno if in register */
1566 struct argument_info *arg_info =
1567 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1571 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1573 if (xtensa_debug_level > 3)
1576 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1577 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1578 "struct_addr=0x%x\n",
1579 (int) sp, (int) struct_return, (int) struct_addr);
1581 for (i = 0; i < nargs; i++)
1583 struct value *arg = args[i];
1584 struct type *arg_type = check_typedef (value_type (arg));
1585 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%08x %3d ",
1586 i, (int) arg, TYPE_LENGTH (arg_type));
1587 switch (TYPE_CODE (arg_type))
1590 fprintf_unfiltered (gdb_stdlog, "int");
1592 case TYPE_CODE_STRUCT:
1593 fprintf_unfiltered (gdb_stdlog, "struct");
1596 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1599 fprintf_unfiltered (gdb_stdlog, " 0x%08x\n",
1600 (unsigned int) value_contents (arg));
1604 /* First loop: collect information.
1605 Cast into type_long. (This shouldn't happen often for C because
1606 GDB already does this earlier.) It's possible that GDB could
1607 do it all the time but it's harmless to leave this code here. */
1614 size = REGISTER_SIZE;
1616 for (i = 0; i < nargs; i++)
1618 struct argument_info *info = &arg_info[i];
1619 struct value *arg = args[i];
1620 struct type *arg_type = check_typedef (value_type (arg));
1622 switch (TYPE_CODE (arg_type))
1625 case TYPE_CODE_BOOL:
1626 case TYPE_CODE_CHAR:
1627 case TYPE_CODE_RANGE:
1628 case TYPE_CODE_ENUM:
1630 /* Cast argument to long if necessary as the mask does it too. */
1631 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1633 arg_type = builtin_type_long;
1634 arg = value_cast (arg_type, arg);
1636 /* Aligment is equal to the type length for the basic types. */
1637 info->align = TYPE_LENGTH (arg_type);
1642 /* Align doubles correctly. */
1643 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1644 info->align = TYPE_LENGTH (builtin_type_double);
1646 info->align = TYPE_LENGTH (builtin_type_long);
1649 case TYPE_CODE_STRUCT:
1651 info->align = TYPE_LENGTH (builtin_type_long);
1654 info->length = TYPE_LENGTH (arg_type);
1655 info->contents = value_contents (arg);
1657 /* Align size and onstack_size. */
1658 size = (size + info->align - 1) & ~(info->align - 1);
1659 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1661 if (size + info->length > REGISTER_SIZE * ARG_NOF)
1664 info->u.offset = onstack_size;
1665 onstack_size += info->length;
1670 info->u.regno = ARG_1ST + size / REGISTER_SIZE;
1672 size += info->length;
1675 /* Adjust the stack pointer and align it. */
1676 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1678 /* Simulate MOVSP, if Windowed ABI. */
1679 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1682 read_memory (osp - 16, buf, 16);
1683 write_memory (sp - 16, buf, 16);
1686 /* Second Loop: Load arguments. */
1690 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1691 regcache_cooked_write (regcache, ARG_1ST, buf);
1694 for (i = 0; i < nargs; i++)
1696 struct argument_info *info = &arg_info[i];
1700 int n = info->length;
1701 CORE_ADDR offset = sp + info->u.offset;
1703 /* Odd-sized structs are aligned to the lower side of a memory
1704 word in big-endian mode and require a shift. This only
1705 applies for structures smaller than one word. */
1707 if (n < REGISTER_SIZE
1708 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1709 offset += (REGISTER_SIZE - n);
1711 write_memory (offset, info->contents, info->length);
1716 int n = info->length;
1717 const bfd_byte *cp = info->contents;
1718 int r = info->u.regno;
1720 /* Odd-sized structs are aligned to the lower side of registers in
1721 big-endian mode and require a shift. The odd-sized leftover will
1722 be at the end. Note that this is only true for structures smaller
1723 than REGISTER_SIZE; for larger odd-sized structures the excess
1724 will be left-aligned in the register on both endiannesses. */
1726 if (n < REGISTER_SIZE
1727 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1729 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1730 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1732 store_unsigned_integer (buf, REGISTER_SIZE, v);
1733 regcache_cooked_write (regcache, r, buf);
1735 cp += REGISTER_SIZE;
1742 regcache_cooked_write (regcache, r, cp);
1744 cp += REGISTER_SIZE;
1751 /* Set the return address of dummy frame to the dummy address.
1752 The return address for the current function (in A0) is
1753 saved in the dummy frame, so we can savely overwrite A0 here. */
1755 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1757 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1758 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
1759 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1760 regcache_cooked_write_unsigned
1761 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1762 regcache_cooked_write_unsigned (regcache,
1763 gdbarch_ps_regnum (gdbarch),
1768 /* Simulate CALL0: write RA into A0 register. */
1769 regcache_cooked_write_unsigned
1770 (regcache, gdbarch_tdep (gdbarch)->a0_base + 0, bp_addr);
1773 /* Set new stack pointer and return it. */
1774 regcache_cooked_write_unsigned (regcache,
1775 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1776 /* Make dummy frame ID unique by adding a constant. */
1777 return sp + SP_ALIGNMENT;
1781 /* Return a breakpoint for the current location of PC. We always use
1782 the density version if we have density instructions (regardless of the
1783 current instruction at PC), and use regular instructions otherwise. */
1785 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1786 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1787 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1788 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1790 static const unsigned char *
1791 xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1793 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1794 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1795 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1796 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1798 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1800 if (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
1802 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1804 *lenptr = sizeof (density_big_breakpoint);
1805 return density_big_breakpoint;
1809 *lenptr = sizeof (density_little_breakpoint);
1810 return density_little_breakpoint;
1815 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1817 *lenptr = sizeof (big_breakpoint);
1818 return big_breakpoint;
1822 *lenptr = sizeof (little_breakpoint);
1823 return little_breakpoint;
1828 /* Call0 ABI support routines. */
1830 /* Call0 opcode class. Opcodes are preclassified according to what they
1831 mean for Call0 prologue analysis, and their number of significant operands.
1832 The purpose of this is to simplify prologue analysis by separating
1833 instruction decoding (libisa) from the semantics of prologue analysis. */
1836 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1837 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1838 c0opc_flow, /* Flow control insn. */
1839 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1840 c0opc_break, /* Debugger software breakpoints. */
1841 c0opc_add, /* Adding two registers. */
1842 c0opc_addi, /* Adding a register and an immediate. */
1843 c0opc_sub, /* Subtracting a register from a register. */
1844 c0opc_mov, /* Moving a register to a register. */
1845 c0opc_movi, /* Moving an immediate to a register. */
1846 c0opc_l32r, /* Loading a literal. */
1847 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1848 c0opc_NrOf /* Number of opcode classifications. */
1852 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1854 static xtensa_insn_kind
1855 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1857 const char *opcname;
1858 xtensa_insn_kind opclass = c0opc_uninteresting;
1860 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1862 /* Get opcode name and handle special classifications. */
1864 opcname = xtensa_opcode_name (isa, opc);
1867 || strcasecmp (opcname, "ill") == 0
1868 || strcasecmp (opcname, "ill.n") == 0)
1869 opclass = c0opc_illegal;
1870 else if (strcasecmp (opcname, "break") == 0
1871 || strcasecmp (opcname, "break.n") == 0)
1872 opclass = c0opc_break;
1873 else if (strcasecmp (opcname, "entry") == 0)
1874 opclass = c0opc_entry;
1875 else if (xtensa_opcode_is_branch (isa, opc) > 0
1876 || xtensa_opcode_is_jump (isa, opc) > 0
1877 || xtensa_opcode_is_loop (isa, opc) > 0
1878 || xtensa_opcode_is_call (isa, opc) > 0
1879 || strcasecmp (opcname, "simcall") == 0
1880 || strcasecmp (opcname, "syscall") == 0)
1881 opclass = c0opc_flow;
1883 /* Also, classify specific opcodes that need to be tracked. */
1884 else if (strcasecmp (opcname, "add") == 0
1885 || strcasecmp (opcname, "add.n") == 0)
1886 opclass = c0opc_add;
1887 else if (strcasecmp (opcname, "addi") == 0
1888 || strcasecmp (opcname, "addi.n") == 0
1889 || strcasecmp (opcname, "addmi") == 0)
1890 opclass = c0opc_addi;
1891 else if (strcasecmp (opcname, "sub") == 0)
1892 opclass = c0opc_sub;
1893 else if (strcasecmp (opcname, "mov.n") == 0
1894 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1895 opclass = c0opc_mov;
1896 else if (strcasecmp (opcname, "movi") == 0
1897 || strcasecmp (opcname, "movi.n") == 0)
1898 opclass = c0opc_movi;
1899 else if (strcasecmp (opcname, "l32r") == 0)
1900 opclass = c0opc_l32r;
1901 else if (strcasecmp (opcname, "s32i") == 0
1902 || strcasecmp (opcname, "s32i.n") == 0)
1903 opclass = c0opc_s32i;
1908 /* Tracks register movement/mutation for a given operation, which may
1909 be within a bundle. Updates the destination register tracking info
1910 accordingly. The pc is needed only for pc-relative load instructions
1911 (eg. l32r). The SP register number is needed to identify stores to
1915 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1916 xtensa_insn_kind opclass, int nods, unsigned odv[],
1917 CORE_ADDR pc, int spreg)
1919 unsigned litbase, litaddr, litval;
1924 /* 3 operands: dst, src, imm. */
1925 gdb_assert (nods == 3);
1926 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1927 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1930 /* 3 operands: dst, src1, src2. */
1931 gdb_assert (nods == 3);
1932 if (src[odv[1]].fr_reg == C0_CONST)
1934 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
1935 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
1937 else if (src[odv[2]].fr_reg == C0_CONST)
1939 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1940 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
1942 else dst[odv[0]].fr_reg = C0_INEXP;
1945 /* 3 operands: dst, src1, src2. */
1946 gdb_assert (nods == 3);
1947 if (src[odv[2]].fr_reg == C0_CONST)
1949 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1950 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
1952 else dst[odv[0]].fr_reg = C0_INEXP;
1955 /* 2 operands: dst, src [, src]. */
1956 gdb_assert (nods == 2);
1957 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1958 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
1961 /* 2 operands: dst, imm. */
1962 gdb_assert (nods == 2);
1963 dst[odv[0]].fr_reg = C0_CONST;
1964 dst[odv[0]].fr_ofs = odv[1];
1967 /* 2 operands: dst, literal offset. */
1968 gdb_assert (nods == 2);
1969 /* litbase = xtensa_get_litbase (pc); can be also used. */
1970 litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1)
1971 ? 0 : xtensa_read_register
1972 (gdbarch_tdep (current_gdbarch)->litbase_regnum);
1973 litaddr = litbase & 1
1974 ? (litbase & ~1) + (signed)odv[1]
1975 : (pc + 3 + (signed)odv[1]) & ~3;
1976 litval = read_memory_integer(litaddr, 4);
1977 dst[odv[0]].fr_reg = C0_CONST;
1978 dst[odv[0]].fr_ofs = litval;
1981 /* 3 operands: value, base, offset. */
1982 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
1983 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
1984 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
1985 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
1986 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
1987 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
1989 /* ISA encoding guarantees alignment. But, check it anyway. */
1990 gdb_assert ((odv[2] & 3) == 0);
1991 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
1999 /* Analyze prologue of the function at start address to determine if it uses
2000 the Call0 ABI, and if so track register moves and linear modifications
2001 in the prologue up to the PC or just beyond the prologue, whichever is first.
2002 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2003 The prologue may overlap non-prologue instructions but is guaranteed to end
2004 by the first flow-control instruction (jump, branch, call or return).
2005 Since an optimized function may move information around and change the
2006 stack frame arbitrarily during the prologue, the information is guaranteed
2007 valid only at the point in the function indicated by the PC.
2008 May be used to skip the prologue or identify the ABI, w/o tracking.
2010 Returns: Address of first instruction after prologue, or PC (whichever
2011 is first), or 0, if decoding failed (in libisa).
2013 start Start address of function/prologue.
2014 pc Program counter to stop at. Use 0 to continue to end of prologue.
2015 If 0, avoids infinite run-on in corrupt code memory by bounding
2016 the scan to the end of the function if that can be determined.
2017 nregs Number of general registers to track (size of rt[] array).
2019 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2020 If NULL, registers are not tracked.
2022 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2023 (more accurately, non-zero until 'entry' insn is encountered).
2025 Note that these may produce useful results even if decoding fails
2026 because they begin with default assumptions that analysis may change. */
2029 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
2030 int nregs, xtensa_c0reg_t rt[], int *call0)
2032 CORE_ADDR ia; /* Current insn address in prologue. */
2033 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2034 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2035 #define BSZ 32 /* Instruction buffer size. */
2036 char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
2037 xtensa_isa isa; /* libisa ISA handle. */
2038 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2039 xtensa_format ifmt; /* libisa instruction format. */
2040 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2041 xtensa_opcode opc; /* Opcode in current slot. */
2042 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2043 int nods; /* Opcode number of operands. */
2044 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2045 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2046 int j; /* General loop counter. */
2047 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2048 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2049 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2051 struct symtab_and_line prologue_sal;
2053 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2054 (int)start, (int)pc);
2056 /* Try to limit the scan to the end of the function if a non-zero pc
2057 arg was not supplied to avoid probing beyond the end of valid memory.
2058 If memory is full of garbage that classifies as c0opc_uninteresting.
2059 If this fails (eg. if no symbols) pc ends up 0 as it was.
2060 Intialize the Call0 frame and register tracking info.
2061 Assume it's Call0 until an 'entry' instruction is encountered.
2062 Assume we may be in the prologue until we hit a flow control instr. */
2068 /* Find out, if we have an information about the prologue from DWARF. */
2069 prologue_sal = find_pc_line (start, 0);
2070 if (prologue_sal.line != 0) /* Found debug info. */
2071 body_pc = prologue_sal.end;
2073 /* If we are going to analyze the prologue in general without knowing about
2074 the current PC, make the best assumtion for the end of the prologue. */
2077 find_pc_partial_function (start, 0, NULL, &end_pc);
2078 body_pc = min (end_pc, body_pc);
2081 body_pc = min (pc, body_pc);
2088 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2089 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2093 isa = xtensa_default_isa;
2094 gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
2095 ins = xtensa_insnbuf_alloc (isa);
2096 slot = xtensa_insnbuf_alloc (isa);
2098 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2100 /* (Re)fill instruction buffer from memory if necessary, but do not
2101 read memory beyond PC to be sure we stay within text section
2102 (this protection only works if a non-zero pc is supplied). */
2104 if (ia + xtensa_isa_maxlength (isa) > bt)
2107 bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
2108 read_memory (ba, ibuf, bt - ba);
2111 /* Decode format information. */
2113 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2114 ifmt = xtensa_format_decode (isa, ins);
2115 if (ifmt == XTENSA_UNDEFINED)
2120 ilen = xtensa_format_length (isa, ifmt);
2121 if (ilen == XTENSA_UNDEFINED)
2126 islots = xtensa_format_num_slots (isa, ifmt);
2127 if (islots == XTENSA_UNDEFINED)
2133 /* Analyze a bundle or a single instruction, using a snapshot of
2134 the register tracking info as input for the entire bundle so that
2135 register changes do not take effect within this bundle. */
2137 for (j = 0; j < nregs; ++j)
2140 for (is = 0; is < islots; ++is)
2142 /* Decode a slot and classify the opcode. */
2144 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2148 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2149 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2151 if (opc == XTENSA_UNDEFINED)
2152 opclass = c0opc_illegal;
2154 opclass = call0_classify_opcode (isa, opc);
2156 /* Decide whether to track this opcode, ignore it, or bail out. */
2165 case c0opc_uninteresting:
2174 ia += ilen; /* Skip over 'entry' insn. */
2182 /* Only expected opcodes should get this far. */
2186 /* Extract and decode the operands. */
2187 nods = xtensa_opcode_num_operands (isa, opc);
2188 if (nods == XTENSA_UNDEFINED)
2194 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2196 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2201 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2206 /* Check operands to verify use of 'mov' assembler macro. */
2207 if (opclass == c0opc_mov && nods == 3)
2209 if (odv[2] == odv[1])
2213 opclass = c0opc_uninteresting;
2218 /* Track register movement and modification for this operation. */
2219 call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
2223 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2224 (unsigned)ia, fail ? "failed" : "succeeded");
2225 xtensa_insnbuf_free(isa, slot);
2226 xtensa_insnbuf_free(isa, ins);
2227 return fail ? 0 : ia;
2230 /* Initialize frame cache for the current frame. The "next_frame" is the next
2231 one relative to current frame. "cache" is the pointer to the data structure
2232 we have to initialize. "pc" is curretnt PC. */
2235 call0_frame_cache (struct frame_info *next_frame,
2236 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2238 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2239 CORE_ADDR start_pc; /* The beginning of the function. */
2240 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2241 CORE_ADDR sp, fp, ra;
2242 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2244 /* Find the beginning of the prologue of the function containing the PC
2245 and analyze it up to the PC or the end of the prologue. */
2247 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2249 body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
2250 &cache->c0.c0_rt[0],
2254 sp = frame_unwind_register_unsigned
2255 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2256 fp = sp; /* Assume FP == SP until proven otherwise. */
2258 /* Get the frame information and FP (if used) at the current PC.
2259 If PC is in the prologue, the prologue analysis is more reliable
2260 than DWARF info. We don't not know for sure if PC is in the prologue,
2261 but we know no calls have yet taken place, so we can almost
2262 certainly rely on the prologue analysis. */
2266 /* Prologue analysis was successful up to the PC.
2267 It includes the cases when PC == START_PC. */
2268 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2269 /* c0_hasfp == true means there is a frame pointer because
2270 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2271 was derived from SP. Otherwise, it would be C0_FP. */
2272 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2273 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2274 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2276 else /* No data from the prologue analysis. */
2279 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2284 prev_sp = fp + c0_frmsz;
2286 /* Frame size from debug info or prologue tracking does not account for
2287 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2290 fp = frame_unwind_register_unsigned (next_frame, fp_regnum);
2292 /* Recalculate previous SP. */
2293 prev_sp = fp + c0_frmsz;
2294 /* Update the stack frame size. */
2295 c0_frmsz += fp - sp;
2298 /* Get the return address (RA) from the stack if saved,
2299 or try to get it from a register. */
2301 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2302 if (to_stk != C0_NOSTK)
2304 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2306 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2307 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2309 /* Special case for terminating backtrace at a function that wants to
2310 be seen as the outermost. Such a function will clear it's RA (A0)
2311 register to 0 in the prologue instead of saving its original value. */
2316 /* RA was copied to another register or (before any function call) may
2317 still be in the original RA register. This is not always reliable:
2318 even in a leaf function, register tracking stops after prologue, and
2319 even in prologue, non-prologue instructions (not tracked) may overwrite
2320 RA or any register it was copied to. If likely in prologue or before
2321 any call, use retracking info and hope for the best (compiler should
2322 have saved RA in stack if not in a leaf function). If not in prologue,
2328 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2330 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2332 if (i < C0_NREGS) /* Read from the next_frame. */
2334 ra = frame_unwind_register_unsigned
2336 gdbarch_tdep (gdbarch)->a0_base + 0
2337 + cache->c0.c0_rt[i].fr_reg);
2342 cache->pc = start_pc;
2344 /* RA == 0 marks the outermost frame. Do not go past it. */
2345 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2346 cache->c0.fp_regnum = fp_regnum;
2347 cache->c0.c0_frmsz = c0_frmsz;
2348 cache->c0.c0_hasfp = c0_hasfp;
2349 cache->c0.c0_fp = fp;
2353 /* Skip function prologue.
2355 Return the pc of the first instruction after prologue. GDB calls this to
2356 find the address of the first line of the function or (if there is no line
2357 number information) to skip the prologue for planting breakpoints on
2358 function entries. Use debug info (if present) or prologue analysis to skip
2359 the prologue to achieve reliable debugging behavior. For windowed ABI,
2360 only the 'entry' instruction is skipped. It is not strictly necessary to
2361 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2362 backtrace at any point in the prologue, however certain potential hazards
2363 are avoided and a more "normal" debugging experience is ensured by
2364 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2365 For example, if we don't skip the prologue:
2366 - Some args may not yet have been saved to the stack where the debug
2367 info expects to find them (true anyway when only 'entry' is skipped);
2368 - Software breakpoints ('break' instrs) may not have been unplanted
2369 when the prologue analysis is done on initializing the frame cache,
2370 and breaks in the prologue will throw off the analysis.
2372 If we have debug info ( line-number info, in particular ) we simply skip
2373 the code associated with the first function line effectively skipping
2374 the prologue code. It works even in cases like
2377 { int local_var = 1;
2381 because, for this source code, both Xtensa compilers will generate two
2382 separate entries ( with the same line number ) in dwarf line-number
2383 section to make sure there is a boundary between the prologue code and
2384 the rest of the function.
2386 If there is no debug info, we need to analyze the code. */
2388 /* #define DONT_SKIP_PROLOGUE */
2391 xtensa_skip_prologue (CORE_ADDR start_pc)
2393 struct symtab_and_line prologue_sal;
2396 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2398 #if DONT_SKIP_PROLOGUE
2402 /* Try to find first body line from debug info. */
2404 prologue_sal = find_pc_line (start_pc, 0);
2405 if (prologue_sal.line != 0) /* Found debug info. */
2407 /* In Call0, it is possible to have a function with only one instruction
2408 ('ret') resulting from a 1-line optimized function that does nothing.
2409 In that case, prologue_sal.end may actually point to the start of the
2410 next function in the text section, causing a breakpoint to be set at
2411 the wrong place. Check if the end address is in a different function,
2412 and if so return the start PC. We know we have symbol info. */
2416 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2417 if (end_func != start_pc)
2420 return prologue_sal.end;
2423 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2424 body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
2425 return body_pc != 0 ? body_pc : start_pc;
2428 /* Verify the current configuration. */
2430 xtensa_verify_config (struct gdbarch *gdbarch)
2432 struct ui_file *log;
2433 struct cleanup *cleanups;
2434 struct gdbarch_tdep *tdep;
2438 tdep = gdbarch_tdep (gdbarch);
2439 log = mem_fileopen ();
2440 cleanups = make_cleanup_ui_file_delete (log);
2442 /* Verify that we got a reasonable number of AREGS. */
2443 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2444 fprintf_unfiltered (log, _("\
2445 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2448 /* Verify that certain registers exist. */
2450 if (tdep->pc_regnum == -1)
2451 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2452 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2453 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2455 if (tdep->isa_use_windowed_registers)
2457 if (tdep->wb_regnum == -1)
2458 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2459 if (tdep->ws_regnum == -1)
2460 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2461 if (tdep->ar_base == -1)
2462 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2465 if (tdep->a0_base == -1)
2466 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2468 buf = ui_file_xstrdup (log, &dummy);
2469 make_cleanup (xfree, buf);
2470 if (strlen (buf) > 0)
2471 internal_error (__FILE__, __LINE__,
2472 _("the following are invalid: %s"), buf);
2473 do_cleanups (cleanups);
2476 /* Module "constructor" function. */
2478 static struct gdbarch *
2479 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2481 struct gdbarch_tdep *tdep;
2482 struct gdbarch *gdbarch;
2483 struct xtensa_abi_handler *abi_handler;
2485 DEBUGTRACE ("gdbarch_init()\n");
2487 /* We have to set the byte order before we call gdbarch_alloc. */
2488 info.byte_order = xtensa_config_byte_order (&info);
2490 tdep = xtensa_config_tdep (&info);
2491 gdbarch = gdbarch_alloc (&info, tdep);
2493 /* Verify our configuration. */
2494 xtensa_verify_config (gdbarch);
2496 /* Pseudo-Register read/write. */
2497 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2498 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2500 /* Set target information. */
2501 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2502 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2503 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2504 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2505 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2507 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
2508 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2509 set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2510 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2512 /* We provide our own function to get register information. */
2513 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2514 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2516 /* To call functions from GDB using dummy frame */
2517 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2519 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2521 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2523 /* Advance PC across any prologue instructions to reach "real" code. */
2524 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2526 /* Stack grows downward. */
2527 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2529 /* Set breakpoints. */
2530 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2532 /* After breakpoint instruction or illegal instruction, pc still
2533 points at break instruction, so don't decrement. */
2534 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2536 /* We don't skip args. */
2537 set_gdbarch_frame_args_skip (gdbarch, 0);
2539 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2541 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2543 set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id);
2545 /* Frame handling. */
2546 frame_base_set_default (gdbarch, &xtensa_frame_base);
2547 frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer);
2549 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2551 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2553 xtensa_add_reggroups (gdbarch);
2554 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2556 set_gdbarch_regset_from_core_section (gdbarch,
2557 xtensa_regset_from_core_section);
2563 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2565 error (_("xtensa_dump_tdep(): not implemented"));
2569 _initialize_xtensa_tdep (void)
2571 struct cmd_list_element *c;
2573 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2574 xtensa_init_reggroups ();
2576 add_setshow_zinteger_cmd ("xtensa",
2578 &xtensa_debug_level, _("\
2579 Set Xtensa debugging."), _("\
2580 Show Xtensa debugging."), _("\
2581 When non-zero, Xtensa-specific debugging is enabled. \
2582 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2585 &setdebuglist, &showdebuglist);