1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "floatformat.h"
32 #include "reggroups.h"
35 #include "dummy-frame.h"
36 #include "elf/dwarf2.h"
37 #include "dwarf2-frame.h"
38 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
50 #include "gdb_assert.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
56 static int xtensa_debug_level = 0;
58 #define DEBUGWARN(args...) \
59 if (xtensa_debug_level > 0) \
60 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
62 #define DEBUGINFO(args...) \
63 if (xtensa_debug_level > 1) \
64 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
66 #define DEBUGTRACE(args...) \
67 if (xtensa_debug_level > 2) \
68 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
70 #define DEBUGVERB(args...) \
71 if (xtensa_debug_level > 3) \
72 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
75 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
76 #define SP_ALIGNMENT 16
79 /* On Windowed ABI, we use a6 through a11 for passing arguments
80 to a function called by GDB because CALL4 is used. */
81 #define ARGS_NUM_REGS 6
82 #define REGISTER_SIZE 4
85 /* Extract the call size from the return address or PS register. */
86 #define PS_CALLINC_SHIFT 16
87 #define PS_CALLINC_MASK 0x00030000
88 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
89 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
91 /* ABI-independent macros. */
92 #define ARG_NOF(gdbarch) \
93 (gdbarch_tdep (gdbarch)->call_abi \
94 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
95 #define ARG_1ST(gdbarch) \
96 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
97 ? (gdbarch_tdep (gdbarch)->a0_base + 0) + C0_ARGS \
98 : (gdbarch_tdep (gdbarch)->a0_base + 6))
100 extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *);
101 extern int xtensa_config_byte_order (struct gdbarch_info *);
104 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
105 indicates that the instruction is an ENTRY instruction. */
107 #define XTENSA_IS_ENTRY(gdbarch, op1) \
108 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
109 ? ((op1) == 0x6c) : ((op1) == 0x36))
111 #define XTENSA_ENTRY_LENGTH 3
113 /* windowing_enabled() returns true, if windowing is enabled.
114 WOE must be set to 1; EXCM to 0.
115 Note: We assume that EXCM is always 0 for XEA1. */
117 #define PS_WOE (1<<18)
118 #define PS_EXC (1<<4)
120 /* Convert a live Ax register number to the corresponding Areg number. */
122 areg_number (struct gdbarch *gdbarch, int regnum, ULONGEST wb)
124 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
127 areg = regnum - tdep->a0_base;
128 areg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
129 areg &= tdep->num_aregs - 1;
131 return areg + tdep->ar_base;
135 windowing_enabled (CORE_ADDR ps)
137 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
140 /* Return the window size of the previous call to the function from which we
143 This function is used to extract the return value after a called function
144 has returned to the caller. On Xtensa, the register that holds the return
145 value (from the perspective of the caller) depends on what call
146 instruction was used. For now, we are assuming that the call instruction
147 precedes the current address, so we simply analyze the call instruction.
148 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
149 method to call the inferior function. */
152 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
158 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
160 /* Read the previous instruction (should be a call[x]{4|8|12}. */
161 read_memory (pc-3, buf, 3);
162 insn = extract_unsigned_integer (buf, 3);
164 /* Decode call instruction:
166 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
167 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
169 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
170 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
172 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
174 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
175 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
179 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
180 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
186 /* REGISTER INFORMATION */
188 /* Returns the name of a register. */
190 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
192 /* Return the name stored in the register map. */
193 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
194 + gdbarch_num_pseudo_regs (gdbarch))
195 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
197 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
202 xtensa_read_register (int regnum)
206 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
207 return (unsigned long) value;
210 /* Return the type of a register. Create a new type, if necessary. */
212 static struct ctype_cache
214 struct ctype_cache *next;
216 struct type *virtual_type;
217 } *type_entries = NULL;
220 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
222 /* Return signed integer for ARx and Ax registers. */
223 if ((regnum >= gdbarch_tdep (gdbarch)->ar_base
224 && regnum < gdbarch_tdep (gdbarch)->ar_base
225 + gdbarch_tdep (gdbarch)->num_aregs)
226 || (regnum >= gdbarch_tdep (gdbarch)->a0_base
227 && regnum < gdbarch_tdep (gdbarch)->a0_base + 16))
228 return builtin_type_int;
230 if (regnum == gdbarch_pc_regnum (gdbarch)
231 || regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
232 return lookup_pointer_type (builtin_type_void);
234 /* Return the stored type for all other registers. */
235 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
236 + gdbarch_num_pseudo_regs (gdbarch))
238 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
240 /* Set ctype for this register (only the first time). */
244 struct ctype_cache *tp;
245 int size = reg->byte_size;
247 /* We always use the memory representation,
248 even if the register width is smaller. */
252 reg->ctype = builtin_type_uint8;
256 reg->ctype = builtin_type_uint16;
260 reg->ctype = builtin_type_uint32;
264 reg->ctype = builtin_type_uint64;
268 reg->ctype = builtin_type_uint128;
272 for (tp = type_entries; tp != NULL; tp = tp->next)
273 if (tp->size == size)
278 char *name = xmalloc (16);
279 tp = xmalloc (sizeof (struct ctype_cache));
280 tp->next = type_entries;
284 sprintf (name, "int%d", size * 8);
285 tp->virtual_type = init_type (TYPE_CODE_INT, size,
286 TYPE_FLAG_UNSIGNED, name,
290 reg->ctype = tp->virtual_type;
296 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
301 /* Return the 'local' register number for stubs, dwarf2, etc.
302 The debugging information enumerates registers starting from 0 for A0
303 to n for An. So, we only have to add the base number for A0. */
306 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
310 if (regnum >= 0 && regnum < 16)
311 return gdbarch_tdep (gdbarch)->a0_base + regnum;
314 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
316 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
319 internal_error (__FILE__, __LINE__,
320 _("invalid dwarf/stabs register number %d"), regnum);
325 /* Write the bits of a masked register to the various registers.
326 Only the masked areas of these registers are modified; the other
327 fields are untouched. The size of masked registers is always less
328 than or equal to 32 bits. */
331 xtensa_register_write_masked (struct regcache *regcache,
332 xtensa_register_t *reg, const gdb_byte *buffer)
334 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
335 const xtensa_mask_t *mask = reg->mask;
337 int shift = 0; /* Shift for next mask (mod 32). */
338 int start, size; /* Start bit and size of current mask. */
340 unsigned int *ptr = value;
341 unsigned int regval, m, mem = 0;
343 int bytesize = reg->byte_size;
344 int bitsize = bytesize * 8;
347 DEBUGTRACE ("xtensa_register_write_masked ()\n");
349 /* Copy the masked register to host byte-order. */
350 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
351 for (i = 0; i < bytesize; i++)
354 mem |= (buffer[bytesize - i - 1] << 24);
359 for (i = 0; i < bytesize; i++)
362 mem |= (buffer[i] << 24);
367 /* We might have to shift the final value:
368 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
369 bytesize & 3 == x -> shift (4-x) * 8. */
371 *ptr = mem >> (((0 - bytesize) & 3) * 8);
375 /* Write the bits to the masked areas of the other registers. */
376 for (i = 0; i < mask->count; i++)
378 start = mask->mask[i].bit_start;
379 size = mask->mask[i].bit_size;
380 regval = mem >> shift;
382 if ((shift += size) > bitsize)
383 error (_("size of all masks is larger than the register"));
392 regval |= mem << (size - shift);
395 /* Make sure we have a valid register. */
396 r = mask->mask[i].reg_num;
397 if (r >= 0 && size > 0)
399 /* Don't overwrite the unmasked areas. */
401 regcache_cooked_read_unsigned (regcache, r, &old_val);
402 m = 0xffffffff >> (32 - size) << start;
404 regval = (regval & m) | (old_val & ~m);
405 regcache_cooked_write_unsigned (regcache, r, regval);
411 /* Read a tie state or mapped registers. Read the masked areas
412 of the registers and assemble them into a single value. */
415 xtensa_register_read_masked (struct regcache *regcache,
416 xtensa_register_t *reg, gdb_byte *buffer)
418 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
419 const xtensa_mask_t *mask = reg->mask;
424 unsigned int *ptr = value;
425 unsigned int regval, mem = 0;
427 int bytesize = reg->byte_size;
428 int bitsize = bytesize * 8;
431 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
432 reg->name == 0 ? "" : reg->name);
434 /* Assemble the register from the masked areas of other registers. */
435 for (i = 0; i < mask->count; i++)
437 int r = mask->mask[i].reg_num;
441 regcache_cooked_read_unsigned (regcache, r, &val);
442 regval = (unsigned int) val;
447 start = mask->mask[i].bit_start;
448 size = mask->mask[i].bit_size;
453 regval &= (0xffffffff >> (32 - size));
455 mem |= regval << shift;
457 if ((shift += size) > bitsize)
458 error (_("size of all masks is larger than the register"));
469 mem = regval >> (size - shift);
476 /* Copy value to target byte order. */
480 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
481 for (i = 0; i < bytesize; i++)
485 buffer[bytesize - i - 1] = mem & 0xff;
489 for (i = 0; i < bytesize; i++)
493 buffer[i] = mem & 0xff;
499 /* Read pseudo registers. */
502 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
503 struct regcache *regcache,
507 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
508 regnum, xtensa_register_name (gdbarch, regnum));
510 if (regnum == gdbarch_num_regs (gdbarch)
511 + gdbarch_num_pseudo_regs (gdbarch))
512 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
514 /* Read aliases a0..a15, if this is a Windowed ABI. */
515 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
516 && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0)
517 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
519 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
521 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
522 regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4));
525 /* We can always read non-pseudo registers. */
526 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
527 regcache_raw_read (regcache, regnum, buffer);
529 /* Pseudo registers. */
531 && regnum < gdbarch_num_regs (gdbarch)
532 + gdbarch_num_pseudo_regs (gdbarch))
534 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
535 xtensa_register_type_t type = reg->type;
536 int flags = gdbarch_tdep (gdbarch)->target_flags;
538 /* We cannot read Unknown or Unmapped registers. */
539 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
541 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
543 warning (_("cannot read register %s"),
544 xtensa_register_name (gdbarch, regnum));
549 /* Some targets cannot read TIE register files. */
550 else if (type == xtRegisterTypeTieRegfile)
552 /* Use 'fetch' to get register? */
553 if (flags & xtTargetFlagsUseFetchStore)
555 warning (_("cannot read register"));
559 /* On some targets (esp. simulators), we can always read the reg. */
560 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
562 warning (_("cannot read register"));
567 /* We can always read mapped registers. */
568 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
570 xtensa_register_read_masked (regcache, reg, buffer);
574 /* Assume that we can read the register. */
575 regcache_raw_read (regcache, regnum, buffer);
578 internal_error (__FILE__, __LINE__,
579 _("invalid register number %d"), regnum);
583 /* Write pseudo registers. */
586 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
587 struct regcache *regcache,
589 const gdb_byte *buffer)
591 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
592 regnum, xtensa_register_name (gdbarch, regnum));
594 if (regnum == gdbarch_num_regs (gdbarch)
595 + gdbarch_num_pseudo_regs (gdbarch))
596 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
598 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
599 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
600 && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0)
601 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
603 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
606 regcache_raw_read (regcache,
607 gdbarch_tdep (gdbarch)->wb_regnum, buf);
608 regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4));
611 /* We can always write 'core' registers.
612 Note: We might have converted Ax->ARy. */
613 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
614 regcache_raw_write (regcache, regnum, buffer);
616 /* Pseudo registers. */
618 && regnum < gdbarch_num_regs (gdbarch)
619 + gdbarch_num_pseudo_regs (gdbarch))
621 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
622 xtensa_register_type_t type = reg->type;
623 int flags = gdbarch_tdep (gdbarch)->target_flags;
625 /* On most targets, we cannot write registers
626 of type "Unknown" or "Unmapped". */
627 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
629 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
631 warning (_("cannot write register %s"),
632 xtensa_register_name (gdbarch, regnum));
637 /* Some targets cannot read TIE register files. */
638 else if (type == xtRegisterTypeTieRegfile)
640 /* Use 'store' to get register? */
641 if (flags & xtTargetFlagsUseFetchStore)
643 warning (_("cannot write register"));
647 /* On some targets (esp. simulators), we can always write
649 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
651 warning (_("cannot write register"));
656 /* We can always write mapped registers. */
657 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
659 xtensa_register_write_masked (regcache, reg, buffer);
663 /* Assume that we can write the register. */
664 regcache_raw_write (regcache, regnum, buffer);
667 internal_error (__FILE__, __LINE__,
668 _("invalid register number %d"), regnum);
671 static struct reggroup *xtensa_ar_reggroup;
672 static struct reggroup *xtensa_user_reggroup;
673 static struct reggroup *xtensa_vectra_reggroup;
674 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
677 xtensa_init_reggroups (void)
679 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
680 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
681 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
683 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
684 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
685 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
686 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
687 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
688 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
689 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
690 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
694 xtensa_add_reggroups (struct gdbarch *gdbarch)
698 /* Predefined groups. */
699 reggroup_add (gdbarch, all_reggroup);
700 reggroup_add (gdbarch, save_reggroup);
701 reggroup_add (gdbarch, restore_reggroup);
702 reggroup_add (gdbarch, system_reggroup);
703 reggroup_add (gdbarch, vector_reggroup);
704 reggroup_add (gdbarch, general_reggroup);
705 reggroup_add (gdbarch, float_reggroup);
707 /* Xtensa-specific groups. */
708 reggroup_add (gdbarch, xtensa_ar_reggroup);
709 reggroup_add (gdbarch, xtensa_user_reggroup);
710 reggroup_add (gdbarch, xtensa_vectra_reggroup);
712 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
713 reggroup_add (gdbarch, xtensa_cp[i]);
717 xtensa_coprocessor_register_group (struct reggroup *group)
721 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
722 if (group == xtensa_cp[i])
728 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
729 | XTENSA_REGISTER_FLAGS_WRITABLE \
730 | XTENSA_REGISTER_FLAGS_VOLATILE)
732 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
733 | XTENSA_REGISTER_FLAGS_WRITABLE)
736 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
738 struct reggroup *group)
740 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
741 xtensa_register_type_t type = reg->type;
742 xtensa_register_group_t rg = reg->group;
745 /* First, skip registers that are not visible to this target
746 (unknown and unmapped registers when not using ISS). */
748 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
750 if (group == all_reggroup)
752 if (group == xtensa_ar_reggroup)
753 return rg & xtRegisterGroupAddrReg;
754 if (group == xtensa_user_reggroup)
755 return rg & xtRegisterGroupUser;
756 if (group == float_reggroup)
757 return rg & xtRegisterGroupFloat;
758 if (group == general_reggroup)
759 return rg & xtRegisterGroupGeneral;
760 if (group == float_reggroup)
761 return rg & xtRegisterGroupFloat;
762 if (group == system_reggroup)
763 return rg & xtRegisterGroupState;
764 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
765 return rg & xtRegisterGroupVectra;
766 if (group == save_reggroup || group == restore_reggroup)
767 return (regnum < gdbarch_num_regs (gdbarch)
768 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
769 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
770 return rg & (xtRegisterGroupCP0 << cp_number);
776 /* Supply register REGNUM from the buffer specified by GREGS and LEN
777 in the general-purpose register set REGSET to register cache
778 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
781 xtensa_supply_gregset (const struct regset *regset,
787 const xtensa_elf_gregset_t *regs = gregs;
788 struct gdbarch *gdbarch = get_regcache_arch (rc);
791 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
793 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
794 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
795 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
796 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
797 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
798 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
799 (char *) ®s->windowbase);
800 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
801 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
802 (char *) ®s->windowstart);
803 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
804 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
805 (char *) ®s->lbeg);
806 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
807 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
808 (char *) ®s->lend);
809 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
810 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
811 (char *) ®s->lcount);
812 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
813 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
814 (char *) ®s->sar);
815 if (regnum == gdbarch_tdep (gdbarch)->exccause_regnum || regnum == -1)
816 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->exccause_regnum,
817 (char *) ®s->exccause);
818 if (regnum == gdbarch_tdep (gdbarch)->excvaddr_regnum || regnum == -1)
819 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->excvaddr_regnum,
820 (char *) ®s->excvaddr);
821 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
822 && regnum < gdbarch_tdep (gdbarch)->ar_base
823 + gdbarch_tdep (gdbarch)->num_aregs)
824 regcache_raw_supply (rc, regnum,
825 (char *) ®s->ar[regnum - gdbarch_tdep
826 (gdbarch)->ar_base]);
827 else if (regnum == -1)
829 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
830 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
831 (char *) ®s->ar[i]);
836 /* Xtensa register set. */
842 xtensa_supply_gregset
846 /* Return the appropriate register set for the core
847 section identified by SECT_NAME and SECT_SIZE. */
849 static const struct regset *
850 xtensa_regset_from_core_section (struct gdbarch *core_arch,
851 const char *sect_name,
854 DEBUGTRACE ("xtensa_regset_from_core_section "
855 "(..., sect_name==\"%s\", sect_size==%x) \n",
856 sect_name, (unsigned int) sect_size);
858 if (strcmp (sect_name, ".reg") == 0
859 && sect_size >= sizeof(xtensa_elf_gregset_t))
860 return &xtensa_gregset;
866 /* Handling frames. */
868 /* Number of registers to save in case of Windowed ABI. */
869 #define XTENSA_NUM_SAVED_AREGS 12
871 /* Frame cache part for Windowed ABI. */
872 typedef struct xtensa_windowed_frame_cache
874 int wb; /* Base for this frame; -1 if not in regfile. */
875 int callsize; /* Call size to next frame. */
877 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
878 } xtensa_windowed_frame_cache_t;
880 /* Call0 ABI Definitions. */
882 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
883 #define C0_NREGS 16 /* Number of A-registers to track. */
884 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
885 #define C0_SP 1 /* Register used as SP. */
886 #define C0_FP 15 /* Register used as FP. */
887 #define C0_RA 0 /* Register used as return address. */
888 #define C0_ARGS 2 /* Register used as first arg/retval. */
889 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
891 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
892 A-register where the current content of the reg came from (in terms
893 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
894 mean that the orignal content of the register was saved to the stack.
895 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
896 know where SP will end up until the entire prologue has been analyzed. */
898 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
899 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
900 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
902 extern xtensa_isa xtensa_default_isa;
904 typedef struct xtensa_c0reg
906 int fr_reg; /* original register from which register content
907 is derived, or C0_CONST, or C0_INEXP. */
908 int fr_ofs; /* constant offset from reg, or immediate value. */
909 int to_stk; /* offset from original SP to register (4-byte aligned),
910 or C0_NOSTK if register has not been saved. */
914 /* Frame cache part for Call0 ABI. */
915 typedef struct xtensa_call0_frame_cache
917 int c0_frmsz; /* Stack frame size. */
918 int c0_hasfp; /* Current frame uses frame pointer. */
919 int fp_regnum; /* A-register used as FP. */
920 int c0_fp; /* Actual value of frame pointer. */
921 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
922 } xtensa_call0_frame_cache_t;
924 typedef struct xtensa_frame_cache
926 CORE_ADDR base; /* Stack pointer of the next frame. */
927 CORE_ADDR pc; /* PC at the entry point to the function. */
928 CORE_ADDR ra; /* The raw return address. */
929 CORE_ADDR ps; /* The PS register of the frame. */
930 CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
931 int call0; /* It's a call0 framework (else windowed). */
934 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
935 xtensa_call0_frame_cache_t c0; /* call0 == true. */
937 } xtensa_frame_cache_t;
940 static struct xtensa_frame_cache *
941 xtensa_alloc_frame_cache (int windowed)
943 xtensa_frame_cache_t *cache;
946 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
948 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
955 cache->call0 = !windowed;
958 cache->c0.c0_frmsz = -1;
959 cache->c0.c0_hasfp = 0;
960 cache->c0.fp_regnum = -1;
961 cache->c0.c0_fp = -1;
963 for (i = 0; i < C0_NREGS; i++)
965 cache->c0.c0_rt[i].fr_reg = i;
966 cache->c0.c0_rt[i].fr_ofs = 0;
967 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
973 cache->wd.callsize = -1;
975 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
976 cache->wd.aregs[i] = -1;
983 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
985 return address & ~15;
990 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
994 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
996 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
998 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
999 extract_typed_address (buf, builtin_type_void_func_ptr));
1001 return extract_typed_address (buf, builtin_type_void_func_ptr);
1005 static struct frame_id
1006 xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1010 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
1012 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
1014 pc = frame_pc_unwind (next_frame);
1015 fp = frame_unwind_register_unsigned
1016 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1018 /* Make dummy frame ID unique by adding a constant. */
1019 return frame_id_build (fp + SP_ALIGNMENT, pc);
1022 /* The key values to identify the frame using "cache" are
1024 cache->base = SP of this frame;
1025 cache->pc = entry-PC (entry point of the frame function);
1026 cache->prev_sp = SP of the previous frame.
1030 call0_frame_cache (struct frame_info *next_frame,
1031 xtensa_frame_cache_t *cache,
1034 static struct xtensa_frame_cache *
1035 xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
1037 xtensa_frame_cache_t *cache;
1038 CORE_ADDR ra, wb, ws, pc, sp, ps;
1039 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1040 unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch);
1044 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
1045 next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
1050 windowed = windowing_enabled (xtensa_read_register (ps_regnum));
1052 /* Get pristine xtensa-frame. */
1053 cache = xtensa_alloc_frame_cache (windowed);
1054 *this_cache = cache;
1056 pc = frame_unwind_register_unsigned (next_frame,
1057 gdbarch_pc_regnum (gdbarch));
1061 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1062 wb = frame_unwind_register_unsigned
1063 (next_frame, gdbarch_tdep (gdbarch)->wb_regnum);
1064 ws = frame_unwind_register_unsigned
1065 (next_frame, gdbarch_tdep (gdbarch)->ws_regnum);
1066 ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
1068 op1 = read_memory_integer (pc, 1);
1069 if (XTENSA_IS_ENTRY (gdbarch, op1))
1071 int callinc = CALLINC (ps);
1072 ra = frame_unwind_register_unsigned
1073 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0 + callinc * 4);
1075 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
1078 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1079 cache->wd.callsize = 0;
1082 cache->prev_sp = frame_unwind_register_unsigned
1083 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1087 ra = frame_unwind_register_unsigned
1088 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0);
1089 cache->wd.callsize = WINSIZE (ra);
1090 cache->wd.wb = (wb - cache->wd.callsize / 4)
1091 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1092 cache->wd.ws = ws & ~(1 << wb);
1095 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
1096 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1097 cache->ps = (ps & ~PS_CALLINC_MASK)
1098 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1100 if (cache->wd.ws == 0)
1105 sp = frame_unwind_register_unsigned
1106 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1108 for (i = 0; i < 4; i++, sp += 4)
1110 cache->wd.aregs[i] = sp;
1113 if (cache->wd.callsize > 4)
1115 /* Set A4...A7/A11. */
1116 /* Read an SP of the previous frame. */
1117 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1118 sp -= cache->wd.callsize * 4;
1120 for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
1122 cache->wd.aregs[i] = sp;
1127 if ((cache->prev_sp == 0) && ( ra != 0 ))
1128 /* If RA is equal to 0 this frame is an outermost frame. Leave
1129 cache->prev_sp unchanged marking the boundary of the frame stack. */
1131 if (cache->wd.ws == 0)
1133 /* Register window overflow already happened.
1134 We can read caller's SP from the proper spill loction. */
1136 read_memory_integer (cache->wd.aregs[1],
1137 register_size (gdbarch,
1138 gdbarch_tdep (gdbarch)->a0_base + 1));
1142 /* Read caller's frame SP directly from the previous window. */
1143 int regnum = areg_number
1144 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1147 cache->prev_sp = xtensa_read_register (regnum);
1151 else /* Call0 framework. */
1153 call0_frame_cache (next_frame, cache, pc);
1156 cache->base = frame_unwind_register_unsigned
1157 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1163 xtensa_frame_this_id (struct frame_info *next_frame,
1165 struct frame_id *this_id)
1167 struct xtensa_frame_cache *cache =
1168 xtensa_frame_cache (next_frame, this_cache);
1171 DEBUGTRACE ("xtensa_frame_this_id (next 0x%lx, *this 0x%lx)\n",
1172 (unsigned long) next_frame, (unsigned long) *this_cache);
1174 if (cache->prev_sp == 0)
1177 id = frame_id_build (cache->prev_sp, cache->pc);
1178 if (frame_id_eq (id, get_frame_id(next_frame)))
1181 Frame stack is corrupted. That could happen because of \
1182 setting register(s) from GDB or stopping execution \
1183 inside exception handler. Frame backtracing has stopped. \
1184 It can make some GDB commands work inappropriately.\n"));
1192 call0_frame_get_reg_at_entry (struct frame_info *next_frame,
1193 struct xtensa_frame_cache *cache,
1196 enum lval_type *lval,
1201 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1202 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1203 && regnum <= (gdbarch_tdep (gdbarch)->ar_base + C0_NREGS))
1204 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1206 /* Determine stack pointer on entry to this function, based on FP. */
1207 spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1209 /* If register was saved to the stack frame in the prologue, retrieve it. */
1210 stkofs = cache->c0.c0_rt[reg].to_stk;
1211 if (stkofs != C0_NOSTK)
1213 *lval = lval_memory;
1214 *addrp = spe + stkofs;
1217 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1222 /* If not callee-saved or if known to have been overwritten, give up. */
1224 || cache->c0.c0_rt[reg].fr_reg != reg
1225 || cache->c0.c0_rt[reg].fr_ofs != 0)
1228 if (get_frame_type (next_frame) != NORMAL_FRAME)
1229 /* TODO: Do we need a special case for DUMMY_FRAME here? */
1232 return call0_frame_get_reg_at_entry (get_next_frame(next_frame),
1233 cache, regnum, addrp, lval, valuep);
1237 xtensa_frame_prev_register (struct frame_info *next_frame,
1241 enum lval_type *lvalp,
1246 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1247 struct xtensa_frame_cache *cache =
1248 xtensa_frame_cache (next_frame, this_cache);
1249 CORE_ADDR saved_reg = 0;
1252 DEBUGTRACE ("xtensa_frame_prev_register (next 0x%lx, "
1253 "*this 0x%lx, regnum %d (%s), ...)\n",
1254 (unsigned long) next_frame,
1255 *this_cache ? (unsigned long) *this_cache : 0, regnum,
1256 xtensa_register_name (gdbarch, regnum));
1258 if (regnum ==gdbarch_pc_regnum (gdbarch))
1259 saved_reg = cache->ra;
1260 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1261 saved_reg = cache->prev_sp;
1262 else if (!cache->call0)
1264 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1266 if (cache->wd.ws != 0)
1267 saved_reg = cache->wd.ws;
1269 saved_reg = 1 << cache->wd.wb;
1271 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1272 saved_reg = cache->wd.wb;
1273 else if (regnum == gdbarch_ps_regnum (gdbarch))
1274 saved_reg = cache->ps;
1288 store_unsigned_integer (valuep, 4, saved_reg);
1293 if (!cache->call0) /* Windowed ABI. */
1295 /* Convert A-register numbers to AR-register numbers. */
1296 if (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0
1297 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1298 regnum = areg_number (gdbarch, regnum, cache->wd.wb);
1300 /* Check if AR-register has been saved to stack. */
1301 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1302 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1303 + gdbarch_tdep (gdbarch)->num_aregs))
1305 int areg = regnum - gdbarch_tdep (gdbarch)->ar_base
1306 - (cache->wd.wb * 4);
1309 && areg < XTENSA_NUM_SAVED_AREGS
1310 && cache->wd.aregs[areg] != -1)
1313 *lvalp = lval_memory;
1314 *addrp = cache->wd.aregs[areg];
1318 read_memory (*addrp, valuep,
1319 register_size (gdbarch, regnum));
1321 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1326 else /* Call0 ABI. */
1328 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1329 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1331 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1338 /* If register was saved in the prologue, retrieve it. */
1339 stkofs = cache->c0.c0_rt[reg].to_stk;
1340 if (stkofs != C0_NOSTK)
1342 /* Determine SP on entry based on FP. */
1343 spe = cache->c0.c0_fp
1344 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1346 *lvalp = lval_memory;
1347 *addrp = spe + stkofs;
1351 read_memory (*addrp, valuep,
1352 register_size (gdbarch, regnum));
1354 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1360 /* All other registers have been either saved to
1361 the stack or are still alive in the processor. */
1364 *lvalp = lval_register;
1368 frame_unwind_register (next_frame, (*realnump), valuep);
1372 static const struct frame_unwind
1373 xtensa_frame_unwind =
1376 xtensa_frame_this_id,
1377 xtensa_frame_prev_register
1380 static const struct frame_unwind *
1381 xtensa_frame_sniffer (struct frame_info *next_frame)
1383 return &xtensa_frame_unwind;
1387 xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache)
1389 struct xtensa_frame_cache *cache =
1390 xtensa_frame_cache (next_frame, this_cache);
1395 static const struct frame_base
1398 &xtensa_frame_unwind,
1399 xtensa_frame_base_address,
1400 xtensa_frame_base_address,
1401 xtensa_frame_base_address
1406 xtensa_extract_return_value (struct type *type,
1407 struct regcache *regcache,
1410 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1411 bfd_byte *valbuf = dst;
1412 int len = TYPE_LENGTH (type);
1417 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1419 gdb_assert(len > 0);
1421 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1423 /* First, we have to find the caller window in the register file. */
1424 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1425 callsize = extract_call_winsize (gdbarch, pc);
1427 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1428 if (len > (callsize > 8 ? 8 : 16))
1429 internal_error (__FILE__, __LINE__,
1430 _("cannot extract return value of %d bytes long"), len);
1432 /* Get the register offset of the return
1433 register (A2) in the caller window. */
1434 regcache_raw_read_unsigned
1435 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1436 areg = areg_number (gdbarch,
1437 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1441 /* No windowing hardware - Call0 ABI. */
1442 areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS;
1445 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1447 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1450 for (; len > 0; len -= 4, areg++, valbuf += 4)
1453 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1455 regcache_raw_read (regcache, areg, valbuf);
1461 xtensa_store_return_value (struct type *type,
1462 struct regcache *regcache,
1465 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1466 const bfd_byte *valbuf = dst;
1470 int len = TYPE_LENGTH (type);
1473 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1475 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1477 regcache_raw_read_unsigned
1478 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1479 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1480 callsize = extract_call_winsize (gdbarch, pc);
1482 if (len > (callsize > 8 ? 8 : 16))
1483 internal_error (__FILE__, __LINE__,
1484 _("unimplemented for this length: %d"),
1485 TYPE_LENGTH (type));
1486 areg = areg_number (gdbarch,
1487 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1489 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1490 callsize, (int) wb);
1494 areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS;
1497 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1500 for (; len > 0; len -= 4, areg++, valbuf += 4)
1503 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1505 regcache_raw_write (regcache, areg, valbuf);
1510 static enum return_value_convention
1511 xtensa_return_value (struct gdbarch *gdbarch,
1512 struct type *valtype,
1513 struct regcache *regcache,
1515 const gdb_byte *writebuf)
1517 /* Structures up to 16 bytes are returned in registers. */
1519 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1520 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1521 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1522 && TYPE_LENGTH (valtype) > 16);
1525 return RETURN_VALUE_STRUCT_CONVENTION;
1527 DEBUGTRACE ("xtensa_return_value(...)\n");
1529 if (writebuf != NULL)
1531 xtensa_store_return_value (valtype, regcache, writebuf);
1534 if (readbuf != NULL)
1536 gdb_assert (!struct_return);
1537 xtensa_extract_return_value (valtype, regcache, readbuf);
1539 return RETURN_VALUE_REGISTER_CONVENTION;
1546 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1547 struct value *function,
1548 struct regcache *regcache,
1551 struct value **args,
1554 CORE_ADDR struct_addr)
1557 int size, onstack_size;
1558 gdb_byte *buf = (gdb_byte *) alloca (16);
1560 struct argument_info
1562 const bfd_byte *contents;
1564 int onstack; /* onstack == 0 => in reg */
1565 int align; /* alignment */
1568 int offset; /* stack offset if on stack */
1569 int regno; /* regno if in register */
1573 struct argument_info *arg_info =
1574 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1578 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1580 if (xtensa_debug_level > 3)
1583 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1584 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1585 "struct_addr=0x%x\n",
1586 (int) sp, (int) struct_return, (int) struct_addr);
1588 for (i = 0; i < nargs; i++)
1590 struct value *arg = args[i];
1591 struct type *arg_type = check_typedef (value_type (arg));
1592 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
1593 i, (unsigned long) arg, TYPE_LENGTH (arg_type));
1594 switch (TYPE_CODE (arg_type))
1597 fprintf_unfiltered (gdb_stdlog, "int");
1599 case TYPE_CODE_STRUCT:
1600 fprintf_unfiltered (gdb_stdlog, "struct");
1603 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1606 fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
1607 (unsigned long) value_contents (arg));
1611 /* First loop: collect information.
1612 Cast into type_long. (This shouldn't happen often for C because
1613 GDB already does this earlier.) It's possible that GDB could
1614 do it all the time but it's harmless to leave this code here. */
1621 size = REGISTER_SIZE;
1623 for (i = 0; i < nargs; i++)
1625 struct argument_info *info = &arg_info[i];
1626 struct value *arg = args[i];
1627 struct type *arg_type = check_typedef (value_type (arg));
1629 switch (TYPE_CODE (arg_type))
1632 case TYPE_CODE_BOOL:
1633 case TYPE_CODE_CHAR:
1634 case TYPE_CODE_RANGE:
1635 case TYPE_CODE_ENUM:
1637 /* Cast argument to long if necessary as the mask does it too. */
1638 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1640 arg_type = builtin_type_long;
1641 arg = value_cast (arg_type, arg);
1643 /* Aligment is equal to the type length for the basic types. */
1644 info->align = TYPE_LENGTH (arg_type);
1649 /* Align doubles correctly. */
1650 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1651 info->align = TYPE_LENGTH (builtin_type_double);
1653 info->align = TYPE_LENGTH (builtin_type_long);
1656 case TYPE_CODE_STRUCT:
1658 info->align = TYPE_LENGTH (builtin_type_long);
1661 info->length = TYPE_LENGTH (arg_type);
1662 info->contents = value_contents (arg);
1664 /* Align size and onstack_size. */
1665 size = (size + info->align - 1) & ~(info->align - 1);
1666 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1668 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1671 info->u.offset = onstack_size;
1672 onstack_size += info->length;
1677 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1679 size += info->length;
1682 /* Adjust the stack pointer and align it. */
1683 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1685 /* Simulate MOVSP, if Windowed ABI. */
1686 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1689 read_memory (osp - 16, buf, 16);
1690 write_memory (sp - 16, buf, 16);
1693 /* Second Loop: Load arguments. */
1697 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1698 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1701 for (i = 0; i < nargs; i++)
1703 struct argument_info *info = &arg_info[i];
1707 int n = info->length;
1708 CORE_ADDR offset = sp + info->u.offset;
1710 /* Odd-sized structs are aligned to the lower side of a memory
1711 word in big-endian mode and require a shift. This only
1712 applies for structures smaller than one word. */
1714 if (n < REGISTER_SIZE
1715 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1716 offset += (REGISTER_SIZE - n);
1718 write_memory (offset, info->contents, info->length);
1723 int n = info->length;
1724 const bfd_byte *cp = info->contents;
1725 int r = info->u.regno;
1727 /* Odd-sized structs are aligned to the lower side of registers in
1728 big-endian mode and require a shift. The odd-sized leftover will
1729 be at the end. Note that this is only true for structures smaller
1730 than REGISTER_SIZE; for larger odd-sized structures the excess
1731 will be left-aligned in the register on both endiannesses. */
1733 if (n < REGISTER_SIZE
1734 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1736 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1737 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1739 store_unsigned_integer (buf, REGISTER_SIZE, v);
1740 regcache_cooked_write (regcache, r, buf);
1742 cp += REGISTER_SIZE;
1749 regcache_cooked_write (regcache, r, cp);
1751 cp += REGISTER_SIZE;
1758 /* Set the return address of dummy frame to the dummy address.
1759 The return address for the current function (in A0) is
1760 saved in the dummy frame, so we can savely overwrite A0 here. */
1762 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1764 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1765 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
1766 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1767 regcache_cooked_write_unsigned
1768 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1769 regcache_cooked_write_unsigned (regcache,
1770 gdbarch_ps_regnum (gdbarch),
1775 /* Simulate CALL0: write RA into A0 register. */
1776 regcache_cooked_write_unsigned
1777 (regcache, gdbarch_tdep (gdbarch)->a0_base + 0, bp_addr);
1780 /* Set new stack pointer and return it. */
1781 regcache_cooked_write_unsigned (regcache,
1782 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1783 /* Make dummy frame ID unique by adding a constant. */
1784 return sp + SP_ALIGNMENT;
1788 /* Return a breakpoint for the current location of PC. We always use
1789 the density version if we have density instructions (regardless of the
1790 current instruction at PC), and use regular instructions otherwise. */
1792 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1793 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1794 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1795 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1797 static const unsigned char *
1798 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1801 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1802 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1803 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1804 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1806 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1808 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1810 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1812 *lenptr = sizeof (density_big_breakpoint);
1813 return density_big_breakpoint;
1817 *lenptr = sizeof (density_little_breakpoint);
1818 return density_little_breakpoint;
1823 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1825 *lenptr = sizeof (big_breakpoint);
1826 return big_breakpoint;
1830 *lenptr = sizeof (little_breakpoint);
1831 return little_breakpoint;
1836 /* Call0 ABI support routines. */
1838 /* Call0 opcode class. Opcodes are preclassified according to what they
1839 mean for Call0 prologue analysis, and their number of significant operands.
1840 The purpose of this is to simplify prologue analysis by separating
1841 instruction decoding (libisa) from the semantics of prologue analysis. */
1844 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1845 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1846 c0opc_flow, /* Flow control insn. */
1847 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1848 c0opc_break, /* Debugger software breakpoints. */
1849 c0opc_add, /* Adding two registers. */
1850 c0opc_addi, /* Adding a register and an immediate. */
1851 c0opc_sub, /* Subtracting a register from a register. */
1852 c0opc_mov, /* Moving a register to a register. */
1853 c0opc_movi, /* Moving an immediate to a register. */
1854 c0opc_l32r, /* Loading a literal. */
1855 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1856 c0opc_NrOf /* Number of opcode classifications. */
1860 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1862 static xtensa_insn_kind
1863 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1865 const char *opcname;
1866 xtensa_insn_kind opclass = c0opc_uninteresting;
1868 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1870 /* Get opcode name and handle special classifications. */
1872 opcname = xtensa_opcode_name (isa, opc);
1875 || strcasecmp (opcname, "ill") == 0
1876 || strcasecmp (opcname, "ill.n") == 0)
1877 opclass = c0opc_illegal;
1878 else if (strcasecmp (opcname, "break") == 0
1879 || strcasecmp (opcname, "break.n") == 0)
1880 opclass = c0opc_break;
1881 else if (strcasecmp (opcname, "entry") == 0)
1882 opclass = c0opc_entry;
1883 else if (xtensa_opcode_is_branch (isa, opc) > 0
1884 || xtensa_opcode_is_jump (isa, opc) > 0
1885 || xtensa_opcode_is_loop (isa, opc) > 0
1886 || xtensa_opcode_is_call (isa, opc) > 0
1887 || strcasecmp (opcname, "simcall") == 0
1888 || strcasecmp (opcname, "syscall") == 0)
1889 opclass = c0opc_flow;
1891 /* Also, classify specific opcodes that need to be tracked. */
1892 else if (strcasecmp (opcname, "add") == 0
1893 || strcasecmp (opcname, "add.n") == 0)
1894 opclass = c0opc_add;
1895 else if (strcasecmp (opcname, "addi") == 0
1896 || strcasecmp (opcname, "addi.n") == 0
1897 || strcasecmp (opcname, "addmi") == 0)
1898 opclass = c0opc_addi;
1899 else if (strcasecmp (opcname, "sub") == 0)
1900 opclass = c0opc_sub;
1901 else if (strcasecmp (opcname, "mov.n") == 0
1902 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1903 opclass = c0opc_mov;
1904 else if (strcasecmp (opcname, "movi") == 0
1905 || strcasecmp (opcname, "movi.n") == 0)
1906 opclass = c0opc_movi;
1907 else if (strcasecmp (opcname, "l32r") == 0)
1908 opclass = c0opc_l32r;
1909 else if (strcasecmp (opcname, "s32i") == 0
1910 || strcasecmp (opcname, "s32i.n") == 0)
1911 opclass = c0opc_s32i;
1916 /* Tracks register movement/mutation for a given operation, which may
1917 be within a bundle. Updates the destination register tracking info
1918 accordingly. The pc is needed only for pc-relative load instructions
1919 (eg. l32r). The SP register number is needed to identify stores to
1923 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1924 xtensa_insn_kind opclass, int nods, unsigned odv[],
1925 CORE_ADDR pc, int spreg)
1927 unsigned litbase, litaddr, litval;
1932 /* 3 operands: dst, src, imm. */
1933 gdb_assert (nods == 3);
1934 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1935 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1938 /* 3 operands: dst, src1, src2. */
1939 gdb_assert (nods == 3);
1940 if (src[odv[1]].fr_reg == C0_CONST)
1942 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
1943 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
1945 else if (src[odv[2]].fr_reg == C0_CONST)
1947 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1948 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
1950 else dst[odv[0]].fr_reg = C0_INEXP;
1953 /* 3 operands: dst, src1, src2. */
1954 gdb_assert (nods == 3);
1955 if (src[odv[2]].fr_reg == C0_CONST)
1957 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1958 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
1960 else dst[odv[0]].fr_reg = C0_INEXP;
1963 /* 2 operands: dst, src [, src]. */
1964 gdb_assert (nods == 2);
1965 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1966 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
1969 /* 2 operands: dst, imm. */
1970 gdb_assert (nods == 2);
1971 dst[odv[0]].fr_reg = C0_CONST;
1972 dst[odv[0]].fr_ofs = odv[1];
1975 /* 2 operands: dst, literal offset. */
1976 gdb_assert (nods == 2);
1977 /* litbase = xtensa_get_litbase (pc); can be also used. */
1978 litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1)
1979 ? 0 : xtensa_read_register
1980 (gdbarch_tdep (current_gdbarch)->litbase_regnum);
1981 litaddr = litbase & 1
1982 ? (litbase & ~1) + (signed)odv[1]
1983 : (pc + 3 + (signed)odv[1]) & ~3;
1984 litval = read_memory_integer(litaddr, 4);
1985 dst[odv[0]].fr_reg = C0_CONST;
1986 dst[odv[0]].fr_ofs = litval;
1989 /* 3 operands: value, base, offset. */
1990 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
1991 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
1992 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
1993 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
1994 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
1995 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
1997 /* ISA encoding guarantees alignment. But, check it anyway. */
1998 gdb_assert ((odv[2] & 3) == 0);
1999 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2007 /* Analyze prologue of the function at start address to determine if it uses
2008 the Call0 ABI, and if so track register moves and linear modifications
2009 in the prologue up to the PC or just beyond the prologue, whichever is first.
2010 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2011 The prologue may overlap non-prologue instructions but is guaranteed to end
2012 by the first flow-control instruction (jump, branch, call or return).
2013 Since an optimized function may move information around and change the
2014 stack frame arbitrarily during the prologue, the information is guaranteed
2015 valid only at the point in the function indicated by the PC.
2016 May be used to skip the prologue or identify the ABI, w/o tracking.
2018 Returns: Address of first instruction after prologue, or PC (whichever
2019 is first), or 0, if decoding failed (in libisa).
2021 start Start address of function/prologue.
2022 pc Program counter to stop at. Use 0 to continue to end of prologue.
2023 If 0, avoids infinite run-on in corrupt code memory by bounding
2024 the scan to the end of the function if that can be determined.
2025 nregs Number of general registers to track (size of rt[] array).
2027 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2028 If NULL, registers are not tracked.
2030 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2031 (more accurately, non-zero until 'entry' insn is encountered).
2033 Note that these may produce useful results even if decoding fails
2034 because they begin with default assumptions that analysis may change. */
2037 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
2038 int nregs, xtensa_c0reg_t rt[], int *call0)
2040 CORE_ADDR ia; /* Current insn address in prologue. */
2041 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2042 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2043 #define BSZ 32 /* Instruction buffer size. */
2044 char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
2045 xtensa_isa isa; /* libisa ISA handle. */
2046 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2047 xtensa_format ifmt; /* libisa instruction format. */
2048 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2049 xtensa_opcode opc; /* Opcode in current slot. */
2050 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2051 int nods; /* Opcode number of operands. */
2052 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2053 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2054 int j; /* General loop counter. */
2055 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2056 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2057 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2059 struct symtab_and_line prologue_sal;
2061 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2062 (int)start, (int)pc);
2064 /* Try to limit the scan to the end of the function if a non-zero pc
2065 arg was not supplied to avoid probing beyond the end of valid memory.
2066 If memory is full of garbage that classifies as c0opc_uninteresting.
2067 If this fails (eg. if no symbols) pc ends up 0 as it was.
2068 Intialize the Call0 frame and register tracking info.
2069 Assume it's Call0 until an 'entry' instruction is encountered.
2070 Assume we may be in the prologue until we hit a flow control instr. */
2076 /* Find out, if we have an information about the prologue from DWARF. */
2077 prologue_sal = find_pc_line (start, 0);
2078 if (prologue_sal.line != 0) /* Found debug info. */
2079 body_pc = prologue_sal.end;
2081 /* If we are going to analyze the prologue in general without knowing about
2082 the current PC, make the best assumtion for the end of the prologue. */
2085 find_pc_partial_function (start, 0, NULL, &end_pc);
2086 body_pc = min (end_pc, body_pc);
2089 body_pc = min (pc, body_pc);
2096 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2097 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2101 isa = xtensa_default_isa;
2102 gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
2103 ins = xtensa_insnbuf_alloc (isa);
2104 slot = xtensa_insnbuf_alloc (isa);
2106 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2108 /* (Re)fill instruction buffer from memory if necessary, but do not
2109 read memory beyond PC to be sure we stay within text section
2110 (this protection only works if a non-zero pc is supplied). */
2112 if (ia + xtensa_isa_maxlength (isa) > bt)
2115 bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
2116 read_memory (ba, ibuf, bt - ba);
2119 /* Decode format information. */
2121 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2122 ifmt = xtensa_format_decode (isa, ins);
2123 if (ifmt == XTENSA_UNDEFINED)
2128 ilen = xtensa_format_length (isa, ifmt);
2129 if (ilen == XTENSA_UNDEFINED)
2134 islots = xtensa_format_num_slots (isa, ifmt);
2135 if (islots == XTENSA_UNDEFINED)
2141 /* Analyze a bundle or a single instruction, using a snapshot of
2142 the register tracking info as input for the entire bundle so that
2143 register changes do not take effect within this bundle. */
2145 for (j = 0; j < nregs; ++j)
2148 for (is = 0; is < islots; ++is)
2150 /* Decode a slot and classify the opcode. */
2152 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2156 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2157 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2159 if (opc == XTENSA_UNDEFINED)
2160 opclass = c0opc_illegal;
2162 opclass = call0_classify_opcode (isa, opc);
2164 /* Decide whether to track this opcode, ignore it, or bail out. */
2173 case c0opc_uninteresting:
2182 ia += ilen; /* Skip over 'entry' insn. */
2190 /* Only expected opcodes should get this far. */
2194 /* Extract and decode the operands. */
2195 nods = xtensa_opcode_num_operands (isa, opc);
2196 if (nods == XTENSA_UNDEFINED)
2202 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2204 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2209 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2214 /* Check operands to verify use of 'mov' assembler macro. */
2215 if (opclass == c0opc_mov && nods == 3)
2217 if (odv[2] == odv[1])
2221 opclass = c0opc_uninteresting;
2226 /* Track register movement and modification for this operation. */
2227 call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
2231 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2232 (unsigned)ia, fail ? "failed" : "succeeded");
2233 xtensa_insnbuf_free(isa, slot);
2234 xtensa_insnbuf_free(isa, ins);
2235 return fail ? 0 : ia;
2238 /* Initialize frame cache for the current frame. The "next_frame" is the next
2239 one relative to current frame. "cache" is the pointer to the data structure
2240 we have to initialize. "pc" is curretnt PC. */
2243 call0_frame_cache (struct frame_info *next_frame,
2244 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2246 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2247 CORE_ADDR start_pc; /* The beginning of the function. */
2248 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2249 CORE_ADDR sp, fp, ra;
2250 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2252 /* Find the beginning of the prologue of the function containing the PC
2253 and analyze it up to the PC or the end of the prologue. */
2255 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2257 body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
2258 &cache->c0.c0_rt[0],
2262 sp = frame_unwind_register_unsigned
2263 (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2264 fp = sp; /* Assume FP == SP until proven otherwise. */
2266 /* Get the frame information and FP (if used) at the current PC.
2267 If PC is in the prologue, the prologue analysis is more reliable
2268 than DWARF info. We don't not know for sure if PC is in the prologue,
2269 but we know no calls have yet taken place, so we can almost
2270 certainly rely on the prologue analysis. */
2274 /* Prologue analysis was successful up to the PC.
2275 It includes the cases when PC == START_PC. */
2276 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2277 /* c0_hasfp == true means there is a frame pointer because
2278 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2279 was derived from SP. Otherwise, it would be C0_FP. */
2280 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2281 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2282 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2284 else /* No data from the prologue analysis. */
2287 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2292 prev_sp = fp + c0_frmsz;
2294 /* Frame size from debug info or prologue tracking does not account for
2295 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2298 fp = frame_unwind_register_unsigned (next_frame, fp_regnum);
2300 /* Recalculate previous SP. */
2301 prev_sp = fp + c0_frmsz;
2302 /* Update the stack frame size. */
2303 c0_frmsz += fp - sp;
2306 /* Get the return address (RA) from the stack if saved,
2307 or try to get it from a register. */
2309 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2310 if (to_stk != C0_NOSTK)
2312 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2314 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2315 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2317 /* Special case for terminating backtrace at a function that wants to
2318 be seen as the outermost. Such a function will clear it's RA (A0)
2319 register to 0 in the prologue instead of saving its original value. */
2324 /* RA was copied to another register or (before any function call) may
2325 still be in the original RA register. This is not always reliable:
2326 even in a leaf function, register tracking stops after prologue, and
2327 even in prologue, non-prologue instructions (not tracked) may overwrite
2328 RA or any register it was copied to. If likely in prologue or before
2329 any call, use retracking info and hope for the best (compiler should
2330 have saved RA in stack if not in a leaf function). If not in prologue,
2336 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2338 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2340 if (i < C0_NREGS) /* Read from the next_frame. */
2342 ra = frame_unwind_register_unsigned
2344 gdbarch_tdep (gdbarch)->a0_base + 0
2345 + cache->c0.c0_rt[i].fr_reg);
2350 cache->pc = start_pc;
2352 /* RA == 0 marks the outermost frame. Do not go past it. */
2353 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2354 cache->c0.fp_regnum = fp_regnum;
2355 cache->c0.c0_frmsz = c0_frmsz;
2356 cache->c0.c0_hasfp = c0_hasfp;
2357 cache->c0.c0_fp = fp;
2361 /* Skip function prologue.
2363 Return the pc of the first instruction after prologue. GDB calls this to
2364 find the address of the first line of the function or (if there is no line
2365 number information) to skip the prologue for planting breakpoints on
2366 function entries. Use debug info (if present) or prologue analysis to skip
2367 the prologue to achieve reliable debugging behavior. For windowed ABI,
2368 only the 'entry' instruction is skipped. It is not strictly necessary to
2369 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2370 backtrace at any point in the prologue, however certain potential hazards
2371 are avoided and a more "normal" debugging experience is ensured by
2372 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2373 For example, if we don't skip the prologue:
2374 - Some args may not yet have been saved to the stack where the debug
2375 info expects to find them (true anyway when only 'entry' is skipped);
2376 - Software breakpoints ('break' instrs) may not have been unplanted
2377 when the prologue analysis is done on initializing the frame cache,
2378 and breaks in the prologue will throw off the analysis.
2380 If we have debug info ( line-number info, in particular ) we simply skip
2381 the code associated with the first function line effectively skipping
2382 the prologue code. It works even in cases like
2385 { int local_var = 1;
2389 because, for this source code, both Xtensa compilers will generate two
2390 separate entries ( with the same line number ) in dwarf line-number
2391 section to make sure there is a boundary between the prologue code and
2392 the rest of the function.
2394 If there is no debug info, we need to analyze the code. */
2396 /* #define DONT_SKIP_PROLOGUE */
2399 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2401 struct symtab_and_line prologue_sal;
2404 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2406 #if DONT_SKIP_PROLOGUE
2410 /* Try to find first body line from debug info. */
2412 prologue_sal = find_pc_line (start_pc, 0);
2413 if (prologue_sal.line != 0) /* Found debug info. */
2415 /* In Call0, it is possible to have a function with only one instruction
2416 ('ret') resulting from a 1-line optimized function that does nothing.
2417 In that case, prologue_sal.end may actually point to the start of the
2418 next function in the text section, causing a breakpoint to be set at
2419 the wrong place. Check if the end address is in a different function,
2420 and if so return the start PC. We know we have symbol info. */
2424 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2425 if (end_func != start_pc)
2428 return prologue_sal.end;
2431 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2432 body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
2433 return body_pc != 0 ? body_pc : start_pc;
2436 /* Verify the current configuration. */
2438 xtensa_verify_config (struct gdbarch *gdbarch)
2440 struct ui_file *log;
2441 struct cleanup *cleanups;
2442 struct gdbarch_tdep *tdep;
2446 tdep = gdbarch_tdep (gdbarch);
2447 log = mem_fileopen ();
2448 cleanups = make_cleanup_ui_file_delete (log);
2450 /* Verify that we got a reasonable number of AREGS. */
2451 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2452 fprintf_unfiltered (log, _("\
2453 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2456 /* Verify that certain registers exist. */
2458 if (tdep->pc_regnum == -1)
2459 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2460 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2461 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2463 if (tdep->isa_use_windowed_registers)
2465 if (tdep->wb_regnum == -1)
2466 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2467 if (tdep->ws_regnum == -1)
2468 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2469 if (tdep->ar_base == -1)
2470 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2473 if (tdep->a0_base == -1)
2474 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2476 buf = ui_file_xstrdup (log, &dummy);
2477 make_cleanup (xfree, buf);
2478 if (strlen (buf) > 0)
2479 internal_error (__FILE__, __LINE__,
2480 _("the following are invalid: %s"), buf);
2481 do_cleanups (cleanups);
2484 /* Module "constructor" function. */
2486 static struct gdbarch *
2487 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2489 struct gdbarch_tdep *tdep;
2490 struct gdbarch *gdbarch;
2491 struct xtensa_abi_handler *abi_handler;
2493 DEBUGTRACE ("gdbarch_init()\n");
2495 /* We have to set the byte order before we call gdbarch_alloc. */
2496 info.byte_order = xtensa_config_byte_order (&info);
2498 tdep = xtensa_config_tdep (&info);
2499 gdbarch = gdbarch_alloc (&info, tdep);
2501 /* Verify our configuration. */
2502 xtensa_verify_config (gdbarch);
2504 /* Pseudo-Register read/write. */
2505 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2506 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2508 /* Set target information. */
2509 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2510 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2511 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2512 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2513 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2515 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
2516 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2517 set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2518 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2520 /* We provide our own function to get register information. */
2521 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2522 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2524 /* To call functions from GDB using dummy frame */
2525 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2527 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2529 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2531 /* Advance PC across any prologue instructions to reach "real" code. */
2532 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2534 /* Stack grows downward. */
2535 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2537 /* Set breakpoints. */
2538 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2540 /* After breakpoint instruction or illegal instruction, pc still
2541 points at break instruction, so don't decrement. */
2542 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2544 /* We don't skip args. */
2545 set_gdbarch_frame_args_skip (gdbarch, 0);
2547 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2549 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2551 set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id);
2553 /* Frame handling. */
2554 frame_base_set_default (gdbarch, &xtensa_frame_base);
2555 frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer);
2557 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2559 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2561 xtensa_add_reggroups (gdbarch);
2562 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2564 set_gdbarch_regset_from_core_section (gdbarch,
2565 xtensa_regset_from_core_section);
2571 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2573 error (_("xtensa_dump_tdep(): not implemented"));
2577 _initialize_xtensa_tdep (void)
2579 struct cmd_list_element *c;
2581 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2582 xtensa_init_reggroups ();
2584 add_setshow_zinteger_cmd ("xtensa",
2586 &xtensa_debug_level, _("\
2587 Set Xtensa debugging."), _("\
2588 Show Xtensa debugging."), _("\
2589 When non-zero, Xtensa-specific debugging is enabled. \
2590 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2593 &setdebuglist, &showdebuglist);