1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
142 arreg = a_regnum - tdep->a0_base;
143 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
144 arreg &= tdep->num_aregs - 1;
146 return arreg + tdep->ar_base;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 areg = ar_regnum - tdep->ar_base;
158 if (areg < 0 || areg >= tdep->num_aregs)
160 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
161 return (areg > 15) ? -1 : areg;
164 static inline unsigned long
165 xtensa_read_register (int regnum)
169 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
170 return (unsigned long) value;
174 xtensa_write_register (int regnum, ULONGEST value)
176 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
179 /* Return the window size of the previous call to the function from which we
182 This function is used to extract the return value after a called function
183 has returned to the caller. On Xtensa, the register that holds the return
184 value (from the perspective of the caller) depends on what call
185 instruction was used. For now, we are assuming that the call instruction
186 precedes the current address, so we simply analyze the call instruction.
187 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
188 method to call the inferior function. */
191 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
193 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
198 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
200 /* Read the previous instruction (should be a call[x]{4|8|12}. */
201 read_memory (pc-3, buf, 3);
202 insn = extract_unsigned_integer (buf, 3, byte_order);
204 /* Decode call instruction:
206 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
207 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
209 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
210 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
212 if (byte_order == BFD_ENDIAN_LITTLE)
214 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
215 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
219 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
220 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
226 /* REGISTER INFORMATION */
228 /* Find register by name. */
230 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
234 for (i = 0; i < gdbarch_num_regs (gdbarch)
235 + gdbarch_num_pseudo_regs (gdbarch);
238 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
244 /* Returns the name of a register. */
246 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
248 /* Return the name stored in the register map. */
249 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
250 + gdbarch_num_pseudo_regs (gdbarch))
251 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
253 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
257 /* Return the type of a register. Create a new type, if necessary. */
260 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
264 /* Return signed integer for ARx and Ax registers. */
265 if ((regnum >= tdep->ar_base
266 && regnum < tdep->ar_base + tdep->num_aregs)
267 || (regnum >= tdep->a0_base
268 && regnum < tdep->a0_base + 16))
269 return builtin_type (gdbarch)->builtin_int;
271 if (regnum == gdbarch_pc_regnum (gdbarch)
272 || regnum == tdep->a0_base + 1)
273 return builtin_type (gdbarch)->builtin_data_ptr;
275 /* Return the stored type for all other registers. */
276 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
277 + gdbarch_num_pseudo_regs (gdbarch))
279 xtensa_register_t* reg = &tdep->regmap[regnum];
281 /* Set ctype for this register (only the first time). */
285 struct ctype_cache *tp;
286 int size = reg->byte_size;
288 /* We always use the memory representation,
289 even if the register width is smaller. */
293 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
297 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
301 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
305 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
309 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
313 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
314 if (tp->size == size)
319 char *name = xmalloc (16);
320 tp = xmalloc (sizeof (struct ctype_cache));
321 tp->next = tdep->type_entries;
322 tdep->type_entries = tp;
325 sprintf (name, "int%d", size * 8);
327 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
330 reg->ctype = tp->virtual_type;
336 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
341 /* Return the 'local' register number for stubs, dwarf2, etc.
342 The debugging information enumerates registers starting from 0 for A0
343 to n for An. So, we only have to add the base number for A0. */
346 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
350 if (regnum >= 0 && regnum < 16)
351 return gdbarch_tdep (gdbarch)->a0_base + regnum;
354 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
356 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
359 internal_error (__FILE__, __LINE__,
360 _("invalid dwarf/stabs register number %d"), regnum);
365 /* Write the bits of a masked register to the various registers.
366 Only the masked areas of these registers are modified; the other
367 fields are untouched. The size of masked registers is always less
368 than or equal to 32 bits. */
371 xtensa_register_write_masked (struct regcache *regcache,
372 xtensa_register_t *reg, const gdb_byte *buffer)
374 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
375 const xtensa_mask_t *mask = reg->mask;
377 int shift = 0; /* Shift for next mask (mod 32). */
378 int start, size; /* Start bit and size of current mask. */
380 unsigned int *ptr = value;
381 unsigned int regval, m, mem = 0;
383 int bytesize = reg->byte_size;
384 int bitsize = bytesize * 8;
387 DEBUGTRACE ("xtensa_register_write_masked ()\n");
389 /* Copy the masked register to host byte-order. */
390 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
391 for (i = 0; i < bytesize; i++)
394 mem |= (buffer[bytesize - i - 1] << 24);
399 for (i = 0; i < bytesize; i++)
402 mem |= (buffer[i] << 24);
407 /* We might have to shift the final value:
408 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
409 bytesize & 3 == x -> shift (4-x) * 8. */
411 *ptr = mem >> (((0 - bytesize) & 3) * 8);
415 /* Write the bits to the masked areas of the other registers. */
416 for (i = 0; i < mask->count; i++)
418 start = mask->mask[i].bit_start;
419 size = mask->mask[i].bit_size;
420 regval = mem >> shift;
422 if ((shift += size) > bitsize)
423 error (_("size of all masks is larger than the register"));
432 regval |= mem << (size - shift);
435 /* Make sure we have a valid register. */
436 r = mask->mask[i].reg_num;
437 if (r >= 0 && size > 0)
439 /* Don't overwrite the unmasked areas. */
441 regcache_cooked_read_unsigned (regcache, r, &old_val);
442 m = 0xffffffff >> (32 - size) << start;
444 regval = (regval & m) | (old_val & ~m);
445 regcache_cooked_write_unsigned (regcache, r, regval);
451 /* Read a tie state or mapped registers. Read the masked areas
452 of the registers and assemble them into a single value. */
455 xtensa_register_read_masked (struct regcache *regcache,
456 xtensa_register_t *reg, gdb_byte *buffer)
458 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
459 const xtensa_mask_t *mask = reg->mask;
464 unsigned int *ptr = value;
465 unsigned int regval, mem = 0;
467 int bytesize = reg->byte_size;
468 int bitsize = bytesize * 8;
471 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
472 reg->name == 0 ? "" : reg->name);
474 /* Assemble the register from the masked areas of other registers. */
475 for (i = 0; i < mask->count; i++)
477 int r = mask->mask[i].reg_num;
481 regcache_cooked_read_unsigned (regcache, r, &val);
482 regval = (unsigned int) val;
487 start = mask->mask[i].bit_start;
488 size = mask->mask[i].bit_size;
493 regval &= (0xffffffff >> (32 - size));
495 mem |= regval << shift;
497 if ((shift += size) > bitsize)
498 error (_("size of all masks is larger than the register"));
509 mem = regval >> (size - shift);
516 /* Copy value to target byte order. */
520 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
521 for (i = 0; i < bytesize; i++)
525 buffer[bytesize - i - 1] = mem & 0xff;
529 for (i = 0; i < bytesize; i++)
533 buffer[i] = mem & 0xff;
539 /* Read pseudo registers. */
542 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
543 struct regcache *regcache,
547 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
549 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
550 regnum, xtensa_register_name (gdbarch, regnum));
552 if (regnum == gdbarch_num_regs (gdbarch)
553 + gdbarch_num_pseudo_regs (gdbarch) - 1)
554 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
556 /* Read aliases a0..a15, if this is a Windowed ABI. */
557 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
558 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
559 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
561 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
563 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
564 regnum = arreg_number (gdbarch, regnum,
565 extract_unsigned_integer (buf, 4, byte_order));
568 /* We can always read non-pseudo registers. */
569 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
570 regcache_raw_read (regcache, regnum, buffer);
573 /* We have to find out how to deal with priveleged registers.
574 Let's treat them as pseudo-registers, but we cannot read/write them. */
576 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
578 buffer[0] = (gdb_byte)0;
579 buffer[1] = (gdb_byte)0;
580 buffer[2] = (gdb_byte)0;
581 buffer[3] = (gdb_byte)0;
583 /* Pseudo registers. */
585 && regnum < gdbarch_num_regs (gdbarch)
586 + gdbarch_num_pseudo_regs (gdbarch))
588 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
589 xtensa_register_type_t type = reg->type;
590 int flags = gdbarch_tdep (gdbarch)->target_flags;
592 /* We cannot read Unknown or Unmapped registers. */
593 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
595 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
597 warning (_("cannot read register %s"),
598 xtensa_register_name (gdbarch, regnum));
603 /* Some targets cannot read TIE register files. */
604 else if (type == xtRegisterTypeTieRegfile)
606 /* Use 'fetch' to get register? */
607 if (flags & xtTargetFlagsUseFetchStore)
609 warning (_("cannot read register"));
613 /* On some targets (esp. simulators), we can always read the reg. */
614 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
616 warning (_("cannot read register"));
621 /* We can always read mapped registers. */
622 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
624 xtensa_register_read_masked (regcache, reg, buffer);
628 /* Assume that we can read the register. */
629 regcache_raw_read (regcache, regnum, buffer);
632 internal_error (__FILE__, __LINE__,
633 _("invalid register number %d"), regnum);
637 /* Write pseudo registers. */
640 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
641 struct regcache *regcache,
643 const gdb_byte *buffer)
645 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
647 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
648 regnum, xtensa_register_name (gdbarch, regnum));
650 if (regnum == gdbarch_num_regs (gdbarch)
651 + gdbarch_num_pseudo_regs (gdbarch) -1)
652 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
654 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
655 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
656 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
657 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
659 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
662 regcache_raw_read (regcache,
663 gdbarch_tdep (gdbarch)->wb_regnum, buf);
664 regnum = arreg_number (gdbarch, regnum,
665 extract_unsigned_integer (buf, 4, byte_order));
668 /* We can always write 'core' registers.
669 Note: We might have converted Ax->ARy. */
670 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
671 regcache_raw_write (regcache, regnum, buffer);
673 /* We have to find out how to deal with priveleged registers.
674 Let's treat them as pseudo-registers, but we cannot read/write them. */
676 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
680 /* Pseudo registers. */
682 && regnum < gdbarch_num_regs (gdbarch)
683 + gdbarch_num_pseudo_regs (gdbarch))
685 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
686 xtensa_register_type_t type = reg->type;
687 int flags = gdbarch_tdep (gdbarch)->target_flags;
689 /* On most targets, we cannot write registers
690 of type "Unknown" or "Unmapped". */
691 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
693 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
695 warning (_("cannot write register %s"),
696 xtensa_register_name (gdbarch, regnum));
701 /* Some targets cannot read TIE register files. */
702 else if (type == xtRegisterTypeTieRegfile)
704 /* Use 'store' to get register? */
705 if (flags & xtTargetFlagsUseFetchStore)
707 warning (_("cannot write register"));
711 /* On some targets (esp. simulators), we can always write
713 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
715 warning (_("cannot write register"));
720 /* We can always write mapped registers. */
721 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
723 xtensa_register_write_masked (regcache, reg, buffer);
727 /* Assume that we can write the register. */
728 regcache_raw_write (regcache, regnum, buffer);
731 internal_error (__FILE__, __LINE__,
732 _("invalid register number %d"), regnum);
735 static inline char xtensa_hextochar (int xdigit)
737 static char hex[]="0123456789abcdef";
739 return hex[xdigit & 0x0f];
742 static struct reggroup *xtensa_ar_reggroup;
743 static struct reggroup *xtensa_user_reggroup;
744 static struct reggroup *xtensa_vectra_reggroup;
745 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
748 xtensa_init_reggroups (void)
751 char cpname[] = "cp0";
753 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
754 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
755 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
757 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
759 cpname[2] = xtensa_hextochar (i);
760 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
765 xtensa_add_reggroups (struct gdbarch *gdbarch)
769 /* Predefined groups. */
770 reggroup_add (gdbarch, all_reggroup);
771 reggroup_add (gdbarch, save_reggroup);
772 reggroup_add (gdbarch, restore_reggroup);
773 reggroup_add (gdbarch, system_reggroup);
774 reggroup_add (gdbarch, vector_reggroup);
775 reggroup_add (gdbarch, general_reggroup);
776 reggroup_add (gdbarch, float_reggroup);
778 /* Xtensa-specific groups. */
779 reggroup_add (gdbarch, xtensa_ar_reggroup);
780 reggroup_add (gdbarch, xtensa_user_reggroup);
781 reggroup_add (gdbarch, xtensa_vectra_reggroup);
783 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
784 reggroup_add (gdbarch, xtensa_cp[i]);
788 xtensa_coprocessor_register_group (struct reggroup *group)
792 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
793 if (group == xtensa_cp[i])
799 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
800 | XTENSA_REGISTER_FLAGS_WRITABLE \
801 | XTENSA_REGISTER_FLAGS_VOLATILE)
803 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
804 | XTENSA_REGISTER_FLAGS_WRITABLE)
807 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
809 struct reggroup *group)
811 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
812 xtensa_register_type_t type = reg->type;
813 xtensa_register_group_t rg = reg->group;
816 if (group == save_reggroup)
817 /* Every single register should be included into the list of registers
818 to be watched for changes while using -data-list-changed-registers. */
821 /* First, skip registers that are not visible to this target
822 (unknown and unmapped registers when not using ISS). */
824 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
826 if (group == all_reggroup)
828 if (group == xtensa_ar_reggroup)
829 return rg & xtRegisterGroupAddrReg;
830 if (group == xtensa_user_reggroup)
831 return rg & xtRegisterGroupUser;
832 if (group == float_reggroup)
833 return rg & xtRegisterGroupFloat;
834 if (group == general_reggroup)
835 return rg & xtRegisterGroupGeneral;
836 if (group == system_reggroup)
837 return rg & xtRegisterGroupState;
838 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
839 return rg & xtRegisterGroupVectra;
840 if (group == restore_reggroup)
841 return (regnum < gdbarch_num_regs (gdbarch)
842 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
843 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
844 return rg & (xtRegisterGroupCP0 << cp_number);
850 /* Supply register REGNUM from the buffer specified by GREGS and LEN
851 in the general-purpose register set REGSET to register cache
852 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
855 xtensa_supply_gregset (const struct regset *regset,
861 const xtensa_elf_gregset_t *regs = gregs;
862 struct gdbarch *gdbarch = get_regcache_arch (rc);
865 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
867 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
868 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
869 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
870 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
871 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
872 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
873 (char *) ®s->windowbase);
874 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
875 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
876 (char *) ®s->windowstart);
877 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
878 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
879 (char *) ®s->lbeg);
880 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
881 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
882 (char *) ®s->lend);
883 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
884 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
885 (char *) ®s->lcount);
886 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
887 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
888 (char *) ®s->sar);
889 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
890 && regnum < gdbarch_tdep (gdbarch)->ar_base
891 + gdbarch_tdep (gdbarch)->num_aregs)
892 regcache_raw_supply (rc, regnum,
893 (char *) ®s->ar[regnum - gdbarch_tdep
894 (gdbarch)->ar_base]);
895 else if (regnum == -1)
897 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
898 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
899 (char *) ®s->ar[i]);
904 /* Xtensa register set. */
910 xtensa_supply_gregset
914 /* Return the appropriate register set for the core
915 section identified by SECT_NAME and SECT_SIZE. */
917 static const struct regset *
918 xtensa_regset_from_core_section (struct gdbarch *core_arch,
919 const char *sect_name,
922 DEBUGTRACE ("xtensa_regset_from_core_section "
923 "(..., sect_name==\"%s\", sect_size==%x)\n",
924 sect_name, (unsigned int) sect_size);
926 if (strcmp (sect_name, ".reg") == 0
927 && sect_size >= sizeof(xtensa_elf_gregset_t))
928 return &xtensa_gregset;
934 /* Handling frames. */
936 /* Number of registers to save in case of Windowed ABI. */
937 #define XTENSA_NUM_SAVED_AREGS 12
939 /* Frame cache part for Windowed ABI. */
940 typedef struct xtensa_windowed_frame_cache
942 int wb; /* WINDOWBASE of the previous frame. */
943 int callsize; /* Call size of this frame. */
944 int ws; /* WINDOWSTART of the previous frame. It keeps track of
945 life windows only. If there is no bit set for the
946 window, that means it had been already spilled
947 because of window overflow. */
949 /* Addresses of spilled A-registers.
950 AREGS[i] == -1, if corresponding AR is alive. */
951 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
952 } xtensa_windowed_frame_cache_t;
954 /* Call0 ABI Definitions. */
956 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
958 #define C0_NREGS 16 /* Number of A-registers to track. */
959 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
960 #define C0_SP 1 /* Register used as SP. */
961 #define C0_FP 15 /* Register used as FP. */
962 #define C0_RA 0 /* Register used as return address. */
963 #define C0_ARGS 2 /* Register used as first arg/retval. */
964 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
966 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
967 A-register where the current content of the reg came from (in terms
968 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
969 mean that the orignal content of the register was saved to the stack.
970 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
971 know where SP will end up until the entire prologue has been analyzed. */
973 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
974 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
975 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
977 extern xtensa_isa xtensa_default_isa;
979 typedef struct xtensa_c0reg
981 int fr_reg; /* original register from which register content
982 is derived, or C0_CONST, or C0_INEXP. */
983 int fr_ofs; /* constant offset from reg, or immediate value. */
984 int to_stk; /* offset from original SP to register (4-byte
985 aligned), or C0_NOSTK if register has not
990 /* Frame cache part for Call0 ABI. */
991 typedef struct xtensa_call0_frame_cache
993 int c0_frmsz; /* Stack frame size. */
994 int c0_hasfp; /* Current frame uses frame
996 int fp_regnum; /* A-register used as FP. */
997 int c0_fp; /* Actual value of frame pointer. */
998 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
999 } xtensa_call0_frame_cache_t;
1001 typedef struct xtensa_frame_cache
1003 CORE_ADDR base; /* Stack pointer of this frame. */
1004 CORE_ADDR pc; /* PC of this frame at the function entry point. */
1005 CORE_ADDR ra; /* The raw return address of this frame. */
1006 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1007 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1008 int call0; /* It's a call0 framework (else windowed). */
1011 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1012 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1014 } xtensa_frame_cache_t;
1017 static struct xtensa_frame_cache *
1018 xtensa_alloc_frame_cache (int windowed)
1020 xtensa_frame_cache_t *cache;
1023 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1025 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1032 cache->call0 = !windowed;
1035 cache->c0.c0_frmsz = -1;
1036 cache->c0.c0_hasfp = 0;
1037 cache->c0.fp_regnum = -1;
1038 cache->c0.c0_fp = -1;
1040 for (i = 0; i < C0_NREGS; i++)
1042 cache->c0.c0_rt[i].fr_reg = i;
1043 cache->c0.c0_rt[i].fr_ofs = 0;
1044 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1051 cache->wd.callsize = -1;
1053 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1054 cache->wd.aregs[i] = -1;
1061 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1063 return address & ~15;
1068 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1073 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1074 host_address_to_string (next_frame));
1076 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1077 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1079 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1085 static struct frame_id
1086 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1090 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1092 pc = get_frame_pc (this_frame);
1093 fp = get_frame_register_unsigned
1094 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1096 /* Make dummy frame ID unique by adding a constant. */
1097 return frame_id_build (fp + SP_ALIGNMENT, pc);
1100 /* Returns true, if instruction to execute next is unique to Xtensa Window
1101 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1104 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1106 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1107 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1110 if (byte_order == BFD_ENDIAN_BIG)
1112 /* Check, if this is L32E or S32E. */
1113 code = insn & 0xf000ff00;
1114 if ((code == 0x00009000) || (code == 0x00009400))
1116 /* Check, if this is RFWU or RFWO. */
1117 code = insn & 0xffffff00;
1118 return ((code == 0x00430000) || (code == 0x00530000));
1122 /* Check, if this is L32E or S32E. */
1123 code = insn & 0x00ff000f;
1124 if ((code == 0x090000) || (code == 0x490000))
1126 /* Check, if this is RFWU or RFWO. */
1127 code = insn & 0x00ffffff;
1128 return ((code == 0x00003400) || (code == 0x00003500));
1132 /* Returns the best guess about which register is a frame pointer
1133 for the function containing CURRENT_PC. */
1135 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1136 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1139 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1141 #define RETURN_FP goto done
1143 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1144 CORE_ADDR start_addr;
1146 xtensa_insnbuf ins, slot;
1147 char ibuf[XTENSA_ISA_BSZ];
1148 CORE_ADDR ia, bt, ba;
1150 int ilen, islots, is;
1152 const char *opcname;
1154 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1155 if (start_addr == 0)
1158 if (!xtensa_default_isa)
1159 xtensa_default_isa = xtensa_isa_init (0, 0);
1160 isa = xtensa_default_isa;
1161 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1162 ins = xtensa_insnbuf_alloc (isa);
1163 slot = xtensa_insnbuf_alloc (isa);
1166 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1168 if (ia + xtensa_isa_maxlength (isa) > bt)
1171 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1172 ? ba + XTENSA_ISA_BSZ : current_pc;
1173 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1177 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1178 ifmt = xtensa_format_decode (isa, ins);
1179 if (ifmt == XTENSA_UNDEFINED)
1181 ilen = xtensa_format_length (isa, ifmt);
1182 if (ilen == XTENSA_UNDEFINED)
1184 islots = xtensa_format_num_slots (isa, ifmt);
1185 if (islots == XTENSA_UNDEFINED)
1188 for (is = 0; is < islots; ++is)
1190 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1193 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1194 if (opc == XTENSA_UNDEFINED)
1197 opcname = xtensa_opcode_name (isa, opc);
1199 if (strcasecmp (opcname, "mov.n") == 0
1200 || strcasecmp (opcname, "or") == 0)
1202 unsigned int register_operand;
1204 /* Possible candidate for setting frame pointer
1205 from A1. This is what we are looking for. */
1207 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1208 is, slot, ®ister_operand) != 0)
1210 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1212 if (register_operand == 1) /* Mov{.n} FP A1. */
1214 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1215 ®ister_operand) != 0)
1217 if (xtensa_operand_decode (isa, opc, 0,
1218 ®ister_operand) != 0)
1222 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1228 /* We have problems decoding the memory. */
1230 || strcasecmp (opcname, "ill") == 0
1231 || strcasecmp (opcname, "ill.n") == 0
1232 /* Hit planted breakpoint. */
1233 || strcasecmp (opcname, "break") == 0
1234 || strcasecmp (opcname, "break.n") == 0
1235 /* Flow control instructions finish prologue. */
1236 || xtensa_opcode_is_branch (isa, opc) > 0
1237 || xtensa_opcode_is_jump (isa, opc) > 0
1238 || xtensa_opcode_is_loop (isa, opc) > 0
1239 || xtensa_opcode_is_call (isa, opc) > 0
1240 || strcasecmp (opcname, "simcall") == 0
1241 || strcasecmp (opcname, "syscall") == 0)
1242 /* Can not continue analysis. */
1247 xtensa_insnbuf_free(isa, slot);
1248 xtensa_insnbuf_free(isa, ins);
1252 /* The key values to identify the frame using "cache" are
1254 cache->base = SP (or best guess about FP) of this frame;
1255 cache->pc = entry-PC (entry point of the frame function);
1256 cache->prev_sp = SP of the previous frame. */
1259 call0_frame_cache (struct frame_info *this_frame,
1260 xtensa_frame_cache_t *cache,
1261 CORE_ADDR pc, CORE_ADDR litbase);
1264 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1265 xtensa_frame_cache_t *cache,
1268 static struct xtensa_frame_cache *
1269 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1271 xtensa_frame_cache_t *cache;
1272 CORE_ADDR ra, wb, ws, pc, sp, ps;
1273 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1274 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1275 unsigned int fp_regnum;
1276 int windowed, ps_regnum;
1281 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1282 ps_regnum = gdbarch_ps_regnum (gdbarch);
1283 ps = (ps_regnum >= 0)
1284 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS;
1286 windowed = windowing_enabled (gdbarch, ps);
1288 /* Get pristine xtensa-frame. */
1289 cache = xtensa_alloc_frame_cache (windowed);
1290 *this_cache = cache;
1296 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1297 wb = get_frame_register_unsigned (this_frame,
1298 gdbarch_tdep (gdbarch)->wb_regnum);
1299 ws = get_frame_register_unsigned (this_frame,
1300 gdbarch_tdep (gdbarch)->ws_regnum);
1302 op1 = read_memory_integer (pc, 1, byte_order);
1303 if (XTENSA_IS_ENTRY (gdbarch, op1))
1305 int callinc = CALLINC (ps);
1306 ra = get_frame_register_unsigned
1307 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1309 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1310 cache->wd.callsize = 0;
1313 cache->prev_sp = get_frame_register_unsigned
1314 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1316 /* This only can be the outermost frame since we are
1317 just about to execute ENTRY. SP hasn't been set yet.
1318 We can assume any frame size, because it does not
1319 matter, and, let's fake frame base in cache. */
1320 cache->base = cache->prev_sp - 16;
1323 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1324 cache->ps = (ps & ~PS_CALLINC_MASK)
1325 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1331 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1332 ra = get_frame_register_unsigned (this_frame,
1333 gdbarch_tdep (gdbarch)->a0_base);
1334 cache->wd.callsize = WINSIZE (ra);
1335 cache->wd.wb = (wb - cache->wd.callsize / 4)
1336 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1337 cache->wd.ws = ws & ~(1 << wb);
1339 cache->pc = get_frame_func (this_frame);
1340 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1341 cache->ps = (ps & ~PS_CALLINC_MASK)
1342 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1345 if (cache->wd.ws == 0)
1350 sp = get_frame_register_unsigned
1351 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1353 for (i = 0; i < 4; i++, sp += 4)
1355 cache->wd.aregs[i] = sp;
1358 if (cache->wd.callsize > 4)
1360 /* Set A4...A7/A11. */
1361 /* Get the SP of the frame previous to the previous one.
1362 To achieve this, we have to dereference SP twice. */
1363 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1364 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1365 sp -= cache->wd.callsize * 4;
1367 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1369 cache->wd.aregs[i] = sp;
1374 if ((cache->prev_sp == 0) && ( ra != 0 ))
1375 /* If RA is equal to 0 this frame is an outermost frame. Leave
1376 cache->prev_sp unchanged marking the boundary of the frame stack. */
1378 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1380 /* Register window overflow already happened.
1381 We can read caller's SP from the proper spill loction. */
1382 sp = get_frame_register_unsigned
1383 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1384 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1388 /* Read caller's frame SP directly from the previous window. */
1389 int regnum = arreg_number
1390 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1393 cache->prev_sp = xtensa_read_register (regnum);
1397 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1399 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1401 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1402 /* Everything was set already, including cache->base. */
1405 else /* Call0 framework. */
1407 unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
1408 CORE_ADDR litbase = (litbase_regnum == -1)
1409 ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
1411 call0_frame_cache (this_frame, cache, pc, litbase);
1412 fp_regnum = cache->c0.fp_regnum;
1415 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1421 xtensa_frame_this_id (struct frame_info *this_frame,
1423 struct frame_id *this_id)
1425 struct xtensa_frame_cache *cache =
1426 xtensa_frame_cache (this_frame, this_cache);
1428 if (cache->prev_sp == 0)
1431 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1434 static struct value *
1435 xtensa_frame_prev_register (struct frame_info *this_frame,
1439 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1440 struct xtensa_frame_cache *cache;
1441 ULONGEST saved_reg = 0;
1444 if (*this_cache == NULL)
1445 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1446 cache = *this_cache;
1448 if (regnum ==gdbarch_pc_regnum (gdbarch))
1449 saved_reg = cache->ra;
1450 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1451 saved_reg = cache->prev_sp;
1452 else if (!cache->call0)
1454 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1455 saved_reg = cache->wd.ws;
1456 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1457 saved_reg = cache->wd.wb;
1458 else if (regnum == gdbarch_ps_regnum (gdbarch))
1459 saved_reg = cache->ps;
1467 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1469 if (!cache->call0) /* Windowed ABI. */
1471 /* Convert A-register numbers to AR-register numbers,
1472 if we deal with A-register. */
1473 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1474 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1475 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1477 /* Check, if we deal with AR-register saved on stack. */
1478 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1479 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1480 + gdbarch_tdep (gdbarch)->num_aregs))
1482 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1485 && areg < XTENSA_NUM_SAVED_AREGS
1486 && cache->wd.aregs[areg] != -1)
1487 return frame_unwind_got_memory (this_frame, regnum,
1488 cache->wd.aregs[areg]);
1491 else /* Call0 ABI. */
1493 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1494 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1496 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1503 /* If register was saved in the prologue, retrieve it. */
1504 stkofs = cache->c0.c0_rt[reg].to_stk;
1505 if (stkofs != C0_NOSTK)
1507 /* Determine SP on entry based on FP. */
1508 spe = cache->c0.c0_fp
1509 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1511 return frame_unwind_got_memory (this_frame, regnum,
1517 /* All other registers have been either saved to
1518 the stack or are still alive in the processor. */
1520 return frame_unwind_got_register (this_frame, regnum, regnum);
1524 static const struct frame_unwind
1528 xtensa_frame_this_id,
1529 xtensa_frame_prev_register,
1531 default_frame_sniffer
1535 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1537 struct xtensa_frame_cache *cache =
1538 xtensa_frame_cache (this_frame, this_cache);
1543 static const struct frame_base
1547 xtensa_frame_base_address,
1548 xtensa_frame_base_address,
1549 xtensa_frame_base_address
1554 xtensa_extract_return_value (struct type *type,
1555 struct regcache *regcache,
1558 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1559 bfd_byte *valbuf = dst;
1560 int len = TYPE_LENGTH (type);
1565 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1567 gdb_assert(len > 0);
1569 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1571 /* First, we have to find the caller window in the register file. */
1572 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1573 callsize = extract_call_winsize (gdbarch, pc);
1575 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1576 if (len > (callsize > 8 ? 8 : 16))
1577 internal_error (__FILE__, __LINE__,
1578 _("cannot extract return value of %d bytes long"),
1581 /* Get the register offset of the return
1582 register (A2) in the caller window. */
1583 regcache_raw_read_unsigned
1584 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1585 areg = arreg_number (gdbarch,
1586 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1590 /* No windowing hardware - Call0 ABI. */
1591 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1594 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1596 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1599 for (; len > 0; len -= 4, areg++, valbuf += 4)
1602 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1604 regcache_raw_read (regcache, areg, valbuf);
1610 xtensa_store_return_value (struct type *type,
1611 struct regcache *regcache,
1614 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1615 const bfd_byte *valbuf = dst;
1619 int len = TYPE_LENGTH (type);
1622 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1624 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1626 regcache_raw_read_unsigned
1627 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1628 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1629 callsize = extract_call_winsize (gdbarch, pc);
1631 if (len > (callsize > 8 ? 8 : 16))
1632 internal_error (__FILE__, __LINE__,
1633 _("unimplemented for this length: %d"),
1634 TYPE_LENGTH (type));
1635 areg = arreg_number (gdbarch,
1636 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1638 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1639 callsize, (int) wb);
1643 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1646 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1649 for (; len > 0; len -= 4, areg++, valbuf += 4)
1652 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1654 regcache_raw_write (regcache, areg, valbuf);
1659 static enum return_value_convention
1660 xtensa_return_value (struct gdbarch *gdbarch,
1661 struct type *func_type,
1662 struct type *valtype,
1663 struct regcache *regcache,
1665 const gdb_byte *writebuf)
1667 /* Structures up to 16 bytes are returned in registers. */
1669 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1670 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1671 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1672 && TYPE_LENGTH (valtype) > 16);
1675 return RETURN_VALUE_STRUCT_CONVENTION;
1677 DEBUGTRACE ("xtensa_return_value(...)\n");
1679 if (writebuf != NULL)
1681 xtensa_store_return_value (valtype, regcache, writebuf);
1684 if (readbuf != NULL)
1686 gdb_assert (!struct_return);
1687 xtensa_extract_return_value (valtype, regcache, readbuf);
1689 return RETURN_VALUE_REGISTER_CONVENTION;
1696 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1697 struct value *function,
1698 struct regcache *regcache,
1701 struct value **args,
1704 CORE_ADDR struct_addr)
1706 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1708 int size, onstack_size;
1709 gdb_byte *buf = (gdb_byte *) alloca (16);
1711 struct argument_info
1713 const bfd_byte *contents;
1715 int onstack; /* onstack == 0 => in reg */
1716 int align; /* alignment */
1719 int offset; /* stack offset if on stack. */
1720 int regno; /* regno if in register. */
1724 struct argument_info *arg_info =
1725 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1729 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1731 if (xtensa_debug_level > 3)
1734 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1735 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1736 "struct_addr=0x%x\n",
1737 (int) sp, (int) struct_return, (int) struct_addr);
1739 for (i = 0; i < nargs; i++)
1741 struct value *arg = args[i];
1742 struct type *arg_type = check_typedef (value_type (arg));
1743 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1744 host_address_to_string (arg),
1745 TYPE_LENGTH (arg_type));
1746 switch (TYPE_CODE (arg_type))
1749 fprintf_unfiltered (gdb_stdlog, "int");
1751 case TYPE_CODE_STRUCT:
1752 fprintf_unfiltered (gdb_stdlog, "struct");
1755 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1758 fprintf_unfiltered (gdb_stdlog, " %s\n",
1759 host_address_to_string (value_contents (arg)));
1763 /* First loop: collect information.
1764 Cast into type_long. (This shouldn't happen often for C because
1765 GDB already does this earlier.) It's possible that GDB could
1766 do it all the time but it's harmless to leave this code here. */
1773 size = REGISTER_SIZE;
1775 for (i = 0; i < nargs; i++)
1777 struct argument_info *info = &arg_info[i];
1778 struct value *arg = args[i];
1779 struct type *arg_type = check_typedef (value_type (arg));
1781 switch (TYPE_CODE (arg_type))
1784 case TYPE_CODE_BOOL:
1785 case TYPE_CODE_CHAR:
1786 case TYPE_CODE_RANGE:
1787 case TYPE_CODE_ENUM:
1789 /* Cast argument to long if necessary as the mask does it too. */
1790 if (TYPE_LENGTH (arg_type)
1791 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1793 arg_type = builtin_type (gdbarch)->builtin_long;
1794 arg = value_cast (arg_type, arg);
1796 /* Aligment is equal to the type length for the basic types. */
1797 info->align = TYPE_LENGTH (arg_type);
1802 /* Align doubles correctly. */
1803 if (TYPE_LENGTH (arg_type)
1804 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1805 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1807 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1810 case TYPE_CODE_STRUCT:
1812 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1815 info->length = TYPE_LENGTH (arg_type);
1816 info->contents = value_contents (arg);
1818 /* Align size and onstack_size. */
1819 size = (size + info->align - 1) & ~(info->align - 1);
1820 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1822 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1825 info->u.offset = onstack_size;
1826 onstack_size += info->length;
1831 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1833 size += info->length;
1836 /* Adjust the stack pointer and align it. */
1837 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1839 /* Simulate MOVSP, if Windowed ABI. */
1840 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1843 read_memory (osp - 16, buf, 16);
1844 write_memory (sp - 16, buf, 16);
1847 /* Second Loop: Load arguments. */
1851 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1852 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1855 for (i = 0; i < nargs; i++)
1857 struct argument_info *info = &arg_info[i];
1861 int n = info->length;
1862 CORE_ADDR offset = sp + info->u.offset;
1864 /* Odd-sized structs are aligned to the lower side of a memory
1865 word in big-endian mode and require a shift. This only
1866 applies for structures smaller than one word. */
1868 if (n < REGISTER_SIZE
1869 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1870 offset += (REGISTER_SIZE - n);
1872 write_memory (offset, info->contents, info->length);
1877 int n = info->length;
1878 const bfd_byte *cp = info->contents;
1879 int r = info->u.regno;
1881 /* Odd-sized structs are aligned to the lower side of registers in
1882 big-endian mode and require a shift. The odd-sized leftover will
1883 be at the end. Note that this is only true for structures smaller
1884 than REGISTER_SIZE; for larger odd-sized structures the excess
1885 will be left-aligned in the register on both endiannesses. */
1887 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1890 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1891 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1893 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1894 regcache_cooked_write (regcache, r, buf);
1896 cp += REGISTER_SIZE;
1903 regcache_cooked_write (regcache, r, cp);
1905 cp += REGISTER_SIZE;
1912 /* Set the return address of dummy frame to the dummy address.
1913 The return address for the current function (in A0) is
1914 saved in the dummy frame, so we can savely overwrite A0 here. */
1916 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1919 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1920 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1921 ps = (unsigned long) val & ~0x00030000;
1922 regcache_cooked_write_unsigned
1923 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1924 regcache_cooked_write_unsigned (regcache,
1925 gdbarch_ps_regnum (gdbarch),
1928 /* All the registers have been saved. After executing
1929 dummy call, they all will be restored. So it's safe
1930 to modify WINDOWSTART register to make it look like there
1931 is only one register window corresponding to WINDOWEBASE. */
1933 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1934 regcache_cooked_write_unsigned
1935 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1936 1 << extract_unsigned_integer (buf, 4, byte_order));
1940 /* Simulate CALL0: write RA into A0 register. */
1941 regcache_cooked_write_unsigned
1942 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1945 /* Set new stack pointer and return it. */
1946 regcache_cooked_write_unsigned (regcache,
1947 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1948 /* Make dummy frame ID unique by adding a constant. */
1949 return sp + SP_ALIGNMENT;
1953 /* Return a breakpoint for the current location of PC. We always use
1954 the density version if we have density instructions (regardless of the
1955 current instruction at PC), and use regular instructions otherwise. */
1957 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1958 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1959 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1960 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1962 static const unsigned char *
1963 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1966 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1967 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1968 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1969 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1971 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1973 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1975 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1977 *lenptr = sizeof (density_big_breakpoint);
1978 return density_big_breakpoint;
1982 *lenptr = sizeof (density_little_breakpoint);
1983 return density_little_breakpoint;
1988 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1990 *lenptr = sizeof (big_breakpoint);
1991 return big_breakpoint;
1995 *lenptr = sizeof (little_breakpoint);
1996 return little_breakpoint;
2001 /* Call0 ABI support routines. */
2003 /* Call0 opcode class. Opcodes are preclassified according to what they
2004 mean for Call0 prologue analysis, and their number of significant operands.
2005 The purpose of this is to simplify prologue analysis by separating
2006 instruction decoding (libisa) from the semantics of prologue analysis. */
2009 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2010 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2011 c0opc_flow, /* Flow control insn. */
2012 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2013 c0opc_break, /* Debugger software breakpoints. */
2014 c0opc_add, /* Adding two registers. */
2015 c0opc_addi, /* Adding a register and an immediate. */
2016 c0opc_sub, /* Subtracting a register from a register. */
2017 c0opc_mov, /* Moving a register to a register. */
2018 c0opc_movi, /* Moving an immediate to a register. */
2019 c0opc_l32r, /* Loading a literal. */
2020 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2021 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2022 c0opc_l32e, /* L32E instruction. */
2023 c0opc_s32e, /* S32E instruction. */
2024 c0opc_rfwo, /* RFWO instruction. */
2025 c0opc_rfwu, /* RFWU instruction. */
2026 c0opc_NrOf /* Number of opcode classifications. */
2029 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2032 rwx_special_register (const char *opcname)
2034 char ch = *opcname++;
2036 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2038 if (*opcname++ != 's')
2040 if (*opcname++ != 'r')
2042 if (*opcname++ != '.')
2048 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2050 static xtensa_insn_kind
2051 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2053 const char *opcname;
2054 xtensa_insn_kind opclass = c0opc_uninteresting;
2056 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2058 /* Get opcode name and handle special classifications. */
2060 opcname = xtensa_opcode_name (isa, opc);
2063 || strcasecmp (opcname, "ill") == 0
2064 || strcasecmp (opcname, "ill.n") == 0)
2065 opclass = c0opc_illegal;
2066 else if (strcasecmp (opcname, "break") == 0
2067 || strcasecmp (opcname, "break.n") == 0)
2068 opclass = c0opc_break;
2069 else if (strcasecmp (opcname, "entry") == 0)
2070 opclass = c0opc_entry;
2071 else if (strcasecmp (opcname, "rfwo") == 0)
2072 opclass = c0opc_rfwo;
2073 else if (strcasecmp (opcname, "rfwu") == 0)
2074 opclass = c0opc_rfwu;
2075 else if (xtensa_opcode_is_branch (isa, opc) > 0
2076 || xtensa_opcode_is_jump (isa, opc) > 0
2077 || xtensa_opcode_is_loop (isa, opc) > 0
2078 || xtensa_opcode_is_call (isa, opc) > 0
2079 || strcasecmp (opcname, "simcall") == 0
2080 || strcasecmp (opcname, "syscall") == 0)
2081 opclass = c0opc_flow;
2083 /* Also, classify specific opcodes that need to be tracked. */
2084 else if (strcasecmp (opcname, "add") == 0
2085 || strcasecmp (opcname, "add.n") == 0)
2086 opclass = c0opc_add;
2087 else if (strcasecmp (opcname, "addi") == 0
2088 || strcasecmp (opcname, "addi.n") == 0
2089 || strcasecmp (opcname, "addmi") == 0)
2090 opclass = c0opc_addi;
2091 else if (strcasecmp (opcname, "sub") == 0)
2092 opclass = c0opc_sub;
2093 else if (strcasecmp (opcname, "mov.n") == 0
2094 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2095 opclass = c0opc_mov;
2096 else if (strcasecmp (opcname, "movi") == 0
2097 || strcasecmp (opcname, "movi.n") == 0)
2098 opclass = c0opc_movi;
2099 else if (strcasecmp (opcname, "l32r") == 0)
2100 opclass = c0opc_l32r;
2101 else if (strcasecmp (opcname, "s32i") == 0
2102 || strcasecmp (opcname, "s32i.n") == 0)
2103 opclass = c0opc_s32i;
2104 else if (strcasecmp (opcname, "l32e") == 0)
2105 opclass = c0opc_l32e;
2106 else if (strcasecmp (opcname, "s32e") == 0)
2107 opclass = c0opc_s32e;
2108 else if (rwx_special_register (opcname))
2109 opclass = c0opc_rwxsr;
2114 /* Tracks register movement/mutation for a given operation, which may
2115 be within a bundle. Updates the destination register tracking info
2116 accordingly. The pc is needed only for pc-relative load instructions
2117 (eg. l32r). The SP register number is needed to identify stores to
2121 call0_track_op (struct gdbarch *gdbarch,
2122 xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2123 xtensa_insn_kind opclass, int nods, unsigned odv[],
2124 CORE_ADDR pc, CORE_ADDR litbase, int spreg)
2126 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2127 unsigned litaddr, litval;
2132 /* 3 operands: dst, src, imm. */
2133 gdb_assert (nods == 3);
2134 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2135 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2138 /* 3 operands: dst, src1, src2. */
2139 gdb_assert (nods == 3);
2140 if (src[odv[1]].fr_reg == C0_CONST)
2142 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2143 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2145 else if (src[odv[2]].fr_reg == C0_CONST)
2147 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2148 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2150 else dst[odv[0]].fr_reg = C0_INEXP;
2153 /* 3 operands: dst, src1, src2. */
2154 gdb_assert (nods == 3);
2155 if (src[odv[2]].fr_reg == C0_CONST)
2157 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2158 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2160 else dst[odv[0]].fr_reg = C0_INEXP;
2163 /* 2 operands: dst, src [, src]. */
2164 gdb_assert (nods == 2);
2165 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2166 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2169 /* 2 operands: dst, imm. */
2170 gdb_assert (nods == 2);
2171 dst[odv[0]].fr_reg = C0_CONST;
2172 dst[odv[0]].fr_ofs = odv[1];
2175 /* 2 operands: dst, literal offset. */
2176 gdb_assert (nods == 2);
2177 litaddr = litbase & 1
2178 ? (litbase & ~1) + (signed)odv[1]
2179 : (pc + 3 + (signed)odv[1]) & ~3;
2180 litval = read_memory_integer (litaddr, 4, byte_order);
2181 dst[odv[0]].fr_reg = C0_CONST;
2182 dst[odv[0]].fr_ofs = litval;
2185 /* 3 operands: value, base, offset. */
2186 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2187 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2188 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2189 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2190 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2191 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2193 /* ISA encoding guarantees alignment. But, check it anyway. */
2194 gdb_assert ((odv[2] & 3) == 0);
2195 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2199 gdb_assert_not_reached ("unexpected instruction kind");
2203 /* Analyze prologue of the function at start address to determine if it uses
2204 the Call0 ABI, and if so track register moves and linear modifications
2205 in the prologue up to the PC or just beyond the prologue, whichever is first.
2206 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2207 The prologue may overlap non-prologue instructions but is guaranteed to end
2208 by the first flow-control instruction (jump, branch, call or return).
2209 Since an optimized function may move information around and change the
2210 stack frame arbitrarily during the prologue, the information is guaranteed
2211 valid only at the point in the function indicated by the PC.
2212 May be used to skip the prologue or identify the ABI, w/o tracking.
2214 Returns: Address of first instruction after prologue, or PC (whichever
2215 is first), or 0, if decoding failed (in libisa).
2217 start Start address of function/prologue.
2218 pc Program counter to stop at. Use 0 to continue to end of prologue.
2219 If 0, avoids infinite run-on in corrupt code memory by bounding
2220 the scan to the end of the function if that can be determined.
2221 nregs Number of general registers to track (size of rt[] array).
2223 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2224 If NULL, registers are not tracked.
2226 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2227 (more accurately, non-zero until 'entry' insn is encountered).
2229 Note that these may produce useful results even if decoding fails
2230 because they begin with default assumptions that analysis may change. */
2233 call0_analyze_prologue (struct gdbarch *gdbarch,
2234 CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
2235 int nregs, xtensa_c0reg_t rt[], int *call0)
2237 CORE_ADDR ia; /* Current insn address in prologue. */
2238 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2239 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2240 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2241 xtensa_isa isa; /* libisa ISA handle. */
2242 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2243 xtensa_format ifmt; /* libisa instruction format. */
2244 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2245 xtensa_opcode opc; /* Opcode in current slot. */
2246 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2247 int nods; /* Opcode number of operands. */
2248 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2249 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2250 int j; /* General loop counter. */
2251 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2252 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2253 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2255 struct symtab_and_line prologue_sal;
2257 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2258 (int)start, (int)pc);
2260 /* Try to limit the scan to the end of the function if a non-zero pc
2261 arg was not supplied to avoid probing beyond the end of valid memory.
2262 If memory is full of garbage that classifies as c0opc_uninteresting.
2263 If this fails (eg. if no symbols) pc ends up 0 as it was.
2264 Intialize the Call0 frame and register tracking info.
2265 Assume it's Call0 until an 'entry' instruction is encountered.
2266 Assume we may be in the prologue until we hit a flow control instr. */
2272 /* Find out, if we have an information about the prologue from DWARF. */
2273 prologue_sal = find_pc_line (start, 0);
2274 if (prologue_sal.line != 0) /* Found debug info. */
2275 body_pc = prologue_sal.end;
2277 /* If we are going to analyze the prologue in general without knowing about
2278 the current PC, make the best assumtion for the end of the prologue. */
2281 find_pc_partial_function (start, 0, NULL, &end_pc);
2282 body_pc = min (end_pc, body_pc);
2285 body_pc = min (pc, body_pc);
2292 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2293 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2297 if (!xtensa_default_isa)
2298 xtensa_default_isa = xtensa_isa_init (0, 0);
2299 isa = xtensa_default_isa;
2300 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2301 ins = xtensa_insnbuf_alloc (isa);
2302 slot = xtensa_insnbuf_alloc (isa);
2304 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2306 /* (Re)fill instruction buffer from memory if necessary, but do not
2307 read memory beyond PC to be sure we stay within text section
2308 (this protection only works if a non-zero pc is supplied). */
2310 if (ia + xtensa_isa_maxlength (isa) > bt)
2313 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2314 read_memory (ba, ibuf, bt - ba);
2315 /* If there is a memory reading error read_memory () will report it
2316 and then throw an exception, stopping command execution. */
2319 /* Decode format information. */
2321 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2322 ifmt = xtensa_format_decode (isa, ins);
2323 if (ifmt == XTENSA_UNDEFINED)
2328 ilen = xtensa_format_length (isa, ifmt);
2329 if (ilen == XTENSA_UNDEFINED)
2334 islots = xtensa_format_num_slots (isa, ifmt);
2335 if (islots == XTENSA_UNDEFINED)
2341 /* Analyze a bundle or a single instruction, using a snapshot of
2342 the register tracking info as input for the entire bundle so that
2343 register changes do not take effect within this bundle. */
2345 for (j = 0; j < nregs; ++j)
2348 for (is = 0; is < islots; ++is)
2350 /* Decode a slot and classify the opcode. */
2352 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2356 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2357 DEBUGVERB ("[call0_analyze_prologue] instr "
2358 "addr = 0x%08x, opc = %d\n",
2360 if (opc == XTENSA_UNDEFINED)
2361 opclass = c0opc_illegal;
2363 opclass = call0_classify_opcode (isa, opc);
2365 /* Decide whether to track this opcode, ignore it, or bail out. */
2374 case c0opc_uninteresting:
2383 ia += ilen; /* Skip over 'entry' insn. */
2391 /* Only expected opcodes should get this far. */
2395 /* Extract and decode the operands. */
2396 nods = xtensa_opcode_num_operands (isa, opc);
2397 if (nods == XTENSA_UNDEFINED)
2403 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2405 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2410 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2415 /* Check operands to verify use of 'mov' assembler macro. */
2416 if (opclass == c0opc_mov && nods == 3)
2418 if (odv[2] == odv[1])
2422 opclass = c0opc_uninteresting;
2427 /* Track register movement and modification for this operation. */
2428 call0_track_op (gdbarch, rt, rtmp, opclass,
2429 nods, odv, ia, litbase, 1);
2433 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2434 (unsigned)ia, fail ? "failed" : "succeeded");
2435 xtensa_insnbuf_free(isa, slot);
2436 xtensa_insnbuf_free(isa, ins);
2437 return fail ? XTENSA_ISA_BADPC : ia;
2440 /* Initialize frame cache for the current frame in CALL0 ABI. */
2443 call0_frame_cache (struct frame_info *this_frame,
2444 xtensa_frame_cache_t *cache,
2445 CORE_ADDR pc, CORE_ADDR litbase)
2447 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2448 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2449 CORE_ADDR start_pc; /* The beginning of the function. */
2450 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2451 CORE_ADDR sp, fp, ra;
2452 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2454 /* Find the beginning of the prologue of the function containing the PC
2455 and analyze it up to the PC or the end of the prologue. */
2457 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2459 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
2461 &cache->c0.c0_rt[0],
2464 if (body_pc == XTENSA_ISA_BADPC)
2465 error (_("Xtensa-specific internal error: CALL0 prologue \
2466 analysis failed in this frame. GDB command execution stopped."));
2469 sp = get_frame_register_unsigned
2470 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2471 fp = sp; /* Assume FP == SP until proven otherwise. */
2473 /* Get the frame information and FP (if used) at the current PC.
2474 If PC is in the prologue, the prologue analysis is more reliable
2475 than DWARF info. We don't not know for sure if PC is in the prologue,
2476 but we know no calls have yet taken place, so we can almost
2477 certainly rely on the prologue analysis. */
2481 /* Prologue analysis was successful up to the PC.
2482 It includes the cases when PC == START_PC. */
2483 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2484 /* c0_hasfp == true means there is a frame pointer because
2485 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2486 was derived from SP. Otherwise, it would be C0_FP. */
2487 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2488 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2489 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2491 else /* No data from the prologue analysis. */
2494 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2499 prev_sp = fp + c0_frmsz;
2501 /* Frame size from debug info or prologue tracking does not account for
2502 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2505 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2507 /* Recalculate previous SP. */
2508 prev_sp = fp + c0_frmsz;
2509 /* Update the stack frame size. */
2510 c0_frmsz += fp - sp;
2513 /* Get the return address (RA) from the stack if saved,
2514 or try to get it from a register. */
2516 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2517 if (to_stk != C0_NOSTK)
2519 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2522 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2523 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2525 /* Special case for terminating backtrace at a function that
2526 wants to be seen as the outermost. Such a function will
2527 clear it's RA (A0) register to 0 in the prologue instead of
2528 saving its original value. */
2533 /* RA was copied to another register or (before any function
2534 call) may still be in the original RA register. This is not
2535 always reliable: even in a leaf function, register tracking
2536 stops after prologue, and even in prologue, non-prologue
2537 instructions (not tracked) may overwrite RA or any register
2538 it was copied to. If likely in prologue or before any call,
2539 use retracking info and hope for the best (compiler should
2540 have saved RA in stack if not in a leaf function). If not in
2541 prologue, too bad. */
2546 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2548 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2552 ra = get_frame_register_unsigned
2554 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2559 cache->pc = start_pc;
2561 /* RA == 0 marks the outermost frame. Do not go past it. */
2562 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2563 cache->c0.fp_regnum = fp_regnum;
2564 cache->c0.c0_frmsz = c0_frmsz;
2565 cache->c0.c0_hasfp = c0_hasfp;
2566 cache->c0.c0_fp = fp;
2569 static CORE_ADDR a0_saved;
2570 static CORE_ADDR a7_saved;
2571 static CORE_ADDR a11_saved;
2572 static int a0_was_saved;
2573 static int a7_was_saved;
2574 static int a11_was_saved;
2576 /* Simulate L32E insn: AT <-- ref (AS + offset). */
2578 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2580 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2581 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2582 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2583 unsigned int spilled_value
2584 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2586 if ((at == 0) && !a0_was_saved)
2588 a0_saved = xtensa_read_register (atreg);
2591 else if ((at == 7) && !a7_was_saved)
2593 a7_saved = xtensa_read_register (atreg);
2596 else if ((at == 11) && !a11_was_saved)
2598 a11_saved = xtensa_read_register (atreg);
2602 xtensa_write_register (atreg, spilled_value);
2605 /* Simulate S32E insn: AT --> ref (AS + offset). */
2607 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2609 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2610 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2611 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2612 ULONGEST spilled_value = xtensa_read_register (atreg);
2614 write_memory_unsigned_integer (addr, 4,
2615 gdbarch_byte_order (gdbarch),
2619 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2624 xtNoExceptionHandler
2625 } xtensa_exception_handler_t;
2627 /* Execute insn stream from current PC until hitting RFWU or RFWO.
2628 Return type of Xtensa Window Interrupt Handler on success. */
2629 static xtensa_exception_handler_t
2630 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2633 xtensa_insnbuf ins, slot;
2634 char ibuf[XTENSA_ISA_BSZ];
2635 CORE_ADDR ia, bt, ba;
2637 int ilen, islots, is;
2641 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2646 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2647 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2649 isa = xtensa_default_isa;
2650 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2651 ins = xtensa_insnbuf_alloc (isa);
2652 slot = xtensa_insnbuf_alloc (isa);
2661 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2663 if (ia + xtensa_isa_maxlength (isa) > bt)
2666 bt = (ba + XTENSA_ISA_BSZ);
2667 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2668 return xtNoExceptionHandler;
2670 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2671 ifmt = xtensa_format_decode (isa, ins);
2672 if (ifmt == XTENSA_UNDEFINED)
2673 return xtNoExceptionHandler;
2674 ilen = xtensa_format_length (isa, ifmt);
2675 if (ilen == XTENSA_UNDEFINED)
2676 return xtNoExceptionHandler;
2677 islots = xtensa_format_num_slots (isa, ifmt);
2678 if (islots == XTENSA_UNDEFINED)
2679 return xtNoExceptionHandler;
2680 for (is = 0; is < islots; ++is)
2682 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2683 return xtNoExceptionHandler;
2684 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2685 if (opc == XTENSA_UNDEFINED)
2686 return xtNoExceptionHandler;
2687 switch (call0_classify_opcode (isa, opc))
2693 /* We expect none of them here. */
2694 return xtNoExceptionHandler;
2696 func = execute_l32e;
2699 func = execute_s32e;
2701 case c0opc_rfwo: /* RFWO. */
2702 /* Here, we return from WindowOverflow handler and,
2703 if we stopped at the very beginning, which means
2704 A0 was saved, we have to restore it now. */
2707 int arreg = arreg_number (gdbarch,
2708 gdbarch_tdep (gdbarch)->a0_base,
2710 xtensa_write_register (arreg, a0_saved);
2712 return xtWindowOverflow;
2713 case c0opc_rfwu: /* RFWU. */
2714 /* Here, we return from WindowUnderflow handler.
2715 Let's see if either A7 or A11 has to be restored. */
2716 if (WindowUnderflow12)
2720 int arreg = arreg_number (gdbarch,
2721 gdbarch_tdep (gdbarch)->a0_base + 11,
2723 xtensa_write_register (arreg, a11_saved);
2726 else if (a7_was_saved)
2728 int arreg = arreg_number (gdbarch,
2729 gdbarch_tdep (gdbarch)->a0_base + 7,
2731 xtensa_write_register (arreg, a7_saved);
2733 return xtWindowUnderflow;
2734 default: /* Simply skip this insns. */
2738 /* Decode arguments for L32E / S32E and simulate their execution. */
2739 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2740 return xtNoExceptionHandler;
2741 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2742 return xtNoExceptionHandler;
2743 if (xtensa_operand_decode (isa, opc, 0, &at))
2744 return xtNoExceptionHandler;
2745 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2746 return xtNoExceptionHandler;
2747 if (xtensa_operand_decode (isa, opc, 1, &as))
2748 return xtNoExceptionHandler;
2749 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2750 return xtNoExceptionHandler;
2751 if (xtensa_operand_decode (isa, opc, 2, &offset))
2752 return xtNoExceptionHandler;
2754 (*func) (gdbarch, at, as, offset, wb);
2759 return xtNoExceptionHandler;
2762 /* Handle Window Overflow / Underflow exception frames. */
2765 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2766 xtensa_frame_cache_t *cache,
2769 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2770 CORE_ADDR ps, wb, ws, ra;
2771 int epc1_regnum, i, regnum;
2772 xtensa_exception_handler_t eh_type;
2774 /* Read PS, WB, and WS from the hardware. Note that PS register
2775 must be present, if Windowed ABI is supported. */
2776 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2777 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2778 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2780 /* Execute all the remaining instructions from Window Interrupt Handler
2781 by simulating them on the remote protocol level. On return, set the
2782 type of Xtensa Window Interrupt Handler, or report an error. */
2783 eh_type = execute_code (gdbarch, pc, wb);
2784 if (eh_type == xtNoExceptionHandler)
2786 Unable to decode Xtensa Window Interrupt Handler's code."));
2788 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2789 cache->call0 = 0; /* It's Windowed ABI. */
2791 /* All registers for the cached frame will be alive. */
2792 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2793 cache->wd.aregs[i] = -1;
2795 if (eh_type == xtWindowOverflow)
2796 cache->wd.ws = ws ^ (1 << wb);
2797 else /* eh_type == xtWindowUnderflow. */
2798 cache->wd.ws = ws | (1 << wb);
2800 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2801 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2803 ra = xtensa_read_register (regnum);
2804 cache->wd.callsize = WINSIZE (ra);
2805 cache->prev_sp = xtensa_read_register (regnum + 1);
2806 /* Set regnum to a frame pointer of the frame being cached. */
2807 regnum = xtensa_scan_prologue (gdbarch, pc);
2808 regnum = arreg_number (gdbarch,
2809 gdbarch_tdep (gdbarch)->a0_base + regnum,
2811 cache->base = get_frame_register_unsigned (this_frame, regnum);
2813 /* Read PC of interrupted function from EPC1 register. */
2814 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2815 if (epc1_regnum < 0)
2816 error(_("Unable to read Xtensa register EPC1"));
2817 cache->ra = xtensa_read_register (epc1_regnum);
2818 cache->pc = get_frame_func (this_frame);
2822 /* Skip function prologue.
2824 Return the pc of the first instruction after prologue. GDB calls this to
2825 find the address of the first line of the function or (if there is no line
2826 number information) to skip the prologue for planting breakpoints on
2827 function entries. Use debug info (if present) or prologue analysis to skip
2828 the prologue to achieve reliable debugging behavior. For windowed ABI,
2829 only the 'entry' instruction is skipped. It is not strictly necessary to
2830 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2831 backtrace at any point in the prologue, however certain potential hazards
2832 are avoided and a more "normal" debugging experience is ensured by
2833 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2834 For example, if we don't skip the prologue:
2835 - Some args may not yet have been saved to the stack where the debug
2836 info expects to find them (true anyway when only 'entry' is skipped);
2837 - Software breakpoints ('break' instrs) may not have been unplanted
2838 when the prologue analysis is done on initializing the frame cache,
2839 and breaks in the prologue will throw off the analysis.
2841 If we have debug info ( line-number info, in particular ) we simply skip
2842 the code associated with the first function line effectively skipping
2843 the prologue code. It works even in cases like
2846 { int local_var = 1;
2850 because, for this source code, both Xtensa compilers will generate two
2851 separate entries ( with the same line number ) in dwarf line-number
2852 section to make sure there is a boundary between the prologue code and
2853 the rest of the function.
2855 If there is no debug info, we need to analyze the code. */
2857 /* #define DONT_SKIP_PROLOGUE */
2860 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2862 struct symtab_and_line prologue_sal;
2865 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2867 #if DONT_SKIP_PROLOGUE
2871 /* Try to find first body line from debug info. */
2873 prologue_sal = find_pc_line (start_pc, 0);
2874 if (prologue_sal.line != 0) /* Found debug info. */
2876 /* In Call0, it is possible to have a function with only one instruction
2877 ('ret') resulting from a 1-line optimized function that does nothing.
2878 In that case, prologue_sal.end may actually point to the start of the
2879 next function in the text section, causing a breakpoint to be set at
2880 the wrong place. Check if the end address is in a different function,
2881 and if so return the start PC. We know we have symbol info. */
2885 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2886 if (end_func != start_pc)
2889 return prologue_sal.end;
2892 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2893 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
2894 return body_pc != 0 ? body_pc : start_pc;
2897 /* Verify the current configuration. */
2899 xtensa_verify_config (struct gdbarch *gdbarch)
2901 struct ui_file *log;
2902 struct cleanup *cleanups;
2903 struct gdbarch_tdep *tdep;
2907 tdep = gdbarch_tdep (gdbarch);
2908 log = mem_fileopen ();
2909 cleanups = make_cleanup_ui_file_delete (log);
2911 /* Verify that we got a reasonable number of AREGS. */
2912 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2913 fprintf_unfiltered (log, _("\
2914 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2917 /* Verify that certain registers exist. */
2919 if (tdep->pc_regnum == -1)
2920 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2921 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2922 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2924 if (tdep->isa_use_windowed_registers)
2926 if (tdep->wb_regnum == -1)
2927 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2928 if (tdep->ws_regnum == -1)
2929 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2930 if (tdep->ar_base == -1)
2931 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2934 if (tdep->a0_base == -1)
2935 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2937 buf = ui_file_xstrdup (log, &length);
2938 make_cleanup (xfree, buf);
2940 internal_error (__FILE__, __LINE__,
2941 _("the following are invalid: %s"), buf);
2942 do_cleanups (cleanups);
2946 /* Derive specific register numbers from the array of registers. */
2949 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2951 xtensa_register_t* rmap;
2952 int n, max_size = 4;
2955 tdep->num_nopriv_regs = 0;
2957 /* Special registers 0..255 (core). */
2958 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2960 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2962 if (rmap->target_number == 0x0020)
2963 tdep->pc_regnum = n;
2964 else if (rmap->target_number == 0x0100)
2966 else if (rmap->target_number == 0x0000)
2968 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2969 tdep->wb_regnum = n;
2970 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2971 tdep->ws_regnum = n;
2972 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2973 tdep->debugcause_regnum = n;
2974 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2975 tdep->exccause_regnum = n;
2976 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2977 tdep->excvaddr_regnum = n;
2978 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2979 tdep->lbeg_regnum = n;
2980 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2981 tdep->lend_regnum = n;
2982 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2983 tdep->lcount_regnum = n;
2984 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2985 tdep->sar_regnum = n;
2986 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2987 tdep->litbase_regnum = n;
2988 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2989 tdep->ps_regnum = n;
2991 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2992 tdep->interrupt_regnum = n;
2993 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2994 tdep->interrupt2_regnum = n;
2995 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2996 tdep->cpenable_regnum = n;
2999 if (rmap->byte_size > max_size)
3000 max_size = rmap->byte_size;
3001 if (rmap->mask != 0 && tdep->num_regs == 0)
3003 /* Find out out how to deal with priveleged registers.
3005 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3006 && tdep->num_nopriv_regs == 0)
3007 tdep->num_nopriv_regs = n;
3009 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3010 && tdep->num_regs == 0)
3014 /* Number of pseudo registers. */
3015 tdep->num_pseudo_regs = n - tdep->num_regs;
3017 /* Empirically determined maximum sizes. */
3018 tdep->max_register_raw_size = max_size;
3019 tdep->max_register_virtual_size = max_size;
3022 /* Module "constructor" function. */
3024 extern struct gdbarch_tdep xtensa_tdep;
3026 static struct gdbarch *
3027 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3029 struct gdbarch_tdep *tdep;
3030 struct gdbarch *gdbarch;
3031 struct xtensa_abi_handler *abi_handler;
3033 DEBUGTRACE ("gdbarch_init()\n");
3035 /* We have to set the byte order before we call gdbarch_alloc. */
3036 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3038 tdep = &xtensa_tdep;
3039 gdbarch = gdbarch_alloc (&info, tdep);
3040 xtensa_derive_tdep (tdep);
3042 /* Verify our configuration. */
3043 xtensa_verify_config (gdbarch);
3045 /* Pseudo-Register read/write. */
3046 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3047 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3049 /* Set target information. */
3050 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3051 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3052 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3053 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3054 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3056 /* Renumber registers for known formats (stabs and dwarf2). */
3057 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3058 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3060 /* We provide our own function to get register information. */
3061 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3062 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3064 /* To call functions from GDB using dummy frame. */
3065 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3067 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3069 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3071 /* Advance PC across any prologue instructions to reach "real" code. */
3072 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3074 /* Stack grows downward. */
3075 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3077 /* Set breakpoints. */
3078 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
3080 /* After breakpoint instruction or illegal instruction, pc still
3081 points at break instruction, so don't decrement. */
3082 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3084 /* We don't skip args. */
3085 set_gdbarch_frame_args_skip (gdbarch, 0);
3087 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3089 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3091 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3093 /* Frame handling. */
3094 frame_base_set_default (gdbarch, &xtensa_frame_base);
3095 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3096 dwarf2_append_unwinders (gdbarch);
3098 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3100 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3102 xtensa_add_reggroups (gdbarch);
3103 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3105 set_gdbarch_regset_from_core_section (gdbarch,
3106 xtensa_regset_from_core_section);
3108 set_solib_svr4_fetch_link_map_offsets
3109 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3115 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3117 error (_("xtensa_dump_tdep(): not implemented"));
3120 /* Provide a prototype to silence -Wmissing-prototypes. */
3121 extern initialize_file_ftype _initialize_xtensa_tdep;
3124 _initialize_xtensa_tdep (void)
3126 struct cmd_list_element *c;
3128 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3129 xtensa_init_reggroups ();
3131 add_setshow_zinteger_cmd ("xtensa",
3133 &xtensa_debug_level,
3134 _("Set Xtensa debugging."),
3135 _("Show Xtensa debugging."), _("\
3136 When non-zero, Xtensa-specific debugging is enabled. \
3137 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3140 &setdebuglist, &showdebuglist);