1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
142 arreg = a_regnum - tdep->a0_base;
143 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
144 arreg &= tdep->num_aregs - 1;
146 return arreg + tdep->ar_base;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 areg = ar_regnum - tdep->ar_base;
158 if (areg < 0 || areg >= tdep->num_aregs)
160 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
161 return (areg > 15) ? -1 : areg;
164 /* Read Xtensa register directly from the hardware. */
166 xtensa_read_register (int regnum)
170 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
171 return (unsigned long) value;
174 /* Write Xtensa register directly to the hardware. */
176 xtensa_write_register (int regnum, ULONGEST value)
178 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
181 /* Return the window size of the previous call to the function from which we
184 This function is used to extract the return value after a called function
185 has returned to the caller. On Xtensa, the register that holds the return
186 value (from the perspective of the caller) depends on what call
187 instruction was used. For now, we are assuming that the call instruction
188 precedes the current address, so we simply analyze the call instruction.
189 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
190 method to call the inferior function. */
193 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
195 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
200 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
202 /* Read the previous instruction (should be a call[x]{4|8|12}. */
203 read_memory (pc-3, buf, 3);
204 insn = extract_unsigned_integer (buf, 3, byte_order);
206 /* Decode call instruction:
208 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
209 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
211 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
212 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
214 if (byte_order == BFD_ENDIAN_LITTLE)
216 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
217 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
221 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
222 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
228 /* REGISTER INFORMATION */
230 /* Find register by name. */
232 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
236 for (i = 0; i < gdbarch_num_regs (gdbarch)
237 + gdbarch_num_pseudo_regs (gdbarch);
240 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
246 /* Returns the name of a register. */
248 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
250 /* Return the name stored in the register map. */
251 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
252 + gdbarch_num_pseudo_regs (gdbarch))
253 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
255 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
259 /* Return the type of a register. Create a new type, if necessary. */
262 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
266 /* Return signed integer for ARx and Ax registers. */
267 if ((regnum >= tdep->ar_base
268 && regnum < tdep->ar_base + tdep->num_aregs)
269 || (regnum >= tdep->a0_base
270 && regnum < tdep->a0_base + 16))
271 return builtin_type (gdbarch)->builtin_int;
273 if (regnum == gdbarch_pc_regnum (gdbarch)
274 || regnum == tdep->a0_base + 1)
275 return builtin_type (gdbarch)->builtin_data_ptr;
277 /* Return the stored type for all other registers. */
278 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
279 + gdbarch_num_pseudo_regs (gdbarch))
281 xtensa_register_t* reg = &tdep->regmap[regnum];
283 /* Set ctype for this register (only the first time). */
287 struct ctype_cache *tp;
288 int size = reg->byte_size;
290 /* We always use the memory representation,
291 even if the register width is smaller. */
295 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
299 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
303 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
307 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
311 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
315 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
316 if (tp->size == size)
321 char *name = xmalloc (16);
322 tp = xmalloc (sizeof (struct ctype_cache));
323 tp->next = tdep->type_entries;
324 tdep->type_entries = tp;
327 sprintf (name, "int%d", size * 8);
329 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
332 reg->ctype = tp->virtual_type;
338 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
343 /* Return the 'local' register number for stubs, dwarf2, etc.
344 The debugging information enumerates registers starting from 0 for A0
345 to n for An. So, we only have to add the base number for A0. */
348 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
352 if (regnum >= 0 && regnum < 16)
353 return gdbarch_tdep (gdbarch)->a0_base + regnum;
356 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
358 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
361 internal_error (__FILE__, __LINE__,
362 _("invalid dwarf/stabs register number %d"), regnum);
367 /* Write the bits of a masked register to the various registers.
368 Only the masked areas of these registers are modified; the other
369 fields are untouched. The size of masked registers is always less
370 than or equal to 32 bits. */
373 xtensa_register_write_masked (struct regcache *regcache,
374 xtensa_register_t *reg, const gdb_byte *buffer)
376 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
377 const xtensa_mask_t *mask = reg->mask;
379 int shift = 0; /* Shift for next mask (mod 32). */
380 int start, size; /* Start bit and size of current mask. */
382 unsigned int *ptr = value;
383 unsigned int regval, m, mem = 0;
385 int bytesize = reg->byte_size;
386 int bitsize = bytesize * 8;
389 DEBUGTRACE ("xtensa_register_write_masked ()\n");
391 /* Copy the masked register to host byte-order. */
392 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
393 for (i = 0; i < bytesize; i++)
396 mem |= (buffer[bytesize - i - 1] << 24);
401 for (i = 0; i < bytesize; i++)
404 mem |= (buffer[i] << 24);
409 /* We might have to shift the final value:
410 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
411 bytesize & 3 == x -> shift (4-x) * 8. */
413 *ptr = mem >> (((0 - bytesize) & 3) * 8);
417 /* Write the bits to the masked areas of the other registers. */
418 for (i = 0; i < mask->count; i++)
420 start = mask->mask[i].bit_start;
421 size = mask->mask[i].bit_size;
422 regval = mem >> shift;
424 if ((shift += size) > bitsize)
425 error (_("size of all masks is larger than the register"));
434 regval |= mem << (size - shift);
437 /* Make sure we have a valid register. */
438 r = mask->mask[i].reg_num;
439 if (r >= 0 && size > 0)
441 /* Don't overwrite the unmasked areas. */
443 regcache_cooked_read_unsigned (regcache, r, &old_val);
444 m = 0xffffffff >> (32 - size) << start;
446 regval = (regval & m) | (old_val & ~m);
447 regcache_cooked_write_unsigned (regcache, r, regval);
453 /* Read a tie state or mapped registers. Read the masked areas
454 of the registers and assemble them into a single value. */
457 xtensa_register_read_masked (struct regcache *regcache,
458 xtensa_register_t *reg, gdb_byte *buffer)
460 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
461 const xtensa_mask_t *mask = reg->mask;
466 unsigned int *ptr = value;
467 unsigned int regval, mem = 0;
469 int bytesize = reg->byte_size;
470 int bitsize = bytesize * 8;
473 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
474 reg->name == 0 ? "" : reg->name);
476 /* Assemble the register from the masked areas of other registers. */
477 for (i = 0; i < mask->count; i++)
479 int r = mask->mask[i].reg_num;
483 regcache_cooked_read_unsigned (regcache, r, &val);
484 regval = (unsigned int) val;
489 start = mask->mask[i].bit_start;
490 size = mask->mask[i].bit_size;
495 regval &= (0xffffffff >> (32 - size));
497 mem |= regval << shift;
499 if ((shift += size) > bitsize)
500 error (_("size of all masks is larger than the register"));
511 mem = regval >> (size - shift);
518 /* Copy value to target byte order. */
522 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
523 for (i = 0; i < bytesize; i++)
527 buffer[bytesize - i - 1] = mem & 0xff;
531 for (i = 0; i < bytesize; i++)
535 buffer[i] = mem & 0xff;
541 /* Read pseudo registers. */
544 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
545 struct regcache *regcache,
549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
551 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
552 regnum, xtensa_register_name (gdbarch, regnum));
554 if (regnum == gdbarch_num_regs (gdbarch)
555 + gdbarch_num_pseudo_regs (gdbarch) - 1)
556 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
558 /* Read aliases a0..a15, if this is a Windowed ABI. */
559 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
560 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
561 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
563 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
565 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
566 regnum = arreg_number (gdbarch, regnum,
567 extract_unsigned_integer (buf, 4, byte_order));
570 /* We can always read non-pseudo registers. */
571 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
572 regcache_raw_read (regcache, regnum, buffer);
575 /* We have to find out how to deal with priveleged registers.
576 Let's treat them as pseudo-registers, but we cannot read/write them. */
578 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
580 buffer[0] = (gdb_byte)0;
581 buffer[1] = (gdb_byte)0;
582 buffer[2] = (gdb_byte)0;
583 buffer[3] = (gdb_byte)0;
585 /* Pseudo registers. */
587 && regnum < gdbarch_num_regs (gdbarch)
588 + gdbarch_num_pseudo_regs (gdbarch))
590 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
591 xtensa_register_type_t type = reg->type;
592 int flags = gdbarch_tdep (gdbarch)->target_flags;
594 /* We cannot read Unknown or Unmapped registers. */
595 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
597 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
599 warning (_("cannot read register %s"),
600 xtensa_register_name (gdbarch, regnum));
605 /* Some targets cannot read TIE register files. */
606 else if (type == xtRegisterTypeTieRegfile)
608 /* Use 'fetch' to get register? */
609 if (flags & xtTargetFlagsUseFetchStore)
611 warning (_("cannot read register"));
615 /* On some targets (esp. simulators), we can always read the reg. */
616 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
618 warning (_("cannot read register"));
623 /* We can always read mapped registers. */
624 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
626 xtensa_register_read_masked (regcache, reg, buffer);
630 /* Assume that we can read the register. */
631 regcache_raw_read (regcache, regnum, buffer);
634 internal_error (__FILE__, __LINE__,
635 _("invalid register number %d"), regnum);
639 /* Write pseudo registers. */
642 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
643 struct regcache *regcache,
645 const gdb_byte *buffer)
647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
649 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
650 regnum, xtensa_register_name (gdbarch, regnum));
652 if (regnum == gdbarch_num_regs (gdbarch)
653 + gdbarch_num_pseudo_regs (gdbarch) -1)
654 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
656 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
657 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
658 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
659 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
661 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
664 regcache_raw_read (regcache,
665 gdbarch_tdep (gdbarch)->wb_regnum, buf);
666 regnum = arreg_number (gdbarch, regnum,
667 extract_unsigned_integer (buf, 4, byte_order));
670 /* We can always write 'core' registers.
671 Note: We might have converted Ax->ARy. */
672 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
673 regcache_raw_write (regcache, regnum, buffer);
675 /* We have to find out how to deal with priveleged registers.
676 Let's treat them as pseudo-registers, but we cannot read/write them. */
678 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
682 /* Pseudo registers. */
684 && regnum < gdbarch_num_regs (gdbarch)
685 + gdbarch_num_pseudo_regs (gdbarch))
687 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
688 xtensa_register_type_t type = reg->type;
689 int flags = gdbarch_tdep (gdbarch)->target_flags;
691 /* On most targets, we cannot write registers
692 of type "Unknown" or "Unmapped". */
693 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
695 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
697 warning (_("cannot write register %s"),
698 xtensa_register_name (gdbarch, regnum));
703 /* Some targets cannot read TIE register files. */
704 else if (type == xtRegisterTypeTieRegfile)
706 /* Use 'store' to get register? */
707 if (flags & xtTargetFlagsUseFetchStore)
709 warning (_("cannot write register"));
713 /* On some targets (esp. simulators), we can always write
715 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
717 warning (_("cannot write register"));
722 /* We can always write mapped registers. */
723 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
725 xtensa_register_write_masked (regcache, reg, buffer);
729 /* Assume that we can write the register. */
730 regcache_raw_write (regcache, regnum, buffer);
733 internal_error (__FILE__, __LINE__,
734 _("invalid register number %d"), regnum);
737 static struct reggroup *xtensa_ar_reggroup;
738 static struct reggroup *xtensa_user_reggroup;
739 static struct reggroup *xtensa_vectra_reggroup;
740 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
743 xtensa_init_reggroups (void)
746 char cpname[] = "cp0";
748 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
749 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
750 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
752 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
755 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
760 xtensa_add_reggroups (struct gdbarch *gdbarch)
764 /* Predefined groups. */
765 reggroup_add (gdbarch, all_reggroup);
766 reggroup_add (gdbarch, save_reggroup);
767 reggroup_add (gdbarch, restore_reggroup);
768 reggroup_add (gdbarch, system_reggroup);
769 reggroup_add (gdbarch, vector_reggroup);
770 reggroup_add (gdbarch, general_reggroup);
771 reggroup_add (gdbarch, float_reggroup);
773 /* Xtensa-specific groups. */
774 reggroup_add (gdbarch, xtensa_ar_reggroup);
775 reggroup_add (gdbarch, xtensa_user_reggroup);
776 reggroup_add (gdbarch, xtensa_vectra_reggroup);
778 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
779 reggroup_add (gdbarch, xtensa_cp[i]);
783 xtensa_coprocessor_register_group (struct reggroup *group)
787 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
788 if (group == xtensa_cp[i])
794 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
795 | XTENSA_REGISTER_FLAGS_WRITABLE \
796 | XTENSA_REGISTER_FLAGS_VOLATILE)
798 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
799 | XTENSA_REGISTER_FLAGS_WRITABLE)
802 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
804 struct reggroup *group)
806 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
807 xtensa_register_type_t type = reg->type;
808 xtensa_register_group_t rg = reg->group;
811 if (group == save_reggroup)
812 /* Every single register should be included into the list of registers
813 to be watched for changes while using -data-list-changed-registers. */
816 /* First, skip registers that are not visible to this target
817 (unknown and unmapped registers when not using ISS). */
819 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
821 if (group == all_reggroup)
823 if (group == xtensa_ar_reggroup)
824 return rg & xtRegisterGroupAddrReg;
825 if (group == xtensa_user_reggroup)
826 return rg & xtRegisterGroupUser;
827 if (group == float_reggroup)
828 return rg & xtRegisterGroupFloat;
829 if (group == general_reggroup)
830 return rg & xtRegisterGroupGeneral;
831 if (group == system_reggroup)
832 return rg & xtRegisterGroupState;
833 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
834 return rg & xtRegisterGroupVectra;
835 if (group == restore_reggroup)
836 return (regnum < gdbarch_num_regs (gdbarch)
837 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
838 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
839 return rg & (xtRegisterGroupCP0 << cp_number);
845 /* Supply register REGNUM from the buffer specified by GREGS and LEN
846 in the general-purpose register set REGSET to register cache
847 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
850 xtensa_supply_gregset (const struct regset *regset,
856 const xtensa_elf_gregset_t *regs = gregs;
857 struct gdbarch *gdbarch = get_regcache_arch (rc);
860 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
862 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
863 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
864 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
865 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
866 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
867 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
868 (char *) ®s->windowbase);
869 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
870 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
871 (char *) ®s->windowstart);
872 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
873 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
874 (char *) ®s->lbeg);
875 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
876 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
877 (char *) ®s->lend);
878 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
879 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
880 (char *) ®s->lcount);
881 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
882 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
883 (char *) ®s->sar);
884 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
885 && regnum < gdbarch_tdep (gdbarch)->ar_base
886 + gdbarch_tdep (gdbarch)->num_aregs)
887 regcache_raw_supply (rc, regnum,
888 (char *) ®s->ar[regnum - gdbarch_tdep
889 (gdbarch)->ar_base]);
890 else if (regnum == -1)
892 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
893 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
894 (char *) ®s->ar[i]);
899 /* Xtensa register set. */
905 xtensa_supply_gregset
909 /* Return the appropriate register set for the core
910 section identified by SECT_NAME and SECT_SIZE. */
912 static const struct regset *
913 xtensa_regset_from_core_section (struct gdbarch *core_arch,
914 const char *sect_name,
917 DEBUGTRACE ("xtensa_regset_from_core_section "
918 "(..., sect_name==\"%s\", sect_size==%x)\n",
919 sect_name, (unsigned int) sect_size);
921 if (strcmp (sect_name, ".reg") == 0
922 && sect_size >= sizeof(xtensa_elf_gregset_t))
923 return &xtensa_gregset;
929 /* Handling frames. */
931 /* Number of registers to save in case of Windowed ABI. */
932 #define XTENSA_NUM_SAVED_AREGS 12
934 /* Frame cache part for Windowed ABI. */
935 typedef struct xtensa_windowed_frame_cache
937 int wb; /* WINDOWBASE of the previous frame. */
938 int callsize; /* Call size of this frame. */
939 int ws; /* WINDOWSTART of the previous frame. It keeps track of
940 life windows only. If there is no bit set for the
941 window, that means it had been already spilled
942 because of window overflow. */
944 /* Addresses of spilled A-registers.
945 AREGS[i] == -1, if corresponding AR is alive. */
946 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
947 } xtensa_windowed_frame_cache_t;
949 /* Call0 ABI Definitions. */
951 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
953 #define C0_NREGS 16 /* Number of A-registers to track. */
954 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
955 #define C0_SP 1 /* Register used as SP. */
956 #define C0_FP 15 /* Register used as FP. */
957 #define C0_RA 0 /* Register used as return address. */
958 #define C0_ARGS 2 /* Register used as first arg/retval. */
959 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
961 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
962 A-register where the current content of the reg came from (in terms
963 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
964 mean that the orignal content of the register was saved to the stack.
965 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
966 know where SP will end up until the entire prologue has been analyzed. */
968 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
969 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
970 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
972 extern xtensa_isa xtensa_default_isa;
974 typedef struct xtensa_c0reg
976 int fr_reg; /* original register from which register content
977 is derived, or C0_CONST, or C0_INEXP. */
978 int fr_ofs; /* constant offset from reg, or immediate value. */
979 int to_stk; /* offset from original SP to register (4-byte aligned),
980 or C0_NOSTK if register has not been saved. */
983 /* Frame cache part for Call0 ABI. */
984 typedef struct xtensa_call0_frame_cache
986 int c0_frmsz; /* Stack frame size. */
987 int c0_hasfp; /* Current frame uses frame pointer. */
988 int fp_regnum; /* A-register used as FP. */
989 int c0_fp; /* Actual value of frame pointer. */
990 int c0_fpalign; /* Dinamic adjustment for the stack
991 pointer. It's an AND mask. Zero,
992 if alignment was not adjusted. */
993 int c0_old_sp; /* In case of dynamic adjustment, it is
994 a register holding unaligned sp.
995 C0_INEXP, when undefined. */
996 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
997 stack offset. C0_NOSTK otherwise. */
999 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
1000 } xtensa_call0_frame_cache_t;
1002 typedef struct xtensa_frame_cache
1004 CORE_ADDR base; /* Stack pointer of this frame. */
1005 CORE_ADDR pc; /* PC of this frame at the function entry point. */
1006 CORE_ADDR ra; /* The raw return address of this frame. */
1007 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1008 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1009 int call0; /* It's a call0 framework (else windowed). */
1012 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1013 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1015 } xtensa_frame_cache_t;
1018 static struct xtensa_frame_cache *
1019 xtensa_alloc_frame_cache (int windowed)
1021 xtensa_frame_cache_t *cache;
1024 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1026 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1033 cache->call0 = !windowed;
1036 cache->c0.c0_frmsz = -1;
1037 cache->c0.c0_hasfp = 0;
1038 cache->c0.fp_regnum = -1;
1039 cache->c0.c0_fp = -1;
1040 cache->c0.c0_fpalign = 0;
1041 cache->c0.c0_old_sp = C0_INEXP;
1042 cache->c0.c0_sp_ofs = C0_NOSTK;
1044 for (i = 0; i < C0_NREGS; i++)
1046 cache->c0.c0_rt[i].fr_reg = i;
1047 cache->c0.c0_rt[i].fr_ofs = 0;
1048 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1055 cache->wd.callsize = -1;
1057 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1058 cache->wd.aregs[i] = -1;
1065 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1067 return address & ~15;
1072 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1077 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1078 host_address_to_string (next_frame));
1080 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1081 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1083 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1089 static struct frame_id
1090 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1094 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1096 pc = get_frame_pc (this_frame);
1097 fp = get_frame_register_unsigned
1098 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1100 /* Make dummy frame ID unique by adding a constant. */
1101 return frame_id_build (fp + SP_ALIGNMENT, pc);
1104 /* Returns true, if instruction to execute next is unique to Xtensa Window
1105 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1108 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1110 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1111 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1114 if (byte_order == BFD_ENDIAN_BIG)
1116 /* Check, if this is L32E or S32E. */
1117 code = insn & 0xf000ff00;
1118 if ((code == 0x00009000) || (code == 0x00009400))
1120 /* Check, if this is RFWU or RFWO. */
1121 code = insn & 0xffffff00;
1122 return ((code == 0x00430000) || (code == 0x00530000));
1126 /* Check, if this is L32E or S32E. */
1127 code = insn & 0x00ff000f;
1128 if ((code == 0x090000) || (code == 0x490000))
1130 /* Check, if this is RFWU or RFWO. */
1131 code = insn & 0x00ffffff;
1132 return ((code == 0x00003400) || (code == 0x00003500));
1136 /* Returns the best guess about which register is a frame pointer
1137 for the function containing CURRENT_PC. */
1139 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1140 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1143 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1145 #define RETURN_FP goto done
1147 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1148 CORE_ADDR start_addr;
1150 xtensa_insnbuf ins, slot;
1151 char ibuf[XTENSA_ISA_BSZ];
1152 CORE_ADDR ia, bt, ba;
1154 int ilen, islots, is;
1156 const char *opcname;
1158 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1159 if (start_addr == 0)
1162 if (!xtensa_default_isa)
1163 xtensa_default_isa = xtensa_isa_init (0, 0);
1164 isa = xtensa_default_isa;
1165 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1166 ins = xtensa_insnbuf_alloc (isa);
1167 slot = xtensa_insnbuf_alloc (isa);
1170 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1172 if (ia + xtensa_isa_maxlength (isa) > bt)
1175 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1176 ? ba + XTENSA_ISA_BSZ : current_pc;
1177 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1181 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1182 ifmt = xtensa_format_decode (isa, ins);
1183 if (ifmt == XTENSA_UNDEFINED)
1185 ilen = xtensa_format_length (isa, ifmt);
1186 if (ilen == XTENSA_UNDEFINED)
1188 islots = xtensa_format_num_slots (isa, ifmt);
1189 if (islots == XTENSA_UNDEFINED)
1192 for (is = 0; is < islots; ++is)
1194 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1197 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1198 if (opc == XTENSA_UNDEFINED)
1201 opcname = xtensa_opcode_name (isa, opc);
1203 if (strcasecmp (opcname, "mov.n") == 0
1204 || strcasecmp (opcname, "or") == 0)
1206 unsigned int register_operand;
1208 /* Possible candidate for setting frame pointer
1209 from A1. This is what we are looking for. */
1211 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1212 is, slot, ®ister_operand) != 0)
1214 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1216 if (register_operand == 1) /* Mov{.n} FP A1. */
1218 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1219 ®ister_operand) != 0)
1221 if (xtensa_operand_decode (isa, opc, 0,
1222 ®ister_operand) != 0)
1226 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1232 /* We have problems decoding the memory. */
1234 || strcasecmp (opcname, "ill") == 0
1235 || strcasecmp (opcname, "ill.n") == 0
1236 /* Hit planted breakpoint. */
1237 || strcasecmp (opcname, "break") == 0
1238 || strcasecmp (opcname, "break.n") == 0
1239 /* Flow control instructions finish prologue. */
1240 || xtensa_opcode_is_branch (isa, opc) > 0
1241 || xtensa_opcode_is_jump (isa, opc) > 0
1242 || xtensa_opcode_is_loop (isa, opc) > 0
1243 || xtensa_opcode_is_call (isa, opc) > 0
1244 || strcasecmp (opcname, "simcall") == 0
1245 || strcasecmp (opcname, "syscall") == 0)
1246 /* Can not continue analysis. */
1251 xtensa_insnbuf_free(isa, slot);
1252 xtensa_insnbuf_free(isa, ins);
1256 /* The key values to identify the frame using "cache" are
1258 cache->base = SP (or best guess about FP) of this frame;
1259 cache->pc = entry-PC (entry point of the frame function);
1260 cache->prev_sp = SP of the previous frame. */
1263 call0_frame_cache (struct frame_info *this_frame,
1264 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1267 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1268 xtensa_frame_cache_t *cache,
1271 static struct xtensa_frame_cache *
1272 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1274 xtensa_frame_cache_t *cache;
1275 CORE_ADDR ra, wb, ws, pc, sp, ps;
1276 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1277 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1278 unsigned int fp_regnum;
1279 int windowed, ps_regnum;
1284 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1285 ps_regnum = gdbarch_ps_regnum (gdbarch);
1286 ps = (ps_regnum >= 0
1287 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1289 windowed = windowing_enabled (gdbarch, ps);
1291 /* Get pristine xtensa-frame. */
1292 cache = xtensa_alloc_frame_cache (windowed);
1293 *this_cache = cache;
1299 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1300 wb = get_frame_register_unsigned (this_frame,
1301 gdbarch_tdep (gdbarch)->wb_regnum);
1302 ws = get_frame_register_unsigned (this_frame,
1303 gdbarch_tdep (gdbarch)->ws_regnum);
1305 op1 = read_memory_integer (pc, 1, byte_order);
1306 if (XTENSA_IS_ENTRY (gdbarch, op1))
1308 int callinc = CALLINC (ps);
1309 ra = get_frame_register_unsigned
1310 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1312 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1313 cache->wd.callsize = 0;
1316 cache->prev_sp = get_frame_register_unsigned
1317 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1319 /* This only can be the outermost frame since we are
1320 just about to execute ENTRY. SP hasn't been set yet.
1321 We can assume any frame size, because it does not
1322 matter, and, let's fake frame base in cache. */
1323 cache->base = cache->prev_sp - 16;
1326 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1327 cache->ps = (ps & ~PS_CALLINC_MASK)
1328 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1334 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1335 ra = get_frame_register_unsigned (this_frame,
1336 gdbarch_tdep (gdbarch)->a0_base);
1337 cache->wd.callsize = WINSIZE (ra);
1338 cache->wd.wb = (wb - cache->wd.callsize / 4)
1339 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1340 cache->wd.ws = ws & ~(1 << wb);
1342 cache->pc = get_frame_func (this_frame);
1343 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1344 cache->ps = (ps & ~PS_CALLINC_MASK)
1345 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1348 if (cache->wd.ws == 0)
1353 sp = get_frame_register_unsigned
1354 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1356 for (i = 0; i < 4; i++, sp += 4)
1358 cache->wd.aregs[i] = sp;
1361 if (cache->wd.callsize > 4)
1363 /* Set A4...A7/A11. */
1364 /* Get the SP of the frame previous to the previous one.
1365 To achieve this, we have to dereference SP twice. */
1366 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1367 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1368 sp -= cache->wd.callsize * 4;
1370 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1372 cache->wd.aregs[i] = sp;
1377 if ((cache->prev_sp == 0) && ( ra != 0 ))
1378 /* If RA is equal to 0 this frame is an outermost frame. Leave
1379 cache->prev_sp unchanged marking the boundary of the frame stack. */
1381 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1383 /* Register window overflow already happened.
1384 We can read caller's SP from the proper spill loction. */
1385 sp = get_frame_register_unsigned
1386 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1387 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1391 /* Read caller's frame SP directly from the previous window. */
1392 int regnum = arreg_number
1393 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1396 cache->prev_sp = xtensa_read_register (regnum);
1400 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1402 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1404 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1405 /* Everything was set already, including cache->base. */
1408 else /* Call0 framework. */
1410 call0_frame_cache (this_frame, cache, pc);
1411 fp_regnum = cache->c0.fp_regnum;
1414 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1419 static int xtensa_session_once_reported = 1;
1421 /* Report a problem with prologue analysis while doing backtracing.
1422 But, do it only once to avoid annoyng repeated messages. */
1427 if (xtensa_session_once_reported == 0)
1429 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1430 This message will not be repeated in this session.\n"));
1432 xtensa_session_once_reported = 1;
1437 xtensa_frame_this_id (struct frame_info *this_frame,
1439 struct frame_id *this_id)
1441 struct xtensa_frame_cache *cache =
1442 xtensa_frame_cache (this_frame, this_cache);
1444 if (cache->prev_sp == 0)
1447 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1450 static struct value *
1451 xtensa_frame_prev_register (struct frame_info *this_frame,
1455 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1456 struct xtensa_frame_cache *cache;
1457 ULONGEST saved_reg = 0;
1460 if (*this_cache == NULL)
1461 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1462 cache = *this_cache;
1464 if (regnum ==gdbarch_pc_regnum (gdbarch))
1465 saved_reg = cache->ra;
1466 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1467 saved_reg = cache->prev_sp;
1468 else if (!cache->call0)
1470 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1471 saved_reg = cache->wd.ws;
1472 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1473 saved_reg = cache->wd.wb;
1474 else if (regnum == gdbarch_ps_regnum (gdbarch))
1475 saved_reg = cache->ps;
1483 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1485 if (!cache->call0) /* Windowed ABI. */
1487 /* Convert A-register numbers to AR-register numbers,
1488 if we deal with A-register. */
1489 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1490 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1491 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1493 /* Check, if we deal with AR-register saved on stack. */
1494 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1495 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1496 + gdbarch_tdep (gdbarch)->num_aregs))
1498 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1501 && areg < XTENSA_NUM_SAVED_AREGS
1502 && cache->wd.aregs[areg] != -1)
1503 return frame_unwind_got_memory (this_frame, regnum,
1504 cache->wd.aregs[areg]);
1507 else /* Call0 ABI. */
1509 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1510 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1512 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1519 /* If register was saved in the prologue, retrieve it. */
1520 stkofs = cache->c0.c0_rt[reg].to_stk;
1521 if (stkofs != C0_NOSTK)
1523 /* Determine SP on entry based on FP. */
1524 spe = cache->c0.c0_fp
1525 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1527 return frame_unwind_got_memory (this_frame, regnum,
1533 /* All other registers have been either saved to
1534 the stack or are still alive in the processor. */
1536 return frame_unwind_got_register (this_frame, regnum, regnum);
1540 static const struct frame_unwind
1544 xtensa_frame_this_id,
1545 xtensa_frame_prev_register,
1547 default_frame_sniffer
1551 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1553 struct xtensa_frame_cache *cache =
1554 xtensa_frame_cache (this_frame, this_cache);
1559 static const struct frame_base
1563 xtensa_frame_base_address,
1564 xtensa_frame_base_address,
1565 xtensa_frame_base_address
1570 xtensa_extract_return_value (struct type *type,
1571 struct regcache *regcache,
1574 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1575 bfd_byte *valbuf = dst;
1576 int len = TYPE_LENGTH (type);
1581 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1583 gdb_assert(len > 0);
1585 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1587 /* First, we have to find the caller window in the register file. */
1588 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1589 callsize = extract_call_winsize (gdbarch, pc);
1591 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1592 if (len > (callsize > 8 ? 8 : 16))
1593 internal_error (__FILE__, __LINE__,
1594 _("cannot extract return value of %d bytes long"),
1597 /* Get the register offset of the return
1598 register (A2) in the caller window. */
1599 regcache_raw_read_unsigned
1600 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1601 areg = arreg_number (gdbarch,
1602 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1606 /* No windowing hardware - Call0 ABI. */
1607 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1610 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1612 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1615 for (; len > 0; len -= 4, areg++, valbuf += 4)
1618 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1620 regcache_raw_read (regcache, areg, valbuf);
1626 xtensa_store_return_value (struct type *type,
1627 struct regcache *regcache,
1630 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1631 const bfd_byte *valbuf = dst;
1635 int len = TYPE_LENGTH (type);
1638 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1640 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1642 regcache_raw_read_unsigned
1643 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1644 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1645 callsize = extract_call_winsize (gdbarch, pc);
1647 if (len > (callsize > 8 ? 8 : 16))
1648 internal_error (__FILE__, __LINE__,
1649 _("unimplemented for this length: %d"),
1650 TYPE_LENGTH (type));
1651 areg = arreg_number (gdbarch,
1652 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1654 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1655 callsize, (int) wb);
1659 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1662 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1665 for (; len > 0; len -= 4, areg++, valbuf += 4)
1668 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1670 regcache_raw_write (regcache, areg, valbuf);
1675 static enum return_value_convention
1676 xtensa_return_value (struct gdbarch *gdbarch,
1677 struct type *func_type,
1678 struct type *valtype,
1679 struct regcache *regcache,
1681 const gdb_byte *writebuf)
1683 /* Structures up to 16 bytes are returned in registers. */
1685 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1686 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1687 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1688 && TYPE_LENGTH (valtype) > 16);
1691 return RETURN_VALUE_STRUCT_CONVENTION;
1693 DEBUGTRACE ("xtensa_return_value(...)\n");
1695 if (writebuf != NULL)
1697 xtensa_store_return_value (valtype, regcache, writebuf);
1700 if (readbuf != NULL)
1702 gdb_assert (!struct_return);
1703 xtensa_extract_return_value (valtype, regcache, readbuf);
1705 return RETURN_VALUE_REGISTER_CONVENTION;
1712 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1713 struct value *function,
1714 struct regcache *regcache,
1717 struct value **args,
1720 CORE_ADDR struct_addr)
1722 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1724 int size, onstack_size;
1725 gdb_byte *buf = (gdb_byte *) alloca (16);
1727 struct argument_info
1729 const bfd_byte *contents;
1731 int onstack; /* onstack == 0 => in reg */
1732 int align; /* alignment */
1735 int offset; /* stack offset if on stack. */
1736 int regno; /* regno if in register. */
1740 struct argument_info *arg_info =
1741 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1745 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1747 if (xtensa_debug_level > 3)
1750 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1751 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1752 "struct_addr=0x%x\n",
1753 (int) sp, (int) struct_return, (int) struct_addr);
1755 for (i = 0; i < nargs; i++)
1757 struct value *arg = args[i];
1758 struct type *arg_type = check_typedef (value_type (arg));
1759 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1760 host_address_to_string (arg),
1761 TYPE_LENGTH (arg_type));
1762 switch (TYPE_CODE (arg_type))
1765 fprintf_unfiltered (gdb_stdlog, "int");
1767 case TYPE_CODE_STRUCT:
1768 fprintf_unfiltered (gdb_stdlog, "struct");
1771 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1774 fprintf_unfiltered (gdb_stdlog, " %s\n",
1775 host_address_to_string (value_contents (arg)));
1779 /* First loop: collect information.
1780 Cast into type_long. (This shouldn't happen often for C because
1781 GDB already does this earlier.) It's possible that GDB could
1782 do it all the time but it's harmless to leave this code here. */
1789 size = REGISTER_SIZE;
1791 for (i = 0; i < nargs; i++)
1793 struct argument_info *info = &arg_info[i];
1794 struct value *arg = args[i];
1795 struct type *arg_type = check_typedef (value_type (arg));
1797 switch (TYPE_CODE (arg_type))
1800 case TYPE_CODE_BOOL:
1801 case TYPE_CODE_CHAR:
1802 case TYPE_CODE_RANGE:
1803 case TYPE_CODE_ENUM:
1805 /* Cast argument to long if necessary as the mask does it too. */
1806 if (TYPE_LENGTH (arg_type)
1807 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1809 arg_type = builtin_type (gdbarch)->builtin_long;
1810 arg = value_cast (arg_type, arg);
1812 /* Aligment is equal to the type length for the basic types. */
1813 info->align = TYPE_LENGTH (arg_type);
1818 /* Align doubles correctly. */
1819 if (TYPE_LENGTH (arg_type)
1820 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1821 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1823 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1826 case TYPE_CODE_STRUCT:
1828 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1831 info->length = TYPE_LENGTH (arg_type);
1832 info->contents = value_contents (arg);
1834 /* Align size and onstack_size. */
1835 size = (size + info->align - 1) & ~(info->align - 1);
1836 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1838 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1841 info->u.offset = onstack_size;
1842 onstack_size += info->length;
1847 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1849 size += info->length;
1852 /* Adjust the stack pointer and align it. */
1853 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1855 /* Simulate MOVSP, if Windowed ABI. */
1856 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1859 read_memory (osp - 16, buf, 16);
1860 write_memory (sp - 16, buf, 16);
1863 /* Second Loop: Load arguments. */
1867 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1868 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1871 for (i = 0; i < nargs; i++)
1873 struct argument_info *info = &arg_info[i];
1877 int n = info->length;
1878 CORE_ADDR offset = sp + info->u.offset;
1880 /* Odd-sized structs are aligned to the lower side of a memory
1881 word in big-endian mode and require a shift. This only
1882 applies for structures smaller than one word. */
1884 if (n < REGISTER_SIZE
1885 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1886 offset += (REGISTER_SIZE - n);
1888 write_memory (offset, info->contents, info->length);
1893 int n = info->length;
1894 const bfd_byte *cp = info->contents;
1895 int r = info->u.regno;
1897 /* Odd-sized structs are aligned to the lower side of registers in
1898 big-endian mode and require a shift. The odd-sized leftover will
1899 be at the end. Note that this is only true for structures smaller
1900 than REGISTER_SIZE; for larger odd-sized structures the excess
1901 will be left-aligned in the register on both endiannesses. */
1903 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1906 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1907 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1909 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1910 regcache_cooked_write (regcache, r, buf);
1912 cp += REGISTER_SIZE;
1919 regcache_cooked_write (regcache, r, cp);
1921 cp += REGISTER_SIZE;
1928 /* Set the return address of dummy frame to the dummy address.
1929 The return address for the current function (in A0) is
1930 saved in the dummy frame, so we can savely overwrite A0 here. */
1932 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1936 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1937 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1938 ps = (unsigned long) val & ~0x00030000;
1939 regcache_cooked_write_unsigned
1940 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1941 regcache_cooked_write_unsigned (regcache,
1942 gdbarch_ps_regnum (gdbarch),
1945 /* All the registers have been saved. After executing
1946 dummy call, they all will be restored. So it's safe
1947 to modify WINDOWSTART register to make it look like there
1948 is only one register window corresponding to WINDOWEBASE. */
1950 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1951 regcache_cooked_write_unsigned
1952 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1953 1 << extract_unsigned_integer (buf, 4, byte_order));
1957 /* Simulate CALL0: write RA into A0 register. */
1958 regcache_cooked_write_unsigned
1959 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1962 /* Set new stack pointer and return it. */
1963 regcache_cooked_write_unsigned (regcache,
1964 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1965 /* Make dummy frame ID unique by adding a constant. */
1966 return sp + SP_ALIGNMENT;
1970 /* Return a breakpoint for the current location of PC. We always use
1971 the density version if we have density instructions (regardless of the
1972 current instruction at PC), and use regular instructions otherwise. */
1974 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1975 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1976 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1977 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1979 static const unsigned char *
1980 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1983 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1984 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1985 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1986 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1988 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1990 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1992 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1994 *lenptr = sizeof (density_big_breakpoint);
1995 return density_big_breakpoint;
1999 *lenptr = sizeof (density_little_breakpoint);
2000 return density_little_breakpoint;
2005 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2007 *lenptr = sizeof (big_breakpoint);
2008 return big_breakpoint;
2012 *lenptr = sizeof (little_breakpoint);
2013 return little_breakpoint;
2018 /* Call0 ABI support routines. */
2020 /* Return true, if PC points to "ret" or "ret.n". */
2023 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2025 #define RETURN_RET goto done
2027 xtensa_insnbuf ins, slot;
2028 char ibuf[XTENSA_ISA_BSZ];
2029 CORE_ADDR ia, bt, ba;
2031 int ilen, islots, is;
2033 const char *opcname;
2036 isa = xtensa_default_isa;
2037 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2038 ins = xtensa_insnbuf_alloc (isa);
2039 slot = xtensa_insnbuf_alloc (isa);
2042 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2044 if (ia + xtensa_isa_maxlength (isa) > bt)
2047 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2048 ? ba + XTENSA_ISA_BSZ : finish_pc;
2049 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2053 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2054 ifmt = xtensa_format_decode (isa, ins);
2055 if (ifmt == XTENSA_UNDEFINED)
2057 ilen = xtensa_format_length (isa, ifmt);
2058 if (ilen == XTENSA_UNDEFINED)
2060 islots = xtensa_format_num_slots (isa, ifmt);
2061 if (islots == XTENSA_UNDEFINED)
2064 for (is = 0; is < islots; ++is)
2066 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2069 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2070 if (opc == XTENSA_UNDEFINED)
2073 opcname = xtensa_opcode_name (isa, opc);
2075 if ((strcasecmp (opcname, "ret.n") == 0)
2076 || (strcasecmp (opcname, "ret") == 0))
2084 xtensa_insnbuf_free(isa, slot);
2085 xtensa_insnbuf_free(isa, ins);
2089 /* Call0 opcode class. Opcodes are preclassified according to what they
2090 mean for Call0 prologue analysis, and their number of significant operands.
2091 The purpose of this is to simplify prologue analysis by separating
2092 instruction decoding (libisa) from the semantics of prologue analysis. */
2096 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2097 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2098 c0opc_flow, /* Flow control insn. */
2099 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2100 c0opc_break, /* Debugger software breakpoints. */
2101 c0opc_add, /* Adding two registers. */
2102 c0opc_addi, /* Adding a register and an immediate. */
2103 c0opc_and, /* Bitwise "and"-ing two registers. */
2104 c0opc_sub, /* Subtracting a register from a register. */
2105 c0opc_mov, /* Moving a register to a register. */
2106 c0opc_movi, /* Moving an immediate to a register. */
2107 c0opc_l32r, /* Loading a literal. */
2108 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2109 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2110 c0opc_l32e, /* L32E instruction. */
2111 c0opc_s32e, /* S32E instruction. */
2112 c0opc_rfwo, /* RFWO instruction. */
2113 c0opc_rfwu, /* RFWU instruction. */
2114 c0opc_NrOf /* Number of opcode classifications. */
2117 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2120 rwx_special_register (const char *opcname)
2122 char ch = *opcname++;
2124 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2126 if (*opcname++ != 's')
2128 if (*opcname++ != 'r')
2130 if (*opcname++ != '.')
2136 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2138 static xtensa_insn_kind
2139 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2141 const char *opcname;
2142 xtensa_insn_kind opclass = c0opc_uninteresting;
2144 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2146 /* Get opcode name and handle special classifications. */
2148 opcname = xtensa_opcode_name (isa, opc);
2151 || strcasecmp (opcname, "ill") == 0
2152 || strcasecmp (opcname, "ill.n") == 0)
2153 opclass = c0opc_illegal;
2154 else if (strcasecmp (opcname, "break") == 0
2155 || strcasecmp (opcname, "break.n") == 0)
2156 opclass = c0opc_break;
2157 else if (strcasecmp (opcname, "entry") == 0)
2158 opclass = c0opc_entry;
2159 else if (strcasecmp (opcname, "rfwo") == 0)
2160 opclass = c0opc_rfwo;
2161 else if (strcasecmp (opcname, "rfwu") == 0)
2162 opclass = c0opc_rfwu;
2163 else if (xtensa_opcode_is_branch (isa, opc) > 0
2164 || xtensa_opcode_is_jump (isa, opc) > 0
2165 || xtensa_opcode_is_loop (isa, opc) > 0
2166 || xtensa_opcode_is_call (isa, opc) > 0
2167 || strcasecmp (opcname, "simcall") == 0
2168 || strcasecmp (opcname, "syscall") == 0)
2169 opclass = c0opc_flow;
2171 /* Also, classify specific opcodes that need to be tracked. */
2172 else if (strcasecmp (opcname, "add") == 0
2173 || strcasecmp (opcname, "add.n") == 0)
2174 opclass = c0opc_add;
2175 else if (strcasecmp (opcname, "and") == 0)
2176 opclass = c0opc_and;
2177 else if (strcasecmp (opcname, "addi") == 0
2178 || strcasecmp (opcname, "addi.n") == 0
2179 || strcasecmp (opcname, "addmi") == 0)
2180 opclass = c0opc_addi;
2181 else if (strcasecmp (opcname, "sub") == 0)
2182 opclass = c0opc_sub;
2183 else if (strcasecmp (opcname, "mov.n") == 0
2184 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2185 opclass = c0opc_mov;
2186 else if (strcasecmp (opcname, "movi") == 0
2187 || strcasecmp (opcname, "movi.n") == 0)
2188 opclass = c0opc_movi;
2189 else if (strcasecmp (opcname, "l32r") == 0)
2190 opclass = c0opc_l32r;
2191 else if (strcasecmp (opcname, "s32i") == 0
2192 || strcasecmp (opcname, "s32i.n") == 0)
2193 opclass = c0opc_s32i;
2194 else if (strcasecmp (opcname, "l32e") == 0)
2195 opclass = c0opc_l32e;
2196 else if (strcasecmp (opcname, "s32e") == 0)
2197 opclass = c0opc_s32e;
2198 else if (rwx_special_register (opcname))
2199 opclass = c0opc_rwxsr;
2204 /* Tracks register movement/mutation for a given operation, which may
2205 be within a bundle. Updates the destination register tracking info
2206 accordingly. The pc is needed only for pc-relative load instructions
2207 (eg. l32r). The SP register number is needed to identify stores to
2208 the stack frame. Returns 0, if analysis was succesfull, non-zero
2212 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2213 xtensa_insn_kind opclass, int nods, unsigned odv[],
2214 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2216 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2217 unsigned litbase, litaddr, litval;
2222 /* 3 operands: dst, src, imm. */
2223 gdb_assert (nods == 3);
2224 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2225 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2228 /* 3 operands: dst, src1, src2. */
2229 gdb_assert (nods == 3);
2230 if (src[odv[1]].fr_reg == C0_CONST)
2232 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2233 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2235 else if (src[odv[2]].fr_reg == C0_CONST)
2237 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2238 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2240 else dst[odv[0]].fr_reg = C0_INEXP;
2243 /* 3 operands: dst, src1, src2. */
2244 gdb_assert (nods == 3);
2245 if (cache->c0.c0_fpalign == 0)
2247 /* Handle dynamic stack alignment. */
2248 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2250 if (src[odv[2]].fr_reg == C0_CONST)
2251 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2254 else if ((src[odv[0]].fr_reg == spreg)
2255 && (src[odv[2]].fr_reg == spreg))
2257 if (src[odv[1]].fr_reg == C0_CONST)
2258 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2261 /* else fall through. */
2263 if (src[odv[1]].fr_reg == C0_CONST)
2265 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2266 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2268 else if (src[odv[2]].fr_reg == C0_CONST)
2270 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2271 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2273 else dst[odv[0]].fr_reg = C0_INEXP;
2276 /* 3 operands: dst, src1, src2. */
2277 gdb_assert (nods == 3);
2278 if (src[odv[2]].fr_reg == C0_CONST)
2280 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2281 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2283 else dst[odv[0]].fr_reg = C0_INEXP;
2286 /* 2 operands: dst, src [, src]. */
2287 gdb_assert (nods == 2);
2288 /* First, check if it's a special case of saving unaligned SP
2289 to a spare register in case of dynamic stack adjustment.
2290 But, only do it one time. The second time could be initializing
2291 frame pointer. We don't want to overwrite the first one. */
2292 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2293 cache->c0.c0_old_sp = odv[0];
2295 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2296 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2299 /* 2 operands: dst, imm. */
2300 gdb_assert (nods == 2);
2301 dst[odv[0]].fr_reg = C0_CONST;
2302 dst[odv[0]].fr_ofs = odv[1];
2305 /* 2 operands: dst, literal offset. */
2306 gdb_assert (nods == 2);
2307 /* litbase = xtensa_get_litbase (pc); can be also used. */
2308 litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
2309 ? 0 : xtensa_read_register
2310 (gdbarch_tdep (gdbarch)->litbase_regnum);
2311 litaddr = litbase & 1
2312 ? (litbase & ~1) + (signed)odv[1]
2313 : (pc + 3 + (signed)odv[1]) & ~3;
2314 litval = read_memory_integer (litaddr, 4, byte_order);
2315 dst[odv[0]].fr_reg = C0_CONST;
2316 dst[odv[0]].fr_ofs = litval;
2319 /* 3 operands: value, base, offset. */
2320 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2321 /* First, check if it's a spill for saved unaligned SP,
2322 when dynamic stack adjustment was applied to this frame. */
2323 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2324 && (odv[1] == spreg) /* SP usage indicates spill. */
2325 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2326 cache->c0.c0_sp_ofs = odv[2];
2328 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2329 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2330 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2331 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2332 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2334 /* ISA encoding guarantees alignment. But, check it anyway. */
2335 gdb_assert ((odv[2] & 3) == 0);
2336 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2339 /* If we end up inside Window Overflow / Underflow interrupt handler
2340 report an error because these handlers should have been handled
2341 already in a different way. */
2353 /* Analyze prologue of the function at start address to determine if it uses
2354 the Call0 ABI, and if so track register moves and linear modifications
2355 in the prologue up to the PC or just beyond the prologue, whichever is
2356 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2357 prologue. The prologue may overlap non-prologue instructions but is
2358 guaranteed to end by the first flow-control instruction (jump, branch,
2359 call or return). Since an optimized function may move information around
2360 and change the stack frame arbitrarily during the prologue, the information
2361 is guaranteed valid only at the point in the function indicated by the PC.
2362 May be used to skip the prologue or identify the ABI, w/o tracking.
2364 Returns: Address of first instruction after prologue, or PC (whichever
2365 is first), or 0, if decoding failed (in libisa).
2367 start Start address of function/prologue.
2368 pc Program counter to stop at. Use 0 to continue to end of prologue.
2369 If 0, avoids infinite run-on in corrupt code memory by bounding
2370 the scan to the end of the function if that can be determined.
2371 nregs Number of general registers to track.
2373 cache Xtensa frame cache.
2375 Note that these may produce useful results even if decoding fails
2376 because they begin with default assumptions that analysis may change. */
2379 call0_analyze_prologue (struct gdbarch *gdbarch,
2380 CORE_ADDR start, CORE_ADDR pc,
2381 int nregs, xtensa_frame_cache_t *cache)
2383 CORE_ADDR ia; /* Current insn address in prologue. */
2384 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2385 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2386 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2387 xtensa_isa isa; /* libisa ISA handle. */
2388 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2389 xtensa_format ifmt; /* libisa instruction format. */
2390 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2391 xtensa_opcode opc; /* Opcode in current slot. */
2392 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2393 int nods; /* Opcode number of operands. */
2394 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2395 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2396 int j; /* General loop counter. */
2397 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2398 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2399 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2401 struct symtab_and_line prologue_sal;
2403 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2404 (int)start, (int)pc);
2406 /* Try to limit the scan to the end of the function if a non-zero pc
2407 arg was not supplied to avoid probing beyond the end of valid memory.
2408 If memory is full of garbage that classifies as c0opc_uninteresting.
2409 If this fails (eg. if no symbols) pc ends up 0 as it was.
2410 Intialize the Call0 frame and register tracking info.
2411 Assume it's Call0 until an 'entry' instruction is encountered.
2412 Assume we may be in the prologue until we hit a flow control instr. */
2418 /* Find out, if we have an information about the prologue from DWARF. */
2419 prologue_sal = find_pc_line (start, 0);
2420 if (prologue_sal.line != 0) /* Found debug info. */
2421 body_pc = prologue_sal.end;
2423 /* If we are going to analyze the prologue in general without knowing about
2424 the current PC, make the best assumtion for the end of the prologue. */
2427 find_pc_partial_function (start, 0, NULL, &end_pc);
2428 body_pc = min (end_pc, body_pc);
2431 body_pc = min (pc, body_pc);
2434 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2436 if (!xtensa_default_isa)
2437 xtensa_default_isa = xtensa_isa_init (0, 0);
2438 isa = xtensa_default_isa;
2439 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2440 ins = xtensa_insnbuf_alloc (isa);
2441 slot = xtensa_insnbuf_alloc (isa);
2443 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2445 /* (Re)fill instruction buffer from memory if necessary, but do not
2446 read memory beyond PC to be sure we stay within text section
2447 (this protection only works if a non-zero pc is supplied). */
2449 if (ia + xtensa_isa_maxlength (isa) > bt)
2452 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2453 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2454 error (_("Unable to read target memory ..."));
2457 /* Decode format information. */
2459 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2460 ifmt = xtensa_format_decode (isa, ins);
2461 if (ifmt == XTENSA_UNDEFINED)
2466 ilen = xtensa_format_length (isa, ifmt);
2467 if (ilen == XTENSA_UNDEFINED)
2472 islots = xtensa_format_num_slots (isa, ifmt);
2473 if (islots == XTENSA_UNDEFINED)
2479 /* Analyze a bundle or a single instruction, using a snapshot of
2480 the register tracking info as input for the entire bundle so that
2481 register changes do not take effect within this bundle. */
2483 for (j = 0; j < nregs; ++j)
2484 rtmp[j] = cache->c0.c0_rt[j];
2486 for (is = 0; is < islots; ++is)
2488 /* Decode a slot and classify the opcode. */
2490 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2494 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2495 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2497 if (opc == XTENSA_UNDEFINED)
2498 opclass = c0opc_illegal;
2500 opclass = call0_classify_opcode (isa, opc);
2502 /* Decide whether to track this opcode, ignore it, or bail out. */
2511 case c0opc_uninteresting:
2514 case c0opc_flow: /* Flow control instructions stop analysis. */
2515 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2520 ia += ilen; /* Skip over 'entry' insn. */
2527 /* Only expected opcodes should get this far. */
2529 /* Extract and decode the operands. */
2530 nods = xtensa_opcode_num_operands (isa, opc);
2531 if (nods == XTENSA_UNDEFINED)
2537 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2539 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2544 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2549 /* Check operands to verify use of 'mov' assembler macro. */
2550 if (opclass == c0opc_mov && nods == 3)
2552 if (odv[2] == odv[1])
2555 if ((odv[0] == 1) && (odv[1] != 1))
2556 /* OR A1, An, An , where n != 1.
2557 This means we are inside epilogue already. */
2562 opclass = c0opc_uninteresting;
2567 /* Track register movement and modification for this operation. */
2568 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2569 opclass, nods, odv, ia, 1, cache);
2575 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2576 (unsigned)ia, fail ? "failed" : "succeeded");
2577 xtensa_insnbuf_free(isa, slot);
2578 xtensa_insnbuf_free(isa, ins);
2579 return fail ? XTENSA_ISA_BADPC : ia;
2582 /* Initialize frame cache for the current frame in CALL0 ABI. */
2585 call0_frame_cache (struct frame_info *this_frame,
2586 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2588 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2589 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2590 CORE_ADDR start_pc; /* The beginning of the function. */
2591 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2592 CORE_ADDR sp, fp, ra;
2593 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2595 sp = get_frame_register_unsigned
2596 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2597 fp = sp; /* Assume FP == SP until proven otherwise. */
2599 /* Find the beginning of the prologue of the function containing the PC
2600 and analyze it up to the PC or the end of the prologue. */
2602 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2604 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2606 if (body_pc == XTENSA_ISA_BADPC)
2610 goto finish_frame_analysis;
2614 /* Get the frame information and FP (if used) at the current PC.
2615 If PC is in the prologue, the prologue analysis is more reliable
2616 than DWARF info. We don't not know for sure, if PC is in the prologue,
2617 but we do know no calls have yet taken place, so we can almost
2618 certainly rely on the prologue analysis. */
2622 /* Prologue analysis was successful up to the PC.
2623 It includes the cases when PC == START_PC. */
2624 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2625 /* c0_hasfp == true means there is a frame pointer because
2626 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2627 was derived from SP. Otherwise, it would be C0_FP. */
2628 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2629 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2630 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2632 else /* No data from the prologue analysis. */
2635 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2640 if (cache->c0.c0_fpalign)
2642 /* This frame has a special prologue with a dynamic stack adjustment
2643 to force an alignment, which is bigger than standard 16 bytes. */
2645 CORE_ADDR unaligned_sp;
2647 if (cache->c0.c0_old_sp == C0_INEXP)
2648 /* This can't be. Prologue code should be consistent.
2649 Unaligned stack pointer should be saved in a spare register. */
2653 goto finish_frame_analysis;
2656 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2657 /* Saved unaligned value of SP is kept in a register. */
2658 unaligned_sp = get_frame_register_unsigned
2659 (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
2661 /* Get the value from stack. */
2662 unaligned_sp = (CORE_ADDR)
2663 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2665 prev_sp = unaligned_sp + c0_frmsz;
2668 prev_sp = fp + c0_frmsz;
2670 /* Frame size from debug info or prologue tracking does not account for
2671 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2674 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2676 /* Update the stack frame size. */
2677 c0_frmsz += fp - sp;
2680 /* Get the return address (RA) from the stack if saved,
2681 or try to get it from a register. */
2683 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2684 if (to_stk != C0_NOSTK)
2686 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2689 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2690 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2692 /* Special case for terminating backtrace at a function that wants to
2693 be seen as the outermost one. Such a function will clear it's RA (A0)
2694 register to 0 in the prologue instead of saving its original value. */
2699 /* RA was copied to another register or (before any function call) may
2700 still be in the original RA register. This is not always reliable:
2701 even in a leaf function, register tracking stops after prologue, and
2702 even in prologue, non-prologue instructions (not tracked) may overwrite
2703 RA or any register it was copied to. If likely in prologue or before
2704 any call, use retracking info and hope for the best (compiler should
2705 have saved RA in stack if not in a leaf function). If not in prologue,
2711 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2713 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2717 ra = get_frame_register_unsigned
2719 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2724 finish_frame_analysis:
2725 cache->pc = start_pc;
2727 /* RA == 0 marks the outermost frame. Do not go past it. */
2728 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2729 cache->c0.fp_regnum = fp_regnum;
2730 cache->c0.c0_frmsz = c0_frmsz;
2731 cache->c0.c0_hasfp = c0_hasfp;
2732 cache->c0.c0_fp = fp;
2735 static CORE_ADDR a0_saved;
2736 static CORE_ADDR a7_saved;
2737 static CORE_ADDR a11_saved;
2738 static int a0_was_saved;
2739 static int a7_was_saved;
2740 static int a11_was_saved;
2742 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2744 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2746 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2747 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2748 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2749 unsigned int spilled_value
2750 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2752 if ((at == 0) && !a0_was_saved)
2754 a0_saved = xtensa_read_register (atreg);
2757 else if ((at == 7) && !a7_was_saved)
2759 a7_saved = xtensa_read_register (atreg);
2762 else if ((at == 11) && !a11_was_saved)
2764 a11_saved = xtensa_read_register (atreg);
2768 xtensa_write_register (atreg, spilled_value);
2771 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2773 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2775 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2776 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2777 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2778 ULONGEST spilled_value = xtensa_read_register (atreg);
2780 write_memory_unsigned_integer (addr, 4,
2781 gdbarch_byte_order (gdbarch),
2785 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2791 xtNoExceptionHandler
2792 } xtensa_exception_handler_t;
2794 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2795 Return type of Xtensa Window Interrupt Handler on success. */
2796 static xtensa_exception_handler_t
2797 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2800 xtensa_insnbuf ins, slot;
2801 char ibuf[XTENSA_ISA_BSZ];
2802 CORE_ADDR ia, bt, ba;
2804 int ilen, islots, is;
2808 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2813 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2814 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2816 isa = xtensa_default_isa;
2817 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2818 ins = xtensa_insnbuf_alloc (isa);
2819 slot = xtensa_insnbuf_alloc (isa);
2828 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2830 if (ia + xtensa_isa_maxlength (isa) > bt)
2833 bt = (ba + XTENSA_ISA_BSZ);
2834 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2835 return xtNoExceptionHandler;
2837 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2838 ifmt = xtensa_format_decode (isa, ins);
2839 if (ifmt == XTENSA_UNDEFINED)
2840 return xtNoExceptionHandler;
2841 ilen = xtensa_format_length (isa, ifmt);
2842 if (ilen == XTENSA_UNDEFINED)
2843 return xtNoExceptionHandler;
2844 islots = xtensa_format_num_slots (isa, ifmt);
2845 if (islots == XTENSA_UNDEFINED)
2846 return xtNoExceptionHandler;
2847 for (is = 0; is < islots; ++is)
2849 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2850 return xtNoExceptionHandler;
2851 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2852 if (opc == XTENSA_UNDEFINED)
2853 return xtNoExceptionHandler;
2854 switch (call0_classify_opcode (isa, opc))
2860 /* We expect none of them here. */
2861 return xtNoExceptionHandler;
2863 func = execute_l32e;
2866 func = execute_s32e;
2868 case c0opc_rfwo: /* RFWO. */
2869 /* Here, we return from WindowOverflow handler and,
2870 if we stopped at the very beginning, which means
2871 A0 was saved, we have to restore it now. */
2874 int arreg = arreg_number (gdbarch,
2875 gdbarch_tdep (gdbarch)->a0_base,
2877 xtensa_write_register (arreg, a0_saved);
2879 return xtWindowOverflow;
2880 case c0opc_rfwu: /* RFWU. */
2881 /* Here, we return from WindowUnderflow handler.
2882 Let's see if either A7 or A11 has to be restored. */
2883 if (WindowUnderflow12)
2887 int arreg = arreg_number (gdbarch,
2888 gdbarch_tdep (gdbarch)->a0_base + 11,
2890 xtensa_write_register (arreg, a11_saved);
2893 else if (a7_was_saved)
2895 int arreg = arreg_number (gdbarch,
2896 gdbarch_tdep (gdbarch)->a0_base + 7,
2898 xtensa_write_register (arreg, a7_saved);
2900 return xtWindowUnderflow;
2901 default: /* Simply skip this insns. */
2905 /* Decode arguments for L32E / S32E and simulate their execution. */
2906 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2907 return xtNoExceptionHandler;
2908 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2909 return xtNoExceptionHandler;
2910 if (xtensa_operand_decode (isa, opc, 0, &at))
2911 return xtNoExceptionHandler;
2912 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2913 return xtNoExceptionHandler;
2914 if (xtensa_operand_decode (isa, opc, 1, &as))
2915 return xtNoExceptionHandler;
2916 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2917 return xtNoExceptionHandler;
2918 if (xtensa_operand_decode (isa, opc, 2, &offset))
2919 return xtNoExceptionHandler;
2921 (*func) (gdbarch, at, as, offset, wb);
2926 return xtNoExceptionHandler;
2929 /* Handle Window Overflow / Underflow exception frames. */
2932 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2933 xtensa_frame_cache_t *cache,
2936 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2937 CORE_ADDR ps, wb, ws, ra;
2938 int epc1_regnum, i, regnum;
2939 xtensa_exception_handler_t eh_type;
2941 /* Read PS, WB, and WS from the hardware. Note that PS register
2942 must be present, if Windowed ABI is supported. */
2943 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2944 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2945 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2947 /* Execute all the remaining instructions from Window Interrupt Handler
2948 by simulating them on the remote protocol level. On return, set the
2949 type of Xtensa Window Interrupt Handler, or report an error. */
2950 eh_type = execute_code (gdbarch, pc, wb);
2951 if (eh_type == xtNoExceptionHandler)
2953 Unable to decode Xtensa Window Interrupt Handler's code."));
2955 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2956 cache->call0 = 0; /* It's Windowed ABI. */
2958 /* All registers for the cached frame will be alive. */
2959 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2960 cache->wd.aregs[i] = -1;
2962 if (eh_type == xtWindowOverflow)
2963 cache->wd.ws = ws ^ (1 << wb);
2964 else /* eh_type == xtWindowUnderflow. */
2965 cache->wd.ws = ws | (1 << wb);
2967 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2968 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2970 ra = xtensa_read_register (regnum);
2971 cache->wd.callsize = WINSIZE (ra);
2972 cache->prev_sp = xtensa_read_register (regnum + 1);
2973 /* Set regnum to a frame pointer of the frame being cached. */
2974 regnum = xtensa_scan_prologue (gdbarch, pc);
2975 regnum = arreg_number (gdbarch,
2976 gdbarch_tdep (gdbarch)->a0_base + regnum,
2978 cache->base = get_frame_register_unsigned (this_frame, regnum);
2980 /* Read PC of interrupted function from EPC1 register. */
2981 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2982 if (epc1_regnum < 0)
2983 error(_("Unable to read Xtensa register EPC1"));
2984 cache->ra = xtensa_read_register (epc1_regnum);
2985 cache->pc = get_frame_func (this_frame);
2989 /* Skip function prologue.
2991 Return the pc of the first instruction after prologue. GDB calls this to
2992 find the address of the first line of the function or (if there is no line
2993 number information) to skip the prologue for planting breakpoints on
2994 function entries. Use debug info (if present) or prologue analysis to skip
2995 the prologue to achieve reliable debugging behavior. For windowed ABI,
2996 only the 'entry' instruction is skipped. It is not strictly necessary to
2997 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2998 backtrace at any point in the prologue, however certain potential hazards
2999 are avoided and a more "normal" debugging experience is ensured by
3000 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
3001 For example, if we don't skip the prologue:
3002 - Some args may not yet have been saved to the stack where the debug
3003 info expects to find them (true anyway when only 'entry' is skipped);
3004 - Software breakpoints ('break' instrs) may not have been unplanted
3005 when the prologue analysis is done on initializing the frame cache,
3006 and breaks in the prologue will throw off the analysis.
3008 If we have debug info ( line-number info, in particular ) we simply skip
3009 the code associated with the first function line effectively skipping
3010 the prologue code. It works even in cases like
3013 { int local_var = 1;
3017 because, for this source code, both Xtensa compilers will generate two
3018 separate entries ( with the same line number ) in dwarf line-number
3019 section to make sure there is a boundary between the prologue code and
3020 the rest of the function.
3022 If there is no debug info, we need to analyze the code. */
3024 /* #define DONT_SKIP_PROLOGUE */
3027 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
3029 struct symtab_and_line prologue_sal;
3032 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3034 #if DONT_SKIP_PROLOGUE
3038 /* Try to find first body line from debug info. */
3040 prologue_sal = find_pc_line (start_pc, 0);
3041 if (prologue_sal.line != 0) /* Found debug info. */
3043 /* In Call0, it is possible to have a function with only one instruction
3044 ('ret') resulting from a one-line optimized function that does nothing.
3045 In that case, prologue_sal.end may actually point to the start of the
3046 next function in the text section, causing a breakpoint to be set at
3047 the wrong place. Check, if the end address is within a different
3048 function, and if so return the start PC. We know we have symbol
3053 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
3054 && call0_ret (start_pc, prologue_sal.end))
3057 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3058 if (end_func != start_pc)
3061 return prologue_sal.end;
3064 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3065 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3066 xtensa_alloc_frame_cache (0));
3067 return body_pc != 0 ? body_pc : start_pc;
3070 /* Verify the current configuration. */
3072 xtensa_verify_config (struct gdbarch *gdbarch)
3074 struct ui_file *log;
3075 struct cleanup *cleanups;
3076 struct gdbarch_tdep *tdep;
3080 tdep = gdbarch_tdep (gdbarch);
3081 log = mem_fileopen ();
3082 cleanups = make_cleanup_ui_file_delete (log);
3084 /* Verify that we got a reasonable number of AREGS. */
3085 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3086 fprintf_unfiltered (log, _("\
3087 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3090 /* Verify that certain registers exist. */
3092 if (tdep->pc_regnum == -1)
3093 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
3094 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3095 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
3097 if (tdep->isa_use_windowed_registers)
3099 if (tdep->wb_regnum == -1)
3100 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
3101 if (tdep->ws_regnum == -1)
3102 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
3103 if (tdep->ar_base == -1)
3104 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
3107 if (tdep->a0_base == -1)
3108 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
3110 buf = ui_file_xstrdup (log, &length);
3111 make_cleanup (xfree, buf);
3113 internal_error (__FILE__, __LINE__,
3114 _("the following are invalid: %s"), buf);
3115 do_cleanups (cleanups);
3119 /* Derive specific register numbers from the array of registers. */
3122 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
3124 xtensa_register_t* rmap;
3125 int n, max_size = 4;
3128 tdep->num_nopriv_regs = 0;
3130 /* Special registers 0..255 (core). */
3131 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3133 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3135 if (rmap->target_number == 0x0020)
3136 tdep->pc_regnum = n;
3137 else if (rmap->target_number == 0x0100)
3139 else if (rmap->target_number == 0x0000)
3141 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3142 tdep->wb_regnum = n;
3143 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3144 tdep->ws_regnum = n;
3145 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3146 tdep->debugcause_regnum = n;
3147 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3148 tdep->exccause_regnum = n;
3149 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3150 tdep->excvaddr_regnum = n;
3151 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3152 tdep->lbeg_regnum = n;
3153 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3154 tdep->lend_regnum = n;
3155 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3156 tdep->lcount_regnum = n;
3157 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3158 tdep->sar_regnum = n;
3159 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3160 tdep->litbase_regnum = n;
3161 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3162 tdep->ps_regnum = n;
3164 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3165 tdep->interrupt_regnum = n;
3166 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3167 tdep->interrupt2_regnum = n;
3168 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3169 tdep->cpenable_regnum = n;
3172 if (rmap->byte_size > max_size)
3173 max_size = rmap->byte_size;
3174 if (rmap->mask != 0 && tdep->num_regs == 0)
3176 /* Find out out how to deal with priveleged registers.
3178 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3179 && tdep->num_nopriv_regs == 0)
3180 tdep->num_nopriv_regs = n;
3182 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3183 && tdep->num_regs == 0)
3187 /* Number of pseudo registers. */
3188 tdep->num_pseudo_regs = n - tdep->num_regs;
3190 /* Empirically determined maximum sizes. */
3191 tdep->max_register_raw_size = max_size;
3192 tdep->max_register_virtual_size = max_size;
3195 /* Module "constructor" function. */
3197 extern struct gdbarch_tdep xtensa_tdep;
3199 static struct gdbarch *
3200 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3202 struct gdbarch_tdep *tdep;
3203 struct gdbarch *gdbarch;
3204 struct xtensa_abi_handler *abi_handler;
3206 DEBUGTRACE ("gdbarch_init()\n");
3208 /* We have to set the byte order before we call gdbarch_alloc. */
3209 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3211 tdep = &xtensa_tdep;
3212 gdbarch = gdbarch_alloc (&info, tdep);
3213 xtensa_derive_tdep (tdep);
3215 /* Verify our configuration. */
3216 xtensa_verify_config (gdbarch);
3217 xtensa_session_once_reported = 0;
3219 /* Pseudo-Register read/write. */
3220 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3221 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3223 /* Set target information. */
3224 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3225 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3226 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3227 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3228 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3230 /* Renumber registers for known formats (stabs and dwarf2). */
3231 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3232 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3234 /* We provide our own function to get register information. */
3235 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3236 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3238 /* To call functions from GDB using dummy frame. */
3239 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3241 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3243 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3245 /* Advance PC across any prologue instructions to reach "real" code. */
3246 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3248 /* Stack grows downward. */
3249 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3251 /* Set breakpoints. */
3252 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
3254 /* After breakpoint instruction or illegal instruction, pc still
3255 points at break instruction, so don't decrement. */
3256 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3258 /* We don't skip args. */
3259 set_gdbarch_frame_args_skip (gdbarch, 0);
3261 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3263 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3265 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3267 /* Frame handling. */
3268 frame_base_set_default (gdbarch, &xtensa_frame_base);
3269 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3270 dwarf2_append_unwinders (gdbarch);
3272 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3274 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3276 xtensa_add_reggroups (gdbarch);
3277 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3279 set_gdbarch_regset_from_core_section (gdbarch,
3280 xtensa_regset_from_core_section);
3282 set_solib_svr4_fetch_link_map_offsets
3283 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3289 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3291 error (_("xtensa_dump_tdep(): not implemented"));
3294 /* Provide a prototype to silence -Wmissing-prototypes. */
3295 extern initialize_file_ftype _initialize_xtensa_tdep;
3298 _initialize_xtensa_tdep (void)
3300 struct cmd_list_element *c;
3302 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3303 xtensa_init_reggroups ();
3305 add_setshow_zinteger_cmd ("xtensa",
3307 &xtensa_debug_level,
3308 _("Set Xtensa debugging."),
3309 _("Show Xtensa debugging."), _("\
3310 When non-zero, Xtensa-specific debugging is enabled. \
3311 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3314 &setdebuglist, &showdebuglist);