1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "floatformat.h"
32 #include "reggroups.h"
35 #include "dummy-frame.h"
36 #include "elf/dwarf2.h"
37 #include "dwarf2-frame.h"
38 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
50 #include "gdb_assert.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
56 static int xtensa_debug_level = 0;
58 #define DEBUGWARN(args...) \
59 if (xtensa_debug_level > 0) \
60 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
62 #define DEBUGINFO(args...) \
63 if (xtensa_debug_level > 1) \
64 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
66 #define DEBUGTRACE(args...) \
67 if (xtensa_debug_level > 2) \
68 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
70 #define DEBUGVERB(args...) \
71 if (xtensa_debug_level > 3) \
72 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
75 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
76 #define SP_ALIGNMENT 16
79 /* On Windowed ABI, we use a6 through a11 for passing arguments
80 to a function called by GDB because CALL4 is used. */
81 #define ARGS_FIRST_REG gdbarch_tdep (current_gdbarch)->a0_base + 6
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
93 /* Convert a live Ax register number to the corresponding Areg number. */
94 #define AREG_NUMBER(r, wb) \
95 ((((r) - (gdbarch_tdep (current_gdbarch)->a0_base + 0) + (((wb) \
96 & ((gdbarch_tdep (current_gdbarch)->num_aregs - 1) >> 2)) << WB_SHIFT)) & \
97 (gdbarch_tdep (current_gdbarch)->num_aregs - 1)) \
98 + gdbarch_tdep (current_gdbarch)->ar_base)
100 /* ABI-independent macros. */
101 #define ARG_NOF (gdbarch_tdep (current_gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST (gdbarch_tdep (current_gdbarch)->call_abi \
104 == CallAbiCall0Only \
105 ? (gdbarch_tdep (current_gdbarch)->a0_base + 0) + C0_ARGS \
108 extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *);
109 extern int xtensa_config_byte_order (struct gdbarch_info *);
112 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
113 indicates that the instruction is an ENTRY instruction. */
115 #define XTENSA_IS_ENTRY(op1) \
116 ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \
117 ? ((op1) == 0x6c) : ((op1) == 0x36))
119 #define XTENSA_ENTRY_LENGTH 3
121 /* windowing_enabled() returns true, if windowing is enabled.
122 WOE must be set to 1; EXCM to 0.
123 Note: We assume that EXCM is always 0 for XEA1. */
125 #define PS_WOE (1<<18)
126 #define PS_EXC (1<<4)
129 windowing_enabled (CORE_ADDR ps)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Return the window size of the previous call to the function from which we
137 This function is used to extract the return value after a called function
138 has returned to the caller. On Xtensa, the register that holds the return
139 value (from the perspective of the caller) depends on what call
140 instruction was used. For now, we are assuming that the call instruction
141 precedes the current address, so we simply analyze the call instruction.
142 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
143 method to call the inferior function. */
146 extract_call_winsize (CORE_ADDR pc)
152 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
154 /* Read the previous instruction (should be a call[x]{4|8|12}. */
155 read_memory (pc-3, buf, 3);
156 insn = extract_unsigned_integer (buf, 3);
158 /* Decode call instruction:
160 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
161 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
163 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
164 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
166 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
168 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
169 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
173 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
174 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
180 /* REGISTER INFORMATION */
182 /* Returns the name of a register. */
184 xtensa_register_name (int regnum)
186 /* Return the name stored in the register map. */
187 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
188 + gdbarch_num_pseudo_regs (current_gdbarch))
189 return gdbarch_tdep (current_gdbarch)->regmap[regnum].name;
191 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
196 xtensa_read_register (int regnum)
200 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
201 return (unsigned long) value;
204 /* Return the type of a register. Create a new type, if necessary. */
206 static struct ctype_cache
208 struct ctype_cache *next;
210 struct type *virtual_type;
211 } *type_entries = NULL;
214 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
216 /* Return signed integer for ARx and Ax registers. */
217 if ((regnum >= gdbarch_tdep (current_gdbarch)->ar_base
218 && regnum < gdbarch_tdep (current_gdbarch)->ar_base
219 + gdbarch_tdep (current_gdbarch)->num_aregs)
220 || (regnum >= gdbarch_tdep (current_gdbarch)->a0_base
221 && regnum < gdbarch_tdep (current_gdbarch)->a0_base + 16))
222 return builtin_type_int;
224 if (regnum == gdbarch_pc_regnum (current_gdbarch)
225 || regnum == gdbarch_tdep (current_gdbarch)->a0_base + 1)
226 return lookup_pointer_type (builtin_type_void);
228 /* Return the stored type for all other registers. */
229 else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
230 + gdbarch_num_pseudo_regs (current_gdbarch))
232 xtensa_register_t* reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
234 /* Set ctype for this register (only the first time). */
238 struct ctype_cache *tp;
239 int size = reg->byte_size;
241 /* We always use the memory representation,
242 even if the register width is smaller. */
246 reg->ctype = builtin_type_uint8;
250 reg->ctype = builtin_type_uint16;
254 reg->ctype = builtin_type_uint32;
258 reg->ctype = builtin_type_uint64;
262 reg->ctype = builtin_type_uint128;
266 for (tp = type_entries; tp != NULL; tp = tp->next)
267 if (tp->size == size)
272 char *name = xmalloc (16);
273 tp = xmalloc (sizeof (struct ctype_cache));
274 tp->next = type_entries;
278 sprintf (name, "int%d", size * 8);
279 tp->virtual_type = init_type (TYPE_CODE_INT, size,
280 TYPE_FLAG_UNSIGNED, name,
284 reg->ctype = tp->virtual_type;
290 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
295 /* Return the 'local' register number for stubs, dwarf2, etc.
296 The debugging information enumerates registers starting from 0 for A0
297 to n for An. So, we only have to add the base number for A0. */
300 xtensa_reg_to_regnum (int regnum)
304 if (regnum >= 0 && regnum < 16)
305 return gdbarch_tdep (current_gdbarch)->a0_base + regnum;
308 i < gdbarch_num_regs (current_gdbarch)
309 + gdbarch_num_pseudo_regs (current_gdbarch);
311 if (regnum == gdbarch_tdep (current_gdbarch)->regmap[i].target_number)
314 internal_error (__FILE__, __LINE__,
315 _("invalid dwarf/stabs register number %d"), regnum);
320 /* Write the bits of a masked register to the various registers.
321 Only the masked areas of these registers are modified; the other
322 fields are untouched. The size of masked registers is always less
323 than or equal to 32 bits. */
326 xtensa_register_write_masked (struct regcache *regcache,
327 xtensa_register_t *reg, const gdb_byte *buffer)
329 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
330 const xtensa_mask_t *mask = reg->mask;
332 int shift = 0; /* Shift for next mask (mod 32). */
333 int start, size; /* Start bit and size of current mask. */
335 unsigned int *ptr = value;
336 unsigned int regval, m, mem = 0;
338 int bytesize = reg->byte_size;
339 int bitsize = bytesize * 8;
342 DEBUGTRACE ("xtensa_register_write_masked ()\n");
344 /* Copy the masked register to host byte-order. */
345 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
346 for (i = 0; i < bytesize; i++)
349 mem |= (buffer[bytesize - i - 1] << 24);
354 for (i = 0; i < bytesize; i++)
357 mem |= (buffer[i] << 24);
362 /* We might have to shift the final value:
363 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
364 bytesize & 3 == x -> shift (4-x) * 8. */
366 *ptr = mem >> (((0 - bytesize) & 3) * 8);
370 /* Write the bits to the masked areas of the other registers. */
371 for (i = 0; i < mask->count; i++)
373 start = mask->mask[i].bit_start;
374 size = mask->mask[i].bit_size;
375 regval = mem >> shift;
377 if ((shift += size) > bitsize)
378 error (_("size of all masks is larger than the register"));
387 regval |= mem << (size - shift);
390 /* Make sure we have a valid register. */
391 r = mask->mask[i].reg_num;
392 if (r >= 0 && size > 0)
394 /* Don't overwrite the unmasked areas. */
396 regcache_cooked_read_unsigned (regcache, r, &old_val);
397 m = 0xffffffff >> (32 - size) << start;
399 regval = (regval & m) | (old_val & ~m);
400 regcache_cooked_write_unsigned (regcache, r, regval);
406 /* Read a tie state or mapped registers. Read the masked areas
407 of the registers and assemble them into a single value. */
410 xtensa_register_read_masked (struct regcache *regcache,
411 xtensa_register_t *reg, gdb_byte *buffer)
413 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
414 const xtensa_mask_t *mask = reg->mask;
419 unsigned int *ptr = value;
420 unsigned int regval, mem = 0;
422 int bytesize = reg->byte_size;
423 int bitsize = bytesize * 8;
426 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
427 reg->name == 0 ? "" : reg->name);
429 /* Assemble the register from the masked areas of other registers. */
430 for (i = 0; i < mask->count; i++)
432 int r = mask->mask[i].reg_num;
436 regcache_cooked_read_unsigned (regcache, r, &val);
437 regval = (unsigned int) val;
442 start = mask->mask[i].bit_start;
443 size = mask->mask[i].bit_size;
448 regval &= (0xffffffff >> (32 - size));
450 mem |= regval << shift;
452 if ((shift += size) > bitsize)
453 error (_("size of all masks is larger than the register"));
464 mem = regval >> (size - shift);
471 /* Copy value to target byte order. */
475 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
476 for (i = 0; i < bytesize; i++)
480 buffer[bytesize - i - 1] = mem & 0xff;
484 for (i = 0; i < bytesize; i++)
488 buffer[i] = mem & 0xff;
494 /* Read pseudo registers. */
497 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
498 struct regcache *regcache,
502 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
503 regnum, xtensa_register_name (regnum));
505 if (regnum == gdbarch_num_regs (current_gdbarch)
506 + gdbarch_num_pseudo_regs (current_gdbarch))
507 regnum = gdbarch_tdep (current_gdbarch)->a0_base + 1;
509 /* Read aliases a0..a15, if this is a Windowed ABI. */
510 if (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers
511 && (regnum >= gdbarch_tdep (current_gdbarch)->a0_base + 0)
512 && (regnum <= gdbarch_tdep (current_gdbarch)->a0_base + 15))
514 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
516 regcache_raw_read (regcache,
517 gdbarch_tdep (current_gdbarch)->wb_regnum, buf);
518 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
521 /* We can always read non-pseudo registers. */
522 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
523 regcache_raw_read (regcache, regnum, buffer);
525 /* Pseudo registers. */
527 && regnum < gdbarch_num_regs (current_gdbarch)
528 + gdbarch_num_pseudo_regs (current_gdbarch))
530 xtensa_register_t *reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
531 xtensa_register_type_t type = reg->type;
532 int flags = gdbarch_tdep (current_gdbarch)->target_flags;
534 /* We cannot read Unknown or Unmapped registers. */
535 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
537 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
539 warning (_("cannot read register %s"),
540 xtensa_register_name (regnum));
545 /* Some targets cannot read TIE register files. */
546 else if (type == xtRegisterTypeTieRegfile)
548 /* Use 'fetch' to get register? */
549 if (flags & xtTargetFlagsUseFetchStore)
551 warning (_("cannot read register"));
555 /* On some targets (esp. simulators), we can always read the reg. */
556 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
558 warning (_("cannot read register"));
563 /* We can always read mapped registers. */
564 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
566 xtensa_register_read_masked (regcache, reg, buffer);
570 /* Assume that we can read the register. */
571 regcache_raw_read (regcache, regnum, buffer);
574 internal_error (__FILE__, __LINE__,
575 _("invalid register number %d"), regnum);
579 /* Write pseudo registers. */
582 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
583 struct regcache *regcache,
585 const gdb_byte *buffer)
587 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
588 regnum, xtensa_register_name (regnum));
590 if (regnum == gdbarch_num_regs (current_gdbarch)
591 + gdbarch_num_pseudo_regs (current_gdbarch))
592 regnum = gdbarch_tdep (current_gdbarch)->a0_base + 1;
594 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
595 if (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers
596 && (regnum >= gdbarch_tdep (current_gdbarch)->a0_base + 0)
597 && (regnum <= gdbarch_tdep (current_gdbarch)->a0_base + 15))
599 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
602 regcache_raw_read (regcache,
603 gdbarch_tdep (current_gdbarch)->wb_regnum, buf);
604 regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
607 /* We can always write 'core' registers.
608 Note: We might have converted Ax->ARy. */
609 if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
610 regcache_raw_write (regcache, regnum, buffer);
612 /* Pseudo registers. */
614 && regnum < gdbarch_num_regs (current_gdbarch)
615 + gdbarch_num_pseudo_regs (current_gdbarch))
617 xtensa_register_t *reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
618 xtensa_register_type_t type = reg->type;
619 int flags = gdbarch_tdep (current_gdbarch)->target_flags;
621 /* On most targets, we cannot write registers
622 of type "Unknown" or "Unmapped". */
623 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
625 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
627 warning (_("cannot write register %s"),
628 xtensa_register_name (regnum));
633 /* Some targets cannot read TIE register files. */
634 else if (type == xtRegisterTypeTieRegfile)
636 /* Use 'store' to get register? */
637 if (flags & xtTargetFlagsUseFetchStore)
639 warning (_("cannot write register"));
643 /* On some targets (esp. simulators), we can always write
645 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
647 warning (_("cannot write register"));
652 /* We can always write mapped registers. */
653 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
655 xtensa_register_write_masked (regcache, reg, buffer);
659 /* Assume that we can write the register. */
660 regcache_raw_write (regcache, regnum, buffer);
663 internal_error (__FILE__, __LINE__,
664 _("invalid register number %d"), regnum);
667 static struct reggroup *xtensa_ar_reggroup;
668 static struct reggroup *xtensa_user_reggroup;
669 static struct reggroup *xtensa_vectra_reggroup;
670 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
673 xtensa_init_reggroups (void)
675 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
676 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
677 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
679 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
680 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
681 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
682 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
683 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
684 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
685 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
686 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
690 xtensa_add_reggroups (struct gdbarch *gdbarch)
694 /* Predefined groups. */
695 reggroup_add (gdbarch, all_reggroup);
696 reggroup_add (gdbarch, save_reggroup);
697 reggroup_add (gdbarch, restore_reggroup);
698 reggroup_add (gdbarch, system_reggroup);
699 reggroup_add (gdbarch, vector_reggroup);
700 reggroup_add (gdbarch, general_reggroup);
701 reggroup_add (gdbarch, float_reggroup);
703 /* Xtensa-specific groups. */
704 reggroup_add (gdbarch, xtensa_ar_reggroup);
705 reggroup_add (gdbarch, xtensa_user_reggroup);
706 reggroup_add (gdbarch, xtensa_vectra_reggroup);
708 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
709 reggroup_add (gdbarch, xtensa_cp[i]);
713 xtensa_coprocessor_register_group (struct reggroup *group)
717 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
718 if (group == xtensa_cp[i])
724 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
725 | XTENSA_REGISTER_FLAGS_WRITABLE \
726 | XTENSA_REGISTER_FLAGS_VOLATILE)
728 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
729 | XTENSA_REGISTER_FLAGS_WRITABLE)
732 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
734 struct reggroup *group)
736 xtensa_register_t* reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
737 xtensa_register_type_t type = reg->type;
738 xtensa_register_group_t rg = reg->group;
741 /* First, skip registers that are not visible to this target
742 (unknown and unmapped registers when not using ISS). */
744 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
746 if (group == all_reggroup)
748 if (group == xtensa_ar_reggroup)
749 return rg & xtRegisterGroupAddrReg;
750 if (group == xtensa_user_reggroup)
751 return rg & xtRegisterGroupUser;
752 if (group == float_reggroup)
753 return rg & xtRegisterGroupFloat;
754 if (group == general_reggroup)
755 return rg & xtRegisterGroupGeneral;
756 if (group == float_reggroup)
757 return rg & xtRegisterGroupFloat;
758 if (group == system_reggroup)
759 return rg & xtRegisterGroupState;
760 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
761 return rg & xtRegisterGroupVectra;
762 if (group == save_reggroup || group == restore_reggroup)
763 return (regnum < gdbarch_num_regs (current_gdbarch)
764 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
765 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
766 return rg & (xtRegisterGroupCP0 << cp_number);
772 /* Supply register REGNUM from the buffer specified by GREGS and LEN
773 in the general-purpose register set REGSET to register cache
774 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
777 xtensa_supply_gregset (const struct regset *regset,
783 const xtensa_elf_gregset_t *regs = gregs;
786 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
788 if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == -1)
789 regcache_raw_supply (rc,
790 gdbarch_pc_regnum (current_gdbarch),
792 if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1)
793 regcache_raw_supply (rc, gdbarch_ps_regnum (current_gdbarch),
795 if (regnum == gdbarch_tdep (current_gdbarch)->wb_regnum || regnum == -1)
796 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->wb_regnum,
797 (char *) ®s->windowbase);
798 if (regnum == gdbarch_tdep (current_gdbarch)->ws_regnum || regnum == -1)
799 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->ws_regnum,
800 (char *) ®s->windowstart);
801 if (regnum == gdbarch_tdep (current_gdbarch)->lbeg_regnum || regnum == -1)
802 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->lbeg_regnum,
803 (char *) ®s->lbeg);
804 if (regnum == gdbarch_tdep (current_gdbarch)->lend_regnum || regnum == -1)
805 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->lend_regnum,
806 (char *) ®s->lend);
807 if (regnum == gdbarch_tdep (current_gdbarch)->lcount_regnum || regnum == -1)
808 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->lcount_regnum,
809 (char *) ®s->lcount);
810 if (regnum == gdbarch_tdep (current_gdbarch)->sar_regnum || regnum == -1)
811 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->sar_regnum,
812 (char *) ®s->sar);
813 if (regnum == gdbarch_tdep (current_gdbarch)->exccause_regnum
815 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->exccause_regnum,
816 (char *) ®s->exccause);
817 if (regnum == gdbarch_tdep (current_gdbarch)->excvaddr_regnum || regnum == -1)
818 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->excvaddr_regnum,
819 (char *) ®s->excvaddr);
820 if (regnum >=gdbarch_tdep (current_gdbarch)->ar_base
821 && regnum < gdbarch_tdep (current_gdbarch)->ar_base
822 + gdbarch_tdep (current_gdbarch)->num_aregs)
823 regcache_raw_supply (rc, regnum,
824 (char *) ®s->ar[regnum - gdbarch_tdep
825 (current_gdbarch)->ar_base]);
826 else if (regnum == -1)
828 for (i = 0; i < gdbarch_tdep (current_gdbarch)->num_aregs; ++i)
829 regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->ar_base + i,
830 (char *) ®s->ar[i]);
835 /* Xtensa register set. */
841 xtensa_supply_gregset
845 /* Return the appropriate register set for the core
846 section identified by SECT_NAME and SECT_SIZE. */
848 static const struct regset *
849 xtensa_regset_from_core_section (struct gdbarch *core_arch,
850 const char *sect_name,
853 DEBUGTRACE ("xtensa_regset_from_core_section "
854 "(..., sect_name==\"%s\", sect_size==%x) \n",
855 sect_name, sect_size);
857 if (strcmp (sect_name, ".reg") == 0
858 && sect_size >= sizeof(xtensa_elf_gregset_t))
859 return &xtensa_gregset;
865 /* Handling frames. */
867 /* Number of registers to save in case of Windowed ABI. */
868 #define XTENSA_NUM_SAVED_AREGS 12
870 /* Frame cache part for Windowed ABI. */
871 typedef struct xtensa_windowed_frame_cache
873 int wb; /* Base for this frame; -1 if not in regfile. */
874 int callsize; /* Call size to next frame. */
876 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
877 } xtensa_windowed_frame_cache_t;
879 /* Call0 ABI Definitions. */
881 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
882 #define C0_NREGS 16 /* Number of A-registers to track. */
883 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
884 #define C0_SP 1 /* Register used as SP. */
885 #define C0_FP 15 /* Register used as FP. */
886 #define C0_RA 0 /* Register used as return address. */
887 #define C0_ARGS 2 /* Register used as first arg/retval. */
888 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
890 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
891 A-register where the current content of the reg came from (in terms
892 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
893 mean that the orignal content of the register was saved to the stack.
894 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
895 know where SP will end up until the entire prologue has been analyzed. */
897 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
898 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
899 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
901 extern xtensa_isa xtensa_default_isa;
903 typedef struct xtensa_c0reg
905 int fr_reg; /* original register from which register content
906 is derived, or C0_CONST, or C0_INEXP. */
907 int fr_ofs; /* constant offset from reg, or immediate value. */
908 int to_stk; /* offset from original SP to register (4-byte aligned),
909 or C0_NOSTK if register has not been saved. */
913 /* Frame cache part for Call0 ABI. */
914 typedef struct xtensa_call0_frame_cache
916 int c0_frmsz; /* Stack frame size. */
917 int c0_hasfp; /* Current frame uses frame pointer. */
918 int fp_regnum; /* A-register used as FP. */
919 int c0_fp; /* Actual value of frame pointer. */
920 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
921 } xtensa_call0_frame_cache_t;
923 typedef struct xtensa_frame_cache
925 CORE_ADDR base; /* Stack pointer of the next frame. */
926 CORE_ADDR pc; /* PC at the entry point to the function. */
927 CORE_ADDR ra; /* The raw return address. */
928 CORE_ADDR ps; /* The PS register of the frame. */
929 CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
930 int call0; /* It's a call0 framework (else windowed). */
933 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
934 xtensa_call0_frame_cache_t c0; /* call0 == true. */
936 } xtensa_frame_cache_t;
939 static struct xtensa_frame_cache *
940 xtensa_alloc_frame_cache (int windowed)
942 xtensa_frame_cache_t *cache;
945 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
947 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
954 cache->call0 = !windowed;
957 cache->c0.c0_frmsz = -1;
958 cache->c0.c0_hasfp = 0;
959 cache->c0.fp_regnum = -1;
960 cache->c0.c0_fp = -1;
962 for (i = 0; i < C0_NREGS; i++)
964 cache->c0.c0_rt[i].fr_reg = i;
965 cache->c0.c0_rt[i].fr_ofs = 0;
966 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
972 cache->wd.callsize = -1;
974 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
975 cache->wd.aregs[i] = -1;
982 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
984 return address & ~15;
989 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
993 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
995 frame_unwind_register (next_frame, gdbarch_pc_regnum (current_gdbarch), buf);
997 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
998 extract_typed_address (buf, builtin_type_void_func_ptr));
1000 return extract_typed_address (buf, builtin_type_void_func_ptr);
1004 static struct frame_id
1005 xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1009 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
1011 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
1013 pc = frame_pc_unwind (next_frame);
1014 fp = frame_unwind_register_unsigned
1015 (next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1);
1017 /* Make dummy frame ID unique by adding a constant. */
1018 return frame_id_build (fp + SP_ALIGNMENT, pc);
1021 /* The key values to identify the frame using "cache" are
1023 cache->base = SP of this frame;
1024 cache->pc = entry-PC (entry point of the frame function);
1025 cache->prev_sp = SP of the previous frame.
1029 call0_frame_cache (struct frame_info *next_frame,
1030 xtensa_frame_cache_t *cache,
1033 static struct xtensa_frame_cache *
1034 xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
1036 xtensa_frame_cache_t *cache;
1037 CORE_ADDR ra, wb, ws, pc, sp, ps;
1038 unsigned int ps_regnum = gdbarch_ps_regnum (current_gdbarch);
1042 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
1043 next_frame, this_cache ? *this_cache : (void*)0xdeadbeef);
1048 windowed = windowing_enabled (xtensa_read_register (ps_regnum));
1050 /* Get pristine xtensa-frame. */
1051 cache = xtensa_alloc_frame_cache (windowed);
1052 *this_cache = cache;
1054 pc = frame_unwind_register_unsigned (next_frame,
1055 gdbarch_pc_regnum (current_gdbarch));
1059 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1060 wb = frame_unwind_register_unsigned
1061 (next_frame, gdbarch_tdep (current_gdbarch)->wb_regnum);
1062 ws = frame_unwind_register_unsigned
1063 (next_frame, gdbarch_tdep (current_gdbarch)->ws_regnum);
1064 ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
1066 op1 = read_memory_integer (pc, 1);
1067 if (XTENSA_IS_ENTRY (op1))
1069 int callinc = CALLINC (ps);
1070 ra = frame_unwind_register_unsigned
1072 gdbarch_tdep (current_gdbarch)->a0_base + 0 + callinc * 4);
1074 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
1077 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1078 cache->wd.callsize = 0;
1081 cache->prev_sp = frame_unwind_register_unsigned
1082 (next_frame, gdbarch_tdep
1083 (current_gdbarch)->a0_base + 1);
1087 ra = frame_unwind_register_unsigned
1088 (next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 0);
1089 cache->wd.callsize = WINSIZE (ra);
1090 cache->wd.wb = (wb - cache->wd.callsize / 4)
1091 & (gdbarch_tdep (current_gdbarch)->num_aregs / 4 - 1);
1092 cache->wd.ws = ws & ~(1 << wb);
1095 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
1096 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1097 cache->ps = (ps & ~PS_CALLINC_MASK)
1098 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1100 if (cache->wd.ws == 0)
1105 sp = frame_unwind_register_unsigned
1106 (next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1) - 16;
1108 for (i = 0; i < 4; i++, sp += 4)
1110 cache->wd.aregs[i] = sp;
1113 if (cache->wd.callsize > 4)
1115 /* Set A4...A7/A11. */
1116 /* Read an SP of the previous frame. */
1117 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1118 sp -= cache->wd.callsize * 4;
1120 for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
1122 cache->wd.aregs[i] = sp;
1127 if ((cache->prev_sp == 0) && ( ra != 0 ))
1128 /* If RA is equal to 0 this frame is an outermost frame. Leave
1129 cache->prev_sp unchanged marking the boundary of the frame stack. */
1131 if (cache->wd.ws == 0)
1133 /* Register window overflow already happened.
1134 We can read caller's SP from the proper spill loction. */
1136 read_memory_integer (cache->wd.aregs[1],
1137 register_size (current_gdbarch,
1138 gdbarch_tdep (current_gdbarch)->a0_base
1143 /* Read caller's frame SP directly from the previous window. */
1144 int regnum = AREG_NUMBER
1145 (gdbarch_tdep (current_gdbarch)->a0_base + 1,
1148 cache->prev_sp = xtensa_read_register (regnum);
1152 else /* Call0 framework. */
1154 call0_frame_cache (next_frame, cache, pc);
1157 cache->base = frame_unwind_register_unsigned
1158 (next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1);
1164 xtensa_frame_this_id (struct frame_info *next_frame,
1166 struct frame_id *this_id)
1168 struct xtensa_frame_cache *cache =
1169 xtensa_frame_cache (next_frame, this_cache);
1172 DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n",
1173 (unsigned int) next_frame, (unsigned int) *this_cache);
1175 if (cache->prev_sp == 0)
1178 id = frame_id_build (cache->prev_sp, cache->pc);
1179 if (frame_id_eq (id, get_frame_id(next_frame)))
1182 Frame stack is corrupted. That could happen because of \
1183 setting register(s) from GDB or stopping execution \
1184 inside exception handler. Frame backtracing has stopped. \
1185 It can make some GDB commands work inappropriately.\n"));
1193 call0_frame_get_reg_at_entry (struct frame_info *next_frame,
1194 struct xtensa_frame_cache *cache,
1197 enum lval_type *lval,
1202 int reg = (regnum >= gdbarch_tdep (current_gdbarch)->ar_base
1203 && regnum <= (gdbarch_tdep (current_gdbarch)->ar_base + C0_NREGS))
1204 ? regnum - gdbarch_tdep (current_gdbarch)->ar_base : regnum;
1206 /* Determine stack pointer on entry to this function, based on FP. */
1207 spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1209 /* If register was saved to the stack frame in the prologue, retrieve it. */
1210 stkofs = cache->c0.c0_rt[reg].to_stk;
1211 if (stkofs != C0_NOSTK)
1213 *lval = lval_memory;
1214 *addrp = spe + stkofs;
1217 read_memory (*addrp, valuep, register_size (current_gdbarch, regnum));
1222 /* If not callee-saved or if known to have been overwritten, give up. */
1224 || cache->c0.c0_rt[reg].fr_reg != reg
1225 || cache->c0.c0_rt[reg].fr_ofs != 0)
1228 if (get_frame_type (next_frame) != NORMAL_FRAME)
1229 /* TODO: Do we need a special case for DUMMY_FRAME here? */
1232 return call0_frame_get_reg_at_entry (get_next_frame(next_frame),
1233 cache, regnum, addrp, lval, valuep);
1237 xtensa_frame_prev_register (struct frame_info *next_frame,
1241 enum lval_type *lvalp,
1246 struct xtensa_frame_cache *cache =
1247 xtensa_frame_cache (next_frame, this_cache);
1248 CORE_ADDR saved_reg = 0;
1251 DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, "
1252 "*this 0x%08x, regnum %d (%s), ...)\n",
1253 (unsigned int) next_frame,
1254 *this_cache ? (unsigned int) *this_cache : 0, regnum,
1255 xtensa_register_name (regnum));
1257 if (regnum ==gdbarch_pc_regnum (current_gdbarch))
1258 saved_reg = cache->ra;
1259 else if (regnum == gdbarch_tdep (current_gdbarch)->a0_base + 1)
1260 saved_reg = cache->prev_sp;
1261 else if (!cache->call0)
1263 if (regnum == gdbarch_tdep (current_gdbarch)->ws_regnum)
1265 if (cache->wd.ws != 0)
1266 saved_reg = cache->wd.ws;
1268 saved_reg = 1 << cache->wd.wb;
1270 else if (regnum == gdbarch_tdep (current_gdbarch)->wb_regnum)
1271 saved_reg = cache->wd.wb;
1272 else if (regnum == gdbarch_ps_regnum (current_gdbarch))
1273 saved_reg = cache->ps;
1287 store_unsigned_integer (valuep, 4, saved_reg);
1292 if (!cache->call0) /* Windowed ABI. */
1294 /* Convert A-register numbers to AR-register numbers. */
1295 if (regnum >= gdbarch_tdep (current_gdbarch)->a0_base + 0
1296 && regnum <= gdbarch_tdep (current_gdbarch)->a0_base + 15)
1297 regnum = AREG_NUMBER (regnum, cache->wd.wb);
1299 /* Check if AR-register has been saved to stack. */
1300 if (regnum >= gdbarch_tdep (current_gdbarch)->ar_base
1301 && regnum <= (gdbarch_tdep (current_gdbarch)->ar_base
1302 + gdbarch_tdep (current_gdbarch)->num_aregs))
1304 int areg = regnum - gdbarch_tdep (current_gdbarch)->ar_base
1305 - (cache->wd.wb * 4);
1308 && areg < XTENSA_NUM_SAVED_AREGS
1309 && cache->wd.aregs[areg] != -1)
1312 *lvalp = lval_memory;
1313 *addrp = cache->wd.aregs[areg];
1317 read_memory (*addrp, valuep,
1318 register_size (current_gdbarch, regnum));
1320 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1325 else /* Call0 ABI. */
1327 int reg = (regnum >= gdbarch_tdep (current_gdbarch)->ar_base
1328 && regnum <= (gdbarch_tdep (current_gdbarch)->ar_base
1330 ? regnum - gdbarch_tdep (current_gdbarch)->ar_base : regnum;
1337 /* If register was saved in the prologue, retrieve it. */
1338 stkofs = cache->c0.c0_rt[reg].to_stk;
1339 if (stkofs != C0_NOSTK)
1341 /* Determine SP on entry based on FP. */
1342 spe = cache->c0.c0_fp
1343 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1345 *lvalp = lval_memory;
1346 *addrp = spe + stkofs;
1350 read_memory (*addrp, valuep,
1351 register_size (current_gdbarch, regnum));
1353 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1359 /* All other registers have been either saved to
1360 the stack or are still alive in the processor. */
1363 *lvalp = lval_register;
1367 frame_unwind_register (next_frame, (*realnump), valuep);
1371 static const struct frame_unwind
1372 xtensa_frame_unwind =
1375 xtensa_frame_this_id,
1376 xtensa_frame_prev_register
1379 static const struct frame_unwind *
1380 xtensa_frame_sniffer (struct frame_info *next_frame)
1382 return &xtensa_frame_unwind;
1386 xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache)
1388 struct xtensa_frame_cache *cache =
1389 xtensa_frame_cache (next_frame, this_cache);
1394 static const struct frame_base
1397 &xtensa_frame_unwind,
1398 xtensa_frame_base_address,
1399 xtensa_frame_base_address,
1400 xtensa_frame_base_address
1405 xtensa_extract_return_value (struct type *type,
1406 struct regcache *regcache,
1409 bfd_byte *valbuf = dst;
1410 int len = TYPE_LENGTH (type);
1415 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1417 gdb_assert(len > 0);
1419 if (gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
1421 /* First, we have to find the caller window in the register file. */
1422 regcache_raw_read_unsigned (regcache,
1423 gdbarch_pc_regnum (current_gdbarch), &pc);
1424 callsize = extract_call_winsize (pc);
1426 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1427 if (len > (callsize > 8 ? 8 : 16))
1428 internal_error (__FILE__, __LINE__,
1429 _("cannot extract return value of %d bytes long"), len);
1431 /* Get the register offset of the return
1432 register (A2) in the caller window. */
1433 regcache_raw_read_unsigned
1434 (regcache, gdbarch_tdep (current_gdbarch)->wb_regnum, &wb);
1435 areg = AREG_NUMBER(gdbarch_tdep (current_gdbarch)->a0_base + 2 + callsize,
1440 /* No windowing hardware - Call0 ABI. */
1441 areg = gdbarch_tdep (current_gdbarch)->a0_base + 0 + C0_ARGS;
1444 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1446 if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1449 for (; len > 0; len -= 4, areg++, valbuf += 4)
1452 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1454 regcache_raw_read (regcache, areg, valbuf);
1460 xtensa_store_return_value (struct type *type,
1461 struct regcache *regcache,
1464 const bfd_byte *valbuf = dst;
1468 int len = TYPE_LENGTH (type);
1471 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1473 if (gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
1475 regcache_raw_read_unsigned
1476 (regcache, gdbarch_tdep (current_gdbarch)->wb_regnum, &wb);
1477 regcache_raw_read_unsigned (regcache,
1478 gdbarch_pc_regnum (current_gdbarch), &pc);
1479 callsize = extract_call_winsize (pc);
1481 if (len > (callsize > 8 ? 8 : 16))
1482 internal_error (__FILE__, __LINE__,
1483 _("unimplemented for this length: %d"),
1484 TYPE_LENGTH (type));
1486 (gdbarch_tdep (current_gdbarch)->a0_base + 2 + callsize, wb);
1488 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1489 callsize, (int) wb);
1493 areg = gdbarch_tdep (current_gdbarch)->a0_base + 0 + C0_ARGS;
1496 if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1499 for (; len > 0; len -= 4, areg++, valbuf += 4)
1502 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1504 regcache_raw_write (regcache, areg, valbuf);
1509 static enum return_value_convention
1510 xtensa_return_value (struct gdbarch *gdbarch,
1511 struct type *valtype,
1512 struct regcache *regcache,
1514 const gdb_byte *writebuf)
1516 /* Structures up to 16 bytes are returned in registers. */
1518 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1519 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1520 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1521 && TYPE_LENGTH (valtype) > 16);
1524 return RETURN_VALUE_STRUCT_CONVENTION;
1526 DEBUGTRACE ("xtensa_return_value(...)\n");
1528 if (writebuf != NULL)
1530 xtensa_store_return_value (valtype, regcache, writebuf);
1533 if (readbuf != NULL)
1535 gdb_assert (!struct_return);
1536 xtensa_extract_return_value (valtype, regcache, readbuf);
1538 return RETURN_VALUE_REGISTER_CONVENTION;
1545 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1546 struct value *function,
1547 struct regcache *regcache,
1550 struct value **args,
1553 CORE_ADDR struct_addr)
1556 int size, onstack_size;
1557 gdb_byte *buf = (gdb_byte *) alloca (16);
1559 struct argument_info
1561 const bfd_byte *contents;
1563 int onstack; /* onstack == 0 => in reg */
1564 int align; /* alignment */
1567 int offset; /* stack offset if on stack */
1568 int regno; /* regno if in register */
1572 struct argument_info *arg_info =
1573 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1577 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1579 if (xtensa_debug_level > 3)
1582 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1583 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1584 "struct_addr=0x%x\n",
1585 (int) sp, (int) struct_return, (int) struct_addr);
1587 for (i = 0; i < nargs; i++)
1589 struct value *arg = args[i];
1590 struct type *arg_type = check_typedef (value_type (arg));
1591 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%08x %3d ",
1592 i, (int) arg, TYPE_LENGTH (arg_type));
1593 switch (TYPE_CODE (arg_type))
1596 fprintf_unfiltered (gdb_stdlog, "int");
1598 case TYPE_CODE_STRUCT:
1599 fprintf_unfiltered (gdb_stdlog, "struct");
1602 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1605 fprintf_unfiltered (gdb_stdlog, " 0x%08x\n",
1606 (unsigned int) value_contents (arg));
1610 /* First loop: collect information.
1611 Cast into type_long. (This shouldn't happen often for C because
1612 GDB already does this earlier.) It's possible that GDB could
1613 do it all the time but it's harmless to leave this code here. */
1620 size = REGISTER_SIZE;
1622 for (i = 0; i < nargs; i++)
1624 struct argument_info *info = &arg_info[i];
1625 struct value *arg = args[i];
1626 struct type *arg_type = check_typedef (value_type (arg));
1628 switch (TYPE_CODE (arg_type))
1631 case TYPE_CODE_BOOL:
1632 case TYPE_CODE_CHAR:
1633 case TYPE_CODE_RANGE:
1634 case TYPE_CODE_ENUM:
1636 /* Cast argument to long if necessary as the mask does it too. */
1637 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1639 arg_type = builtin_type_long;
1640 arg = value_cast (arg_type, arg);
1642 /* Aligment is equal to the type length for the basic types. */
1643 info->align = TYPE_LENGTH (arg_type);
1648 /* Align doubles correctly. */
1649 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1650 info->align = TYPE_LENGTH (builtin_type_double);
1652 info->align = TYPE_LENGTH (builtin_type_long);
1655 case TYPE_CODE_STRUCT:
1657 info->align = TYPE_LENGTH (builtin_type_long);
1660 info->length = TYPE_LENGTH (arg_type);
1661 info->contents = value_contents (arg);
1663 /* Align size and onstack_size. */
1664 size = (size + info->align - 1) & ~(info->align - 1);
1665 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1667 if (size + info->length > REGISTER_SIZE * ARG_NOF)
1670 info->u.offset = onstack_size;
1671 onstack_size += info->length;
1676 info->u.regno = ARG_1ST + size / REGISTER_SIZE;
1678 size += info->length;
1681 /* Adjust the stack pointer and align it. */
1682 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1684 /* Simulate MOVSP, if Windowed ABI. */
1685 if ((gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
1688 read_memory (osp - 16, buf, 16);
1689 write_memory (sp - 16, buf, 16);
1692 /* Second Loop: Load arguments. */
1696 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1697 regcache_cooked_write (regcache, ARG_1ST, buf);
1700 for (i = 0; i < nargs; i++)
1702 struct argument_info *info = &arg_info[i];
1706 int n = info->length;
1707 CORE_ADDR offset = sp + info->u.offset;
1709 /* Odd-sized structs are aligned to the lower side of a memory
1710 word in big-endian mode and require a shift. This only
1711 applies for structures smaller than one word. */
1713 if (n < REGISTER_SIZE
1714 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1715 offset += (REGISTER_SIZE - n);
1717 write_memory (offset, info->contents, info->length);
1722 int n = info->length;
1723 const bfd_byte *cp = info->contents;
1724 int r = info->u.regno;
1726 /* Odd-sized structs are aligned to the lower side of registers in
1727 big-endian mode and require a shift. The odd-sized leftover will
1728 be at the end. Note that this is only true for structures smaller
1729 than REGISTER_SIZE; for larger odd-sized structures the excess
1730 will be left-aligned in the register on both endiannesses. */
1732 if (n < REGISTER_SIZE
1733 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1735 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1736 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1738 store_unsigned_integer (buf, REGISTER_SIZE, v);
1739 regcache_cooked_write (regcache, r, buf);
1741 cp += REGISTER_SIZE;
1748 regcache_cooked_write (regcache, r, cp);
1750 cp += REGISTER_SIZE;
1757 /* Set the return address of dummy frame to the dummy address.
1758 The return address for the current function (in A0) is
1759 saved in the dummy frame, so we can savely overwrite A0 here. */
1761 if (gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
1763 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1764 regcache_raw_read (regcache, gdbarch_ps_regnum (current_gdbarch), buf);
1765 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1766 regcache_cooked_write_unsigned
1767 (regcache, gdbarch_tdep (current_gdbarch)->a0_base + 4, ra);
1768 regcache_cooked_write_unsigned (regcache,
1769 gdbarch_ps_regnum (current_gdbarch),
1774 /* Simulate CALL0: write RA into A0 register. */
1775 regcache_cooked_write_unsigned
1776 (regcache, gdbarch_tdep (current_gdbarch)->a0_base + 0, bp_addr);
1779 /* Set new stack pointer and return it. */
1780 regcache_cooked_write_unsigned (regcache,
1781 gdbarch_tdep (current_gdbarch)->a0_base + 1,
1783 /* Make dummy frame ID unique by adding a constant. */
1784 return sp + SP_ALIGNMENT;
1788 /* Return a breakpoint for the current location of PC. We always use
1789 the density version if we have density instructions (regardless of the
1790 current instruction at PC), and use regular instructions otherwise. */
1792 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1793 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1794 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1795 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1797 static const unsigned char *
1798 xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1800 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1801 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1802 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1803 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1805 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1807 if (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
1809 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1811 *lenptr = sizeof (density_big_breakpoint);
1812 return density_big_breakpoint;
1816 *lenptr = sizeof (density_little_breakpoint);
1817 return density_little_breakpoint;
1822 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1824 *lenptr = sizeof (big_breakpoint);
1825 return big_breakpoint;
1829 *lenptr = sizeof (little_breakpoint);
1830 return little_breakpoint;
1835 /* Call0 ABI support routines. */
1837 /* Call0 opcode class. Opcodes are preclassified according to what they
1838 mean for Call0 prologue analysis, and their number of significant operands.
1839 The purpose of this is to simplify prologue analysis by separating
1840 instruction decoding (libisa) from the semantics of prologue analysis. */
1843 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1844 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1845 c0opc_flow, /* Flow control insn. */
1846 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1847 c0opc_break, /* Debugger software breakpoints. */
1848 c0opc_add, /* Adding two registers. */
1849 c0opc_addi, /* Adding a register and an immediate. */
1850 c0opc_sub, /* Subtracting a register from a register. */
1851 c0opc_mov, /* Moving a register to a register. */
1852 c0opc_movi, /* Moving an immediate to a register. */
1853 c0opc_l32r, /* Loading a literal. */
1854 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1855 c0opc_NrOf /* Number of opcode classifications. */
1859 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1861 static xtensa_insn_kind
1862 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1864 const char *opcname;
1865 xtensa_insn_kind opclass = c0opc_uninteresting;
1867 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1869 /* Get opcode name and handle special classifications. */
1871 opcname = xtensa_opcode_name (isa, opc);
1874 || strcasecmp (opcname, "ill") == 0
1875 || strcasecmp (opcname, "ill.n") == 0)
1876 opclass = c0opc_illegal;
1877 else if (strcasecmp (opcname, "break") == 0
1878 || strcasecmp (opcname, "break.n") == 0)
1879 opclass = c0opc_break;
1880 else if (strcasecmp (opcname, "entry") == 0)
1881 opclass = c0opc_entry;
1882 else if (xtensa_opcode_is_branch (isa, opc) > 0
1883 || xtensa_opcode_is_jump (isa, opc) > 0
1884 || xtensa_opcode_is_loop (isa, opc) > 0
1885 || xtensa_opcode_is_call (isa, opc) > 0
1886 || strcasecmp (opcname, "simcall") == 0
1887 || strcasecmp (opcname, "syscall") == 0)
1888 opclass = c0opc_flow;
1890 /* Also, classify specific opcodes that need to be tracked. */
1891 else if (strcasecmp (opcname, "add") == 0
1892 || strcasecmp (opcname, "add.n") == 0)
1893 opclass = c0opc_add;
1894 else if (strcasecmp (opcname, "addi") == 0
1895 || strcasecmp (opcname, "addi.n") == 0
1896 || strcasecmp (opcname, "addmi") == 0)
1897 opclass = c0opc_addi;
1898 else if (strcasecmp (opcname, "sub") == 0)
1899 opclass = c0opc_sub;
1900 else if (strcasecmp (opcname, "mov.n") == 0
1901 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1902 opclass = c0opc_mov;
1903 else if (strcasecmp (opcname, "movi") == 0
1904 || strcasecmp (opcname, "movi.n") == 0)
1905 opclass = c0opc_movi;
1906 else if (strcasecmp (opcname, "l32r") == 0)
1907 opclass = c0opc_l32r;
1908 else if (strcasecmp (opcname, "s32i") == 0
1909 || strcasecmp (opcname, "s32i.n") == 0)
1910 opclass = c0opc_s32i;
1915 /* Tracks register movement/mutation for a given operation, which may
1916 be within a bundle. Updates the destination register tracking info
1917 accordingly. The pc is needed only for pc-relative load instructions
1918 (eg. l32r). The SP register number is needed to identify stores to
1922 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1923 xtensa_insn_kind opclass, int nods, unsigned odv[],
1924 CORE_ADDR pc, int spreg)
1926 unsigned litbase, litaddr, litval;
1931 /* 3 operands: dst, src, imm. */
1932 gdb_assert (nods == 3);
1933 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1934 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1937 /* 3 operands: dst, src1, src2. */
1938 gdb_assert (nods == 3);
1939 if (src[odv[1]].fr_reg == C0_CONST)
1941 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
1942 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
1944 else if (src[odv[2]].fr_reg == C0_CONST)
1946 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1947 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
1949 else dst[odv[0]].fr_reg = C0_INEXP;
1952 /* 3 operands: dst, src1, src2. */
1953 gdb_assert (nods == 3);
1954 if (src[odv[2]].fr_reg == C0_CONST)
1956 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1957 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
1959 else dst[odv[0]].fr_reg = C0_INEXP;
1962 /* 2 operands: dst, src [, src]. */
1963 gdb_assert (nods == 2);
1964 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1965 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
1968 /* 2 operands: dst, imm. */
1969 gdb_assert (nods == 2);
1970 dst[odv[0]].fr_reg = C0_CONST;
1971 dst[odv[0]].fr_ofs = odv[1];
1974 /* 2 operands: dst, literal offset. */
1975 gdb_assert (nods == 2);
1976 /* litbase = xtensa_get_litbase (pc); can be also used. */
1977 litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1)
1978 ? 0 : xtensa_read_register
1979 (gdbarch_tdep (current_gdbarch)->litbase_regnum);
1980 litaddr = litbase & 1
1981 ? (litbase & ~1) + (signed)odv[1]
1982 : (pc + 3 + (signed)odv[1]) & ~3;
1983 litval = read_memory_integer(litaddr, 4);
1984 dst[odv[0]].fr_reg = C0_CONST;
1985 dst[odv[0]].fr_ofs = litval;
1988 /* 3 operands: value, base, offset. */
1989 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
1990 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
1991 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
1992 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
1993 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
1994 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
1996 /* ISA encoding guarantees alignment. But, check it anyway. */
1997 gdb_assert ((odv[2] & 3) == 0);
1998 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2006 /* Analyze prologue of the function at start address to determine if it uses
2007 the Call0 ABI, and if so track register moves and linear modifications
2008 in the prologue up to the PC or just beyond the prologue, whichever is first.
2009 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2010 The prologue may overlap non-prologue instructions but is guaranteed to end
2011 by the first flow-control instruction (jump, branch, call or return).
2012 Since an optimized function may move information around and change the
2013 stack frame arbitrarily during the prologue, the information is guaranteed
2014 valid only at the point in the function indicated by the PC.
2015 May be used to skip the prologue or identify the ABI, w/o tracking.
2017 Returns: Address of first instruction after prologue, or PC (whichever
2018 is first), or 0, if decoding failed (in libisa).
2020 start Start address of function/prologue.
2021 pc Program counter to stop at. Use 0 to continue to end of prologue.
2022 If 0, avoids infinite run-on in corrupt code memory by bounding
2023 the scan to the end of the function if that can be determined.
2024 nregs Number of general registers to track (size of rt[] array).
2026 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2027 If NULL, registers are not tracked.
2029 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2030 (more accurately, non-zero until 'entry' insn is encountered).
2032 Note that these may produce useful results even if decoding fails
2033 because they begin with default assumptions that analysis may change. */
2036 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
2037 int nregs, xtensa_c0reg_t rt[], int *call0)
2039 CORE_ADDR ia; /* Current insn address in prologue. */
2040 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2041 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2042 #define BSZ 32 /* Instruction buffer size. */
2043 char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
2044 xtensa_isa isa; /* libisa ISA handle. */
2045 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2046 xtensa_format ifmt; /* libisa instruction format. */
2047 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2048 xtensa_opcode opc; /* Opcode in current slot. */
2049 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2050 int nods; /* Opcode number of operands. */
2051 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2052 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2053 int j; /* General loop counter. */
2054 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2055 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2056 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2058 struct symtab_and_line prologue_sal;
2060 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2061 (int)start, (int)pc);
2063 /* Try to limit the scan to the end of the function if a non-zero pc
2064 arg was not supplied to avoid probing beyond the end of valid memory.
2065 If memory is full of garbage that classifies as c0opc_uninteresting.
2066 If this fails (eg. if no symbols) pc ends up 0 as it was.
2067 Intialize the Call0 frame and register tracking info.
2068 Assume it's Call0 until an 'entry' instruction is encountered.
2069 Assume we may be in the prologue until we hit a flow control instr. */
2075 /* Find out, if we have an information about the prologue from DWARF. */
2076 prologue_sal = find_pc_line (start, 0);
2077 if (prologue_sal.line != 0) /* Found debug info. */
2078 body_pc = prologue_sal.end;
2080 /* If we are going to analyze the prologue in general without knowing about
2081 the current PC, make the best assumtion for the end of the prologue. */
2084 find_pc_partial_function (start, 0, NULL, &end_pc);
2085 body_pc = min (end_pc, body_pc);
2088 body_pc = min (pc, body_pc);
2095 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2096 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2100 isa = xtensa_default_isa;
2101 gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
2102 ins = xtensa_insnbuf_alloc (isa);
2103 slot = xtensa_insnbuf_alloc (isa);
2105 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2107 /* (Re)fill instruction buffer from memory if necessary, but do not
2108 read memory beyond PC to be sure we stay within text section
2109 (this protection only works if a non-zero pc is supplied). */
2111 if (ia + xtensa_isa_maxlength (isa) > bt)
2114 bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
2115 read_memory (ba, ibuf, bt - ba);
2118 /* Decode format information. */
2120 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2121 ifmt = xtensa_format_decode (isa, ins);
2122 if (ifmt == XTENSA_UNDEFINED)
2127 ilen = xtensa_format_length (isa, ifmt);
2128 if (ilen == XTENSA_UNDEFINED)
2133 islots = xtensa_format_num_slots (isa, ifmt);
2134 if (islots == XTENSA_UNDEFINED)
2140 /* Analyze a bundle or a single instruction, using a snapshot of
2141 the register tracking info as input for the entire bundle so that
2142 register changes do not take effect within this bundle. */
2144 for (j = 0; j < nregs; ++j)
2147 for (is = 0; is < islots; ++is)
2149 /* Decode a slot and classify the opcode. */
2151 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2155 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2156 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2158 if (opc == XTENSA_UNDEFINED)
2159 opclass = c0opc_illegal;
2161 opclass = call0_classify_opcode (isa, opc);
2163 /* Decide whether to track this opcode, ignore it, or bail out. */
2172 case c0opc_uninteresting:
2181 ia += ilen; /* Skip over 'entry' insn. */
2189 /* Only expected opcodes should get this far. */
2193 /* Extract and decode the operands. */
2194 nods = xtensa_opcode_num_operands (isa, opc);
2195 if (nods == XTENSA_UNDEFINED)
2201 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2203 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2208 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2213 /* Check operands to verify use of 'mov' assembler macro. */
2214 if (opclass == c0opc_mov && nods == 3)
2216 if (odv[2] == odv[1])
2220 opclass = c0opc_uninteresting;
2225 /* Track register movement and modification for this operation. */
2226 call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
2230 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2231 (unsigned)ia, fail ? "failed" : "succeeded");
2232 xtensa_insnbuf_free(isa, slot);
2233 xtensa_insnbuf_free(isa, ins);
2234 return fail ? 0 : ia;
2237 /* Initialize frame cache for the current frame. The "next_frame" is the next
2238 one relative to current frame. "cache" is the pointer to the data structure
2239 we have to initialize. "pc" is curretnt PC. */
2242 call0_frame_cache (struct frame_info *next_frame,
2243 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2245 CORE_ADDR start_pc; /* The beginning of the function. */
2246 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2247 CORE_ADDR sp, fp, ra;
2248 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2250 /* Find the beginning of the prologue of the function containing the PC
2251 and analyze it up to the PC or the end of the prologue. */
2253 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2255 body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
2256 &cache->c0.c0_rt[0],
2260 sp = frame_unwind_register_unsigned
2261 (next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1);
2262 fp = sp; /* Assume FP == SP until proven otherwise. */
2264 /* Get the frame information and FP (if used) at the current PC.
2265 If PC is in the prologue, the prologue analysis is more reliable
2266 than DWARF info. We don't not know for sure if PC is in the prologue,
2267 but we know no calls have yet taken place, so we can almost
2268 certainly rely on the prologue analysis. */
2272 /* Prologue analysis was successful up to the PC.
2273 It includes the cases when PC == START_PC. */
2274 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2275 /* c0_hasfp == true means there is a frame pointer because
2276 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2277 was derived from SP. Otherwise, it would be C0_FP. */
2278 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2279 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2280 fp_regnum += gdbarch_tdep (current_gdbarch)->a0_base;
2282 else /* No data from the prologue analysis. */
2285 fp_regnum = gdbarch_tdep (current_gdbarch)->a0_base + C0_SP;
2290 prev_sp = fp + c0_frmsz;
2292 /* Frame size from debug info or prologue tracking does not account for
2293 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2296 fp = frame_unwind_register_unsigned (next_frame, fp_regnum);
2298 /* Recalculate previous SP. */
2299 prev_sp = fp + c0_frmsz;
2300 /* Update the stack frame size. */
2301 c0_frmsz += fp - sp;
2304 /* Get the return address (RA) from the stack if saved,
2305 or try to get it from a register. */
2307 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2308 if (to_stk != C0_NOSTK)
2310 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2312 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2313 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2315 /* Special case for terminating backtrace at a function that wants to
2316 be seen as the outermost. Such a function will clear it's RA (A0)
2317 register to 0 in the prologue instead of saving its original value. */
2322 /* RA was copied to another register or (before any function call) may
2323 still be in the original RA register. This is not always reliable:
2324 even in a leaf function, register tracking stops after prologue, and
2325 even in prologue, non-prologue instructions (not tracked) may overwrite
2326 RA or any register it was copied to. If likely in prologue or before
2327 any call, use retracking info and hope for the best (compiler should
2328 have saved RA in stack if not in a leaf function). If not in prologue,
2334 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2336 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2338 if (i < C0_NREGS) /* Read from the next_frame. */
2340 ra = frame_unwind_register_unsigned
2342 gdbarch_tdep (current_gdbarch)->a0_base + 0
2343 + cache->c0.c0_rt[i].fr_reg);
2348 cache->pc = start_pc;
2350 /* RA == 0 marks the outermost frame. Do not go past it. */
2351 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2352 cache->c0.fp_regnum = fp_regnum;
2353 cache->c0.c0_frmsz = c0_frmsz;
2354 cache->c0.c0_hasfp = c0_hasfp;
2355 cache->c0.c0_fp = fp;
2359 /* Skip function prologue.
2361 Return the pc of the first instruction after prologue. GDB calls this to
2362 find the address of the first line of the function or (if there is no line
2363 number information) to skip the prologue for planting breakpoints on
2364 function entries. Use debug info (if present) or prologue analysis to skip
2365 the prologue to achieve reliable debugging behavior. For windowed ABI,
2366 only the 'entry' instruction is skipped. It is not strictly necessary to
2367 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2368 backtrace at any point in the prologue, however certain potential hazards
2369 are avoided and a more "normal" debugging experience is ensured by
2370 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2371 For example, if we don't skip the prologue:
2372 - Some args may not yet have been saved to the stack where the debug
2373 info expects to find them (true anyway when only 'entry' is skipped);
2374 - Software breakpoints ('break' instrs) may not have been unplanted
2375 when the prologue analysis is done on initializing the frame cache,
2376 and breaks in the prologue will throw off the analysis.
2378 If we have debug info ( line-number info, in particular ) we simply skip
2379 the code associated with the first function line effectively skipping
2380 the prologue code. It works even in cases like
2383 { int local_var = 1;
2387 because, for this source code, both Xtensa compilers will generate two
2388 separate entries ( with the same line number ) in dwarf line-number
2389 section to make sure there is a boundary between the prologue code and
2390 the rest of the function.
2392 If there is no debug info, we need to analyze the code. */
2394 /* #define DONT_SKIP_PROLOGUE */
2397 xtensa_skip_prologue (CORE_ADDR start_pc)
2399 struct symtab_and_line prologue_sal;
2402 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2404 #if DONT_SKIP_PROLOGUE
2408 /* Try to find first body line from debug info. */
2410 prologue_sal = find_pc_line (start_pc, 0);
2411 if (prologue_sal.line != 0) /* Found debug info. */
2413 /* In Call0, it is possible to have a function with only one instruction
2414 ('ret') resulting from a 1-line optimized function that does nothing.
2415 In that case, prologue_sal.end may actually point to the start of the
2416 next function in the text section, causing a breakpoint to be set at
2417 the wrong place. Check if the end address is in a different function,
2418 and if so return the start PC. We know we have symbol info. */
2422 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2423 if (end_func != start_pc)
2426 return prologue_sal.end;
2429 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2430 body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
2431 return body_pc != 0 ? body_pc : start_pc;
2434 /* Verify the current configuration. */
2436 xtensa_verify_config (struct gdbarch *gdbarch)
2438 struct ui_file *log;
2439 struct cleanup *cleanups;
2440 struct gdbarch_tdep *tdep;
2444 tdep = gdbarch_tdep (gdbarch);
2445 log = mem_fileopen ();
2446 cleanups = make_cleanup_ui_file_delete (log);
2448 /* Verify that we got a reasonable number of AREGS. */
2449 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2450 fprintf_unfiltered (log, _("\
2451 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2454 /* Verify that certain registers exist. */
2456 if (tdep->pc_regnum == -1)
2457 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2458 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2459 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2461 if (tdep->isa_use_windowed_registers)
2463 if (tdep->wb_regnum == -1)
2464 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2465 if (tdep->ws_regnum == -1)
2466 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2467 if (tdep->ar_base == -1)
2468 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2471 if (tdep->a0_base == -1)
2472 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2474 buf = ui_file_xstrdup (log, &dummy);
2475 make_cleanup (xfree, buf);
2476 if (strlen (buf) > 0)
2477 internal_error (__FILE__, __LINE__,
2478 _("the following are invalid: %s"), buf);
2479 do_cleanups (cleanups);
2482 /* Module "constructor" function. */
2484 static struct gdbarch *
2485 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2487 struct gdbarch_tdep *tdep;
2488 struct gdbarch *gdbarch;
2489 struct xtensa_abi_handler *abi_handler;
2491 DEBUGTRACE ("gdbarch_init()\n");
2493 /* We have to set the byte order before we call gdbarch_alloc. */
2494 info.byte_order = xtensa_config_byte_order (&info);
2496 tdep = xtensa_config_tdep (&info);
2497 gdbarch = gdbarch_alloc (&info, tdep);
2499 /* Verify our configuration. */
2500 xtensa_verify_config (gdbarch);
2502 /* Pseudo-Register read/write. */
2503 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2504 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2506 /* Set target information. */
2507 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2508 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2509 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2510 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2511 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2513 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
2514 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2515 set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2516 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2518 /* We provide our own function to get register information. */
2519 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2520 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2522 /* To call functions from GDB using dummy frame */
2523 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2525 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2527 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2529 /* Advance PC across any prologue instructions to reach "real" code. */
2530 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2532 /* Stack grows downward. */
2533 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2535 /* Set breakpoints. */
2536 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2538 /* After breakpoint instruction or illegal instruction, pc still
2539 points at break instruction, so don't decrement. */
2540 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2542 /* We don't skip args. */
2543 set_gdbarch_frame_args_skip (gdbarch, 0);
2545 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2547 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2549 set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id);
2551 /* Frame handling. */
2552 frame_base_set_default (gdbarch, &xtensa_frame_base);
2553 frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer);
2555 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2557 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2559 xtensa_add_reggroups (gdbarch);
2560 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2562 set_gdbarch_regset_from_core_section (gdbarch,
2563 xtensa_regset_from_core_section);
2569 xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2571 error (_("xtensa_dump_tdep(): not implemented"));
2575 _initialize_xtensa_tdep (void)
2577 struct cmd_list_element *c;
2579 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2580 xtensa_init_reggroups ();
2582 add_setshow_zinteger_cmd ("xtensa",
2584 &xtensa_debug_level, _("\
2585 Set Xtensa debugging."), _("\
2586 Show Xtensa debugging."), _("\
2587 When non-zero, Xtensa-specific debugging is enabled. \
2588 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2591 &setdebuglist, &showdebuglist);