1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* ABI-independent macros. */
95 #define ARG_NOF(gdbarch) \
96 (gdbarch_tdep (gdbarch)->call_abi \
97 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
98 #define ARG_1ST(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
100 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
101 : (gdbarch_tdep (gdbarch)->a0_base + 6))
103 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
104 indicates that the instruction is an ENTRY instruction. */
106 #define XTENSA_IS_ENTRY(gdbarch, op1) \
107 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
108 ? ((op1) == 0x6c) : ((op1) == 0x36))
110 #define XTENSA_ENTRY_LENGTH 3
112 /* windowing_enabled() returns true, if windowing is enabled.
113 WOE must be set to 1; EXCM to 0.
114 Note: We assume that EXCM is always 0 for XEA1. */
116 #define PS_WOE (1<<18)
117 #define PS_EXC (1<<4)
119 /* Convert a live A-register number to the corresponding AR-register number. */
121 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
123 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
126 arreg = a_regnum - tdep->a0_base;
127 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
128 arreg &= tdep->num_aregs - 1;
130 return arreg + tdep->ar_base;
133 /* Convert a live AR-register number to the corresponding A-register order
134 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
136 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
141 areg = ar_regnum - tdep->ar_base;
142 if (areg < 0 || areg >= tdep->num_aregs)
144 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
145 return (areg > 15) ? -1 : areg;
149 windowing_enabled (CORE_ADDR ps)
151 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
154 /* Return the window size of the previous call to the function from which we
157 This function is used to extract the return value after a called function
158 has returned to the caller. On Xtensa, the register that holds the return
159 value (from the perspective of the caller) depends on what call
160 instruction was used. For now, we are assuming that the call instruction
161 precedes the current address, so we simply analyze the call instruction.
162 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
163 method to call the inferior function. */
166 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
172 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
174 /* Read the previous instruction (should be a call[x]{4|8|12}. */
175 read_memory (pc-3, buf, 3);
176 insn = extract_unsigned_integer (buf, 3);
178 /* Decode call instruction:
180 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
181 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
183 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
184 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
186 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
188 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
189 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
193 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
194 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
200 /* REGISTER INFORMATION */
202 /* Returns the name of a register. */
204 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
206 /* Return the name stored in the register map. */
207 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
208 + gdbarch_num_pseudo_regs (gdbarch))
209 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
211 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
215 /* Return the type of a register. Create a new type, if necessary. */
217 static struct ctype_cache
219 struct ctype_cache *next;
221 struct type *virtual_type;
222 } *type_entries = NULL;
225 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
227 /* Return signed integer for ARx and Ax registers. */
228 if ((regnum >= gdbarch_tdep (gdbarch)->ar_base
229 && regnum < gdbarch_tdep (gdbarch)->ar_base
230 + gdbarch_tdep (gdbarch)->num_aregs)
231 || (regnum >= gdbarch_tdep (gdbarch)->a0_base
232 && regnum < gdbarch_tdep (gdbarch)->a0_base + 16))
233 return builtin_type (gdbarch)->builtin_int;
235 if (regnum == gdbarch_pc_regnum (gdbarch)
236 || regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
237 return builtin_type (gdbarch)->builtin_data_ptr;
239 /* Return the stored type for all other registers. */
240 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
241 + gdbarch_num_pseudo_regs (gdbarch))
243 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
245 /* Set ctype for this register (only the first time). */
249 struct ctype_cache *tp;
250 int size = reg->byte_size;
252 /* We always use the memory representation,
253 even if the register width is smaller. */
257 reg->ctype = builtin_type_uint8;
261 reg->ctype = builtin_type_uint16;
265 reg->ctype = builtin_type_uint32;
269 reg->ctype = builtin_type_uint64;
273 reg->ctype = builtin_type_uint128;
277 for (tp = type_entries; tp != NULL; tp = tp->next)
278 if (tp->size == size)
283 char *name = xmalloc (16);
284 tp = xmalloc (sizeof (struct ctype_cache));
285 tp->next = type_entries;
289 sprintf (name, "int%d", size * 8);
290 tp->virtual_type = init_type (TYPE_CODE_INT, size,
291 TYPE_FLAG_UNSIGNED, name,
295 reg->ctype = tp->virtual_type;
301 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
306 /* Return the 'local' register number for stubs, dwarf2, etc.
307 The debugging information enumerates registers starting from 0 for A0
308 to n for An. So, we only have to add the base number for A0. */
311 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
315 if (regnum >= 0 && regnum < 16)
316 return gdbarch_tdep (gdbarch)->a0_base + regnum;
319 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
321 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
324 internal_error (__FILE__, __LINE__,
325 _("invalid dwarf/stabs register number %d"), regnum);
330 /* Write the bits of a masked register to the various registers.
331 Only the masked areas of these registers are modified; the other
332 fields are untouched. The size of masked registers is always less
333 than or equal to 32 bits. */
336 xtensa_register_write_masked (struct regcache *regcache,
337 xtensa_register_t *reg, const gdb_byte *buffer)
339 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
340 const xtensa_mask_t *mask = reg->mask;
342 int shift = 0; /* Shift for next mask (mod 32). */
343 int start, size; /* Start bit and size of current mask. */
345 unsigned int *ptr = value;
346 unsigned int regval, m, mem = 0;
348 int bytesize = reg->byte_size;
349 int bitsize = bytesize * 8;
352 DEBUGTRACE ("xtensa_register_write_masked ()\n");
354 /* Copy the masked register to host byte-order. */
355 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
356 for (i = 0; i < bytesize; i++)
359 mem |= (buffer[bytesize - i - 1] << 24);
364 for (i = 0; i < bytesize; i++)
367 mem |= (buffer[i] << 24);
372 /* We might have to shift the final value:
373 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
374 bytesize & 3 == x -> shift (4-x) * 8. */
376 *ptr = mem >> (((0 - bytesize) & 3) * 8);
380 /* Write the bits to the masked areas of the other registers. */
381 for (i = 0; i < mask->count; i++)
383 start = mask->mask[i].bit_start;
384 size = mask->mask[i].bit_size;
385 regval = mem >> shift;
387 if ((shift += size) > bitsize)
388 error (_("size of all masks is larger than the register"));
397 regval |= mem << (size - shift);
400 /* Make sure we have a valid register. */
401 r = mask->mask[i].reg_num;
402 if (r >= 0 && size > 0)
404 /* Don't overwrite the unmasked areas. */
406 regcache_cooked_read_unsigned (regcache, r, &old_val);
407 m = 0xffffffff >> (32 - size) << start;
409 regval = (regval & m) | (old_val & ~m);
410 regcache_cooked_write_unsigned (regcache, r, regval);
416 /* Read a tie state or mapped registers. Read the masked areas
417 of the registers and assemble them into a single value. */
420 xtensa_register_read_masked (struct regcache *regcache,
421 xtensa_register_t *reg, gdb_byte *buffer)
423 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
424 const xtensa_mask_t *mask = reg->mask;
429 unsigned int *ptr = value;
430 unsigned int regval, mem = 0;
432 int bytesize = reg->byte_size;
433 int bitsize = bytesize * 8;
436 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
437 reg->name == 0 ? "" : reg->name);
439 /* Assemble the register from the masked areas of other registers. */
440 for (i = 0; i < mask->count; i++)
442 int r = mask->mask[i].reg_num;
446 regcache_cooked_read_unsigned (regcache, r, &val);
447 regval = (unsigned int) val;
452 start = mask->mask[i].bit_start;
453 size = mask->mask[i].bit_size;
458 regval &= (0xffffffff >> (32 - size));
460 mem |= regval << shift;
462 if ((shift += size) > bitsize)
463 error (_("size of all masks is larger than the register"));
474 mem = regval >> (size - shift);
481 /* Copy value to target byte order. */
485 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
486 for (i = 0; i < bytesize; i++)
490 buffer[bytesize - i - 1] = mem & 0xff;
494 for (i = 0; i < bytesize; i++)
498 buffer[i] = mem & 0xff;
504 /* Read pseudo registers. */
507 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
508 struct regcache *regcache,
512 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
513 regnum, xtensa_register_name (gdbarch, regnum));
515 if (regnum == gdbarch_num_regs (gdbarch)
516 + gdbarch_num_pseudo_regs (gdbarch) - 1)
517 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
519 /* Read aliases a0..a15, if this is a Windowed ABI. */
520 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
521 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
522 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
524 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
526 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
527 regnum = arreg_number (gdbarch, regnum,
528 extract_unsigned_integer (buf, 4));
531 /* We can always read non-pseudo registers. */
532 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
533 regcache_raw_read (regcache, regnum, buffer);
536 /* We have to find out how to deal with priveleged registers.
537 Let's treat them as pseudo-registers, but we cannot read/write them. */
539 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
541 buffer[0] = (gdb_byte)0;
542 buffer[1] = (gdb_byte)0;
543 buffer[2] = (gdb_byte)0;
544 buffer[3] = (gdb_byte)0;
546 /* Pseudo registers. */
548 && regnum < gdbarch_num_regs (gdbarch)
549 + gdbarch_num_pseudo_regs (gdbarch))
551 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
552 xtensa_register_type_t type = reg->type;
553 int flags = gdbarch_tdep (gdbarch)->target_flags;
555 /* We cannot read Unknown or Unmapped registers. */
556 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
558 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
560 warning (_("cannot read register %s"),
561 xtensa_register_name (gdbarch, regnum));
566 /* Some targets cannot read TIE register files. */
567 else if (type == xtRegisterTypeTieRegfile)
569 /* Use 'fetch' to get register? */
570 if (flags & xtTargetFlagsUseFetchStore)
572 warning (_("cannot read register"));
576 /* On some targets (esp. simulators), we can always read the reg. */
577 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
579 warning (_("cannot read register"));
584 /* We can always read mapped registers. */
585 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
587 xtensa_register_read_masked (regcache, reg, buffer);
591 /* Assume that we can read the register. */
592 regcache_raw_read (regcache, regnum, buffer);
595 internal_error (__FILE__, __LINE__,
596 _("invalid register number %d"), regnum);
600 /* Write pseudo registers. */
603 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
604 struct regcache *regcache,
606 const gdb_byte *buffer)
608 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
609 regnum, xtensa_register_name (gdbarch, regnum));
611 if (regnum == gdbarch_num_regs (gdbarch)
612 + gdbarch_num_pseudo_regs (gdbarch) -1)
613 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
615 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
616 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
617 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
618 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
620 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
623 regcache_raw_read (regcache,
624 gdbarch_tdep (gdbarch)->wb_regnum, buf);
625 regnum = arreg_number (gdbarch, regnum,
626 extract_unsigned_integer (buf, 4));
629 /* We can always write 'core' registers.
630 Note: We might have converted Ax->ARy. */
631 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
632 regcache_raw_write (regcache, regnum, buffer);
634 /* We have to find out how to deal with priveleged registers.
635 Let's treat them as pseudo-registers, but we cannot read/write them. */
637 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
641 /* Pseudo registers. */
643 && regnum < gdbarch_num_regs (gdbarch)
644 + gdbarch_num_pseudo_regs (gdbarch))
646 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
647 xtensa_register_type_t type = reg->type;
648 int flags = gdbarch_tdep (gdbarch)->target_flags;
650 /* On most targets, we cannot write registers
651 of type "Unknown" or "Unmapped". */
652 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
654 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
656 warning (_("cannot write register %s"),
657 xtensa_register_name (gdbarch, regnum));
662 /* Some targets cannot read TIE register files. */
663 else if (type == xtRegisterTypeTieRegfile)
665 /* Use 'store' to get register? */
666 if (flags & xtTargetFlagsUseFetchStore)
668 warning (_("cannot write register"));
672 /* On some targets (esp. simulators), we can always write
674 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
676 warning (_("cannot write register"));
681 /* We can always write mapped registers. */
682 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
684 xtensa_register_write_masked (regcache, reg, buffer);
688 /* Assume that we can write the register. */
689 regcache_raw_write (regcache, regnum, buffer);
692 internal_error (__FILE__, __LINE__,
693 _("invalid register number %d"), regnum);
696 static struct reggroup *xtensa_ar_reggroup;
697 static struct reggroup *xtensa_user_reggroup;
698 static struct reggroup *xtensa_vectra_reggroup;
699 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
702 xtensa_init_reggroups (void)
704 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
705 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
706 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
708 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
709 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
710 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
711 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
712 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
713 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
714 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
715 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
719 xtensa_add_reggroups (struct gdbarch *gdbarch)
723 /* Predefined groups. */
724 reggroup_add (gdbarch, all_reggroup);
725 reggroup_add (gdbarch, save_reggroup);
726 reggroup_add (gdbarch, restore_reggroup);
727 reggroup_add (gdbarch, system_reggroup);
728 reggroup_add (gdbarch, vector_reggroup);
729 reggroup_add (gdbarch, general_reggroup);
730 reggroup_add (gdbarch, float_reggroup);
732 /* Xtensa-specific groups. */
733 reggroup_add (gdbarch, xtensa_ar_reggroup);
734 reggroup_add (gdbarch, xtensa_user_reggroup);
735 reggroup_add (gdbarch, xtensa_vectra_reggroup);
737 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
738 reggroup_add (gdbarch, xtensa_cp[i]);
742 xtensa_coprocessor_register_group (struct reggroup *group)
746 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
747 if (group == xtensa_cp[i])
753 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
754 | XTENSA_REGISTER_FLAGS_WRITABLE \
755 | XTENSA_REGISTER_FLAGS_VOLATILE)
757 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
758 | XTENSA_REGISTER_FLAGS_WRITABLE)
761 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
763 struct reggroup *group)
765 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
766 xtensa_register_type_t type = reg->type;
767 xtensa_register_group_t rg = reg->group;
770 /* First, skip registers that are not visible to this target
771 (unknown and unmapped registers when not using ISS). */
773 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
775 if (group == all_reggroup)
777 if (group == xtensa_ar_reggroup)
778 return rg & xtRegisterGroupAddrReg;
779 if (group == xtensa_user_reggroup)
780 return rg & xtRegisterGroupUser;
781 if (group == float_reggroup)
782 return rg & xtRegisterGroupFloat;
783 if (group == general_reggroup)
784 return rg & xtRegisterGroupGeneral;
785 if (group == float_reggroup)
786 return rg & xtRegisterGroupFloat;
787 if (group == system_reggroup)
788 return rg & xtRegisterGroupState;
789 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
790 return rg & xtRegisterGroupVectra;
791 if (group == save_reggroup || group == restore_reggroup)
792 return (regnum < gdbarch_num_regs (gdbarch)
793 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
794 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
795 return rg & (xtRegisterGroupCP0 << cp_number);
801 /* Supply register REGNUM from the buffer specified by GREGS and LEN
802 in the general-purpose register set REGSET to register cache
803 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
806 xtensa_supply_gregset (const struct regset *regset,
812 const xtensa_elf_gregset_t *regs = gregs;
813 struct gdbarch *gdbarch = get_regcache_arch (rc);
816 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
818 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
819 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
820 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
821 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
822 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
823 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
824 (char *) ®s->windowbase);
825 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
826 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
827 (char *) ®s->windowstart);
828 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
829 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
830 (char *) ®s->lbeg);
831 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
832 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
833 (char *) ®s->lend);
834 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
835 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
836 (char *) ®s->lcount);
837 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
838 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
839 (char *) ®s->sar);
840 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
841 && regnum < gdbarch_tdep (gdbarch)->ar_base
842 + gdbarch_tdep (gdbarch)->num_aregs)
843 regcache_raw_supply (rc, regnum,
844 (char *) ®s->ar[regnum - gdbarch_tdep
845 (gdbarch)->ar_base]);
846 else if (regnum == -1)
848 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
849 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
850 (char *) ®s->ar[i]);
855 /* Xtensa register set. */
861 xtensa_supply_gregset
865 /* Return the appropriate register set for the core
866 section identified by SECT_NAME and SECT_SIZE. */
868 static const struct regset *
869 xtensa_regset_from_core_section (struct gdbarch *core_arch,
870 const char *sect_name,
873 DEBUGTRACE ("xtensa_regset_from_core_section "
874 "(..., sect_name==\"%s\", sect_size==%x) \n",
875 sect_name, (unsigned int) sect_size);
877 if (strcmp (sect_name, ".reg") == 0
878 && sect_size >= sizeof(xtensa_elf_gregset_t))
879 return &xtensa_gregset;
885 /* Handling frames. */
887 /* Number of registers to save in case of Windowed ABI. */
888 #define XTENSA_NUM_SAVED_AREGS 12
890 /* Frame cache part for Windowed ABI. */
891 typedef struct xtensa_windowed_frame_cache
893 int wb; /* WINDOWBASE of the previous frame. */
894 int callsize; /* Call size of this frame. */
895 int ws; /* WINDOWSTART of the previous frame. It keeps track of
896 life windows only. If there is no bit set for the
897 window, that means it had been already spilled
898 because of window overflow. */
900 /* Spilled A-registers from the previous frame.
901 AREGS[i] == -1, if corresponding AR is alive. */
902 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
903 } xtensa_windowed_frame_cache_t;
905 /* Call0 ABI Definitions. */
907 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
908 #define C0_NREGS 16 /* Number of A-registers to track. */
909 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
910 #define C0_SP 1 /* Register used as SP. */
911 #define C0_FP 15 /* Register used as FP. */
912 #define C0_RA 0 /* Register used as return address. */
913 #define C0_ARGS 2 /* Register used as first arg/retval. */
914 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
916 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
917 A-register where the current content of the reg came from (in terms
918 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
919 mean that the orignal content of the register was saved to the stack.
920 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
921 know where SP will end up until the entire prologue has been analyzed. */
923 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
924 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
925 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
927 extern xtensa_isa xtensa_default_isa;
929 typedef struct xtensa_c0reg
931 int fr_reg; /* original register from which register content
932 is derived, or C0_CONST, or C0_INEXP. */
933 int fr_ofs; /* constant offset from reg, or immediate value. */
934 int to_stk; /* offset from original SP to register (4-byte aligned),
935 or C0_NOSTK if register has not been saved. */
939 /* Frame cache part for Call0 ABI. */
940 typedef struct xtensa_call0_frame_cache
942 int c0_frmsz; /* Stack frame size. */
943 int c0_hasfp; /* Current frame uses frame pointer. */
944 int fp_regnum; /* A-register used as FP. */
945 int c0_fp; /* Actual value of frame pointer. */
946 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
947 } xtensa_call0_frame_cache_t;
949 typedef struct xtensa_frame_cache
951 CORE_ADDR base; /* Stack pointer of this frame. */
952 CORE_ADDR pc; /* PC at the entry point to the function. */
953 CORE_ADDR ra; /* The raw return address (without CALLINC). */
954 CORE_ADDR ps; /* The PS register of this frame. */
955 CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
956 int call0; /* It's a call0 framework (else windowed). */
959 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
960 xtensa_call0_frame_cache_t c0; /* call0 == true. */
962 } xtensa_frame_cache_t;
965 static struct xtensa_frame_cache *
966 xtensa_alloc_frame_cache (int windowed)
968 xtensa_frame_cache_t *cache;
971 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
973 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
980 cache->call0 = !windowed;
983 cache->c0.c0_frmsz = -1;
984 cache->c0.c0_hasfp = 0;
985 cache->c0.fp_regnum = -1;
986 cache->c0.c0_fp = -1;
988 for (i = 0; i < C0_NREGS; i++)
990 cache->c0.c0_rt[i].fr_reg = i;
991 cache->c0.c0_rt[i].fr_ofs = 0;
992 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
999 cache->wd.callsize = -1;
1001 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1002 cache->wd.aregs[i] = -1;
1009 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1011 return address & ~15;
1016 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1021 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
1023 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1024 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1026 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1032 static struct frame_id
1033 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1037 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1039 pc = get_frame_pc (this_frame);
1040 fp = get_frame_register_unsigned
1041 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1043 /* Make dummy frame ID unique by adding a constant. */
1044 return frame_id_build (fp + SP_ALIGNMENT, pc);
1047 /* Returns the best guess about which register is a frame pointer
1048 for the function containing CURRENT_PC. */
1050 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1053 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1055 #define RETURN_FP goto done
1057 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1058 CORE_ADDR start_addr;
1060 xtensa_insnbuf ins, slot;
1061 char ibuf[XTENSA_ISA_BSZ];
1062 CORE_ADDR ia, bt, ba;
1064 int ilen, islots, is;
1066 const char *opcname;
1068 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1069 if (start_addr == 0)
1072 if (!xtensa_default_isa)
1073 xtensa_default_isa = xtensa_isa_init (0, 0);
1074 isa = xtensa_default_isa;
1075 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1076 ins = xtensa_insnbuf_alloc (isa);
1077 slot = xtensa_insnbuf_alloc (isa);
1080 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1082 if (ia + xtensa_isa_maxlength (isa) > bt)
1085 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1086 ? ba + XTENSA_ISA_BSZ : current_pc;
1087 read_memory (ba, ibuf, bt - ba);
1090 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1091 ifmt = xtensa_format_decode (isa, ins);
1092 if (ifmt == XTENSA_UNDEFINED)
1094 ilen = xtensa_format_length (isa, ifmt);
1095 if (ilen == XTENSA_UNDEFINED)
1097 islots = xtensa_format_num_slots (isa, ifmt);
1098 if (islots == XTENSA_UNDEFINED)
1101 for (is = 0; is < islots; ++is)
1103 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1106 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1107 if (opc == XTENSA_UNDEFINED)
1110 opcname = xtensa_opcode_name (isa, opc);
1112 if (strcasecmp (opcname, "mov.n") == 0
1113 || strcasecmp (opcname, "or") == 0)
1115 unsigned int register_operand;
1117 /* Possible candidate for setting frame pointer
1118 from A1. This is what we are looking for. */
1120 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1121 is, slot, ®ister_operand) != 0)
1123 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1125 if (register_operand == 1) /* Mov{.n} FP A1. */
1127 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1128 ®ister_operand) != 0)
1130 if (xtensa_operand_decode (isa, opc, 0,
1131 ®ister_operand) != 0)
1134 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1140 /* We have problems decoding the memory. */
1142 || strcasecmp (opcname, "ill") == 0
1143 || strcasecmp (opcname, "ill.n") == 0
1144 /* Hit planted breakpoint. */
1145 || strcasecmp (opcname, "break") == 0
1146 || strcasecmp (opcname, "break.n") == 0
1147 /* Flow control instructions finish prologue. */
1148 || xtensa_opcode_is_branch (isa, opc) > 0
1149 || xtensa_opcode_is_jump (isa, opc) > 0
1150 || xtensa_opcode_is_loop (isa, opc) > 0
1151 || xtensa_opcode_is_call (isa, opc) > 0
1152 || strcasecmp (opcname, "simcall") == 0
1153 || strcasecmp (opcname, "syscall") == 0)
1154 /* Can not continue analysis. */
1159 xtensa_insnbuf_free(isa, slot);
1160 xtensa_insnbuf_free(isa, ins);
1164 /* The key values to identify the frame using "cache" are
1166 cache->base = SP (or best guess about FP) of this frame;
1167 cache->pc = entry-PC (entry point of the frame function);
1168 cache->prev_sp = SP of the previous frame.
1172 call0_frame_cache (struct frame_info *this_frame,
1173 xtensa_frame_cache_t *cache,
1174 CORE_ADDR pc, CORE_ADDR litbase);
1176 static struct xtensa_frame_cache *
1177 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1179 xtensa_frame_cache_t *cache;
1180 CORE_ADDR ra, wb, ws, pc, sp, ps;
1181 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1182 unsigned int fp_regnum;
1189 ps = get_frame_register_unsigned (this_frame, gdbarch_ps_regnum (gdbarch));
1190 windowed = windowing_enabled (ps);
1192 /* Get pristine xtensa-frame. */
1193 cache = xtensa_alloc_frame_cache (windowed);
1194 *this_cache = cache;
1196 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1200 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1201 wb = get_frame_register_unsigned (this_frame,
1202 gdbarch_tdep (gdbarch)->wb_regnum);
1203 ws = get_frame_register_unsigned (this_frame,
1204 gdbarch_tdep (gdbarch)->ws_regnum);
1206 op1 = read_memory_integer (pc, 1);
1207 if (XTENSA_IS_ENTRY (gdbarch, op1))
1209 int callinc = CALLINC (ps);
1210 ra = get_frame_register_unsigned
1211 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1213 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1214 cache->wd.callsize = 0;
1217 cache->prev_sp = get_frame_register_unsigned
1218 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1220 /* This only can be the outermost frame since we are
1221 just about to execute ENTRY. SP hasn't been set yet.
1222 We can assume any frame size, because it does not
1223 matter, and, let's fake frame base in cache. */
1224 cache->base = cache->prev_sp + 16;
1227 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1228 cache->ps = (ps & ~PS_CALLINC_MASK)
1229 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1235 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1236 ra = get_frame_register_unsigned (this_frame,
1237 gdbarch_tdep (gdbarch)->a0_base);
1238 cache->wd.callsize = WINSIZE (ra);
1239 cache->wd.wb = (wb - cache->wd.callsize / 4)
1240 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1241 cache->wd.ws = ws & ~(1 << wb);
1243 cache->pc = get_frame_func (this_frame);
1244 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1245 cache->ps = (ps & ~PS_CALLINC_MASK)
1246 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1249 if (cache->wd.ws == 0)
1254 sp = get_frame_register_unsigned
1255 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1257 for (i = 0; i < 4; i++, sp += 4)
1259 cache->wd.aregs[i] = sp;
1262 if (cache->wd.callsize > 4)
1264 /* Set A4...A7/A11. */
1265 /* Get the SP of the frame previous to the previous one.
1266 To achieve this, we have to dereference SP twice. */
1267 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1268 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
1269 sp -= cache->wd.callsize * 4;
1271 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1273 cache->wd.aregs[i] = sp;
1278 if ((cache->prev_sp == 0) && ( ra != 0 ))
1279 /* If RA is equal to 0 this frame is an outermost frame. Leave
1280 cache->prev_sp unchanged marking the boundary of the frame stack. */
1282 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1284 /* Register window overflow already happened.
1285 We can read caller's SP from the proper spill loction. */
1286 sp = get_frame_register_unsigned
1287 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1288 cache->prev_sp = read_memory_integer (sp - 12, 4);
1292 /* Read caller's frame SP directly from the previous window. */
1293 int regnum = arreg_number
1294 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1297 cache->prev_sp = get_frame_register_unsigned (this_frame, regnum);
1301 else /* Call0 framework. */
1303 unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
1304 CORE_ADDR litbase = (litbase_regnum == -1)
1305 ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
1307 call0_frame_cache (this_frame, cache, pc, litbase);
1308 fp_regnum = cache->c0.fp_regnum;
1311 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1317 xtensa_frame_this_id (struct frame_info *this_frame,
1319 struct frame_id *this_id)
1321 struct xtensa_frame_cache *cache =
1322 xtensa_frame_cache (this_frame, this_cache);
1324 if (cache->prev_sp == 0)
1327 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1330 static struct value *
1331 xtensa_frame_prev_register (struct frame_info *this_frame,
1335 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1336 struct xtensa_frame_cache *cache;
1337 ULONGEST saved_reg = 0;
1340 if (*this_cache == NULL)
1341 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1342 cache = *this_cache;
1344 if (regnum ==gdbarch_pc_regnum (gdbarch))
1345 saved_reg = cache->ra;
1346 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1347 saved_reg = cache->prev_sp;
1348 else if (!cache->call0)
1350 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1351 saved_reg = cache->wd.ws;
1352 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1353 saved_reg = cache->wd.wb;
1354 else if (regnum == gdbarch_ps_regnum (gdbarch))
1355 saved_reg = cache->ps;
1363 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1365 if (!cache->call0) /* Windowed ABI. */
1367 /* Convert A-register numbers to AR-register numbers,
1368 if we deal with A-register. */
1369 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1370 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1371 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1373 /* Check, if we deal with AR-register saved on stack. */
1374 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1375 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1376 + gdbarch_tdep (gdbarch)->num_aregs))
1378 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1381 && areg < XTENSA_NUM_SAVED_AREGS
1382 && cache->wd.aregs[areg] != -1)
1383 return frame_unwind_got_memory (this_frame, regnum,
1384 cache->wd.aregs[areg]);
1387 else /* Call0 ABI. */
1389 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1390 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1392 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1399 /* If register was saved in the prologue, retrieve it. */
1400 stkofs = cache->c0.c0_rt[reg].to_stk;
1401 if (stkofs != C0_NOSTK)
1403 /* Determine SP on entry based on FP. */
1404 spe = cache->c0.c0_fp
1405 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1407 return frame_unwind_got_memory (this_frame, regnum, spe + stkofs);
1412 /* All other registers have been either saved to
1413 the stack or are still alive in the processor. */
1415 return frame_unwind_got_register (this_frame, regnum, regnum);
1419 static const struct frame_unwind
1423 xtensa_frame_this_id,
1424 xtensa_frame_prev_register,
1426 default_frame_sniffer
1430 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1432 struct xtensa_frame_cache *cache =
1433 xtensa_frame_cache (this_frame, this_cache);
1438 static const struct frame_base
1442 xtensa_frame_base_address,
1443 xtensa_frame_base_address,
1444 xtensa_frame_base_address
1449 xtensa_extract_return_value (struct type *type,
1450 struct regcache *regcache,
1453 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1454 bfd_byte *valbuf = dst;
1455 int len = TYPE_LENGTH (type);
1460 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1462 gdb_assert(len > 0);
1464 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1466 /* First, we have to find the caller window in the register file. */
1467 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1468 callsize = extract_call_winsize (gdbarch, pc);
1470 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1471 if (len > (callsize > 8 ? 8 : 16))
1472 internal_error (__FILE__, __LINE__,
1473 _("cannot extract return value of %d bytes long"), len);
1475 /* Get the register offset of the return
1476 register (A2) in the caller window. */
1477 regcache_raw_read_unsigned
1478 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1479 areg = arreg_number (gdbarch,
1480 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1484 /* No windowing hardware - Call0 ABI. */
1485 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1488 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1490 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1493 for (; len > 0; len -= 4, areg++, valbuf += 4)
1496 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1498 regcache_raw_read (regcache, areg, valbuf);
1504 xtensa_store_return_value (struct type *type,
1505 struct regcache *regcache,
1508 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1509 const bfd_byte *valbuf = dst;
1513 int len = TYPE_LENGTH (type);
1516 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1518 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1520 regcache_raw_read_unsigned
1521 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1522 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1523 callsize = extract_call_winsize (gdbarch, pc);
1525 if (len > (callsize > 8 ? 8 : 16))
1526 internal_error (__FILE__, __LINE__,
1527 _("unimplemented for this length: %d"),
1528 TYPE_LENGTH (type));
1529 areg = arreg_number (gdbarch,
1530 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1532 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1533 callsize, (int) wb);
1537 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1540 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1543 for (; len > 0; len -= 4, areg++, valbuf += 4)
1546 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1548 regcache_raw_write (regcache, areg, valbuf);
1553 static enum return_value_convention
1554 xtensa_return_value (struct gdbarch *gdbarch,
1555 struct type *func_type,
1556 struct type *valtype,
1557 struct regcache *regcache,
1559 const gdb_byte *writebuf)
1561 /* Structures up to 16 bytes are returned in registers. */
1563 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1564 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1565 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1566 && TYPE_LENGTH (valtype) > 16);
1569 return RETURN_VALUE_STRUCT_CONVENTION;
1571 DEBUGTRACE ("xtensa_return_value(...)\n");
1573 if (writebuf != NULL)
1575 xtensa_store_return_value (valtype, regcache, writebuf);
1578 if (readbuf != NULL)
1580 gdb_assert (!struct_return);
1581 xtensa_extract_return_value (valtype, regcache, readbuf);
1583 return RETURN_VALUE_REGISTER_CONVENTION;
1590 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1591 struct value *function,
1592 struct regcache *regcache,
1595 struct value **args,
1598 CORE_ADDR struct_addr)
1601 int size, onstack_size;
1602 gdb_byte *buf = (gdb_byte *) alloca (16);
1604 struct argument_info
1606 const bfd_byte *contents;
1608 int onstack; /* onstack == 0 => in reg */
1609 int align; /* alignment */
1612 int offset; /* stack offset if on stack */
1613 int regno; /* regno if in register */
1617 struct argument_info *arg_info =
1618 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1622 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1624 if (xtensa_debug_level > 3)
1627 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1628 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1629 "struct_addr=0x%x\n",
1630 (int) sp, (int) struct_return, (int) struct_addr);
1632 for (i = 0; i < nargs; i++)
1634 struct value *arg = args[i];
1635 struct type *arg_type = check_typedef (value_type (arg));
1636 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
1637 i, (unsigned long) arg, TYPE_LENGTH (arg_type));
1638 switch (TYPE_CODE (arg_type))
1641 fprintf_unfiltered (gdb_stdlog, "int");
1643 case TYPE_CODE_STRUCT:
1644 fprintf_unfiltered (gdb_stdlog, "struct");
1647 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1650 fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
1651 (unsigned long) value_contents (arg));
1655 /* First loop: collect information.
1656 Cast into type_long. (This shouldn't happen often for C because
1657 GDB already does this earlier.) It's possible that GDB could
1658 do it all the time but it's harmless to leave this code here. */
1665 size = REGISTER_SIZE;
1667 for (i = 0; i < nargs; i++)
1669 struct argument_info *info = &arg_info[i];
1670 struct value *arg = args[i];
1671 struct type *arg_type = check_typedef (value_type (arg));
1673 switch (TYPE_CODE (arg_type))
1676 case TYPE_CODE_BOOL:
1677 case TYPE_CODE_CHAR:
1678 case TYPE_CODE_RANGE:
1679 case TYPE_CODE_ENUM:
1681 /* Cast argument to long if necessary as the mask does it too. */
1682 if (TYPE_LENGTH (arg_type)
1683 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1685 arg_type = builtin_type (gdbarch)->builtin_long;
1686 arg = value_cast (arg_type, arg);
1688 /* Aligment is equal to the type length for the basic types. */
1689 info->align = TYPE_LENGTH (arg_type);
1694 /* Align doubles correctly. */
1695 if (TYPE_LENGTH (arg_type)
1696 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1697 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1699 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1702 case TYPE_CODE_STRUCT:
1704 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1707 info->length = TYPE_LENGTH (arg_type);
1708 info->contents = value_contents (arg);
1710 /* Align size and onstack_size. */
1711 size = (size + info->align - 1) & ~(info->align - 1);
1712 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1714 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1717 info->u.offset = onstack_size;
1718 onstack_size += info->length;
1723 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1725 size += info->length;
1728 /* Adjust the stack pointer and align it. */
1729 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1731 /* Simulate MOVSP, if Windowed ABI. */
1732 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1735 read_memory (osp - 16, buf, 16);
1736 write_memory (sp - 16, buf, 16);
1739 /* Second Loop: Load arguments. */
1743 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
1744 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1747 for (i = 0; i < nargs; i++)
1749 struct argument_info *info = &arg_info[i];
1753 int n = info->length;
1754 CORE_ADDR offset = sp + info->u.offset;
1756 /* Odd-sized structs are aligned to the lower side of a memory
1757 word in big-endian mode and require a shift. This only
1758 applies for structures smaller than one word. */
1760 if (n < REGISTER_SIZE
1761 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1762 offset += (REGISTER_SIZE - n);
1764 write_memory (offset, info->contents, info->length);
1769 int n = info->length;
1770 const bfd_byte *cp = info->contents;
1771 int r = info->u.regno;
1773 /* Odd-sized structs are aligned to the lower side of registers in
1774 big-endian mode and require a shift. The odd-sized leftover will
1775 be at the end. Note that this is only true for structures smaller
1776 than REGISTER_SIZE; for larger odd-sized structures the excess
1777 will be left-aligned in the register on both endiannesses. */
1779 if (n < REGISTER_SIZE
1780 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1782 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1783 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1785 store_unsigned_integer (buf, REGISTER_SIZE, v);
1786 regcache_cooked_write (regcache, r, buf);
1788 cp += REGISTER_SIZE;
1795 regcache_cooked_write (regcache, r, cp);
1797 cp += REGISTER_SIZE;
1804 /* Set the return address of dummy frame to the dummy address.
1805 The return address for the current function (in A0) is
1806 saved in the dummy frame, so we can savely overwrite A0 here. */
1808 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1810 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1811 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
1812 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
1813 regcache_cooked_write_unsigned
1814 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1815 regcache_cooked_write_unsigned (regcache,
1816 gdbarch_ps_regnum (gdbarch),
1819 /* All the registers have been saved. After executing
1820 dummy call, they all will be restored. So it's safe
1821 to modify WINDOWSTART register to make it look like there
1822 is only one register window corresponding to WINDOWEBASE. */
1824 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1825 regcache_cooked_write_unsigned (regcache,
1826 gdbarch_tdep (gdbarch)->ws_regnum,
1827 1 << extract_unsigned_integer (buf, 4));
1831 /* Simulate CALL0: write RA into A0 register. */
1832 regcache_cooked_write_unsigned
1833 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1836 /* Set new stack pointer and return it. */
1837 regcache_cooked_write_unsigned (regcache,
1838 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1839 /* Make dummy frame ID unique by adding a constant. */
1840 return sp + SP_ALIGNMENT;
1844 /* Return a breakpoint for the current location of PC. We always use
1845 the density version if we have density instructions (regardless of the
1846 current instruction at PC), and use regular instructions otherwise. */
1848 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1849 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1850 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1851 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1853 static const unsigned char *
1854 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1857 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1858 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1859 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1860 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1862 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1864 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1866 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1868 *lenptr = sizeof (density_big_breakpoint);
1869 return density_big_breakpoint;
1873 *lenptr = sizeof (density_little_breakpoint);
1874 return density_little_breakpoint;
1879 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1881 *lenptr = sizeof (big_breakpoint);
1882 return big_breakpoint;
1886 *lenptr = sizeof (little_breakpoint);
1887 return little_breakpoint;
1892 /* Call0 ABI support routines. */
1894 /* Call0 opcode class. Opcodes are preclassified according to what they
1895 mean for Call0 prologue analysis, and their number of significant operands.
1896 The purpose of this is to simplify prologue analysis by separating
1897 instruction decoding (libisa) from the semantics of prologue analysis. */
1900 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1901 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1902 c0opc_flow, /* Flow control insn. */
1903 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1904 c0opc_break, /* Debugger software breakpoints. */
1905 c0opc_add, /* Adding two registers. */
1906 c0opc_addi, /* Adding a register and an immediate. */
1907 c0opc_sub, /* Subtracting a register from a register. */
1908 c0opc_mov, /* Moving a register to a register. */
1909 c0opc_movi, /* Moving an immediate to a register. */
1910 c0opc_l32r, /* Loading a literal. */
1911 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1912 c0opc_NrOf /* Number of opcode classifications. */
1916 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1918 static xtensa_insn_kind
1919 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1921 const char *opcname;
1922 xtensa_insn_kind opclass = c0opc_uninteresting;
1924 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1926 /* Get opcode name and handle special classifications. */
1928 opcname = xtensa_opcode_name (isa, opc);
1931 || strcasecmp (opcname, "ill") == 0
1932 || strcasecmp (opcname, "ill.n") == 0)
1933 opclass = c0opc_illegal;
1934 else if (strcasecmp (opcname, "break") == 0
1935 || strcasecmp (opcname, "break.n") == 0)
1936 opclass = c0opc_break;
1937 else if (strcasecmp (opcname, "entry") == 0)
1938 opclass = c0opc_entry;
1939 else if (xtensa_opcode_is_branch (isa, opc) > 0
1940 || xtensa_opcode_is_jump (isa, opc) > 0
1941 || xtensa_opcode_is_loop (isa, opc) > 0
1942 || xtensa_opcode_is_call (isa, opc) > 0
1943 || strcasecmp (opcname, "simcall") == 0
1944 || strcasecmp (opcname, "syscall") == 0)
1945 opclass = c0opc_flow;
1947 /* Also, classify specific opcodes that need to be tracked. */
1948 else if (strcasecmp (opcname, "add") == 0
1949 || strcasecmp (opcname, "add.n") == 0)
1950 opclass = c0opc_add;
1951 else if (strcasecmp (opcname, "addi") == 0
1952 || strcasecmp (opcname, "addi.n") == 0
1953 || strcasecmp (opcname, "addmi") == 0)
1954 opclass = c0opc_addi;
1955 else if (strcasecmp (opcname, "sub") == 0)
1956 opclass = c0opc_sub;
1957 else if (strcasecmp (opcname, "mov.n") == 0
1958 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1959 opclass = c0opc_mov;
1960 else if (strcasecmp (opcname, "movi") == 0
1961 || strcasecmp (opcname, "movi.n") == 0)
1962 opclass = c0opc_movi;
1963 else if (strcasecmp (opcname, "l32r") == 0)
1964 opclass = c0opc_l32r;
1965 else if (strcasecmp (opcname, "s32i") == 0
1966 || strcasecmp (opcname, "s32i.n") == 0)
1967 opclass = c0opc_s32i;
1972 /* Tracks register movement/mutation for a given operation, which may
1973 be within a bundle. Updates the destination register tracking info
1974 accordingly. The pc is needed only for pc-relative load instructions
1975 (eg. l32r). The SP register number is needed to identify stores to
1979 call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1980 xtensa_insn_kind opclass, int nods, unsigned odv[],
1981 CORE_ADDR pc, CORE_ADDR litbase, int spreg)
1983 unsigned litaddr, litval;
1988 /* 3 operands: dst, src, imm. */
1989 gdb_assert (nods == 3);
1990 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1991 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1994 /* 3 operands: dst, src1, src2. */
1995 gdb_assert (nods == 3);
1996 if (src[odv[1]].fr_reg == C0_CONST)
1998 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
1999 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2001 else if (src[odv[2]].fr_reg == C0_CONST)
2003 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2004 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2006 else dst[odv[0]].fr_reg = C0_INEXP;
2009 /* 3 operands: dst, src1, src2. */
2010 gdb_assert (nods == 3);
2011 if (src[odv[2]].fr_reg == C0_CONST)
2013 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2014 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2016 else dst[odv[0]].fr_reg = C0_INEXP;
2019 /* 2 operands: dst, src [, src]. */
2020 gdb_assert (nods == 2);
2021 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2022 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2025 /* 2 operands: dst, imm. */
2026 gdb_assert (nods == 2);
2027 dst[odv[0]].fr_reg = C0_CONST;
2028 dst[odv[0]].fr_ofs = odv[1];
2031 /* 2 operands: dst, literal offset. */
2032 gdb_assert (nods == 2);
2033 litaddr = litbase & 1
2034 ? (litbase & ~1) + (signed)odv[1]
2035 : (pc + 3 + (signed)odv[1]) & ~3;
2036 litval = read_memory_integer(litaddr, 4);
2037 dst[odv[0]].fr_reg = C0_CONST;
2038 dst[odv[0]].fr_ofs = litval;
2041 /* 3 operands: value, base, offset. */
2042 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2043 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2044 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2045 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2046 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2047 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2049 /* ISA encoding guarantees alignment. But, check it anyway. */
2050 gdb_assert ((odv[2] & 3) == 0);
2051 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2059 /* Analyze prologue of the function at start address to determine if it uses
2060 the Call0 ABI, and if so track register moves and linear modifications
2061 in the prologue up to the PC or just beyond the prologue, whichever is first.
2062 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2063 The prologue may overlap non-prologue instructions but is guaranteed to end
2064 by the first flow-control instruction (jump, branch, call or return).
2065 Since an optimized function may move information around and change the
2066 stack frame arbitrarily during the prologue, the information is guaranteed
2067 valid only at the point in the function indicated by the PC.
2068 May be used to skip the prologue or identify the ABI, w/o tracking.
2070 Returns: Address of first instruction after prologue, or PC (whichever
2071 is first), or 0, if decoding failed (in libisa).
2073 start Start address of function/prologue.
2074 pc Program counter to stop at. Use 0 to continue to end of prologue.
2075 If 0, avoids infinite run-on in corrupt code memory by bounding
2076 the scan to the end of the function if that can be determined.
2077 nregs Number of general registers to track (size of rt[] array).
2079 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2080 If NULL, registers are not tracked.
2082 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2083 (more accurately, non-zero until 'entry' insn is encountered).
2085 Note that these may produce useful results even if decoding fails
2086 because they begin with default assumptions that analysis may change. */
2089 call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
2090 int nregs, xtensa_c0reg_t rt[], int *call0)
2092 CORE_ADDR ia; /* Current insn address in prologue. */
2093 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2094 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2095 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2096 xtensa_isa isa; /* libisa ISA handle. */
2097 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2098 xtensa_format ifmt; /* libisa instruction format. */
2099 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2100 xtensa_opcode opc; /* Opcode in current slot. */
2101 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2102 int nods; /* Opcode number of operands. */
2103 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2104 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2105 int j; /* General loop counter. */
2106 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2107 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2108 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2110 struct symtab_and_line prologue_sal;
2112 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2113 (int)start, (int)pc);
2115 /* Try to limit the scan to the end of the function if a non-zero pc
2116 arg was not supplied to avoid probing beyond the end of valid memory.
2117 If memory is full of garbage that classifies as c0opc_uninteresting.
2118 If this fails (eg. if no symbols) pc ends up 0 as it was.
2119 Intialize the Call0 frame and register tracking info.
2120 Assume it's Call0 until an 'entry' instruction is encountered.
2121 Assume we may be in the prologue until we hit a flow control instr. */
2127 /* Find out, if we have an information about the prologue from DWARF. */
2128 prologue_sal = find_pc_line (start, 0);
2129 if (prologue_sal.line != 0) /* Found debug info. */
2130 body_pc = prologue_sal.end;
2132 /* If we are going to analyze the prologue in general without knowing about
2133 the current PC, make the best assumtion for the end of the prologue. */
2136 find_pc_partial_function (start, 0, NULL, &end_pc);
2137 body_pc = min (end_pc, body_pc);
2140 body_pc = min (pc, body_pc);
2147 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2148 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2152 if (!xtensa_default_isa)
2153 xtensa_default_isa = xtensa_isa_init (0, 0);
2154 isa = xtensa_default_isa;
2155 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2156 ins = xtensa_insnbuf_alloc (isa);
2157 slot = xtensa_insnbuf_alloc (isa);
2159 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2161 /* (Re)fill instruction buffer from memory if necessary, but do not
2162 read memory beyond PC to be sure we stay within text section
2163 (this protection only works if a non-zero pc is supplied). */
2165 if (ia + xtensa_isa_maxlength (isa) > bt)
2168 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2169 read_memory (ba, ibuf, bt - ba);
2172 /* Decode format information. */
2174 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2175 ifmt = xtensa_format_decode (isa, ins);
2176 if (ifmt == XTENSA_UNDEFINED)
2181 ilen = xtensa_format_length (isa, ifmt);
2182 if (ilen == XTENSA_UNDEFINED)
2187 islots = xtensa_format_num_slots (isa, ifmt);
2188 if (islots == XTENSA_UNDEFINED)
2194 /* Analyze a bundle or a single instruction, using a snapshot of
2195 the register tracking info as input for the entire bundle so that
2196 register changes do not take effect within this bundle. */
2198 for (j = 0; j < nregs; ++j)
2201 for (is = 0; is < islots; ++is)
2203 /* Decode a slot and classify the opcode. */
2205 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2209 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2210 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2212 if (opc == XTENSA_UNDEFINED)
2213 opclass = c0opc_illegal;
2215 opclass = call0_classify_opcode (isa, opc);
2217 /* Decide whether to track this opcode, ignore it, or bail out. */
2226 case c0opc_uninteresting:
2235 ia += ilen; /* Skip over 'entry' insn. */
2243 /* Only expected opcodes should get this far. */
2247 /* Extract and decode the operands. */
2248 nods = xtensa_opcode_num_operands (isa, opc);
2249 if (nods == XTENSA_UNDEFINED)
2255 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2257 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2262 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2267 /* Check operands to verify use of 'mov' assembler macro. */
2268 if (opclass == c0opc_mov && nods == 3)
2270 if (odv[2] == odv[1])
2274 opclass = c0opc_uninteresting;
2279 /* Track register movement and modification for this operation. */
2280 call0_track_op (rt, rtmp, opclass, nods, odv, ia, litbase, 1);
2284 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2285 (unsigned)ia, fail ? "failed" : "succeeded");
2286 xtensa_insnbuf_free(isa, slot);
2287 xtensa_insnbuf_free(isa, ins);
2288 return fail ? 0 : ia;
2291 /* Initialize frame cache for the current frame in CALL0 ABI. */
2294 call0_frame_cache (struct frame_info *this_frame,
2295 xtensa_frame_cache_t *cache, CORE_ADDR pc, CORE_ADDR litbase)
2297 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2298 CORE_ADDR start_pc; /* The beginning of the function. */
2299 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2300 CORE_ADDR sp, fp, ra;
2301 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2303 /* Find the beginning of the prologue of the function containing the PC
2304 and analyze it up to the PC or the end of the prologue. */
2306 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2308 body_pc = call0_analyze_prologue (start_pc, pc, litbase, C0_NREGS,
2309 &cache->c0.c0_rt[0],
2313 sp = get_frame_register_unsigned
2314 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2315 fp = sp; /* Assume FP == SP until proven otherwise. */
2317 /* Get the frame information and FP (if used) at the current PC.
2318 If PC is in the prologue, the prologue analysis is more reliable
2319 than DWARF info. We don't not know for sure if PC is in the prologue,
2320 but we know no calls have yet taken place, so we can almost
2321 certainly rely on the prologue analysis. */
2325 /* Prologue analysis was successful up to the PC.
2326 It includes the cases when PC == START_PC. */
2327 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2328 /* c0_hasfp == true means there is a frame pointer because
2329 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2330 was derived from SP. Otherwise, it would be C0_FP. */
2331 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2332 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2333 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2335 else /* No data from the prologue analysis. */
2338 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2343 prev_sp = fp + c0_frmsz;
2345 /* Frame size from debug info or prologue tracking does not account for
2346 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2349 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2351 /* Recalculate previous SP. */
2352 prev_sp = fp + c0_frmsz;
2353 /* Update the stack frame size. */
2354 c0_frmsz += fp - sp;
2357 /* Get the return address (RA) from the stack if saved,
2358 or try to get it from a register. */
2360 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2361 if (to_stk != C0_NOSTK)
2363 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2365 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2366 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2368 /* Special case for terminating backtrace at a function that wants to
2369 be seen as the outermost. Such a function will clear it's RA (A0)
2370 register to 0 in the prologue instead of saving its original value. */
2375 /* RA was copied to another register or (before any function call) may
2376 still be in the original RA register. This is not always reliable:
2377 even in a leaf function, register tracking stops after prologue, and
2378 even in prologue, non-prologue instructions (not tracked) may overwrite
2379 RA or any register it was copied to. If likely in prologue or before
2380 any call, use retracking info and hope for the best (compiler should
2381 have saved RA in stack if not in a leaf function). If not in prologue,
2387 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2389 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2393 ra = get_frame_register_unsigned
2395 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2400 cache->pc = start_pc;
2402 /* RA == 0 marks the outermost frame. Do not go past it. */
2403 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2404 cache->c0.fp_regnum = fp_regnum;
2405 cache->c0.c0_frmsz = c0_frmsz;
2406 cache->c0.c0_hasfp = c0_hasfp;
2407 cache->c0.c0_fp = fp;
2411 /* Skip function prologue.
2413 Return the pc of the first instruction after prologue. GDB calls this to
2414 find the address of the first line of the function or (if there is no line
2415 number information) to skip the prologue for planting breakpoints on
2416 function entries. Use debug info (if present) or prologue analysis to skip
2417 the prologue to achieve reliable debugging behavior. For windowed ABI,
2418 only the 'entry' instruction is skipped. It is not strictly necessary to
2419 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2420 backtrace at any point in the prologue, however certain potential hazards
2421 are avoided and a more "normal" debugging experience is ensured by
2422 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2423 For example, if we don't skip the prologue:
2424 - Some args may not yet have been saved to the stack where the debug
2425 info expects to find them (true anyway when only 'entry' is skipped);
2426 - Software breakpoints ('break' instrs) may not have been unplanted
2427 when the prologue analysis is done on initializing the frame cache,
2428 and breaks in the prologue will throw off the analysis.
2430 If we have debug info ( line-number info, in particular ) we simply skip
2431 the code associated with the first function line effectively skipping
2432 the prologue code. It works even in cases like
2435 { int local_var = 1;
2439 because, for this source code, both Xtensa compilers will generate two
2440 separate entries ( with the same line number ) in dwarf line-number
2441 section to make sure there is a boundary between the prologue code and
2442 the rest of the function.
2444 If there is no debug info, we need to analyze the code. */
2446 /* #define DONT_SKIP_PROLOGUE */
2449 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2451 struct symtab_and_line prologue_sal;
2454 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2456 #if DONT_SKIP_PROLOGUE
2460 /* Try to find first body line from debug info. */
2462 prologue_sal = find_pc_line (start_pc, 0);
2463 if (prologue_sal.line != 0) /* Found debug info. */
2465 /* In Call0, it is possible to have a function with only one instruction
2466 ('ret') resulting from a 1-line optimized function that does nothing.
2467 In that case, prologue_sal.end may actually point to the start of the
2468 next function in the text section, causing a breakpoint to be set at
2469 the wrong place. Check if the end address is in a different function,
2470 and if so return the start PC. We know we have symbol info. */
2474 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2475 if (end_func != start_pc)
2478 return prologue_sal.end;
2481 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2482 body_pc = call0_analyze_prologue(start_pc, 0, 0, 0, NULL, NULL);
2483 return body_pc != 0 ? body_pc : start_pc;
2486 /* Verify the current configuration. */
2488 xtensa_verify_config (struct gdbarch *gdbarch)
2490 struct ui_file *log;
2491 struct cleanup *cleanups;
2492 struct gdbarch_tdep *tdep;
2496 tdep = gdbarch_tdep (gdbarch);
2497 log = mem_fileopen ();
2498 cleanups = make_cleanup_ui_file_delete (log);
2500 /* Verify that we got a reasonable number of AREGS. */
2501 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2502 fprintf_unfiltered (log, _("\
2503 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2506 /* Verify that certain registers exist. */
2508 if (tdep->pc_regnum == -1)
2509 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2510 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2511 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2513 if (tdep->isa_use_windowed_registers)
2515 if (tdep->wb_regnum == -1)
2516 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2517 if (tdep->ws_regnum == -1)
2518 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2519 if (tdep->ar_base == -1)
2520 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2523 if (tdep->a0_base == -1)
2524 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
2526 buf = ui_file_xstrdup (log, &dummy);
2527 make_cleanup (xfree, buf);
2528 if (strlen (buf) > 0)
2529 internal_error (__FILE__, __LINE__,
2530 _("the following are invalid: %s"), buf);
2531 do_cleanups (cleanups);
2535 /* Derive specific register numbers from the array of registers. */
2538 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2540 xtensa_register_t* rmap;
2541 int n, max_size = 4;
2544 tdep->num_nopriv_regs = 0;
2546 /* Special registers 0..255 (core). */
2547 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2549 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2551 if (rmap->target_number == 0x0020)
2552 tdep->pc_regnum = n;
2553 else if (rmap->target_number == 0x0100)
2555 else if (rmap->target_number == 0x0000)
2557 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2558 tdep->wb_regnum = n;
2559 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2560 tdep->ws_regnum = n;
2561 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2562 tdep->debugcause_regnum = n;
2563 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2564 tdep->exccause_regnum = n;
2565 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2566 tdep->excvaddr_regnum = n;
2567 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2568 tdep->lbeg_regnum = n;
2569 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2570 tdep->lend_regnum = n;
2571 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2572 tdep->lcount_regnum = n;
2573 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2574 tdep->sar_regnum = n;
2575 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2576 tdep->litbase_regnum = n;
2577 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2578 tdep->ps_regnum = n;
2580 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2581 tdep->interrupt_regnum = n;
2582 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2583 tdep->interrupt2_regnum = n;
2584 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2585 tdep->cpenable_regnum = n;
2588 if (rmap->byte_size > max_size)
2589 max_size = rmap->byte_size;
2590 if (rmap->mask != 0 && tdep->num_regs == 0)
2592 /* Find out out how to deal with priveleged registers.
2594 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2595 && tdep->num_nopriv_regs == 0)
2596 tdep->num_nopriv_regs = n;
2598 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2599 && tdep->num_regs == 0)
2603 /* Number of pseudo registers. */
2604 tdep->num_pseudo_regs = n - tdep->num_regs;
2606 /* Empirically determined maximum sizes. */
2607 tdep->max_register_raw_size = max_size;
2608 tdep->max_register_virtual_size = max_size;
2611 /* Module "constructor" function. */
2613 extern struct gdbarch_tdep xtensa_tdep;
2615 static struct gdbarch *
2616 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2618 struct gdbarch_tdep *tdep;
2619 struct gdbarch *gdbarch;
2620 struct xtensa_abi_handler *abi_handler;
2622 DEBUGTRACE ("gdbarch_init()\n");
2624 /* We have to set the byte order before we call gdbarch_alloc. */
2625 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
2627 tdep = &xtensa_tdep;
2628 gdbarch = gdbarch_alloc (&info, tdep);
2629 xtensa_derive_tdep (tdep);
2631 /* Verify our configuration. */
2632 xtensa_verify_config (gdbarch);
2634 /* Pseudo-Register read/write. */
2635 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2636 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2638 /* Set target information. */
2639 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2640 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2641 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2642 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2643 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2645 /* Renumber registers for known formats (stabs and dwarf2). */
2646 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2647 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2649 /* We provide our own function to get register information. */
2650 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2651 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2653 /* To call functions from GDB using dummy frame */
2654 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2656 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2658 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2660 /* Advance PC across any prologue instructions to reach "real" code. */
2661 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2663 /* Stack grows downward. */
2664 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2666 /* Set breakpoints. */
2667 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2669 /* After breakpoint instruction or illegal instruction, pc still
2670 points at break instruction, so don't decrement. */
2671 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2673 /* We don't skip args. */
2674 set_gdbarch_frame_args_skip (gdbarch, 0);
2676 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2678 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2680 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
2682 /* Frame handling. */
2683 frame_base_set_default (gdbarch, &xtensa_frame_base);
2684 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
2685 dwarf2_append_unwinders (gdbarch);
2687 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2689 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2691 xtensa_add_reggroups (gdbarch);
2692 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2694 set_gdbarch_regset_from_core_section (gdbarch,
2695 xtensa_regset_from_core_section);
2697 set_solib_svr4_fetch_link_map_offsets
2698 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
2704 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2706 error (_("xtensa_dump_tdep(): not implemented"));
2710 _initialize_xtensa_tdep (void)
2712 struct cmd_list_element *c;
2714 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2715 xtensa_init_reggroups ();
2717 add_setshow_zinteger_cmd ("xtensa",
2719 &xtensa_debug_level, _("\
2720 Set Xtensa debugging."), _("\
2721 Show Xtensa debugging."), _("\
2722 When non-zero, Xtensa-specific debugging is enabled. \
2723 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2726 &setdebuglist, &showdebuglist);