1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
41 #include "frame-base.h"
42 #include "frame-unwind.h"
44 #include "arch-utils.h"
52 #include "xtensa-isa.h"
53 #include "xtensa-tdep.h"
54 #include "xtensa-config.h"
58 static unsigned int xtensa_debug_level = 0;
60 #define DEBUGWARN(args...) \
61 if (xtensa_debug_level > 0) \
62 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
64 #define DEBUGINFO(args...) \
65 if (xtensa_debug_level > 1) \
66 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
68 #define DEBUGTRACE(args...) \
69 if (xtensa_debug_level > 2) \
70 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
72 #define DEBUGVERB(args...) \
73 if (xtensa_debug_level > 3) \
74 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
77 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* On Windowed ABI, we use a6 through a11 for passing arguments
82 to a function called by GDB because CALL4 is used. */
83 #define ARGS_NUM_REGS 6
84 #define REGISTER_SIZE 4
87 /* Extract the call size from the return address or PS register. */
88 #define PS_CALLINC_SHIFT 16
89 #define PS_CALLINC_MASK 0x00030000
90 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
91 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
93 /* On TX, hardware can be configured without Exception Option.
94 There is no PS register in this case. Inside XT-GDB, let us treat
95 it as a virtual read-only register always holding the same value. */
98 /* ABI-independent macros. */
99 #define ARG_NOF(gdbarch) \
100 (gdbarch_tdep (gdbarch)->call_abi \
101 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
102 #define ARG_1ST(gdbarch) \
103 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
104 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
105 : (gdbarch_tdep (gdbarch)->a0_base + 6))
107 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
108 indicates that the instruction is an ENTRY instruction. */
110 #define XTENSA_IS_ENTRY(gdbarch, op1) \
111 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
112 ? ((op1) == 0x6c) : ((op1) == 0x36))
114 #define XTENSA_ENTRY_LENGTH 3
116 /* windowing_enabled() returns true, if windowing is enabled.
117 WOE must be set to 1; EXCM to 0.
118 Note: We assume that EXCM is always 0 for XEA1. */
120 #define PS_WOE (1<<18)
121 #define PS_EXC (1<<4)
124 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
126 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
127 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
130 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
133 /* Convert a live A-register number to the corresponding AR-register
136 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
138 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
141 arreg = a_regnum - tdep->a0_base;
142 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
143 arreg &= tdep->num_aregs - 1;
145 return arreg + tdep->ar_base;
148 /* Convert a live AR-register number to the corresponding A-register order
149 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
151 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
153 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 areg = ar_regnum - tdep->ar_base;
157 if (areg < 0 || areg >= tdep->num_aregs)
159 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
160 return (areg > 15) ? -1 : areg;
163 /* Read Xtensa register directly from the hardware. */
165 xtensa_read_register (int regnum)
169 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
170 return (unsigned long) value;
173 /* Write Xtensa register directly to the hardware. */
175 xtensa_write_register (int regnum, ULONGEST value)
177 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
180 /* Return the window size of the previous call to the function from which we
183 This function is used to extract the return value after a called function
184 has returned to the caller. On Xtensa, the register that holds the return
185 value (from the perspective of the caller) depends on what call
186 instruction was used. For now, we are assuming that the call instruction
187 precedes the current address, so we simply analyze the call instruction.
188 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
189 method to call the inferior function. */
192 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
194 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
199 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
201 /* Read the previous instruction (should be a call[x]{4|8|12}. */
202 read_memory (pc-3, buf, 3);
203 insn = extract_unsigned_integer (buf, 3, byte_order);
205 /* Decode call instruction:
207 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
208 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
210 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
211 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
213 if (byte_order == BFD_ENDIAN_LITTLE)
215 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
216 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
220 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
221 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
227 /* REGISTER INFORMATION */
229 /* Find register by name. */
231 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
235 for (i = 0; i < gdbarch_num_regs (gdbarch)
236 + gdbarch_num_pseudo_regs (gdbarch);
239 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
245 /* Returns the name of a register. */
247 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
249 /* Return the name stored in the register map. */
250 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
251 + gdbarch_num_pseudo_regs (gdbarch))
252 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
254 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
258 /* Return the type of a register. Create a new type, if necessary. */
261 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
263 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
265 /* Return signed integer for ARx and Ax registers. */
266 if ((regnum >= tdep->ar_base
267 && regnum < tdep->ar_base + tdep->num_aregs)
268 || (regnum >= tdep->a0_base
269 && regnum < tdep->a0_base + 16))
270 return builtin_type (gdbarch)->builtin_int;
272 if (regnum == gdbarch_pc_regnum (gdbarch)
273 || regnum == tdep->a0_base + 1)
274 return builtin_type (gdbarch)->builtin_data_ptr;
276 /* Return the stored type for all other registers. */
277 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
278 + gdbarch_num_pseudo_regs (gdbarch))
280 xtensa_register_t* reg = &tdep->regmap[regnum];
282 /* Set ctype for this register (only the first time). */
286 struct ctype_cache *tp;
287 int size = reg->byte_size;
289 /* We always use the memory representation,
290 even if the register width is smaller. */
294 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
298 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
302 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
306 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
310 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
314 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
315 if (tp->size == size)
320 char *name = xstrprintf ("int%d", size * 8);
322 tp = XNEW (struct ctype_cache);
323 tp->next = tdep->type_entries;
324 tdep->type_entries = tp;
327 = arch_integer_type (gdbarch, size * 8, 1, name);
331 reg->ctype = tp->virtual_type;
337 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
342 /* Return the 'local' register number for stubs, dwarf2, etc.
343 The debugging information enumerates registers starting from 0 for A0
344 to n for An. So, we only have to add the base number for A0. */
347 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
351 if (regnum >= 0 && regnum < 16)
352 return gdbarch_tdep (gdbarch)->a0_base + regnum;
355 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
357 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
364 /* Write the bits of a masked register to the various registers.
365 Only the masked areas of these registers are modified; the other
366 fields are untouched. The size of masked registers is always less
367 than or equal to 32 bits. */
370 xtensa_register_write_masked (struct regcache *regcache,
371 xtensa_register_t *reg, const gdb_byte *buffer)
373 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
374 const xtensa_mask_t *mask = reg->mask;
376 int shift = 0; /* Shift for next mask (mod 32). */
377 int start, size; /* Start bit and size of current mask. */
379 unsigned int *ptr = value;
380 unsigned int regval, m, mem = 0;
382 int bytesize = reg->byte_size;
383 int bitsize = bytesize * 8;
386 DEBUGTRACE ("xtensa_register_write_masked ()\n");
388 /* Copy the masked register to host byte-order. */
389 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
390 for (i = 0; i < bytesize; i++)
393 mem |= (buffer[bytesize - i - 1] << 24);
398 for (i = 0; i < bytesize; i++)
401 mem |= (buffer[i] << 24);
406 /* We might have to shift the final value:
407 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
408 bytesize & 3 == x -> shift (4-x) * 8. */
410 *ptr = mem >> (((0 - bytesize) & 3) * 8);
414 /* Write the bits to the masked areas of the other registers. */
415 for (i = 0; i < mask->count; i++)
417 start = mask->mask[i].bit_start;
418 size = mask->mask[i].bit_size;
419 regval = mem >> shift;
421 if ((shift += size) > bitsize)
422 error (_("size of all masks is larger than the register"));
431 regval |= mem << (size - shift);
434 /* Make sure we have a valid register. */
435 r = mask->mask[i].reg_num;
436 if (r >= 0 && size > 0)
438 /* Don't overwrite the unmasked areas. */
440 regcache_cooked_read_unsigned (regcache, r, &old_val);
441 m = 0xffffffff >> (32 - size) << start;
443 regval = (regval & m) | (old_val & ~m);
444 regcache_cooked_write_unsigned (regcache, r, regval);
450 /* Read a tie state or mapped registers. Read the masked areas
451 of the registers and assemble them into a single value. */
453 static enum register_status
454 xtensa_register_read_masked (struct regcache *regcache,
455 xtensa_register_t *reg, gdb_byte *buffer)
457 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
458 const xtensa_mask_t *mask = reg->mask;
463 unsigned int *ptr = value;
464 unsigned int regval, mem = 0;
466 int bytesize = reg->byte_size;
467 int bitsize = bytesize * 8;
470 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
471 reg->name == 0 ? "" : reg->name);
473 /* Assemble the register from the masked areas of other registers. */
474 for (i = 0; i < mask->count; i++)
476 int r = mask->mask[i].reg_num;
479 enum register_status status;
482 status = regcache_cooked_read_unsigned (regcache, r, &val);
483 if (status != REG_VALID)
485 regval = (unsigned int) val;
490 start = mask->mask[i].bit_start;
491 size = mask->mask[i].bit_size;
496 regval &= (0xffffffff >> (32 - size));
498 mem |= regval << shift;
500 if ((shift += size) > bitsize)
501 error (_("size of all masks is larger than the register"));
512 mem = regval >> (size - shift);
519 /* Copy value to target byte order. */
523 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
524 for (i = 0; i < bytesize; i++)
528 buffer[bytesize - i - 1] = mem & 0xff;
532 for (i = 0; i < bytesize; i++)
536 buffer[i] = mem & 0xff;
544 /* Read pseudo registers. */
546 static enum register_status
547 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
548 struct regcache *regcache,
552 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
554 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
555 regnum, xtensa_register_name (gdbarch, regnum));
557 /* Read aliases a0..a15, if this is a Windowed ABI. */
558 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
559 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
560 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
562 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
563 enum register_status status;
565 status = regcache_raw_read (regcache,
566 gdbarch_tdep (gdbarch)->wb_regnum,
568 if (status != REG_VALID)
570 regnum = arreg_number (gdbarch, regnum,
571 extract_unsigned_integer (buf, 4, byte_order));
574 /* We can always read non-pseudo registers. */
575 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
576 return regcache_raw_read (regcache, regnum, buffer);
578 /* We have to find out how to deal with priveleged registers.
579 Let's treat them as pseudo-registers, but we cannot read/write them. */
581 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
583 buffer[0] = (gdb_byte)0;
584 buffer[1] = (gdb_byte)0;
585 buffer[2] = (gdb_byte)0;
586 buffer[3] = (gdb_byte)0;
589 /* Pseudo registers. */
591 && regnum < gdbarch_num_regs (gdbarch)
592 + gdbarch_num_pseudo_regs (gdbarch))
594 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
595 xtensa_register_type_t type = reg->type;
596 int flags = gdbarch_tdep (gdbarch)->target_flags;
598 /* We cannot read Unknown or Unmapped registers. */
599 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
601 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
603 warning (_("cannot read register %s"),
604 xtensa_register_name (gdbarch, regnum));
609 /* Some targets cannot read TIE register files. */
610 else if (type == xtRegisterTypeTieRegfile)
612 /* Use 'fetch' to get register? */
613 if (flags & xtTargetFlagsUseFetchStore)
615 warning (_("cannot read register"));
619 /* On some targets (esp. simulators), we can always read the reg. */
620 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
622 warning (_("cannot read register"));
627 /* We can always read mapped registers. */
628 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
629 return xtensa_register_read_masked (regcache, reg, buffer);
631 /* Assume that we can read the register. */
632 return regcache_raw_read (regcache, regnum, buffer);
635 internal_error (__FILE__, __LINE__,
636 _("invalid register number %d"), regnum);
640 /* Write pseudo registers. */
643 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
644 struct regcache *regcache,
646 const gdb_byte *buffer)
648 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
650 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
651 regnum, xtensa_register_name (gdbarch, regnum));
653 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
654 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
655 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
656 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
658 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
660 regcache_raw_read (regcache,
661 gdbarch_tdep (gdbarch)->wb_regnum, buf);
662 regnum = arreg_number (gdbarch, regnum,
663 extract_unsigned_integer (buf, 4, byte_order));
666 /* We can always write 'core' registers.
667 Note: We might have converted Ax->ARy. */
668 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
669 regcache_raw_write (regcache, regnum, buffer);
671 /* We have to find out how to deal with priveleged registers.
672 Let's treat them as pseudo-registers, but we cannot read/write them. */
674 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
678 /* Pseudo registers. */
680 && regnum < gdbarch_num_regs (gdbarch)
681 + gdbarch_num_pseudo_regs (gdbarch))
683 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
684 xtensa_register_type_t type = reg->type;
685 int flags = gdbarch_tdep (gdbarch)->target_flags;
687 /* On most targets, we cannot write registers
688 of type "Unknown" or "Unmapped". */
689 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
691 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
693 warning (_("cannot write register %s"),
694 xtensa_register_name (gdbarch, regnum));
699 /* Some targets cannot read TIE register files. */
700 else if (type == xtRegisterTypeTieRegfile)
702 /* Use 'store' to get register? */
703 if (flags & xtTargetFlagsUseFetchStore)
705 warning (_("cannot write register"));
709 /* On some targets (esp. simulators), we can always write
711 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
713 warning (_("cannot write register"));
718 /* We can always write mapped registers. */
719 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
721 xtensa_register_write_masked (regcache, reg, buffer);
725 /* Assume that we can write the register. */
726 regcache_raw_write (regcache, regnum, buffer);
729 internal_error (__FILE__, __LINE__,
730 _("invalid register number %d"), regnum);
733 static struct reggroup *xtensa_ar_reggroup;
734 static struct reggroup *xtensa_user_reggroup;
735 static struct reggroup *xtensa_vectra_reggroup;
736 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
739 xtensa_init_reggroups (void)
742 char cpname[] = "cp0";
744 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
745 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
746 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
748 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
751 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
756 xtensa_add_reggroups (struct gdbarch *gdbarch)
760 /* Predefined groups. */
761 reggroup_add (gdbarch, all_reggroup);
762 reggroup_add (gdbarch, save_reggroup);
763 reggroup_add (gdbarch, restore_reggroup);
764 reggroup_add (gdbarch, system_reggroup);
765 reggroup_add (gdbarch, vector_reggroup);
766 reggroup_add (gdbarch, general_reggroup);
767 reggroup_add (gdbarch, float_reggroup);
769 /* Xtensa-specific groups. */
770 reggroup_add (gdbarch, xtensa_ar_reggroup);
771 reggroup_add (gdbarch, xtensa_user_reggroup);
772 reggroup_add (gdbarch, xtensa_vectra_reggroup);
774 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
775 reggroup_add (gdbarch, xtensa_cp[i]);
779 xtensa_coprocessor_register_group (struct reggroup *group)
783 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
784 if (group == xtensa_cp[i])
790 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
791 | XTENSA_REGISTER_FLAGS_WRITABLE \
792 | XTENSA_REGISTER_FLAGS_VOLATILE)
794 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
795 | XTENSA_REGISTER_FLAGS_WRITABLE)
798 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
800 struct reggroup *group)
802 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
803 xtensa_register_type_t type = reg->type;
804 xtensa_register_group_t rg = reg->group;
807 if (group == save_reggroup)
808 /* Every single register should be included into the list of registers
809 to be watched for changes while using -data-list-changed-registers. */
812 /* First, skip registers that are not visible to this target
813 (unknown and unmapped registers when not using ISS). */
815 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
817 if (group == all_reggroup)
819 if (group == xtensa_ar_reggroup)
820 return rg & xtRegisterGroupAddrReg;
821 if (group == xtensa_user_reggroup)
822 return rg & xtRegisterGroupUser;
823 if (group == float_reggroup)
824 return rg & xtRegisterGroupFloat;
825 if (group == general_reggroup)
826 return rg & xtRegisterGroupGeneral;
827 if (group == system_reggroup)
828 return rg & xtRegisterGroupState;
829 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
830 return rg & xtRegisterGroupVectra;
831 if (group == restore_reggroup)
832 return (regnum < gdbarch_num_regs (gdbarch)
833 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
834 cp_number = xtensa_coprocessor_register_group (group);
836 return rg & (xtRegisterGroupCP0 << cp_number);
842 /* Supply register REGNUM from the buffer specified by GREGS and LEN
843 in the general-purpose register set REGSET to register cache
844 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
847 xtensa_supply_gregset (const struct regset *regset,
853 const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs;
854 struct gdbarch *gdbarch = get_regcache_arch (rc);
857 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
859 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
860 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
861 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
862 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
863 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
864 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
865 (char *) ®s->windowbase);
866 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
867 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
868 (char *) ®s->windowstart);
869 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
870 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
871 (char *) ®s->lbeg);
872 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
873 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
874 (char *) ®s->lend);
875 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
876 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
877 (char *) ®s->lcount);
878 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
879 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
880 (char *) ®s->sar);
881 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
882 && regnum < gdbarch_tdep (gdbarch)->ar_base
883 + gdbarch_tdep (gdbarch)->num_aregs)
884 regcache_raw_supply (rc, regnum,
885 (char *) ®s->ar[regnum - gdbarch_tdep
886 (gdbarch)->ar_base]);
887 else if (regnum == -1)
889 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
890 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
891 (char *) ®s->ar[i]);
896 /* Xtensa register set. */
902 xtensa_supply_gregset
906 /* Iterate over supported core file register note sections. */
909 xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch,
910 iterate_over_regset_sections_cb *cb,
912 const struct regcache *regcache)
914 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
916 cb (".reg", sizeof (xtensa_elf_gregset_t), &xtensa_gregset,
921 /* Handling frames. */
923 /* Number of registers to save in case of Windowed ABI. */
924 #define XTENSA_NUM_SAVED_AREGS 12
926 /* Frame cache part for Windowed ABI. */
927 typedef struct xtensa_windowed_frame_cache
929 int wb; /* WINDOWBASE of the previous frame. */
930 int callsize; /* Call size of this frame. */
931 int ws; /* WINDOWSTART of the previous frame. It keeps track of
932 life windows only. If there is no bit set for the
933 window, that means it had been already spilled
934 because of window overflow. */
936 /* Addresses of spilled A-registers.
937 AREGS[i] == -1, if corresponding AR is alive. */
938 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
939 } xtensa_windowed_frame_cache_t;
941 /* Call0 ABI Definitions. */
943 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
945 #define C0_NREGS 16 /* Number of A-registers to track. */
946 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
947 #define C0_SP 1 /* Register used as SP. */
948 #define C0_FP 15 /* Register used as FP. */
949 #define C0_RA 0 /* Register used as return address. */
950 #define C0_ARGS 2 /* Register used as first arg/retval. */
951 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
953 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
954 A-register where the current content of the reg came from (in terms
955 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
956 mean that the orignal content of the register was saved to the stack.
957 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
958 know where SP will end up until the entire prologue has been analyzed. */
960 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
961 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
962 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
964 extern xtensa_isa xtensa_default_isa;
966 typedef struct xtensa_c0reg
968 int fr_reg; /* original register from which register content
969 is derived, or C0_CONST, or C0_INEXP. */
970 int fr_ofs; /* constant offset from reg, or immediate value. */
971 int to_stk; /* offset from original SP to register (4-byte aligned),
972 or C0_NOSTK if register has not been saved. */
975 /* Frame cache part for Call0 ABI. */
976 typedef struct xtensa_call0_frame_cache
978 int c0_frmsz; /* Stack frame size. */
979 int c0_hasfp; /* Current frame uses frame pointer. */
980 int fp_regnum; /* A-register used as FP. */
981 int c0_fp; /* Actual value of frame pointer. */
982 int c0_fpalign; /* Dinamic adjustment for the stack
983 pointer. It's an AND mask. Zero,
984 if alignment was not adjusted. */
985 int c0_old_sp; /* In case of dynamic adjustment, it is
986 a register holding unaligned sp.
987 C0_INEXP, when undefined. */
988 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
989 stack offset. C0_NOSTK otherwise. */
991 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
992 } xtensa_call0_frame_cache_t;
994 typedef struct xtensa_frame_cache
996 CORE_ADDR base; /* Stack pointer of this frame. */
997 CORE_ADDR pc; /* PC of this frame at the function entry point. */
998 CORE_ADDR ra; /* The raw return address of this frame. */
999 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1000 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1001 int call0; /* It's a call0 framework (else windowed). */
1004 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1005 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1007 } xtensa_frame_cache_t;
1010 static struct xtensa_frame_cache *
1011 xtensa_alloc_frame_cache (int windowed)
1013 xtensa_frame_cache_t *cache;
1016 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1018 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1025 cache->call0 = !windowed;
1028 cache->c0.c0_frmsz = -1;
1029 cache->c0.c0_hasfp = 0;
1030 cache->c0.fp_regnum = -1;
1031 cache->c0.c0_fp = -1;
1032 cache->c0.c0_fpalign = 0;
1033 cache->c0.c0_old_sp = C0_INEXP;
1034 cache->c0.c0_sp_ofs = C0_NOSTK;
1036 for (i = 0; i < C0_NREGS; i++)
1038 cache->c0.c0_rt[i].fr_reg = i;
1039 cache->c0.c0_rt[i].fr_ofs = 0;
1040 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1047 cache->wd.callsize = -1;
1049 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1050 cache->wd.aregs[i] = -1;
1057 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1059 return address & ~15;
1064 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1069 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1070 host_address_to_string (next_frame));
1072 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1073 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1075 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1081 static struct frame_id
1082 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1086 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1088 pc = get_frame_pc (this_frame);
1089 fp = get_frame_register_unsigned
1090 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1092 /* Make dummy frame ID unique by adding a constant. */
1093 return frame_id_build (fp + SP_ALIGNMENT, pc);
1096 /* Returns true, if instruction to execute next is unique to Xtensa Window
1097 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1100 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1102 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1103 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1106 if (byte_order == BFD_ENDIAN_BIG)
1108 /* Check, if this is L32E or S32E. */
1109 code = insn & 0xf000ff00;
1110 if ((code == 0x00009000) || (code == 0x00009400))
1112 /* Check, if this is RFWU or RFWO. */
1113 code = insn & 0xffffff00;
1114 return ((code == 0x00430000) || (code == 0x00530000));
1118 /* Check, if this is L32E or S32E. */
1119 code = insn & 0x00ff000f;
1120 if ((code == 0x090000) || (code == 0x490000))
1122 /* Check, if this is RFWU or RFWO. */
1123 code = insn & 0x00ffffff;
1124 return ((code == 0x00003400) || (code == 0x00003500));
1128 /* Returns the best guess about which register is a frame pointer
1129 for the function containing CURRENT_PC. */
1131 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1132 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1135 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1137 #define RETURN_FP goto done
1139 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1140 CORE_ADDR start_addr;
1142 xtensa_insnbuf ins, slot;
1143 gdb_byte ibuf[XTENSA_ISA_BSZ];
1144 CORE_ADDR ia, bt, ba;
1146 int ilen, islots, is;
1148 const char *opcname;
1150 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1151 if (start_addr == 0)
1154 if (!xtensa_default_isa)
1155 xtensa_default_isa = xtensa_isa_init (0, 0);
1156 isa = xtensa_default_isa;
1157 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1158 ins = xtensa_insnbuf_alloc (isa);
1159 slot = xtensa_insnbuf_alloc (isa);
1162 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1164 if (ia + xtensa_isa_maxlength (isa) > bt)
1167 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1168 ? ba + XTENSA_ISA_BSZ : current_pc;
1169 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1173 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1174 ifmt = xtensa_format_decode (isa, ins);
1175 if (ifmt == XTENSA_UNDEFINED)
1177 ilen = xtensa_format_length (isa, ifmt);
1178 if (ilen == XTENSA_UNDEFINED)
1180 islots = xtensa_format_num_slots (isa, ifmt);
1181 if (islots == XTENSA_UNDEFINED)
1184 for (is = 0; is < islots; ++is)
1186 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1189 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1190 if (opc == XTENSA_UNDEFINED)
1193 opcname = xtensa_opcode_name (isa, opc);
1195 if (strcasecmp (opcname, "mov.n") == 0
1196 || strcasecmp (opcname, "or") == 0)
1198 unsigned int register_operand;
1200 /* Possible candidate for setting frame pointer
1201 from A1. This is what we are looking for. */
1203 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1204 is, slot, ®ister_operand) != 0)
1206 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1208 if (register_operand == 1) /* Mov{.n} FP A1. */
1210 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1211 ®ister_operand) != 0)
1213 if (xtensa_operand_decode (isa, opc, 0,
1214 ®ister_operand) != 0)
1218 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1224 /* We have problems decoding the memory. */
1226 || strcasecmp (opcname, "ill") == 0
1227 || strcasecmp (opcname, "ill.n") == 0
1228 /* Hit planted breakpoint. */
1229 || strcasecmp (opcname, "break") == 0
1230 || strcasecmp (opcname, "break.n") == 0
1231 /* Flow control instructions finish prologue. */
1232 || xtensa_opcode_is_branch (isa, opc) > 0
1233 || xtensa_opcode_is_jump (isa, opc) > 0
1234 || xtensa_opcode_is_loop (isa, opc) > 0
1235 || xtensa_opcode_is_call (isa, opc) > 0
1236 || strcasecmp (opcname, "simcall") == 0
1237 || strcasecmp (opcname, "syscall") == 0)
1238 /* Can not continue analysis. */
1243 xtensa_insnbuf_free(isa, slot);
1244 xtensa_insnbuf_free(isa, ins);
1248 /* The key values to identify the frame using "cache" are
1250 cache->base = SP (or best guess about FP) of this frame;
1251 cache->pc = entry-PC (entry point of the frame function);
1252 cache->prev_sp = SP of the previous frame. */
1255 call0_frame_cache (struct frame_info *this_frame,
1256 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1259 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1260 xtensa_frame_cache_t *cache,
1263 static struct xtensa_frame_cache *
1264 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1266 xtensa_frame_cache_t *cache;
1267 CORE_ADDR ra, wb, ws, pc, sp, ps;
1268 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1269 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1270 unsigned int fp_regnum;
1271 int windowed, ps_regnum;
1274 return (struct xtensa_frame_cache *) *this_cache;
1276 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1277 ps_regnum = gdbarch_ps_regnum (gdbarch);
1278 ps = (ps_regnum >= 0
1279 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1281 windowed = windowing_enabled (gdbarch, ps);
1283 /* Get pristine xtensa-frame. */
1284 cache = xtensa_alloc_frame_cache (windowed);
1285 *this_cache = cache;
1291 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1292 wb = get_frame_register_unsigned (this_frame,
1293 gdbarch_tdep (gdbarch)->wb_regnum);
1294 ws = get_frame_register_unsigned (this_frame,
1295 gdbarch_tdep (gdbarch)->ws_regnum);
1297 if (safe_read_memory_integer (pc, 1, byte_order, &op1)
1298 && XTENSA_IS_ENTRY (gdbarch, op1))
1300 int callinc = CALLINC (ps);
1301 ra = get_frame_register_unsigned
1302 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1304 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1305 cache->wd.callsize = 0;
1308 cache->prev_sp = get_frame_register_unsigned
1309 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1311 /* This only can be the outermost frame since we are
1312 just about to execute ENTRY. SP hasn't been set yet.
1313 We can assume any frame size, because it does not
1314 matter, and, let's fake frame base in cache. */
1315 cache->base = cache->prev_sp - 16;
1318 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1319 cache->ps = (ps & ~PS_CALLINC_MASK)
1320 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1326 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1327 ra = get_frame_register_unsigned (this_frame,
1328 gdbarch_tdep (gdbarch)->a0_base);
1329 cache->wd.callsize = WINSIZE (ra);
1330 cache->wd.wb = (wb - cache->wd.callsize / 4)
1331 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1332 cache->wd.ws = ws & ~(1 << wb);
1334 cache->pc = get_frame_func (this_frame);
1335 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1336 cache->ps = (ps & ~PS_CALLINC_MASK)
1337 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1340 if (cache->wd.ws == 0)
1345 sp = get_frame_register_unsigned
1346 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1348 for (i = 0; i < 4; i++, sp += 4)
1350 cache->wd.aregs[i] = sp;
1353 if (cache->wd.callsize > 4)
1355 /* Set A4...A7/A11. */
1356 /* Get the SP of the frame previous to the previous one.
1357 To achieve this, we have to dereference SP twice. */
1358 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1359 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1360 sp -= cache->wd.callsize * 4;
1362 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1364 cache->wd.aregs[i] = sp;
1369 if ((cache->prev_sp == 0) && ( ra != 0 ))
1370 /* If RA is equal to 0 this frame is an outermost frame. Leave
1371 cache->prev_sp unchanged marking the boundary of the frame stack. */
1373 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1375 /* Register window overflow already happened.
1376 We can read caller's SP from the proper spill loction. */
1377 sp = get_frame_register_unsigned
1378 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1379 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1383 /* Read caller's frame SP directly from the previous window. */
1384 int regnum = arreg_number
1385 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1388 cache->prev_sp = xtensa_read_register (regnum);
1392 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1394 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1396 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1397 /* Everything was set already, including cache->base. */
1400 else /* Call0 framework. */
1402 call0_frame_cache (this_frame, cache, pc);
1403 fp_regnum = cache->c0.fp_regnum;
1406 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1411 static int xtensa_session_once_reported = 1;
1413 /* Report a problem with prologue analysis while doing backtracing.
1414 But, do it only once to avoid annoyng repeated messages. */
1419 if (xtensa_session_once_reported == 0)
1421 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1422 This message will not be repeated in this session.\n"));
1424 xtensa_session_once_reported = 1;
1429 xtensa_frame_this_id (struct frame_info *this_frame,
1431 struct frame_id *this_id)
1433 struct xtensa_frame_cache *cache =
1434 xtensa_frame_cache (this_frame, this_cache);
1436 if (cache->prev_sp == 0)
1439 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1442 static struct value *
1443 xtensa_frame_prev_register (struct frame_info *this_frame,
1447 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1448 struct xtensa_frame_cache *cache;
1449 ULONGEST saved_reg = 0;
1452 if (*this_cache == NULL)
1453 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1454 cache = (struct xtensa_frame_cache *) *this_cache;
1456 if (regnum ==gdbarch_pc_regnum (gdbarch))
1457 saved_reg = cache->ra;
1458 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1459 saved_reg = cache->prev_sp;
1460 else if (!cache->call0)
1462 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1463 saved_reg = cache->wd.ws;
1464 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1465 saved_reg = cache->wd.wb;
1466 else if (regnum == gdbarch_ps_regnum (gdbarch))
1467 saved_reg = cache->ps;
1475 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1477 if (!cache->call0) /* Windowed ABI. */
1479 /* Convert A-register numbers to AR-register numbers,
1480 if we deal with A-register. */
1481 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1482 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1483 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1485 /* Check, if we deal with AR-register saved on stack. */
1486 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1487 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1488 + gdbarch_tdep (gdbarch)->num_aregs))
1490 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1493 && areg < XTENSA_NUM_SAVED_AREGS
1494 && cache->wd.aregs[areg] != -1)
1495 return frame_unwind_got_memory (this_frame, regnum,
1496 cache->wd.aregs[areg]);
1499 else /* Call0 ABI. */
1501 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1502 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1504 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1511 /* If register was saved in the prologue, retrieve it. */
1512 stkofs = cache->c0.c0_rt[reg].to_stk;
1513 if (stkofs != C0_NOSTK)
1515 /* Determine SP on entry based on FP. */
1516 spe = cache->c0.c0_fp
1517 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1519 return frame_unwind_got_memory (this_frame, regnum,
1525 /* All other registers have been either saved to
1526 the stack or are still alive in the processor. */
1528 return frame_unwind_got_register (this_frame, regnum, regnum);
1532 static const struct frame_unwind
1536 default_frame_unwind_stop_reason,
1537 xtensa_frame_this_id,
1538 xtensa_frame_prev_register,
1540 default_frame_sniffer
1544 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1546 struct xtensa_frame_cache *cache =
1547 xtensa_frame_cache (this_frame, this_cache);
1552 static const struct frame_base
1556 xtensa_frame_base_address,
1557 xtensa_frame_base_address,
1558 xtensa_frame_base_address
1563 xtensa_extract_return_value (struct type *type,
1564 struct regcache *regcache,
1567 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1568 bfd_byte *valbuf = (bfd_byte *) dst;
1569 int len = TYPE_LENGTH (type);
1574 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1576 gdb_assert(len > 0);
1578 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1580 /* First, we have to find the caller window in the register file. */
1581 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1582 callsize = extract_call_winsize (gdbarch, pc);
1584 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1585 if (len > (callsize > 8 ? 8 : 16))
1586 internal_error (__FILE__, __LINE__,
1587 _("cannot extract return value of %d bytes long"),
1590 /* Get the register offset of the return
1591 register (A2) in the caller window. */
1592 regcache_raw_read_unsigned
1593 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1594 areg = arreg_number (gdbarch,
1595 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1599 /* No windowing hardware - Call0 ABI. */
1600 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1603 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1605 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1608 for (; len > 0; len -= 4, areg++, valbuf += 4)
1611 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1613 regcache_raw_read (regcache, areg, valbuf);
1619 xtensa_store_return_value (struct type *type,
1620 struct regcache *regcache,
1623 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1624 const bfd_byte *valbuf = (const bfd_byte *) dst;
1628 int len = TYPE_LENGTH (type);
1631 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1633 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1635 regcache_raw_read_unsigned
1636 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1637 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1638 callsize = extract_call_winsize (gdbarch, pc);
1640 if (len > (callsize > 8 ? 8 : 16))
1641 internal_error (__FILE__, __LINE__,
1642 _("unimplemented for this length: %d"),
1643 TYPE_LENGTH (type));
1644 areg = arreg_number (gdbarch,
1645 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1647 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1648 callsize, (int) wb);
1652 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1655 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1658 for (; len > 0; len -= 4, areg++, valbuf += 4)
1661 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1663 regcache_raw_write (regcache, areg, valbuf);
1668 static enum return_value_convention
1669 xtensa_return_value (struct gdbarch *gdbarch,
1670 struct value *function,
1671 struct type *valtype,
1672 struct regcache *regcache,
1674 const gdb_byte *writebuf)
1676 /* Structures up to 16 bytes are returned in registers. */
1678 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1679 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1680 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1681 && TYPE_LENGTH (valtype) > 16);
1684 return RETURN_VALUE_STRUCT_CONVENTION;
1686 DEBUGTRACE ("xtensa_return_value(...)\n");
1688 if (writebuf != NULL)
1690 xtensa_store_return_value (valtype, regcache, writebuf);
1693 if (readbuf != NULL)
1695 gdb_assert (!struct_return);
1696 xtensa_extract_return_value (valtype, regcache, readbuf);
1698 return RETURN_VALUE_REGISTER_CONVENTION;
1705 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1706 struct value *function,
1707 struct regcache *regcache,
1710 struct value **args,
1713 CORE_ADDR struct_addr)
1715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1717 int size, onstack_size;
1718 gdb_byte *buf = (gdb_byte *) alloca (16);
1720 struct argument_info
1722 const bfd_byte *contents;
1724 int onstack; /* onstack == 0 => in reg */
1725 int align; /* alignment */
1728 int offset; /* stack offset if on stack. */
1729 int regno; /* regno if in register. */
1733 struct argument_info *arg_info =
1734 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1738 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1740 if (xtensa_debug_level > 3)
1743 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1744 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1745 "struct_addr=0x%x\n",
1746 (int) sp, (int) struct_return, (int) struct_addr);
1748 for (i = 0; i < nargs; i++)
1750 struct value *arg = args[i];
1751 struct type *arg_type = check_typedef (value_type (arg));
1752 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1753 host_address_to_string (arg),
1754 TYPE_LENGTH (arg_type));
1755 switch (TYPE_CODE (arg_type))
1758 fprintf_unfiltered (gdb_stdlog, "int");
1760 case TYPE_CODE_STRUCT:
1761 fprintf_unfiltered (gdb_stdlog, "struct");
1764 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1767 fprintf_unfiltered (gdb_stdlog, " %s\n",
1768 host_address_to_string (value_contents (arg)));
1772 /* First loop: collect information.
1773 Cast into type_long. (This shouldn't happen often for C because
1774 GDB already does this earlier.) It's possible that GDB could
1775 do it all the time but it's harmless to leave this code here. */
1782 size = REGISTER_SIZE;
1784 for (i = 0; i < nargs; i++)
1786 struct argument_info *info = &arg_info[i];
1787 struct value *arg = args[i];
1788 struct type *arg_type = check_typedef (value_type (arg));
1790 switch (TYPE_CODE (arg_type))
1793 case TYPE_CODE_BOOL:
1794 case TYPE_CODE_CHAR:
1795 case TYPE_CODE_RANGE:
1796 case TYPE_CODE_ENUM:
1798 /* Cast argument to long if necessary as the mask does it too. */
1799 if (TYPE_LENGTH (arg_type)
1800 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1802 arg_type = builtin_type (gdbarch)->builtin_long;
1803 arg = value_cast (arg_type, arg);
1805 /* Aligment is equal to the type length for the basic types. */
1806 info->align = TYPE_LENGTH (arg_type);
1811 /* Align doubles correctly. */
1812 if (TYPE_LENGTH (arg_type)
1813 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1814 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1816 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1819 case TYPE_CODE_STRUCT:
1821 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1824 info->length = TYPE_LENGTH (arg_type);
1825 info->contents = value_contents (arg);
1827 /* Align size and onstack_size. */
1828 size = (size + info->align - 1) & ~(info->align - 1);
1829 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1831 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1834 info->u.offset = onstack_size;
1835 onstack_size += info->length;
1840 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1842 size += info->length;
1845 /* Adjust the stack pointer and align it. */
1846 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1848 /* Simulate MOVSP, if Windowed ABI. */
1849 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1852 read_memory (osp - 16, buf, 16);
1853 write_memory (sp - 16, buf, 16);
1856 /* Second Loop: Load arguments. */
1860 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1861 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1864 for (i = 0; i < nargs; i++)
1866 struct argument_info *info = &arg_info[i];
1870 int n = info->length;
1871 CORE_ADDR offset = sp + info->u.offset;
1873 /* Odd-sized structs are aligned to the lower side of a memory
1874 word in big-endian mode and require a shift. This only
1875 applies for structures smaller than one word. */
1877 if (n < REGISTER_SIZE
1878 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1879 offset += (REGISTER_SIZE - n);
1881 write_memory (offset, info->contents, info->length);
1886 int n = info->length;
1887 const bfd_byte *cp = info->contents;
1888 int r = info->u.regno;
1890 /* Odd-sized structs are aligned to the lower side of registers in
1891 big-endian mode and require a shift. The odd-sized leftover will
1892 be at the end. Note that this is only true for structures smaller
1893 than REGISTER_SIZE; for larger odd-sized structures the excess
1894 will be left-aligned in the register on both endiannesses. */
1896 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1899 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1900 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1902 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1903 regcache_cooked_write (regcache, r, buf);
1905 cp += REGISTER_SIZE;
1912 regcache_cooked_write (regcache, r, cp);
1914 cp += REGISTER_SIZE;
1921 /* Set the return address of dummy frame to the dummy address.
1922 The return address for the current function (in A0) is
1923 saved in the dummy frame, so we can savely overwrite A0 here. */
1925 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1929 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1930 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1931 ps = (unsigned long) val & ~0x00030000;
1932 regcache_cooked_write_unsigned
1933 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1934 regcache_cooked_write_unsigned (regcache,
1935 gdbarch_ps_regnum (gdbarch),
1938 /* All the registers have been saved. After executing
1939 dummy call, they all will be restored. So it's safe
1940 to modify WINDOWSTART register to make it look like there
1941 is only one register window corresponding to WINDOWEBASE. */
1943 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1944 regcache_cooked_write_unsigned
1945 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1946 1 << extract_unsigned_integer (buf, 4, byte_order));
1950 /* Simulate CALL0: write RA into A0 register. */
1951 regcache_cooked_write_unsigned
1952 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1955 /* Set new stack pointer and return it. */
1956 regcache_cooked_write_unsigned (regcache,
1957 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1958 /* Make dummy frame ID unique by adding a constant. */
1959 return sp + SP_ALIGNMENT;
1962 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1965 xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1967 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1973 /* Return a breakpoint for the current location of PC. We always use
1974 the density version if we have density instructions (regardless of the
1975 current instruction at PC), and use regular instructions otherwise. */
1977 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1978 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1979 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1980 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1982 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1984 static const gdb_byte *
1985 xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1991 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1992 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1994 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1995 return big_breakpoint;
1997 return little_breakpoint;
2001 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
2002 static unsigned char density_little_breakpoint[]
2003 = DENSITY_LITTLE_BREAKPOINT;
2005 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2006 return density_big_breakpoint;
2008 return density_little_breakpoint;
2012 /* Call0 ABI support routines. */
2014 /* Return true, if PC points to "ret" or "ret.n". */
2017 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2019 #define RETURN_RET goto done
2021 xtensa_insnbuf ins, slot;
2022 gdb_byte ibuf[XTENSA_ISA_BSZ];
2023 CORE_ADDR ia, bt, ba;
2025 int ilen, islots, is;
2027 const char *opcname;
2030 isa = xtensa_default_isa;
2031 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2032 ins = xtensa_insnbuf_alloc (isa);
2033 slot = xtensa_insnbuf_alloc (isa);
2036 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2038 if (ia + xtensa_isa_maxlength (isa) > bt)
2041 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2042 ? ba + XTENSA_ISA_BSZ : finish_pc;
2043 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2047 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2048 ifmt = xtensa_format_decode (isa, ins);
2049 if (ifmt == XTENSA_UNDEFINED)
2051 ilen = xtensa_format_length (isa, ifmt);
2052 if (ilen == XTENSA_UNDEFINED)
2054 islots = xtensa_format_num_slots (isa, ifmt);
2055 if (islots == XTENSA_UNDEFINED)
2058 for (is = 0; is < islots; ++is)
2060 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2063 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2064 if (opc == XTENSA_UNDEFINED)
2067 opcname = xtensa_opcode_name (isa, opc);
2069 if ((strcasecmp (opcname, "ret.n") == 0)
2070 || (strcasecmp (opcname, "ret") == 0))
2078 xtensa_insnbuf_free(isa, slot);
2079 xtensa_insnbuf_free(isa, ins);
2083 /* Call0 opcode class. Opcodes are preclassified according to what they
2084 mean for Call0 prologue analysis, and their number of significant operands.
2085 The purpose of this is to simplify prologue analysis by separating
2086 instruction decoding (libisa) from the semantics of prologue analysis. */
2090 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2091 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2092 c0opc_flow, /* Flow control insn. */
2093 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2094 c0opc_break, /* Debugger software breakpoints. */
2095 c0opc_add, /* Adding two registers. */
2096 c0opc_addi, /* Adding a register and an immediate. */
2097 c0opc_and, /* Bitwise "and"-ing two registers. */
2098 c0opc_sub, /* Subtracting a register from a register. */
2099 c0opc_mov, /* Moving a register to a register. */
2100 c0opc_movi, /* Moving an immediate to a register. */
2101 c0opc_l32r, /* Loading a literal. */
2102 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2103 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2104 c0opc_l32e, /* L32E instruction. */
2105 c0opc_s32e, /* S32E instruction. */
2106 c0opc_rfwo, /* RFWO instruction. */
2107 c0opc_rfwu, /* RFWU instruction. */
2108 c0opc_NrOf /* Number of opcode classifications. */
2111 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2114 rwx_special_register (const char *opcname)
2116 char ch = *opcname++;
2118 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2120 if (*opcname++ != 's')
2122 if (*opcname++ != 'r')
2124 if (*opcname++ != '.')
2130 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2132 static xtensa_insn_kind
2133 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2135 const char *opcname;
2136 xtensa_insn_kind opclass = c0opc_uninteresting;
2138 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2140 /* Get opcode name and handle special classifications. */
2142 opcname = xtensa_opcode_name (isa, opc);
2145 || strcasecmp (opcname, "ill") == 0
2146 || strcasecmp (opcname, "ill.n") == 0)
2147 opclass = c0opc_illegal;
2148 else if (strcasecmp (opcname, "break") == 0
2149 || strcasecmp (opcname, "break.n") == 0)
2150 opclass = c0opc_break;
2151 else if (strcasecmp (opcname, "entry") == 0)
2152 opclass = c0opc_entry;
2153 else if (strcasecmp (opcname, "rfwo") == 0)
2154 opclass = c0opc_rfwo;
2155 else if (strcasecmp (opcname, "rfwu") == 0)
2156 opclass = c0opc_rfwu;
2157 else if (xtensa_opcode_is_branch (isa, opc) > 0
2158 || xtensa_opcode_is_jump (isa, opc) > 0
2159 || xtensa_opcode_is_loop (isa, opc) > 0
2160 || xtensa_opcode_is_call (isa, opc) > 0
2161 || strcasecmp (opcname, "simcall") == 0
2162 || strcasecmp (opcname, "syscall") == 0)
2163 opclass = c0opc_flow;
2165 /* Also, classify specific opcodes that need to be tracked. */
2166 else if (strcasecmp (opcname, "add") == 0
2167 || strcasecmp (opcname, "add.n") == 0)
2168 opclass = c0opc_add;
2169 else if (strcasecmp (opcname, "and") == 0)
2170 opclass = c0opc_and;
2171 else if (strcasecmp (opcname, "addi") == 0
2172 || strcasecmp (opcname, "addi.n") == 0
2173 || strcasecmp (opcname, "addmi") == 0)
2174 opclass = c0opc_addi;
2175 else if (strcasecmp (opcname, "sub") == 0)
2176 opclass = c0opc_sub;
2177 else if (strcasecmp (opcname, "mov.n") == 0
2178 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2179 opclass = c0opc_mov;
2180 else if (strcasecmp (opcname, "movi") == 0
2181 || strcasecmp (opcname, "movi.n") == 0)
2182 opclass = c0opc_movi;
2183 else if (strcasecmp (opcname, "l32r") == 0)
2184 opclass = c0opc_l32r;
2185 else if (strcasecmp (opcname, "s32i") == 0
2186 || strcasecmp (opcname, "s32i.n") == 0)
2187 opclass = c0opc_s32i;
2188 else if (strcasecmp (opcname, "l32e") == 0)
2189 opclass = c0opc_l32e;
2190 else if (strcasecmp (opcname, "s32e") == 0)
2191 opclass = c0opc_s32e;
2192 else if (rwx_special_register (opcname))
2193 opclass = c0opc_rwxsr;
2198 /* Tracks register movement/mutation for a given operation, which may
2199 be within a bundle. Updates the destination register tracking info
2200 accordingly. The pc is needed only for pc-relative load instructions
2201 (eg. l32r). The SP register number is needed to identify stores to
2202 the stack frame. Returns 0, if analysis was succesfull, non-zero
2206 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2207 xtensa_insn_kind opclass, int nods, unsigned odv[],
2208 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2210 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2211 unsigned litbase, litaddr, litval;
2216 /* 3 operands: dst, src, imm. */
2217 gdb_assert (nods == 3);
2218 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2219 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2222 /* 3 operands: dst, src1, src2. */
2223 gdb_assert (nods == 3);
2224 if (src[odv[1]].fr_reg == C0_CONST)
2226 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2227 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2229 else if (src[odv[2]].fr_reg == C0_CONST)
2231 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2232 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2234 else dst[odv[0]].fr_reg = C0_INEXP;
2237 /* 3 operands: dst, src1, src2. */
2238 gdb_assert (nods == 3);
2239 if (cache->c0.c0_fpalign == 0)
2241 /* Handle dynamic stack alignment. */
2242 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2244 if (src[odv[2]].fr_reg == C0_CONST)
2245 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2248 else if ((src[odv[0]].fr_reg == spreg)
2249 && (src[odv[2]].fr_reg == spreg))
2251 if (src[odv[1]].fr_reg == C0_CONST)
2252 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2255 /* else fall through. */
2257 if (src[odv[1]].fr_reg == C0_CONST)
2259 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2260 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2262 else if (src[odv[2]].fr_reg == C0_CONST)
2264 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2265 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2267 else dst[odv[0]].fr_reg = C0_INEXP;
2270 /* 3 operands: dst, src1, src2. */
2271 gdb_assert (nods == 3);
2272 if (src[odv[2]].fr_reg == C0_CONST)
2274 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2275 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2277 else dst[odv[0]].fr_reg = C0_INEXP;
2280 /* 2 operands: dst, src [, src]. */
2281 gdb_assert (nods == 2);
2282 /* First, check if it's a special case of saving unaligned SP
2283 to a spare register in case of dynamic stack adjustment.
2284 But, only do it one time. The second time could be initializing
2285 frame pointer. We don't want to overwrite the first one. */
2286 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2287 cache->c0.c0_old_sp = odv[0];
2289 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2290 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2293 /* 2 operands: dst, imm. */
2294 gdb_assert (nods == 2);
2295 dst[odv[0]].fr_reg = C0_CONST;
2296 dst[odv[0]].fr_ofs = odv[1];
2299 /* 2 operands: dst, literal offset. */
2300 gdb_assert (nods == 2);
2301 /* litbase = xtensa_get_litbase (pc); can be also used. */
2302 litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
2303 ? 0 : xtensa_read_register
2304 (gdbarch_tdep (gdbarch)->litbase_regnum);
2305 litaddr = litbase & 1
2306 ? (litbase & ~1) + (signed)odv[1]
2307 : (pc + 3 + (signed)odv[1]) & ~3;
2308 litval = read_memory_integer (litaddr, 4, byte_order);
2309 dst[odv[0]].fr_reg = C0_CONST;
2310 dst[odv[0]].fr_ofs = litval;
2313 /* 3 operands: value, base, offset. */
2314 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2315 /* First, check if it's a spill for saved unaligned SP,
2316 when dynamic stack adjustment was applied to this frame. */
2317 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2318 && (odv[1] == spreg) /* SP usage indicates spill. */
2319 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2320 cache->c0.c0_sp_ofs = odv[2];
2322 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2323 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2324 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2325 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2326 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2328 /* ISA encoding guarantees alignment. But, check it anyway. */
2329 gdb_assert ((odv[2] & 3) == 0);
2330 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2333 /* If we end up inside Window Overflow / Underflow interrupt handler
2334 report an error because these handlers should have been handled
2335 already in a different way. */
2347 /* Analyze prologue of the function at start address to determine if it uses
2348 the Call0 ABI, and if so track register moves and linear modifications
2349 in the prologue up to the PC or just beyond the prologue, whichever is
2350 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2351 prologue. The prologue may overlap non-prologue instructions but is
2352 guaranteed to end by the first flow-control instruction (jump, branch,
2353 call or return). Since an optimized function may move information around
2354 and change the stack frame arbitrarily during the prologue, the information
2355 is guaranteed valid only at the point in the function indicated by the PC.
2356 May be used to skip the prologue or identify the ABI, w/o tracking.
2358 Returns: Address of first instruction after prologue, or PC (whichever
2359 is first), or 0, if decoding failed (in libisa).
2361 start Start address of function/prologue.
2362 pc Program counter to stop at. Use 0 to continue to end of prologue.
2363 If 0, avoids infinite run-on in corrupt code memory by bounding
2364 the scan to the end of the function if that can be determined.
2365 nregs Number of general registers to track.
2367 cache Xtensa frame cache.
2369 Note that these may produce useful results even if decoding fails
2370 because they begin with default assumptions that analysis may change. */
2373 call0_analyze_prologue (struct gdbarch *gdbarch,
2374 CORE_ADDR start, CORE_ADDR pc,
2375 int nregs, xtensa_frame_cache_t *cache)
2377 CORE_ADDR ia; /* Current insn address in prologue. */
2378 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2379 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2380 gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2381 xtensa_isa isa; /* libisa ISA handle. */
2382 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2383 xtensa_format ifmt; /* libisa instruction format. */
2384 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2385 xtensa_opcode opc; /* Opcode in current slot. */
2386 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2387 int nods; /* Opcode number of operands. */
2388 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2389 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2390 int j; /* General loop counter. */
2391 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2392 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2393 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2395 struct symtab_and_line prologue_sal;
2397 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2398 (int)start, (int)pc);
2400 /* Try to limit the scan to the end of the function if a non-zero pc
2401 arg was not supplied to avoid probing beyond the end of valid memory.
2402 If memory is full of garbage that classifies as c0opc_uninteresting.
2403 If this fails (eg. if no symbols) pc ends up 0 as it was.
2404 Initialize the Call0 frame and register tracking info.
2405 Assume it's Call0 until an 'entry' instruction is encountered.
2406 Assume we may be in the prologue until we hit a flow control instr. */
2412 /* Find out, if we have an information about the prologue from DWARF. */
2413 prologue_sal = find_pc_line (start, 0);
2414 if (prologue_sal.line != 0) /* Found debug info. */
2415 body_pc = prologue_sal.end;
2417 /* If we are going to analyze the prologue in general without knowing about
2418 the current PC, make the best assumtion for the end of the prologue. */
2421 find_pc_partial_function (start, 0, NULL, &end_pc);
2422 body_pc = std::min (end_pc, body_pc);
2425 body_pc = std::min (pc, body_pc);
2428 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2430 if (!xtensa_default_isa)
2431 xtensa_default_isa = xtensa_isa_init (0, 0);
2432 isa = xtensa_default_isa;
2433 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2434 ins = xtensa_insnbuf_alloc (isa);
2435 slot = xtensa_insnbuf_alloc (isa);
2437 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2439 /* (Re)fill instruction buffer from memory if necessary, but do not
2440 read memory beyond PC to be sure we stay within text section
2441 (this protection only works if a non-zero pc is supplied). */
2443 if (ia + xtensa_isa_maxlength (isa) > bt)
2446 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2447 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2448 error (_("Unable to read target memory ..."));
2451 /* Decode format information. */
2453 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2454 ifmt = xtensa_format_decode (isa, ins);
2455 if (ifmt == XTENSA_UNDEFINED)
2460 ilen = xtensa_format_length (isa, ifmt);
2461 if (ilen == XTENSA_UNDEFINED)
2466 islots = xtensa_format_num_slots (isa, ifmt);
2467 if (islots == XTENSA_UNDEFINED)
2473 /* Analyze a bundle or a single instruction, using a snapshot of
2474 the register tracking info as input for the entire bundle so that
2475 register changes do not take effect within this bundle. */
2477 for (j = 0; j < nregs; ++j)
2478 rtmp[j] = cache->c0.c0_rt[j];
2480 for (is = 0; is < islots; ++is)
2482 /* Decode a slot and classify the opcode. */
2484 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2488 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2489 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2491 if (opc == XTENSA_UNDEFINED)
2492 opclass = c0opc_illegal;
2494 opclass = call0_classify_opcode (isa, opc);
2496 /* Decide whether to track this opcode, ignore it, or bail out. */
2505 case c0opc_uninteresting:
2508 case c0opc_flow: /* Flow control instructions stop analysis. */
2509 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2514 ia += ilen; /* Skip over 'entry' insn. */
2521 /* Only expected opcodes should get this far. */
2523 /* Extract and decode the operands. */
2524 nods = xtensa_opcode_num_operands (isa, opc);
2525 if (nods == XTENSA_UNDEFINED)
2531 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2533 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2538 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2543 /* Check operands to verify use of 'mov' assembler macro. */
2544 if (opclass == c0opc_mov && nods == 3)
2546 if (odv[2] == odv[1])
2549 if ((odv[0] == 1) && (odv[1] != 1))
2550 /* OR A1, An, An , where n != 1.
2551 This means we are inside epilogue already. */
2556 opclass = c0opc_uninteresting;
2561 /* Track register movement and modification for this operation. */
2562 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2563 opclass, nods, odv, ia, 1, cache);
2569 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2570 (unsigned)ia, fail ? "failed" : "succeeded");
2571 xtensa_insnbuf_free(isa, slot);
2572 xtensa_insnbuf_free(isa, ins);
2573 return fail ? XTENSA_ISA_BADPC : ia;
2576 /* Initialize frame cache for the current frame in CALL0 ABI. */
2579 call0_frame_cache (struct frame_info *this_frame,
2580 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2582 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2583 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2584 CORE_ADDR start_pc; /* The beginning of the function. */
2585 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2586 CORE_ADDR sp, fp, ra;
2587 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2589 sp = get_frame_register_unsigned
2590 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2591 fp = sp; /* Assume FP == SP until proven otherwise. */
2593 /* Find the beginning of the prologue of the function containing the PC
2594 and analyze it up to the PC or the end of the prologue. */
2596 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2598 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2600 if (body_pc == XTENSA_ISA_BADPC)
2604 goto finish_frame_analysis;
2608 /* Get the frame information and FP (if used) at the current PC.
2609 If PC is in the prologue, the prologue analysis is more reliable
2610 than DWARF info. We don't not know for sure, if PC is in the prologue,
2611 but we do know no calls have yet taken place, so we can almost
2612 certainly rely on the prologue analysis. */
2616 /* Prologue analysis was successful up to the PC.
2617 It includes the cases when PC == START_PC. */
2618 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2619 /* c0_hasfp == true means there is a frame pointer because
2620 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2621 was derived from SP. Otherwise, it would be C0_FP. */
2622 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2623 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2624 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2626 else /* No data from the prologue analysis. */
2629 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2634 if (cache->c0.c0_fpalign)
2636 /* This frame has a special prologue with a dynamic stack adjustment
2637 to force an alignment, which is bigger than standard 16 bytes. */
2639 CORE_ADDR unaligned_sp;
2641 if (cache->c0.c0_old_sp == C0_INEXP)
2642 /* This can't be. Prologue code should be consistent.
2643 Unaligned stack pointer should be saved in a spare register. */
2647 goto finish_frame_analysis;
2650 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2651 /* Saved unaligned value of SP is kept in a register. */
2652 unaligned_sp = get_frame_register_unsigned
2653 (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
2655 /* Get the value from stack. */
2656 unaligned_sp = (CORE_ADDR)
2657 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2659 prev_sp = unaligned_sp + c0_frmsz;
2662 prev_sp = fp + c0_frmsz;
2664 /* Frame size from debug info or prologue tracking does not account for
2665 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2668 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2670 /* Update the stack frame size. */
2671 c0_frmsz += fp - sp;
2674 /* Get the return address (RA) from the stack if saved,
2675 or try to get it from a register. */
2677 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2678 if (to_stk != C0_NOSTK)
2680 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2683 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2684 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2686 /* Special case for terminating backtrace at a function that wants to
2687 be seen as the outermost one. Such a function will clear it's RA (A0)
2688 register to 0 in the prologue instead of saving its original value. */
2693 /* RA was copied to another register or (before any function call) may
2694 still be in the original RA register. This is not always reliable:
2695 even in a leaf function, register tracking stops after prologue, and
2696 even in prologue, non-prologue instructions (not tracked) may overwrite
2697 RA or any register it was copied to. If likely in prologue or before
2698 any call, use retracking info and hope for the best (compiler should
2699 have saved RA in stack if not in a leaf function). If not in prologue,
2705 && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2707 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2711 ra = get_frame_register_unsigned
2713 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2718 finish_frame_analysis:
2719 cache->pc = start_pc;
2721 /* RA == 0 marks the outermost frame. Do not go past it. */
2722 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2723 cache->c0.fp_regnum = fp_regnum;
2724 cache->c0.c0_frmsz = c0_frmsz;
2725 cache->c0.c0_hasfp = c0_hasfp;
2726 cache->c0.c0_fp = fp;
2729 static CORE_ADDR a0_saved;
2730 static CORE_ADDR a7_saved;
2731 static CORE_ADDR a11_saved;
2732 static int a0_was_saved;
2733 static int a7_was_saved;
2734 static int a11_was_saved;
2736 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2738 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2740 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2741 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2742 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2743 unsigned int spilled_value
2744 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2746 if ((at == 0) && !a0_was_saved)
2748 a0_saved = xtensa_read_register (atreg);
2751 else if ((at == 7) && !a7_was_saved)
2753 a7_saved = xtensa_read_register (atreg);
2756 else if ((at == 11) && !a11_was_saved)
2758 a11_saved = xtensa_read_register (atreg);
2762 xtensa_write_register (atreg, spilled_value);
2765 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2767 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2769 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2770 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2771 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2772 ULONGEST spilled_value = xtensa_read_register (atreg);
2774 write_memory_unsigned_integer (addr, 4,
2775 gdbarch_byte_order (gdbarch),
2779 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2785 xtNoExceptionHandler
2786 } xtensa_exception_handler_t;
2788 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2789 Return type of Xtensa Window Interrupt Handler on success. */
2790 static xtensa_exception_handler_t
2791 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2794 xtensa_insnbuf ins, slot;
2795 gdb_byte ibuf[XTENSA_ISA_BSZ];
2796 CORE_ADDR ia, bt, ba;
2798 int ilen, islots, is;
2801 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2803 uint32_t at, as, offset;
2805 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2806 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2808 isa = xtensa_default_isa;
2809 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2810 ins = xtensa_insnbuf_alloc (isa);
2811 slot = xtensa_insnbuf_alloc (isa);
2820 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2822 if (ia + xtensa_isa_maxlength (isa) > bt)
2825 bt = (ba + XTENSA_ISA_BSZ);
2826 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2827 return xtNoExceptionHandler;
2829 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2830 ifmt = xtensa_format_decode (isa, ins);
2831 if (ifmt == XTENSA_UNDEFINED)
2832 return xtNoExceptionHandler;
2833 ilen = xtensa_format_length (isa, ifmt);
2834 if (ilen == XTENSA_UNDEFINED)
2835 return xtNoExceptionHandler;
2836 islots = xtensa_format_num_slots (isa, ifmt);
2837 if (islots == XTENSA_UNDEFINED)
2838 return xtNoExceptionHandler;
2839 for (is = 0; is < islots; ++is)
2841 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2842 return xtNoExceptionHandler;
2843 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2844 if (opc == XTENSA_UNDEFINED)
2845 return xtNoExceptionHandler;
2846 switch (call0_classify_opcode (isa, opc))
2852 /* We expect none of them here. */
2853 return xtNoExceptionHandler;
2855 func = execute_l32e;
2858 func = execute_s32e;
2860 case c0opc_rfwo: /* RFWO. */
2861 /* Here, we return from WindowOverflow handler and,
2862 if we stopped at the very beginning, which means
2863 A0 was saved, we have to restore it now. */
2866 int arreg = arreg_number (gdbarch,
2867 gdbarch_tdep (gdbarch)->a0_base,
2869 xtensa_write_register (arreg, a0_saved);
2871 return xtWindowOverflow;
2872 case c0opc_rfwu: /* RFWU. */
2873 /* Here, we return from WindowUnderflow handler.
2874 Let's see if either A7 or A11 has to be restored. */
2875 if (WindowUnderflow12)
2879 int arreg = arreg_number (gdbarch,
2880 gdbarch_tdep (gdbarch)->a0_base + 11,
2882 xtensa_write_register (arreg, a11_saved);
2885 else if (a7_was_saved)
2887 int arreg = arreg_number (gdbarch,
2888 gdbarch_tdep (gdbarch)->a0_base + 7,
2890 xtensa_write_register (arreg, a7_saved);
2892 return xtWindowUnderflow;
2893 default: /* Simply skip this insns. */
2897 /* Decode arguments for L32E / S32E and simulate their execution. */
2898 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2899 return xtNoExceptionHandler;
2900 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2901 return xtNoExceptionHandler;
2902 if (xtensa_operand_decode (isa, opc, 0, &at))
2903 return xtNoExceptionHandler;
2904 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2905 return xtNoExceptionHandler;
2906 if (xtensa_operand_decode (isa, opc, 1, &as))
2907 return xtNoExceptionHandler;
2908 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2909 return xtNoExceptionHandler;
2910 if (xtensa_operand_decode (isa, opc, 2, &offset))
2911 return xtNoExceptionHandler;
2913 (*func) (gdbarch, at, as, offset, wb);
2918 return xtNoExceptionHandler;
2921 /* Handle Window Overflow / Underflow exception frames. */
2924 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2925 xtensa_frame_cache_t *cache,
2928 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2929 CORE_ADDR ps, wb, ws, ra;
2930 int epc1_regnum, i, regnum;
2931 xtensa_exception_handler_t eh_type;
2933 /* Read PS, WB, and WS from the hardware. Note that PS register
2934 must be present, if Windowed ABI is supported. */
2935 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2936 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2937 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2939 /* Execute all the remaining instructions from Window Interrupt Handler
2940 by simulating them on the remote protocol level. On return, set the
2941 type of Xtensa Window Interrupt Handler, or report an error. */
2942 eh_type = execute_code (gdbarch, pc, wb);
2943 if (eh_type == xtNoExceptionHandler)
2945 Unable to decode Xtensa Window Interrupt Handler's code."));
2947 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2948 cache->call0 = 0; /* It's Windowed ABI. */
2950 /* All registers for the cached frame will be alive. */
2951 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2952 cache->wd.aregs[i] = -1;
2954 if (eh_type == xtWindowOverflow)
2955 cache->wd.ws = ws ^ (1 << wb);
2956 else /* eh_type == xtWindowUnderflow. */
2957 cache->wd.ws = ws | (1 << wb);
2959 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2960 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2962 ra = xtensa_read_register (regnum);
2963 cache->wd.callsize = WINSIZE (ra);
2964 cache->prev_sp = xtensa_read_register (regnum + 1);
2965 /* Set regnum to a frame pointer of the frame being cached. */
2966 regnum = xtensa_scan_prologue (gdbarch, pc);
2967 regnum = arreg_number (gdbarch,
2968 gdbarch_tdep (gdbarch)->a0_base + regnum,
2970 cache->base = get_frame_register_unsigned (this_frame, regnum);
2972 /* Read PC of interrupted function from EPC1 register. */
2973 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2974 if (epc1_regnum < 0)
2975 error(_("Unable to read Xtensa register EPC1"));
2976 cache->ra = xtensa_read_register (epc1_regnum);
2977 cache->pc = get_frame_func (this_frame);
2981 /* Skip function prologue.
2983 Return the pc of the first instruction after prologue. GDB calls this to
2984 find the address of the first line of the function or (if there is no line
2985 number information) to skip the prologue for planting breakpoints on
2986 function entries. Use debug info (if present) or prologue analysis to skip
2987 the prologue to achieve reliable debugging behavior. For windowed ABI,
2988 only the 'entry' instruction is skipped. It is not strictly necessary to
2989 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2990 backtrace at any point in the prologue, however certain potential hazards
2991 are avoided and a more "normal" debugging experience is ensured by
2992 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2993 For example, if we don't skip the prologue:
2994 - Some args may not yet have been saved to the stack where the debug
2995 info expects to find them (true anyway when only 'entry' is skipped);
2996 - Software breakpoints ('break' instrs) may not have been unplanted
2997 when the prologue analysis is done on initializing the frame cache,
2998 and breaks in the prologue will throw off the analysis.
3000 If we have debug info ( line-number info, in particular ) we simply skip
3001 the code associated with the first function line effectively skipping
3002 the prologue code. It works even in cases like
3005 { int local_var = 1;
3009 because, for this source code, both Xtensa compilers will generate two
3010 separate entries ( with the same line number ) in dwarf line-number
3011 section to make sure there is a boundary between the prologue code and
3012 the rest of the function.
3014 If there is no debug info, we need to analyze the code. */
3016 /* #define DONT_SKIP_PROLOGUE */
3019 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
3021 struct symtab_and_line prologue_sal;
3024 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3026 #if DONT_SKIP_PROLOGUE
3030 /* Try to find first body line from debug info. */
3032 prologue_sal = find_pc_line (start_pc, 0);
3033 if (prologue_sal.line != 0) /* Found debug info. */
3035 /* In Call0, it is possible to have a function with only one instruction
3036 ('ret') resulting from a one-line optimized function that does nothing.
3037 In that case, prologue_sal.end may actually point to the start of the
3038 next function in the text section, causing a breakpoint to be set at
3039 the wrong place. Check, if the end address is within a different
3040 function, and if so return the start PC. We know we have symbol
3045 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
3046 && call0_ret (start_pc, prologue_sal.end))
3049 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3050 if (end_func != start_pc)
3053 return prologue_sal.end;
3056 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3057 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3058 xtensa_alloc_frame_cache (0));
3059 return body_pc != 0 ? body_pc : start_pc;
3062 /* Verify the current configuration. */
3064 xtensa_verify_config (struct gdbarch *gdbarch)
3066 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3069 /* Verify that we got a reasonable number of AREGS. */
3070 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3072 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3075 /* Verify that certain registers exist. */
3077 if (tdep->pc_regnum == -1)
3078 log.printf (_("\n\tpc_regnum: No PC register"));
3079 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3080 log.printf (_("\n\tps_regnum: No PS register"));
3082 if (tdep->isa_use_windowed_registers)
3084 if (tdep->wb_regnum == -1)
3085 log.printf (_("\n\twb_regnum: No WB register"));
3086 if (tdep->ws_regnum == -1)
3087 log.printf (_("\n\tws_regnum: No WS register"));
3088 if (tdep->ar_base == -1)
3089 log.printf (_("\n\tar_base: No AR registers"));
3092 if (tdep->a0_base == -1)
3093 log.printf (_("\n\ta0_base: No Ax registers"));
3096 internal_error (__FILE__, __LINE__,
3097 _("the following are invalid: %s"), log.c_str ());
3101 /* Derive specific register numbers from the array of registers. */
3104 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
3106 xtensa_register_t* rmap;
3107 int n, max_size = 4;
3110 tdep->num_nopriv_regs = 0;
3112 /* Special registers 0..255 (core). */
3113 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3115 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3117 if (rmap->target_number == 0x0020)
3118 tdep->pc_regnum = n;
3119 else if (rmap->target_number == 0x0100)
3121 else if (rmap->target_number == 0x0000)
3123 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3124 tdep->wb_regnum = n;
3125 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3126 tdep->ws_regnum = n;
3127 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3128 tdep->debugcause_regnum = n;
3129 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3130 tdep->exccause_regnum = n;
3131 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3132 tdep->excvaddr_regnum = n;
3133 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3134 tdep->lbeg_regnum = n;
3135 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3136 tdep->lend_regnum = n;
3137 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3138 tdep->lcount_regnum = n;
3139 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3140 tdep->sar_regnum = n;
3141 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3142 tdep->litbase_regnum = n;
3143 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3144 tdep->ps_regnum = n;
3146 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3147 tdep->interrupt_regnum = n;
3148 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3149 tdep->interrupt2_regnum = n;
3150 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3151 tdep->cpenable_regnum = n;
3154 if (rmap->byte_size > max_size)
3155 max_size = rmap->byte_size;
3156 if (rmap->mask != 0 && tdep->num_regs == 0)
3158 /* Find out out how to deal with priveleged registers.
3160 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3161 && tdep->num_nopriv_regs == 0)
3162 tdep->num_nopriv_regs = n;
3164 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3165 && tdep->num_regs == 0)
3169 /* Number of pseudo registers. */
3170 tdep->num_pseudo_regs = n - tdep->num_regs;
3172 /* Empirically determined maximum sizes. */
3173 tdep->max_register_raw_size = max_size;
3174 tdep->max_register_virtual_size = max_size;
3177 /* Module "constructor" function. */
3179 extern struct gdbarch_tdep xtensa_tdep;
3181 static struct gdbarch *
3182 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3184 struct gdbarch_tdep *tdep;
3185 struct gdbarch *gdbarch;
3187 DEBUGTRACE ("gdbarch_init()\n");
3189 /* We have to set the byte order before we call gdbarch_alloc. */
3190 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3192 tdep = &xtensa_tdep;
3193 gdbarch = gdbarch_alloc (&info, tdep);
3194 xtensa_derive_tdep (tdep);
3196 /* Verify our configuration. */
3197 xtensa_verify_config (gdbarch);
3198 xtensa_session_once_reported = 0;
3200 /* Pseudo-Register read/write. */
3201 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3202 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3204 /* Set target information. */
3205 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3206 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3207 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3208 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3209 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3211 /* Renumber registers for known formats (stabs and dwarf2). */
3212 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3213 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3215 /* We provide our own function to get register information. */
3216 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3217 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3219 /* To call functions from GDB using dummy frame. */
3220 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3222 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3224 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3226 /* Advance PC across any prologue instructions to reach "real" code. */
3227 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3229 /* Stack grows downward. */
3230 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3232 /* Set breakpoints. */
3233 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3234 xtensa_breakpoint_kind_from_pc);
3235 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3236 xtensa_sw_breakpoint_from_kind);
3238 /* After breakpoint instruction or illegal instruction, pc still
3239 points at break instruction, so don't decrement. */
3240 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3242 /* We don't skip args. */
3243 set_gdbarch_frame_args_skip (gdbarch, 0);
3245 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3247 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3249 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3251 /* Frame handling. */
3252 frame_base_set_default (gdbarch, &xtensa_frame_base);
3253 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3254 dwarf2_append_unwinders (gdbarch);
3256 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3258 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3260 xtensa_add_reggroups (gdbarch);
3261 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3263 set_gdbarch_iterate_over_regset_sections
3264 (gdbarch, xtensa_iterate_over_regset_sections);
3266 set_solib_svr4_fetch_link_map_offsets
3267 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3269 /* Hook in the ABI-specific overrides, if they have been registered. */
3270 gdbarch_init_osabi (info, gdbarch);
3276 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3278 error (_("xtensa_dump_tdep(): not implemented"));
3281 /* Provide a prototype to silence -Wmissing-prototypes. */
3282 extern initialize_file_ftype _initialize_xtensa_tdep;
3285 _initialize_xtensa_tdep (void)
3287 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3288 xtensa_init_reggroups ();
3290 add_setshow_zuinteger_cmd ("xtensa",
3292 &xtensa_debug_level,
3293 _("Set Xtensa debugging."),
3294 _("Show Xtensa debugging."), _("\
3295 When non-zero, Xtensa-specific debugging is enabled. \
3296 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3299 &setdebuglist, &showdebuglist);