1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010-2013 Free Software Foundation, Inc.
4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
40 #include "glibc-tdep.h"
43 #include "tramp-frame.h"
44 #include "linux-tdep.h"
47 #include "gdb_assert.h"
49 #include "tic6x-tdep.h"
51 #include "target-descriptions.h"
53 #include "features/tic6x-c64xp.c"
54 #include "features/tic6x-c64x.c"
55 #include "features/tic6x-c62x.c"
57 #define TIC6X_OPCODE_SIZE 4
58 #define TIC6X_FETCH_PACKET_SIZE 32
60 #define INST_S_BIT(INST) ((INST >> 1) & 1)
61 #define INST_X_BIT(INST) ((INST >> 12) & 1)
63 const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
64 const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };
66 struct tic6x_unwind_cache
68 /* The frame's base, optionally used by the high-level debug info. */
71 /* The previous frame's inner most stack address. Used as this
72 frame ID's stack_addr. */
75 /* The address of the first instruction in this function */
78 /* Which register holds the return address for the frame. */
81 /* The offset of register saved on stack. If register is not saved, the
82 corresponding element is -1. */
83 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
87 /* Name of TI C6x core registers. */
88 static const char *const tic6x_register_names[] =
90 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
91 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
92 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
93 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
94 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
95 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
96 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
97 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
98 "CSR", "PC", /* 32 33 */
101 /* This array maps the arguments to the register number which passes argument
102 in function call according to C6000 ELF ABI. */
103 static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
105 /* This is the implementation of gdbarch method register_name. */
108 tic6x_register_name (struct gdbarch *gdbarch, int regno)
113 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
114 return tdesc_register_name (gdbarch, regno);
115 else if (regno >= ARRAY_SIZE (tic6x_register_names))
118 return tic6x_register_names[regno];
121 /* This is the implementation of gdbarch method register_type. */
124 tic6x_register_type (struct gdbarch *gdbarch, int regno)
127 if (regno == TIC6X_PC_REGNUM)
128 return builtin_type (gdbarch)->builtin_func_ptr;
130 return builtin_type (gdbarch)->builtin_uint32;
134 tic6x_setup_default (struct tic6x_unwind_cache *cache)
138 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
139 cache->reg_saved[i] = -1;
142 static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
143 static int tic6x_register_number (int reg, int side, int crosspath);
145 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
146 Bail out early if CURRENT_PC is reached. Returns the address of the first
147 instruction after the prologue. */
150 tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
151 const CORE_ADDR current_pc,
152 struct tic6x_unwind_cache *cache,
153 struct frame_info *this_frame)
155 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
157 unsigned int src_reg, base_reg, dst_reg;
159 CORE_ADDR pc = start_pc;
160 CORE_ADDR return_pc = start_pc;
161 int frame_base_offset_to_sp = 0;
162 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
163 int non_stw_insn_counter = 0;
165 if (start_pc >= current_pc)
166 return_pc = current_pc;
170 /* The landmarks in prologue is one or two SUB instructions to SP.
171 Instructions on setting up dsbt are in the last part of prologue, if
172 needed. In maxim, prologue can be divided to three parts by two
173 `sub sp, xx, sp' insns. */
175 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
176 2nd one is optional. */
177 while (pc < current_pc)
181 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
183 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
184 || (inst & 0x0ffc) == 0x9c0)
186 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
187 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
188 INST_S_BIT (inst), 0);
189 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
190 INST_S_BIT (inst), 0);
192 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
194 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
195 offset. The constant offset is decoded in bit 13-17 in all
196 these three kinds of instructions. */
197 unsigned int ucst5 = (inst >> 13) & 0x1f;
199 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */
200 frame_base_offset_to_sp += ucst5 << 2;
201 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */
202 frame_base_offset_to_sp += ucst5 << 1;
203 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */
204 frame_base_offset_to_sp += ucst5;
206 gdb_assert_not_reached ("unexpected instruction");
211 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
213 /* The y bit determines which file base is read from. */
214 base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
217 if (base_reg == TIC6X_SP_REGNUM)
219 src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
220 INST_S_BIT (inst), 0);
222 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;
226 non_stw_insn_counter = 0;
230 non_stw_insn_counter++;
231 /* Following instruction sequence may be emitted in prologue:
233 <+0>: subah .D2 b15,28,b15
234 <+4>: or .L2X 0,a4,b0
235 <+8>: || stw .D2T2 b14,*+b15(56)
236 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
237 <+16>:|| stw .D2T1 a10,*+b15(48)
238 <+20>:stw .D2T2 b3,*+b15(52)
239 <+24>:stw .D2T1 a4,*+b15(40)
241 we should look forward for next instruction instead of breaking loop
242 here. So far, we allow almost two sequential non-stw instructions
244 if (non_stw_insn_counter >= 2)
251 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
252 ldw .D2T2 *+b14(0),b14 */
253 inst = tic6x_fetch_instruction (gdbarch, pc);
254 /* The s bit determines which file dst will be loaded into, same effect as
256 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
257 /* The y bit (bit 7), instead of s bit, determines which file base be
259 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);
261 if ((inst & 0x164) == 0x64 /* ldw */
262 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */
263 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */
270 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
272 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
274 /* If the FP now holds an offset from the CFA then this is a frame
275 which uses the frame pointer. */
277 cache->cfa = get_frame_register_unsigned (this_frame,
282 /* FP doesn't hold an offset from the CFA. If SP still holds an
283 offset from the CFA then we might be in a function which omits
284 the frame pointer. */
286 cache->cfa = cache->base + frame_base_offset_to_sp;
290 /* Adjust all the saved registers such that they contain addresses
291 instead of offsets. */
292 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
293 if (cache->reg_saved[i] != -1)
294 cache->reg_saved[i] = cache->base + cache->reg_saved[i];
299 /* This is the implementation of gdbarch method skip_prologue. */
302 tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
305 struct tic6x_unwind_cache cache;
307 /* See if we can determine the end of the prologue via the symbol table.
308 If so, then return either PC, or the PC after the prologue, whichever is
310 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
312 CORE_ADDR post_prologue_pc
313 = skip_prologue_using_sal (gdbarch, func_addr);
314 if (post_prologue_pc != 0)
315 return max (start_pc, post_prologue_pc);
318 /* Can't determine prologue from the symbol table, need to examine
320 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
324 /* This is the implementation of gdbarch method breakpiont_from_pc. */
326 static const gdb_byte *
327 tic6x_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 if (tdep == NULL || tdep->breakpoint == NULL)
336 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
337 return tic6x_bkpt_illegal_opcode_be;
339 return tic6x_bkpt_illegal_opcode_le;
342 return tdep->breakpoint;
345 /* This is the implementation of gdbarch method print_insn. */
348 tic6x_print_insn (bfd_vma memaddr, disassemble_info *info)
350 return print_insn_tic6x (memaddr, info);
354 tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
355 struct dwarf2_frame_state_reg *reg,
356 struct frame_info *this_frame)
358 /* Mark the PC as the destination for the return address. */
359 if (regnum == gdbarch_pc_regnum (gdbarch))
360 reg->how = DWARF2_FRAME_REG_RA;
362 /* Mark the stack pointer as the call frame address. */
363 else if (regnum == gdbarch_sp_regnum (gdbarch))
364 reg->how = DWARF2_FRAME_REG_CFA;
366 /* The above was taken from the default init_reg in dwarf2-frame.c
367 while the below is c6x specific. */
369 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
371 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
372 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
374 /* All other registers are caller-save. */
375 reg->how = DWARF2_FRAME_REG_UNDEFINED;
378 /* This is the implementation of gdbarch method unwind_pc. */
381 tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
385 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf);
386 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
389 /* This is the implementation of gdbarch method unwind_sp. */
392 tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
394 return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM);
398 /* Frame base handling. */
400 static struct tic6x_unwind_cache*
401 tic6x_frame_unwind_cache (struct frame_info *this_frame,
402 void **this_prologue_cache)
404 struct gdbarch *gdbarch = get_frame_arch (this_frame);
405 CORE_ADDR current_pc;
406 struct tic6x_unwind_cache *cache;
408 if (*this_prologue_cache)
409 return *this_prologue_cache;
411 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
412 (*this_prologue_cache) = cache;
414 cache->return_regnum = TIC6X_RA_REGNUM;
416 tic6x_setup_default (cache);
418 cache->pc = get_frame_func (this_frame);
419 current_pc = get_frame_pc (this_frame);
421 /* Prologue analysis does the rest... */
423 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
429 tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
430 struct frame_id *this_id)
432 struct tic6x_unwind_cache *cache =
433 tic6x_frame_unwind_cache (this_frame, this_cache);
435 /* This marks the outermost frame. */
436 if (cache->base == 0)
439 (*this_id) = frame_id_build (cache->cfa, cache->pc);
442 static struct value *
443 tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
446 struct tic6x_unwind_cache *cache =
447 tic6x_frame_unwind_cache (this_frame, this_cache);
449 gdb_assert (regnum >= 0);
451 /* The PC of the previous frame is stored in the RA register of
452 the current frame. Frob regnum so that we pull the value from
453 the correct place. */
454 if (regnum == TIC6X_PC_REGNUM)
455 regnum = cache->return_regnum;
457 if (regnum == TIC6X_SP_REGNUM && cache->cfa)
458 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
460 /* If we've worked out where a register is stored then load it from
462 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
463 return frame_unwind_got_memory (this_frame, regnum,
464 cache->reg_saved[regnum]);
466 return frame_unwind_got_register (this_frame, regnum, regnum);
470 tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
472 struct tic6x_unwind_cache *info
473 = tic6x_frame_unwind_cache (this_frame, this_cache);
477 static const struct frame_unwind tic6x_frame_unwind =
480 default_frame_unwind_stop_reason,
482 tic6x_frame_prev_register,
484 default_frame_sniffer
487 static const struct frame_base tic6x_frame_base =
490 tic6x_frame_base_address,
491 tic6x_frame_base_address,
492 tic6x_frame_base_address
496 static struct tic6x_unwind_cache *
497 tic6x_make_stub_cache (struct frame_info *this_frame)
499 struct tic6x_unwind_cache *cache;
501 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
503 cache->return_regnum = TIC6X_RA_REGNUM;
505 tic6x_setup_default (cache);
507 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
513 tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
514 struct frame_id *this_id)
516 struct tic6x_unwind_cache *cache;
518 if (*this_cache == NULL)
519 *this_cache = tic6x_make_stub_cache (this_frame);
522 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
526 tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
527 struct frame_info *this_frame,
528 void **this_prologue_cache)
530 CORE_ADDR addr_in_block;
532 addr_in_block = get_frame_address_in_block (this_frame);
533 if (in_plt_section (addr_in_block, NULL))
539 static const struct frame_unwind tic6x_stub_unwind =
542 default_frame_unwind_stop_reason,
544 tic6x_frame_prev_register,
546 tic6x_stub_unwind_sniffer
549 /* Return the instruction on address PC. */
552 tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
554 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
555 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
558 /* Compute the condition of INST if it is a conditional instruction. Always
559 return 1 if INST is not a conditional instruction. */
562 tic6x_condition_true (struct frame_info *frame, unsigned long inst)
566 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
568 register_number = register_numbers[(inst >> 29) & 7];
569 if (register_number == -1)
572 register_value = get_frame_register_signed (frame, register_number);
573 if ((inst & 0x10000000) != 0)
574 return register_value == 0;
575 return register_value != 0;
578 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
582 tic6x_register_number (int reg, int side, int crosspath)
584 int r = (reg & 15) | ((crosspath ^ side) << 4);
585 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
591 tic6x_extract_signed_field (int value, int low_bit, int bits)
593 int mask = (1 << bits) - 1;
594 int r = (value >> low_bit) & mask;
595 if ((r & (1 << (bits - 1))) != 0)
600 /* Determine where to set a single step breakpoint. */
603 tic6x_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
605 struct gdbarch *gdbarch = get_frame_arch (frame);
612 inst = tic6x_fetch_instruction (gdbarch, pc);
616 if (inst == TIC6X_INST_SWE)
618 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
620 if (tdep->syscall_next_pc != NULL)
621 return tdep->syscall_next_pc (frame);
624 if (tic6x_condition_true (frame, inst))
626 if ((inst & 0x0000007c) == 0x00000010)
628 /* B with displacement */
629 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
630 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
633 if ((inst & 0x0f83effc) == 0x00000360)
635 /* B with register */
637 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
640 pc = get_frame_register_unsigned (frame, register_number);
643 if ((inst & 0x00001ffc) == 0x00001020)
646 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
647 INST_S_BIT (inst), 0);
648 if (get_frame_register_signed (frame, register_number) >= 0)
650 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
651 pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
655 if ((inst & 0x00001ffc) == 0x00000120)
657 /* BNOP with displacement */
658 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
659 pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
662 if ((inst & 0x0f830ffe) == 0x00800362)
664 /* BNOP with register */
665 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
666 1, INST_X_BIT (inst));
667 pc = get_frame_register_unsigned (frame, register_number);
670 if ((inst & 0x00001ffc) == 0x00000020)
673 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
674 INST_S_BIT (inst), 0);
675 if (get_frame_register_signed (frame, register_number) >= 0)
677 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
678 pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
682 if ((inst & 0xf000007c) == 0x10000010)
685 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
686 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
690 pc += TIC6X_OPCODE_SIZE;
696 /* This is the implementation of gdbarch method software_single_step. */
699 tic6x_software_single_step (struct frame_info *frame)
701 struct gdbarch *gdbarch = get_frame_arch (frame);
702 struct address_space *aspace = get_frame_address_space (frame);
703 CORE_ADDR next_pc = tic6x_get_next_pc (frame, get_frame_pc (frame));
705 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
710 /* This is the implementation of gdbarch method frame_align. */
713 tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
715 return align_down (addr, 8);
718 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
719 value into VALBUF. */
722 tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
723 enum bfd_endian byte_order, gdb_byte *valbuf)
725 int len = TYPE_LENGTH (valtype);
727 /* pointer types are returned in register A4,
728 up to 32-bit types in A4
729 up to 64-bit types in A5:A4 */
733 - one-byte structure or union occupies the LSB of single even register.
734 - for two-byte structure or union, the first byte occupies byte 1 of
735 register and the second byte occupies byte 0.
736 so, we read the contents in VAL from the LSBs of register. */
737 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
738 regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
741 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
745 /* For a 5-8 byte structure or union in big-endian, the first byte
746 occupies byte 3 (the MSB) of the upper (odd) register and the
747 remaining bytes fill the decreasingly significant bytes. 5-7
748 byte structures or unions have padding in the LSBs of the
749 lower (even) register. */
750 if (byte_order == BFD_ENDIAN_BIG)
752 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4);
753 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf);
757 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
758 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4);
763 /* Write into appropriate registers a function return value
764 of type TYPE, given in virtual format. */
767 tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
768 enum bfd_endian byte_order, const gdb_byte *valbuf)
770 int len = TYPE_LENGTH (valtype);
772 /* return values of up to 8 bytes are returned in A5:A4 */
776 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
777 regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
780 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
784 if (byte_order == BFD_ENDIAN_BIG)
786 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4);
787 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf);
791 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
792 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4);
797 /* This is the implementation of gdbarch method return_value. */
799 static enum return_value_convention
800 tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
801 struct type *type, struct regcache *regcache,
802 gdb_byte *readbuf, const gdb_byte *writebuf)
804 /* In C++, when function returns an object, even its size is small
805 enough, it stii has to be passed via reference, pointed by register
807 if (current_language->la_language == language_cplus)
811 CHECK_TYPEDEF (type);
812 if (language_pass_by_reference (type))
813 return RETURN_VALUE_STRUCT_CONVENTION;
817 if (TYPE_LENGTH (type) > 8)
818 return RETURN_VALUE_STRUCT_CONVENTION;
821 tic6x_extract_return_value (type, regcache,
822 gdbarch_byte_order (gdbarch), readbuf);
824 tic6x_store_return_value (type, regcache,
825 gdbarch_byte_order (gdbarch), writebuf);
827 return RETURN_VALUE_REGISTER_CONVENTION;
830 /* This is the implementation of gdbarch method dummy_id. */
832 static struct frame_id
833 tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
835 return frame_id_build
836 (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM),
837 get_frame_pc (this_frame));
840 /* Get the alignment requirement of TYPE. */
843 tic6x_arg_type_alignment (struct type *type)
845 int len = TYPE_LENGTH (check_typedef (type));
846 enum type_code typecode = TYPE_CODE (check_typedef (type));
848 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
850 /* The stack alignment of a structure (and union) passed by value is the
851 smallest power of two greater than or equal to its size.
852 This cannot exceed 8 bytes, which is the largest allowable size for
853 a structure passed by value. */
862 gdb_assert_not_reached ("unexpected length of data");
870 if (typecode == TYPE_CODE_COMPLEX)
877 if (typecode == TYPE_CODE_COMPLEX)
883 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
888 /* This is the implementation of gdbarch method push_dummy_call. */
891 tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
892 struct regcache *regcache, CORE_ADDR bp_addr,
893 int nargs, struct value **args, CORE_ADDR sp,
894 int struct_return, CORE_ADDR struct_addr)
898 int stack_offset = 4;
899 int references_offset = 4;
900 CORE_ADDR func_addr = find_function_addr (function, NULL);
901 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
902 struct type *func_type = value_type (function);
903 /* The first arg passed on stack. Mostly the first 10 args are passed by
905 int first_arg_on_stack = 10;
907 /* Set the return address register to point to the entry point of
908 the program, where a breakpoint lies in wait. */
909 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);
911 /* The caller must pass an argument in A3 containing a destination address
912 for the returned value. The callee returns the object by copying it to
913 the address in A3. */
915 regcache_cooked_write_unsigned (regcache, 3, struct_addr);
917 /* Determine the type of this function. */
918 func_type = check_typedef (func_type);
919 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
920 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
922 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
923 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
925 /* For a variadic C function, the last explicitly declared argument and all
926 remaining arguments are passed on the stack. */
927 if (TYPE_VARARGS (func_type))
928 first_arg_on_stack = TYPE_NFIELDS (func_type) - 1;
930 /* Now make space on the stack for the args. */
931 for (argnum = 0; argnum < nargs; argnum++)
933 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
934 if (argnum >= 10 - argreg)
935 references_offset += len;
939 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
941 sp = align_down (sp, 8);
944 /* Now load as many as possible of the first arguments into
945 registers, and push the rest onto the stack. Loop through args
946 from first to last. */
947 for (argnum = 0; argnum < nargs; argnum++)
950 struct value *arg = args[argnum];
951 struct type *arg_type = check_typedef (value_type (arg));
952 int len = TYPE_LENGTH (arg_type);
953 enum type_code typecode = TYPE_CODE (arg_type);
955 val = value_contents (arg);
957 /* Copy the argument to general registers or the stack in
958 register-sized pieces. */
959 if (argreg < first_arg_on_stack)
963 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
966 - one-byte structure or union occupies the LSB of single
968 - for two-byte structure or union, the first byte
969 occupies byte 1 of register and the second byte occupies
971 so, we write the contents in VAL to the lsp of
973 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
974 regcache_cooked_write_part (regcache, arg_regs[argreg],
977 regcache_cooked_write (regcache, arg_regs[argreg], val);
981 /* The argument is being passed by value in a single
983 CORE_ADDR regval = extract_unsigned_integer (val, len,
986 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
994 if (typecode == TYPE_CODE_STRUCT
995 || typecode == TYPE_CODE_UNION)
997 /* For a 5-8 byte structure or union in big-endian, the
998 first byte occupies byte 3 (the MSB) of the upper (odd)
999 register and the remaining bytes fill the decreasingly
1000 significant bytes. 5-7 byte structures or unions have
1001 padding in the LSBs of the lower (even) register. */
1002 if (byte_order == BFD_ENDIAN_BIG)
1004 regcache_cooked_write (regcache,
1005 arg_regs[argreg] + 1, val);
1006 regcache_cooked_write_part (regcache,
1007 arg_regs[argreg], 0,
1012 regcache_cooked_write (regcache, arg_regs[argreg],
1014 regcache_cooked_write_part (regcache,
1015 arg_regs[argreg] + 1, 0,
1021 /* The argument is being passed by value in a pair of
1023 ULONGEST regval = extract_unsigned_integer (val, len,
1026 regcache_cooked_write_unsigned (regcache,
1029 regcache_cooked_write_unsigned (regcache,
1030 arg_regs[argreg] + 1,
1036 /* The argument is being passed by reference in a single
1040 /* It is not necessary to adjust REFERENCES_OFFSET to
1041 8-byte aligned in some cases, in which 4-byte alignment
1042 is sufficient. For simplicity, we adjust
1043 REFERENCES_OFFSET to 8-byte aligned. */
1044 references_offset = align_up (references_offset, 8);
1046 addr = sp + references_offset;
1047 write_memory (addr, val, len);
1048 references_offset += align_up (len, 4);
1049 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
1057 /* The argument is being passed on the stack. */
1060 /* There are six different cases of alignment, and these rules can
1061 be found in tic6x_arg_type_alignment:
1063 1) 4-byte aligned if size is less than or equal to 4 byte, such
1064 as short, int, struct, union etc.
1065 2) 8-byte aligned if size is less than or equal to 8-byte, such
1066 as double, long long,
1067 3) 4-byte aligned if it is of type _Complex float, even its size
1069 4) 8-byte aligned if it is of type _Complex double or _Complex
1070 long double, even its size is 16-byte. Because, the address of
1071 variable is passed as reference.
1072 5) struct and union larger than 8-byte are passed by reference, so
1073 it is 4-byte aligned.
1074 6) struct and union of size between 4 byte and 8 byte varies.
1075 alignment of struct variable is the alignment of its first field,
1076 while alignment of union variable is the max of all its fields'
1080 ; /* Default is 4-byte aligned. Nothing to be done. */
1082 stack_offset = align_up (stack_offset,
1083 tic6x_arg_type_alignment (arg_type));
1086 /* _Complex double or _Complex long double */
1087 if (typecode == TYPE_CODE_COMPLEX)
1089 /* The argument is being passed by reference on stack. */
1091 references_offset = align_up (references_offset, 8);
1093 addr = sp + references_offset;
1094 /* Store variable on stack. */
1095 write_memory (addr, val, len);
1097 references_offset += align_up (len, 4);
1099 /* Pass the address of variable on stack as reference. */
1100 store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
1106 internal_error (__FILE__, __LINE__,
1107 _("unexpected type %d of arg %d"),
1111 internal_error (__FILE__, __LINE__,
1112 _("unexpected length %d of arg %d"), len, argnum);
1114 addr = sp + stack_offset;
1115 write_memory (addr, val, len);
1116 stack_offset += align_up (len, 4);
1120 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);
1122 /* Return adjusted stack pointer. */
1126 /* This is the implementation of gdbarch method in_function_epilogue_p. */
1129 tic6x_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1131 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
1132 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1133 if ((inst & 0x0f83effc) == 0x360)
1135 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
1138 if (src2 == TIC6X_RA_REGNUM)
1145 /* This is the implementation of gdbarch method get_longjmp_target. */
1148 tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1150 struct gdbarch *gdbarch = get_frame_arch (frame);
1151 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1155 /* JMP_BUF is passed by reference in A4. */
1156 jb_addr = get_frame_register_unsigned (frame, 4);
1158 /* JMP_BUF contains 13 elements of type int, and return address is stored
1159 in the last slot. */
1160 if (target_read_memory (jb_addr + 12 * 4, buf, 4))
1163 *pc = extract_unsigned_integer (buf, 4, byte_order);
1168 /* This is the implementation of gdbarch method
1169 return_in_first_hidden_param_p. */
1172 tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
1178 static struct gdbarch *
1179 tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1181 struct gdbarch *gdbarch;
1182 struct gdbarch_tdep *tdep;
1183 struct tdesc_arch_data *tdesc_data = NULL;
1184 const struct target_desc *tdesc = info.target_desc;
1187 /* Check any target description for validity. */
1188 if (tdesc_has_registers (tdesc))
1190 const struct tdesc_feature *feature;
1193 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");
1195 if (feature == NULL)
1198 tdesc_data = tdesc_data_alloc ();
1201 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */
1202 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1203 tic6x_register_names[i]);
1206 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1207 tic6x_register_names[TIC6X_CSR_REGNUM]);
1208 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1209 tic6x_register_names[TIC6X_PC_REGNUM]);
1213 tdesc_data_cleanup (tdesc_data);
1217 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
1221 static const char *const gp[] =
1223 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1224 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1225 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1226 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1231 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */
1232 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1237 tdesc_data_cleanup (tdesc_data);
1242 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
1245 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR");
1246 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC");
1247 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC");
1251 tdesc_data_cleanup (tdesc_data);
1258 /* Find a candidate among extant architectures. */
1259 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1261 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1263 tdep = gdbarch_tdep (arches->gdbarch);
1265 if (has_gp != tdep->has_gp)
1268 if (tdep && tdep->breakpoint)
1269 return arches->gdbarch;
1272 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
1274 tdep->has_gp = has_gp;
1275 gdbarch = gdbarch_alloc (&info, tdep);
1277 /* Data type sizes. */
1278 set_gdbarch_ptr_bit (gdbarch, 32);
1279 set_gdbarch_addr_bit (gdbarch, 32);
1280 set_gdbarch_short_bit (gdbarch, 16);
1281 set_gdbarch_int_bit (gdbarch, 32);
1282 set_gdbarch_long_bit (gdbarch, 32);
1283 set_gdbarch_long_long_bit (gdbarch, 64);
1284 set_gdbarch_float_bit (gdbarch, 32);
1285 set_gdbarch_double_bit (gdbarch, 64);
1287 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1288 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1290 /* The register set. */
1291 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
1292 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
1293 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);
1295 set_gdbarch_register_name (gdbarch, tic6x_register_name);
1296 set_gdbarch_register_type (gdbarch, tic6x_register_type);
1298 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1300 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
1301 set_gdbarch_breakpoint_from_pc (gdbarch, tic6x_breakpoint_from_pc);
1303 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
1304 set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp);
1307 dwarf2_append_unwinders (gdbarch);
1309 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
1310 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
1312 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);
1314 /* Single stepping. */
1315 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);
1317 set_gdbarch_print_insn (gdbarch, tic6x_print_insn);
1319 /* Call dummy code. */
1320 set_gdbarch_frame_align (gdbarch, tic6x_frame_align);
1322 set_gdbarch_return_value (gdbarch, tic6x_return_value);
1324 set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id);
1326 /* Enable inferior call support. */
1327 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);
1329 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);
1331 set_gdbarch_in_function_epilogue_p (gdbarch, tic6x_in_function_epilogue_p);
1333 set_gdbarch_return_in_first_hidden_param_p (gdbarch,
1334 tic6x_return_in_first_hidden_param_p);
1336 /* Hook in ABI-specific overrides, if they have been registered. */
1337 gdbarch_init_osabi (info, gdbarch);
1340 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1345 /* -Wmissing-prototypes */
1346 extern initialize_file_ftype _initialize_tic6x_tdep;
1349 _initialize_tic6x_tdep (void)
1351 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);
1353 initialize_tdesc_tic6x_c64xp ();
1354 initialize_tdesc_tic6x_c64x ();
1355 initialize_tdesc_tic6x_c62x ();