1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010-2017 Free Software Foundation, Inc.
4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
38 #include "arch-utils.h"
39 #include "glibc-tdep.h"
42 #include "tramp-frame.h"
43 #include "linux-tdep.h"
47 #include "tic6x-tdep.h"
49 #include "target-descriptions.h"
52 #define TIC6X_OPCODE_SIZE 4
53 #define TIC6X_FETCH_PACKET_SIZE 32
55 #define INST_S_BIT(INST) ((INST >> 1) & 1)
56 #define INST_X_BIT(INST) ((INST >> 12) & 1)
58 const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
59 const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };
61 struct tic6x_unwind_cache
63 /* The frame's base, optionally used by the high-level debug info. */
66 /* The previous frame's inner most stack address. Used as this
67 frame ID's stack_addr. */
70 /* The address of the first instruction in this function */
73 /* Which register holds the return address for the frame. */
76 /* The offset of register saved on stack. If register is not saved, the
77 corresponding element is -1. */
78 CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
82 /* Name of TI C6x core registers. */
83 static const char *const tic6x_register_names[] =
85 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
86 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
87 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
88 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
89 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
90 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
91 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
92 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
93 "CSR", "PC", /* 32 33 */
96 /* This array maps the arguments to the register number which passes argument
97 in function call according to C6000 ELF ABI. */
98 static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
100 /* This is the implementation of gdbarch method register_name. */
103 tic6x_register_name (struct gdbarch *gdbarch, int regno)
108 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
109 return tdesc_register_name (gdbarch, regno);
110 else if (regno >= ARRAY_SIZE (tic6x_register_names))
113 return tic6x_register_names[regno];
116 /* This is the implementation of gdbarch method register_type. */
119 tic6x_register_type (struct gdbarch *gdbarch, int regno)
122 if (regno == TIC6X_PC_REGNUM)
123 return builtin_type (gdbarch)->builtin_func_ptr;
125 return builtin_type (gdbarch)->builtin_uint32;
129 tic6x_setup_default (struct tic6x_unwind_cache *cache)
133 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
134 cache->reg_saved[i] = -1;
137 static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
138 static int tic6x_register_number (int reg, int side, int crosspath);
140 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
141 Bail out early if CURRENT_PC is reached. Returns the address of the first
142 instruction after the prologue. */
145 tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
146 const CORE_ADDR current_pc,
147 struct tic6x_unwind_cache *cache,
148 struct frame_info *this_frame)
151 unsigned int src_reg, base_reg, dst_reg;
153 CORE_ADDR pc = start_pc;
154 CORE_ADDR return_pc = start_pc;
155 int frame_base_offset_to_sp = 0;
156 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
157 int non_stw_insn_counter = 0;
159 if (start_pc >= current_pc)
160 return_pc = current_pc;
164 /* The landmarks in prologue is one or two SUB instructions to SP.
165 Instructions on setting up dsbt are in the last part of prologue, if
166 needed. In maxim, prologue can be divided to three parts by two
167 `sub sp, xx, sp' insns. */
169 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
170 2nd one is optional. */
171 while (pc < current_pc)
173 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
175 if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
176 || (inst & 0x0ffc) == 0x9c0)
178 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
179 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
180 INST_S_BIT (inst), 0);
181 unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
182 INST_S_BIT (inst), 0);
184 if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
186 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
187 offset. The constant offset is decoded in bit 13-17 in all
188 these three kinds of instructions. */
189 unsigned int ucst5 = (inst >> 13) & 0x1f;
191 if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */
192 frame_base_offset_to_sp += ucst5 << 2;
193 else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */
194 frame_base_offset_to_sp += ucst5 << 1;
195 else if ((inst & 0x0ffc) == 0x9c0) /* SUB */
196 frame_base_offset_to_sp += ucst5;
198 gdb_assert_not_reached ("unexpected instruction");
203 else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
205 /* The y bit determines which file base is read from. */
206 base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
209 if (base_reg == TIC6X_SP_REGNUM)
211 src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
212 INST_S_BIT (inst), 0);
214 cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;
218 non_stw_insn_counter = 0;
222 non_stw_insn_counter++;
223 /* Following instruction sequence may be emitted in prologue:
225 <+0>: subah .D2 b15,28,b15
226 <+4>: or .L2X 0,a4,b0
227 <+8>: || stw .D2T2 b14,*+b15(56)
228 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
229 <+16>:|| stw .D2T1 a10,*+b15(48)
230 <+20>:stw .D2T2 b3,*+b15(52)
231 <+24>:stw .D2T1 a4,*+b15(40)
233 we should look forward for next instruction instead of breaking loop
234 here. So far, we allow almost two sequential non-stw instructions
236 if (non_stw_insn_counter >= 2)
243 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
244 ldw .D2T2 *+b14(0),b14 */
245 inst = tic6x_fetch_instruction (gdbarch, pc);
246 /* The s bit determines which file dst will be loaded into, same effect as
248 dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
249 /* The y bit (bit 7), instead of s bit, determines which file base be
251 base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);
253 if ((inst & 0x164) == 0x64 /* ldw */
254 && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */
255 && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */
262 cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
264 if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
266 /* If the FP now holds an offset from the CFA then this is a frame
267 which uses the frame pointer. */
269 cache->cfa = get_frame_register_unsigned (this_frame,
274 /* FP doesn't hold an offset from the CFA. If SP still holds an
275 offset from the CFA then we might be in a function which omits
276 the frame pointer. */
278 cache->cfa = cache->base + frame_base_offset_to_sp;
282 /* Adjust all the saved registers such that they contain addresses
283 instead of offsets. */
284 for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
285 if (cache->reg_saved[i] != -1)
286 cache->reg_saved[i] = cache->base + cache->reg_saved[i];
291 /* This is the implementation of gdbarch method skip_prologue. */
294 tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
297 struct tic6x_unwind_cache cache;
299 /* See if we can determine the end of the prologue via the symbol table.
300 If so, then return either PC, or the PC after the prologue, whichever is
302 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
304 CORE_ADDR post_prologue_pc
305 = skip_prologue_using_sal (gdbarch, func_addr);
306 if (post_prologue_pc != 0)
307 return std::max (start_pc, post_prologue_pc);
310 /* Can't determine prologue from the symbol table, need to examine
312 return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
316 /* Implement the breakpoint_kind_from_pc gdbarch method. */
319 tic6x_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
324 /* Implement the sw_breakpoint_from_kind gdbarch method. */
326 static const gdb_byte *
327 tic6x_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
329 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
333 if (tdep == NULL || tdep->breakpoint == NULL)
335 if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
336 return tic6x_bkpt_illegal_opcode_be;
338 return tic6x_bkpt_illegal_opcode_le;
341 return tdep->breakpoint;
345 tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
346 struct dwarf2_frame_state_reg *reg,
347 struct frame_info *this_frame)
349 /* Mark the PC as the destination for the return address. */
350 if (regnum == gdbarch_pc_regnum (gdbarch))
351 reg->how = DWARF2_FRAME_REG_RA;
353 /* Mark the stack pointer as the call frame address. */
354 else if (regnum == gdbarch_sp_regnum (gdbarch))
355 reg->how = DWARF2_FRAME_REG_CFA;
357 /* The above was taken from the default init_reg in dwarf2-frame.c
358 while the below is c6x specific. */
360 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
362 else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
363 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
365 /* All other registers are caller-save. */
366 reg->how = DWARF2_FRAME_REG_UNDEFINED;
369 /* This is the implementation of gdbarch method unwind_pc. */
372 tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
376 frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf);
377 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
380 /* This is the implementation of gdbarch method unwind_sp. */
383 tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
385 return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM);
389 /* Frame base handling. */
391 static struct tic6x_unwind_cache*
392 tic6x_frame_unwind_cache (struct frame_info *this_frame,
393 void **this_prologue_cache)
395 struct gdbarch *gdbarch = get_frame_arch (this_frame);
396 CORE_ADDR current_pc;
397 struct tic6x_unwind_cache *cache;
399 if (*this_prologue_cache)
400 return (struct tic6x_unwind_cache *) *this_prologue_cache;
402 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
403 (*this_prologue_cache) = cache;
405 cache->return_regnum = TIC6X_RA_REGNUM;
407 tic6x_setup_default (cache);
409 cache->pc = get_frame_func (this_frame);
410 current_pc = get_frame_pc (this_frame);
412 /* Prologue analysis does the rest... */
414 tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
420 tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
421 struct frame_id *this_id)
423 struct tic6x_unwind_cache *cache =
424 tic6x_frame_unwind_cache (this_frame, this_cache);
426 /* This marks the outermost frame. */
427 if (cache->base == 0)
430 (*this_id) = frame_id_build (cache->cfa, cache->pc);
433 static struct value *
434 tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
437 struct tic6x_unwind_cache *cache =
438 tic6x_frame_unwind_cache (this_frame, this_cache);
440 gdb_assert (regnum >= 0);
442 /* The PC of the previous frame is stored in the RA register of
443 the current frame. Frob regnum so that we pull the value from
444 the correct place. */
445 if (regnum == TIC6X_PC_REGNUM)
446 regnum = cache->return_regnum;
448 if (regnum == TIC6X_SP_REGNUM && cache->cfa)
449 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
451 /* If we've worked out where a register is stored then load it from
453 if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
454 return frame_unwind_got_memory (this_frame, regnum,
455 cache->reg_saved[regnum]);
457 return frame_unwind_got_register (this_frame, regnum, regnum);
461 tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
463 struct tic6x_unwind_cache *info
464 = tic6x_frame_unwind_cache (this_frame, this_cache);
468 static const struct frame_unwind tic6x_frame_unwind =
471 default_frame_unwind_stop_reason,
473 tic6x_frame_prev_register,
475 default_frame_sniffer
478 static const struct frame_base tic6x_frame_base =
481 tic6x_frame_base_address,
482 tic6x_frame_base_address,
483 tic6x_frame_base_address
487 static struct tic6x_unwind_cache *
488 tic6x_make_stub_cache (struct frame_info *this_frame)
490 struct tic6x_unwind_cache *cache;
492 cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
494 cache->return_regnum = TIC6X_RA_REGNUM;
496 tic6x_setup_default (cache);
498 cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);
504 tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
505 struct frame_id *this_id)
507 struct tic6x_unwind_cache *cache;
509 if (*this_cache == NULL)
510 *this_cache = tic6x_make_stub_cache (this_frame);
511 cache = (struct tic6x_unwind_cache *) *this_cache;
513 *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
517 tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
518 struct frame_info *this_frame,
519 void **this_prologue_cache)
521 CORE_ADDR addr_in_block;
523 addr_in_block = get_frame_address_in_block (this_frame);
524 if (in_plt_section (addr_in_block))
530 static const struct frame_unwind tic6x_stub_unwind =
533 default_frame_unwind_stop_reason,
535 tic6x_frame_prev_register,
537 tic6x_stub_unwind_sniffer
540 /* Return the instruction on address PC. */
543 tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
545 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
546 return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
549 /* Compute the condition of INST if it is a conditional instruction. Always
550 return 1 if INST is not a conditional instruction. */
553 tic6x_condition_true (struct regcache *regcache, unsigned long inst)
557 static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
559 register_number = register_numbers[(inst >> 29) & 7];
560 if (register_number == -1)
563 register_value = regcache_raw_get_signed (regcache, register_number);
564 if ((inst & 0x10000000) != 0)
565 return register_value == 0;
566 return register_value != 0;
569 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
573 tic6x_register_number (int reg, int side, int crosspath)
575 int r = (reg & 15) | ((crosspath ^ side) << 4);
576 if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
582 tic6x_extract_signed_field (int value, int low_bit, int bits)
584 int mask = (1 << bits) - 1;
585 int r = (value >> low_bit) & mask;
586 if ((r & (1 << (bits - 1))) != 0)
591 /* Determine where to set a single step breakpoint. */
594 tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
596 struct gdbarch *gdbarch = get_regcache_arch (regcache);
603 inst = tic6x_fetch_instruction (gdbarch, pc);
607 if (inst == TIC6X_INST_SWE)
609 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
611 if (tdep->syscall_next_pc != NULL)
612 return tdep->syscall_next_pc (get_current_frame ());
615 if (tic6x_condition_true (regcache, inst))
617 if ((inst & 0x0000007c) == 0x00000010)
619 /* B with displacement */
620 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
621 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
624 if ((inst & 0x0f83effc) == 0x00000360)
626 /* B with register */
628 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
631 pc = regcache_raw_get_unsigned (regcache, register_number);
634 if ((inst & 0x00001ffc) == 0x00001020)
637 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
638 INST_S_BIT (inst), 0);
639 if (regcache_raw_get_signed (regcache, register_number) >= 0)
641 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
642 pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
646 if ((inst & 0x00001ffc) == 0x00000120)
648 /* BNOP with displacement */
649 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
650 pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
653 if ((inst & 0x0f830ffe) == 0x00800362)
655 /* BNOP with register */
656 register_number = tic6x_register_number ((inst >> 18) & 0x1f,
657 1, INST_X_BIT (inst));
658 pc = regcache_raw_get_unsigned (regcache, register_number);
661 if ((inst & 0x00001ffc) == 0x00000020)
664 register_number = tic6x_register_number ((inst >> 23) & 0x1f,
665 INST_S_BIT (inst), 0);
666 if (regcache_raw_get_signed (regcache, register_number) >= 0)
668 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
669 pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
673 if ((inst & 0xf000007c) == 0x10000010)
676 pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
677 pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
681 pc += TIC6X_OPCODE_SIZE;
687 /* This is the implementation of gdbarch method software_single_step. */
689 static std::vector<CORE_ADDR>
690 tic6x_software_single_step (struct regcache *regcache)
692 CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache));
697 /* This is the implementation of gdbarch method frame_align. */
700 tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
702 return align_down (addr, 8);
705 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
706 value into VALBUF. */
709 tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
710 enum bfd_endian byte_order, gdb_byte *valbuf)
712 int len = TYPE_LENGTH (valtype);
714 /* pointer types are returned in register A4,
715 up to 32-bit types in A4
716 up to 64-bit types in A5:A4 */
720 - one-byte structure or union occupies the LSB of single even register.
721 - for two-byte structure or union, the first byte occupies byte 1 of
722 register and the second byte occupies byte 0.
723 so, we read the contents in VAL from the LSBs of register. */
724 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
725 regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
728 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
732 /* For a 5-8 byte structure or union in big-endian, the first byte
733 occupies byte 3 (the MSB) of the upper (odd) register and the
734 remaining bytes fill the decreasingly significant bytes. 5-7
735 byte structures or unions have padding in the LSBs of the
736 lower (even) register. */
737 if (byte_order == BFD_ENDIAN_BIG)
739 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4);
740 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf);
744 regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
745 regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4);
750 /* Write into appropriate registers a function return value
751 of type TYPE, given in virtual format. */
754 tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
755 enum bfd_endian byte_order, const gdb_byte *valbuf)
757 int len = TYPE_LENGTH (valtype);
759 /* return values of up to 8 bytes are returned in A5:A4 */
763 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
764 regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
767 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
771 if (byte_order == BFD_ENDIAN_BIG)
773 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4);
774 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf);
778 regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
779 regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4);
784 /* This is the implementation of gdbarch method return_value. */
786 static enum return_value_convention
787 tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
788 struct type *type, struct regcache *regcache,
789 gdb_byte *readbuf, const gdb_byte *writebuf)
791 /* In C++, when function returns an object, even its size is small
792 enough, it stii has to be passed via reference, pointed by register
794 if (current_language->la_language == language_cplus)
798 type = check_typedef (type);
799 if (language_pass_by_reference (type))
800 return RETURN_VALUE_STRUCT_CONVENTION;
804 if (TYPE_LENGTH (type) > 8)
805 return RETURN_VALUE_STRUCT_CONVENTION;
808 tic6x_extract_return_value (type, regcache,
809 gdbarch_byte_order (gdbarch), readbuf);
811 tic6x_store_return_value (type, regcache,
812 gdbarch_byte_order (gdbarch), writebuf);
814 return RETURN_VALUE_REGISTER_CONVENTION;
817 /* This is the implementation of gdbarch method dummy_id. */
819 static struct frame_id
820 tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
822 return frame_id_build
823 (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM),
824 get_frame_pc (this_frame));
827 /* Get the alignment requirement of TYPE. */
830 tic6x_arg_type_alignment (struct type *type)
832 int len = TYPE_LENGTH (check_typedef (type));
833 enum type_code typecode = TYPE_CODE (check_typedef (type));
835 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
837 /* The stack alignment of a structure (and union) passed by value is the
838 smallest power of two greater than or equal to its size.
839 This cannot exceed 8 bytes, which is the largest allowable size for
840 a structure passed by value. */
849 gdb_assert_not_reached ("unexpected length of data");
857 if (typecode == TYPE_CODE_COMPLEX)
864 if (typecode == TYPE_CODE_COMPLEX)
870 internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
875 /* This is the implementation of gdbarch method push_dummy_call. */
878 tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
879 struct regcache *regcache, CORE_ADDR bp_addr,
880 int nargs, struct value **args, CORE_ADDR sp,
881 int struct_return, CORE_ADDR struct_addr)
885 int stack_offset = 4;
886 int references_offset = 4;
887 CORE_ADDR func_addr = find_function_addr (function, NULL);
888 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
889 struct type *func_type = value_type (function);
890 /* The first arg passed on stack. Mostly the first 10 args are passed by
892 int first_arg_on_stack = 10;
894 /* Set the return address register to point to the entry point of
895 the program, where a breakpoint lies in wait. */
896 regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);
898 /* The caller must pass an argument in A3 containing a destination address
899 for the returned value. The callee returns the object by copying it to
900 the address in A3. */
902 regcache_cooked_write_unsigned (regcache, 3, struct_addr);
904 /* Determine the type of this function. */
905 func_type = check_typedef (func_type);
906 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
907 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
909 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
910 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
912 /* For a variadic C function, the last explicitly declared argument and all
913 remaining arguments are passed on the stack. */
914 if (TYPE_VARARGS (func_type))
915 first_arg_on_stack = TYPE_NFIELDS (func_type) - 1;
917 /* Now make space on the stack for the args. */
918 for (argnum = 0; argnum < nargs; argnum++)
920 int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
921 if (argnum >= 10 - argreg)
922 references_offset += len;
926 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
928 sp = align_down (sp, 8);
931 /* Now load as many as possible of the first arguments into
932 registers, and push the rest onto the stack. Loop through args
933 from first to last. */
934 for (argnum = 0; argnum < nargs; argnum++)
937 struct value *arg = args[argnum];
938 struct type *arg_type = check_typedef (value_type (arg));
939 int len = TYPE_LENGTH (arg_type);
940 enum type_code typecode = TYPE_CODE (arg_type);
942 val = value_contents (arg);
944 /* Copy the argument to general registers or the stack in
945 register-sized pieces. */
946 if (argreg < first_arg_on_stack)
950 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
953 - one-byte structure or union occupies the LSB of single
955 - for two-byte structure or union, the first byte
956 occupies byte 1 of register and the second byte occupies
958 so, we write the contents in VAL to the lsp of
960 if (len < 3 && byte_order == BFD_ENDIAN_BIG)
961 regcache_cooked_write_part (regcache, arg_regs[argreg],
964 regcache_cooked_write (regcache, arg_regs[argreg], val);
968 /* The argument is being passed by value in a single
970 CORE_ADDR regval = extract_unsigned_integer (val, len,
973 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
981 if (typecode == TYPE_CODE_STRUCT
982 || typecode == TYPE_CODE_UNION)
984 /* For a 5-8 byte structure or union in big-endian, the
985 first byte occupies byte 3 (the MSB) of the upper (odd)
986 register and the remaining bytes fill the decreasingly
987 significant bytes. 5-7 byte structures or unions have
988 padding in the LSBs of the lower (even) register. */
989 if (byte_order == BFD_ENDIAN_BIG)
991 regcache_cooked_write (regcache,
992 arg_regs[argreg] + 1, val);
993 regcache_cooked_write_part (regcache,
999 regcache_cooked_write (regcache, arg_regs[argreg],
1001 regcache_cooked_write_part (regcache,
1002 arg_regs[argreg] + 1, 0,
1008 /* The argument is being passed by value in a pair of
1010 ULONGEST regval = extract_unsigned_integer (val, len,
1013 regcache_cooked_write_unsigned (regcache,
1016 regcache_cooked_write_unsigned (regcache,
1017 arg_regs[argreg] + 1,
1023 /* The argument is being passed by reference in a single
1027 /* It is not necessary to adjust REFERENCES_OFFSET to
1028 8-byte aligned in some cases, in which 4-byte alignment
1029 is sufficient. For simplicity, we adjust
1030 REFERENCES_OFFSET to 8-byte aligned. */
1031 references_offset = align_up (references_offset, 8);
1033 addr = sp + references_offset;
1034 write_memory (addr, val, len);
1035 references_offset += align_up (len, 4);
1036 regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
1044 /* The argument is being passed on the stack. */
1047 /* There are six different cases of alignment, and these rules can
1048 be found in tic6x_arg_type_alignment:
1050 1) 4-byte aligned if size is less than or equal to 4 byte, such
1051 as short, int, struct, union etc.
1052 2) 8-byte aligned if size is less than or equal to 8-byte, such
1053 as double, long long,
1054 3) 4-byte aligned if it is of type _Complex float, even its size
1056 4) 8-byte aligned if it is of type _Complex double or _Complex
1057 long double, even its size is 16-byte. Because, the address of
1058 variable is passed as reference.
1059 5) struct and union larger than 8-byte are passed by reference, so
1060 it is 4-byte aligned.
1061 6) struct and union of size between 4 byte and 8 byte varies.
1062 alignment of struct variable is the alignment of its first field,
1063 while alignment of union variable is the max of all its fields'
1067 ; /* Default is 4-byte aligned. Nothing to be done. */
1069 stack_offset = align_up (stack_offset,
1070 tic6x_arg_type_alignment (arg_type));
1073 /* _Complex double or _Complex long double */
1074 if (typecode == TYPE_CODE_COMPLEX)
1076 /* The argument is being passed by reference on stack. */
1078 references_offset = align_up (references_offset, 8);
1080 addr = sp + references_offset;
1081 /* Store variable on stack. */
1082 write_memory (addr, val, len);
1084 references_offset += align_up (len, 4);
1086 /* Pass the address of variable on stack as reference. */
1087 store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
1093 internal_error (__FILE__, __LINE__,
1094 _("unexpected type %d of arg %d"),
1098 internal_error (__FILE__, __LINE__,
1099 _("unexpected length %d of arg %d"), len, argnum);
1101 addr = sp + stack_offset;
1102 write_memory (addr, val, len);
1103 stack_offset += align_up (len, 4);
1107 regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);
1109 /* Return adjusted stack pointer. */
1113 /* This is the implementation of gdbarch method stack_frame_destroyed_p. */
1116 tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1118 unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
1119 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1120 if ((inst & 0x0f83effc) == 0x360)
1122 unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
1125 if (src2 == TIC6X_RA_REGNUM)
1132 /* This is the implementation of gdbarch method get_longjmp_target. */
1135 tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1137 struct gdbarch *gdbarch = get_frame_arch (frame);
1138 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1142 /* JMP_BUF is passed by reference in A4. */
1143 jb_addr = get_frame_register_unsigned (frame, 4);
1145 /* JMP_BUF contains 13 elements of type int, and return address is stored
1146 in the last slot. */
1147 if (target_read_memory (jb_addr + 12 * 4, buf, 4))
1150 *pc = extract_unsigned_integer (buf, 4, byte_order);
1155 /* This is the implementation of gdbarch method
1156 return_in_first_hidden_param_p. */
1159 tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
1165 static struct gdbarch *
1166 tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1168 struct gdbarch *gdbarch;
1169 struct gdbarch_tdep *tdep;
1170 struct tdesc_arch_data *tdesc_data = NULL;
1171 const struct target_desc *tdesc = info.target_desc;
1174 /* Check any target description for validity. */
1175 if (tdesc_has_registers (tdesc))
1177 const struct tdesc_feature *feature;
1180 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");
1182 if (feature == NULL)
1185 tdesc_data = tdesc_data_alloc ();
1188 for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */
1189 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1190 tic6x_register_names[i]);
1193 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1194 tic6x_register_names[TIC6X_CSR_REGNUM]);
1195 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1196 tic6x_register_names[TIC6X_PC_REGNUM]);
1200 tdesc_data_cleanup (tdesc_data);
1204 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
1208 static const char *const gp[] =
1210 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1211 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1212 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1213 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1218 for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */
1219 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
1224 tdesc_data_cleanup (tdesc_data);
1229 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
1232 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR");
1233 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC");
1234 valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC");
1238 tdesc_data_cleanup (tdesc_data);
1245 /* Find a candidate among extant architectures. */
1246 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1248 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1250 tdep = gdbarch_tdep (arches->gdbarch);
1252 if (has_gp != tdep->has_gp)
1255 if (tdep && tdep->breakpoint)
1256 return arches->gdbarch;
1259 tdep = XCNEW (struct gdbarch_tdep);
1261 tdep->has_gp = has_gp;
1262 gdbarch = gdbarch_alloc (&info, tdep);
1264 /* Data type sizes. */
1265 set_gdbarch_ptr_bit (gdbarch, 32);
1266 set_gdbarch_addr_bit (gdbarch, 32);
1267 set_gdbarch_short_bit (gdbarch, 16);
1268 set_gdbarch_int_bit (gdbarch, 32);
1269 set_gdbarch_long_bit (gdbarch, 32);
1270 set_gdbarch_long_long_bit (gdbarch, 64);
1271 set_gdbarch_float_bit (gdbarch, 32);
1272 set_gdbarch_double_bit (gdbarch, 64);
1274 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1275 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1277 /* The register set. */
1278 set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
1279 set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
1280 set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);
1282 set_gdbarch_register_name (gdbarch, tic6x_register_name);
1283 set_gdbarch_register_type (gdbarch, tic6x_register_type);
1285 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1287 set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
1288 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1289 tic6x_breakpoint_kind_from_pc);
1290 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1291 tic6x_sw_breakpoint_from_kind);
1293 set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
1294 set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp);
1297 dwarf2_append_unwinders (gdbarch);
1299 frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
1300 frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
1301 frame_base_set_default (gdbarch, &tic6x_frame_base);
1303 dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);
1305 /* Single stepping. */
1306 set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);
1308 /* Call dummy code. */
1309 set_gdbarch_frame_align (gdbarch, tic6x_frame_align);
1311 set_gdbarch_return_value (gdbarch, tic6x_return_value);
1313 set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id);
1315 /* Enable inferior call support. */
1316 set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);
1318 set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);
1320 set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p);
1322 set_gdbarch_return_in_first_hidden_param_p (gdbarch,
1323 tic6x_return_in_first_hidden_param_p);
1325 /* Hook in ABI-specific overrides, if they have been registered. */
1326 gdbarch_init_osabi (info, gdbarch);
1329 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1335 _initialize_tic6x_tdep (void)
1337 register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);