1 # Copyright (C) 2008-2017 Free Software Foundation, Inc.
3 # This program is free software; you can redistribute it and/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation; either version 3 of the License, or
6 # (at your option) any later version.
8 # This program is distributed in the hope that it will be useful,
9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with this program. If not, see <http://www.gnu.org/licenses/>.
18 # Test the use of VSX registers, for Powerpc.
22 if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
23 verbose "Skipping vsx register tests."
29 set compile_flags {debug nowarnings quiet}
30 if [get_compiler_info] {
31 warning "get_compiler failed"
35 if [test_compiler_info gcc*] {
36 set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
37 } elseif [test_compiler_info xlc*] {
38 set compile_flags "$compile_flags additional_flags=-qaltivec"
40 warning "unknown compiler"
44 if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
45 untested "failed to compile"
50 gdb_reinitialize_dir $srcdir/$subdir
53 # Run to `main' where we begin our tests.
55 if ![runto_main] then {
60 set msg "detect endianness"
61 gdb_test_multiple "show endian" "$msg" {
62 -re "(The target endianness is set automatically .currently )(big|little)( endian.*)$gdb_prompt $" {
64 set endianness $expect_out(2,string)
66 -re ".*$gdb_prompt $" {
71 # Data sets used throughout the test
73 if {$endianness == "big"} {
74 set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
76 set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
78 set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
80 set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
82 set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
84 set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
86 set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
88 set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
90 set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
92 set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
94 set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
96 set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
99 set float_register ".raw 0xdeadbeefdeadbeef."
101 # First run the F0~F31/VS0~VS31 tests
103 # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
104 for {set i 0} {$i < 32} {incr i 1} {
105 gdb_test_no_output "set \$f$i = 1\.3"
108 for {set i 0} {$i < 32} {incr i 1} {
109 gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
112 # 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
113 for {set i 0} {$i < 32} {incr i 1} {
114 for {set j 0} {$j < 4} {incr j 1} {
115 gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
119 for {set i 0} {$i < 32} {incr i 1} {
120 gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
123 for {set i 0} {$i < 32} {incr i 1} {
124 gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
127 # Now run the VR0~VR31/VS32~VS63 tests
129 # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
130 for {set i 0} {$i < 32} {incr i 1} {
131 for {set j 0} {$j < 4} {incr j 1} {
132 gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
136 for {set i 32} {$i < 64} {incr i 1} {
137 gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
139 # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
140 for {set i 32} {$i < 64} {incr i 1} {
141 for {set j 0} {$j < 4} {incr j 1} {
142 gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
146 for {set i 0} {$i < 32} {incr i 1} {
147 gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
150 # Create a core file. We create the core file before the F32~F63/VR0~VR31 test
151 # below because then we'll have more interesting register values to verify
152 # later when loading the core file (i.e., different register values for different
153 # vector register banks).
155 set corefile [standard_output_file vsx-core.test]
156 set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"]
158 # Now run the F32~F63/VR0~VR31 tests.
160 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
161 for {set i 32} {$i < 64} {incr i 1} {
162 gdb_test_no_output "set \$f$i = 1\.3"
165 for {set i 0} {$i < 32} {incr i 1} {
166 gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
169 # 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
170 for {set i 0} {$i < 32} {incr i 1} {
171 for {set j 0} {$j < 4} {incr j 1} {
172 gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
176 for {set i 32} {$i < 64} {incr i 1} {
177 gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
180 for {set i 0} {$i < 32} {incr i 1} {
181 gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
184 # Test reading the core file.
186 if {!$core_supported} {
192 gdb_reinitialize_dir $srcdir/$subdir
195 set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"]
196 if { $core_loaded == -1 } {
197 # No use proceeding from here.
201 for {set i 0} {$i < 32} {incr i 1} {
202 gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file"
205 for {set i 32} {$i < 64} {incr i 1} {
206 gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file"