1 # Copyright (C) 2008-2012 Free Software Foundation, Inc.
3 # This program is free software; you can redistribute it and/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation; either version 3 of the License, or
6 # (at your option) any later version.
8 # This program is distributed in the hope that it will be useful,
9 # but WITHOUT ANY WARRANTY; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with this program. If not, see <http://www.gnu.org/licenses/>.
22 # Test the use of VSX registers, for Powerpc.
26 if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
27 verbose "Skipping vsx register tests."
31 set testfile "vsx-regs"
32 set binfile ${objdir}/${subdir}/${testfile}
33 set srcfile ${testfile}.c
35 set compile_flags {debug nowarnings quiet}
36 if [get_compiler_info $binfile] {
37 warning "get_compiler failed"
41 if [test_compiler_info gcc*] {
42 set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
43 } elseif [test_compiler_info xlc*] {
44 set compile_flags "$compile_flags additional_flags=-qaltivec"
46 warning "unknown compiler"
50 if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
56 gdb_reinitialize_dir $srcdir/$subdir
59 # Run to `main' where we begin our tests.
61 if ![runto_main] then {
65 # Data sets used throughout the test
67 set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
69 set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
71 set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
73 set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
75 set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
77 set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
79 set float_register ".raw 0xdeadbeefdeadbeef."
81 # First run the F0~F31/VS0~VS31 tests
83 # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
84 for {set i 0} {$i < 32} {incr i 1} {
85 gdb_test_no_output "set \$f$i = 1\.3"
88 for {set i 0} {$i < 32} {incr i 1} {
89 gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
92 # 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
93 for {set i 0} {$i < 32} {incr i 1} {
94 for {set j 0} {$j < 4} {incr j 1} {
95 gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
99 for {set i 0} {$i < 32} {incr i 1} {
100 gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
103 for {set i 0} {$i < 32} {incr i 1} {
104 gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
107 # Now run the VR0~VR31/VS32~VS63 tests
109 # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
110 for {set i 0} {$i < 32} {incr i 1} {
111 for {set j 0} {$j < 4} {incr j 1} {
112 gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
116 for {set i 32} {$i < 64} {incr i 1} {
117 gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
119 # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
120 for {set i 32} {$i < 64} {incr i 1} {
121 for {set j 0} {$j < 4} {incr j 1} {
122 gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
126 for {set i 0} {$i < 32} {incr i 1} {
127 gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
130 # Create a core file. We create the core file before the F32~F63/VR0~VR31 test
131 # below because then we'll have more interesting register values to verify
132 # later when loading the core file (i.e., different register values for different
133 # vector register banks).
135 set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]
139 gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
140 "Save a VSX-enabled corefile" \
142 -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" {
143 pass "Save a VSX-enabled corefile"
144 global core_supported
147 -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" {
148 unsupported "Save a VSX-enabled corefile"
149 global core_supported
154 # Now run the F32~F63/VR0~VR31 tests.
156 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
157 for {set i 32} {$i < 64} {incr i 1} {
158 gdb_test_no_output "set \$f$i = 1\.3"
161 for {set i 0} {$i < 32} {incr i 1} {
162 gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
165 # 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
166 for {set i 0} {$i < 32} {incr i 1} {
167 for {set j 0} {$j < 4} {incr j 1} {
168 gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
172 for {set i 32} {$i < 64} {incr i 1} {
173 gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
176 for {set i 0} {$i < 32} {incr i 1} {
177 gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
180 # Test reading the core file.
182 if {!$core_supported} {
188 gdb_reinitialize_dir $srcdir/$subdir
191 gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \
192 "re-load generated corefile" \
194 -re ".* is not a core dump:.*$gdb_prompt $" {
195 fail "re-load generated corefile (bad file format)"
196 # No use proceeding from here.
199 -re ".*: No such file or directory.*$gdb_prompt $" {
200 fail "re-load generated corefile (file not found)"
201 # No use proceeding from here.
204 -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" {
205 fail "re-load generated corefile (incomplete note section)"
207 -re "Core was generated by .*$gdb_prompt $" {
208 pass "re-load generated corefile"
210 -re ".*$gdb_prompt $" {
211 fail "re-load generated corefile"
214 fail "re-load generated corefile (timeout)"
218 for {set i 0} {$i < 32} {incr i 1} {
219 gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file"
222 for {set i 32} {$i < 64} {incr i 1} {
223 gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file"