1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006-2018 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
40 #include "reggroups.h"
45 #include "dwarf2-frame.h"
50 /* The list of available "set spu " and "show spu " commands. */
51 static struct cmd_list_element *setspucmdlist = NULL;
52 static struct cmd_list_element *showspucmdlist = NULL;
54 /* Whether to stop for new SPE contexts. */
55 static int spu_stop_on_load_p = 0;
56 /* Whether to automatically flush the SW-managed cache. */
57 static int spu_auto_flush_cache_p = 1;
60 /* The tdep structure. */
63 /* The spufs ID identifying our address space. */
66 /* SPU-specific vector type. */
67 struct type *spu_builtin_type_vec128;
71 /* SPU-specific vector type. */
73 spu_builtin_type_vec128 (struct gdbarch *gdbarch)
75 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
77 if (!tdep->spu_builtin_type_vec128)
79 const struct builtin_type *bt = builtin_type (gdbarch);
82 t = arch_composite_type (gdbarch,
83 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
84 append_composite_type_field (t, "uint128", bt->builtin_int128);
85 append_composite_type_field (t, "v2_int64",
86 init_vector_type (bt->builtin_int64, 2));
87 append_composite_type_field (t, "v4_int32",
88 init_vector_type (bt->builtin_int32, 4));
89 append_composite_type_field (t, "v8_int16",
90 init_vector_type (bt->builtin_int16, 8));
91 append_composite_type_field (t, "v16_int8",
92 init_vector_type (bt->builtin_int8, 16));
93 append_composite_type_field (t, "v2_double",
94 init_vector_type (bt->builtin_double, 2));
95 append_composite_type_field (t, "v4_float",
96 init_vector_type (bt->builtin_float, 4));
99 TYPE_NAME (t) = "spu_builtin_type_vec128";
101 tdep->spu_builtin_type_vec128 = t;
104 return tdep->spu_builtin_type_vec128;
108 /* The list of available "info spu " commands. */
109 static struct cmd_list_element *infospucmdlist = NULL;
114 spu_register_name (struct gdbarch *gdbarch, int reg_nr)
116 static const char *register_names[] =
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
122 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
123 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
124 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
125 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
126 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
127 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
128 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
129 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
130 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
131 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
132 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
133 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
134 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
139 if (reg_nr >= sizeof register_names / sizeof *register_names)
142 return register_names[reg_nr];
146 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
148 if (reg_nr < SPU_NUM_GPRS)
149 return spu_builtin_type_vec128 (gdbarch);
154 return builtin_type (gdbarch)->builtin_uint32;
157 return builtin_type (gdbarch)->builtin_func_ptr;
160 return builtin_type (gdbarch)->builtin_data_ptr;
162 case SPU_FPSCR_REGNUM:
163 return builtin_type (gdbarch)->builtin_uint128;
165 case SPU_SRR0_REGNUM:
166 return builtin_type (gdbarch)->builtin_uint32;
168 case SPU_LSLR_REGNUM:
169 return builtin_type (gdbarch)->builtin_uint32;
171 case SPU_DECR_REGNUM:
172 return builtin_type (gdbarch)->builtin_uint32;
174 case SPU_DECR_STATUS_REGNUM:
175 return builtin_type (gdbarch)->builtin_uint32;
178 internal_error (__FILE__, __LINE__, _("invalid regnum"));
182 /* Pseudo registers for preferred slots - stack pointer. */
184 static enum register_status
185 spu_pseudo_register_read_spu (readable_regcache *regcache, const char *regname,
188 struct gdbarch *gdbarch = regcache->arch ();
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 enum register_status status;
196 status = regcache->raw_read (SPU_ID_REGNUM, &id);
197 if (status != REG_VALID)
199 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
200 memset (reg, 0, sizeof reg);
201 target_read (¤t_target, TARGET_OBJECT_SPU, annex,
204 ul = strtoulst ((char *) reg, NULL, 16);
205 store_unsigned_integer (buf, 4, byte_order, ul);
209 static enum register_status
210 spu_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache,
211 int regnum, gdb_byte *buf)
216 enum register_status status;
221 status = regcache->raw_read (SPU_RAW_SP_REGNUM, reg);
222 if (status != REG_VALID)
224 memcpy (buf, reg, 4);
227 case SPU_FPSCR_REGNUM:
228 status = regcache->raw_read (SPU_ID_REGNUM, &id);
229 if (status != REG_VALID)
231 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
232 target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
235 case SPU_SRR0_REGNUM:
236 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
238 case SPU_LSLR_REGNUM:
239 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
241 case SPU_DECR_REGNUM:
242 return spu_pseudo_register_read_spu (regcache, "decr", buf);
244 case SPU_DECR_STATUS_REGNUM:
245 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
248 internal_error (__FILE__, __LINE__, _("invalid regnum"));
253 spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
256 struct gdbarch *gdbarch = regcache->arch ();
257 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
262 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
263 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
264 xsnprintf (reg, sizeof reg, "0x%s",
265 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
266 target_write (¤t_target, TARGET_OBJECT_SPU, annex,
267 (gdb_byte *) reg, 0, strlen (reg));
271 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
272 int regnum, const gdb_byte *buf)
281 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
282 memcpy (reg, buf, 4);
283 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
286 case SPU_FPSCR_REGNUM:
287 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
288 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
289 target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
292 case SPU_SRR0_REGNUM:
293 spu_pseudo_register_write_spu (regcache, "srr0", buf);
296 case SPU_LSLR_REGNUM:
297 spu_pseudo_register_write_spu (regcache, "lslr", buf);
300 case SPU_DECR_REGNUM:
301 spu_pseudo_register_write_spu (regcache, "decr", buf);
304 case SPU_DECR_STATUS_REGNUM:
305 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
309 internal_error (__FILE__, __LINE__, _("invalid regnum"));
314 spu_ax_pseudo_register_collect (struct gdbarch *gdbarch,
315 struct agent_expr *ax, int regnum)
320 ax_reg_mask (ax, SPU_RAW_SP_REGNUM);
323 case SPU_FPSCR_REGNUM:
324 case SPU_SRR0_REGNUM:
325 case SPU_LSLR_REGNUM:
326 case SPU_DECR_REGNUM:
327 case SPU_DECR_STATUS_REGNUM:
331 internal_error (__FILE__, __LINE__, _("invalid regnum"));
336 spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
337 struct agent_expr *ax, int regnum)
342 ax_reg (ax, SPU_RAW_SP_REGNUM);
345 case SPU_FPSCR_REGNUM:
346 case SPU_SRR0_REGNUM:
347 case SPU_LSLR_REGNUM:
348 case SPU_DECR_REGNUM:
349 case SPU_DECR_STATUS_REGNUM:
353 internal_error (__FILE__, __LINE__, _("invalid regnum"));
358 /* Value conversion -- access scalar values at the preferred slot. */
360 static struct value *
361 spu_value_from_register (struct gdbarch *gdbarch, struct type *type,
362 int regnum, struct frame_id frame_id)
364 struct value *value = default_value_from_register (gdbarch, type,
366 LONGEST len = TYPE_LENGTH (type);
368 if (regnum < SPU_NUM_GPRS && len < 16)
370 int preferred_slot = len < 4 ? 4 - len : 0;
371 set_value_offset (value, preferred_slot);
377 /* Register groups. */
380 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
381 struct reggroup *group)
383 /* Registers displayed via 'info regs'. */
384 if (group == general_reggroup)
387 /* Registers displayed via 'info float'. */
388 if (group == float_reggroup)
391 /* Registers that need to be saved/restored in order to
392 push or pop frames. */
393 if (group == save_reggroup || group == restore_reggroup)
396 return default_register_reggroup_p (gdbarch, regnum, group);
399 /* DWARF-2 register numbers. */
402 spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
404 /* Use cooked instead of raw SP. */
405 return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg;
409 /* Address handling. */
412 spu_gdbarch_id (struct gdbarch *gdbarch)
414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
417 /* The objfile architecture of a standalone SPU executable does not
418 provide an SPU ID. Retrieve it from the objfile's relocated
419 address range in this special case. */
421 && symfile_objfile && symfile_objfile->obfd
422 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
423 && symfile_objfile->sections != symfile_objfile->sections_end)
424 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
430 spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
432 if (dwarf2_addr_class == 1)
433 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
439 spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
441 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
448 spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
449 const char *name, int *type_flags_ptr)
451 if (strcmp (name, "__ea") == 0)
453 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
461 spu_address_to_pointer (struct gdbarch *gdbarch,
462 struct type *type, gdb_byte *buf, CORE_ADDR addr)
464 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
465 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
466 SPUADDR_ADDR (addr));
470 spu_pointer_to_address (struct gdbarch *gdbarch,
471 struct type *type, const gdb_byte *buf)
473 int id = spu_gdbarch_id (gdbarch);
474 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
476 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
478 /* Do not convert __ea pointers. */
479 if (TYPE_ADDRESS_CLASS_1 (type))
482 return addr? SPUADDR (id, addr) : 0;
486 spu_integer_to_address (struct gdbarch *gdbarch,
487 struct type *type, const gdb_byte *buf)
489 int id = spu_gdbarch_id (gdbarch);
490 ULONGEST addr = unpack_long (type, buf);
492 return SPUADDR (id, addr);
496 /* Decoding SPU instructions. */
533 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
535 if ((insn >> 21) == op)
538 *ra = (insn >> 7) & 127;
539 *rb = (insn >> 14) & 127;
547 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
549 if ((insn >> 28) == op)
551 *rt = (insn >> 21) & 127;
552 *ra = (insn >> 7) & 127;
553 *rb = (insn >> 14) & 127;
562 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
564 if ((insn >> 21) == op)
567 *ra = (insn >> 7) & 127;
568 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
576 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
578 if ((insn >> 24) == op)
581 *ra = (insn >> 7) & 127;
582 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
590 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
592 if ((insn >> 23) == op)
595 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
603 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
605 if ((insn >> 25) == op)
608 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
616 is_branch (unsigned int insn, int *offset, int *reg)
620 if (is_ri16 (insn, op_br, &rt, &i16)
621 || is_ri16 (insn, op_brsl, &rt, &i16)
622 || is_ri16 (insn, op_brnz, &rt, &i16)
623 || is_ri16 (insn, op_brz, &rt, &i16)
624 || is_ri16 (insn, op_brhnz, &rt, &i16)
625 || is_ri16 (insn, op_brhz, &rt, &i16))
627 *reg = SPU_PC_REGNUM;
632 if (is_ri16 (insn, op_bra, &rt, &i16)
633 || is_ri16 (insn, op_brasl, &rt, &i16))
640 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
641 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
642 || is_ri7 (insn, op_biz, &rt, reg, &i7)
643 || is_ri7 (insn, op_binz, &rt, reg, &i7)
644 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
645 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
655 /* Prolog parsing. */
657 struct spu_prologue_data
659 /* Stack frame size. -1 if analysis was unsuccessful. */
662 /* How to find the CFA. The CFA is equal to SP at function entry. */
666 /* Offset relative to CFA where a register is saved. -1 if invalid. */
667 int reg_offset[SPU_NUM_GPRS];
671 spu_analyze_prologue (struct gdbarch *gdbarch,
672 CORE_ADDR start_pc, CORE_ADDR end_pc,
673 struct spu_prologue_data *data)
675 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
680 int reg_immed[SPU_NUM_GPRS];
682 CORE_ADDR prolog_pc = start_pc;
687 /* Initialize DATA to default values. */
690 data->cfa_reg = SPU_RAW_SP_REGNUM;
691 data->cfa_offset = 0;
693 for (i = 0; i < SPU_NUM_GPRS; i++)
694 data->reg_offset[i] = -1;
696 /* Set up REG_IMMED array. This is non-zero for a register if we know its
697 preferred slot currently holds this immediate value. */
698 for (i = 0; i < SPU_NUM_GPRS; i++)
701 /* Scan instructions until the first branch.
703 The following instructions are important prolog components:
705 - The first instruction to set up the stack pointer.
706 - The first instruction to set up the frame pointer.
707 - The first instruction to save the link register.
708 - The first instruction to save the backchain.
710 We return the instruction after the latest of these four,
711 or the incoming PC if none is found. The first instruction
712 to set up the stack pointer also defines the frame size.
714 Note that instructions saving incoming arguments to their stack
715 slots are not counted as important, because they are hard to
716 identify with certainty. This should not matter much, because
717 arguments are relevant only in code compiled with debug data,
718 and in such code the GDB core will advance until the first source
719 line anyway, using SAL data.
721 For purposes of stack unwinding, we analyze the following types
722 of instructions in addition:
724 - Any instruction adding to the current frame pointer.
725 - Any instruction loading an immediate constant into a register.
726 - Any instruction storing a register onto the stack.
728 These are used to compute the CFA and REG_OFFSET output. */
730 for (pc = start_pc; pc < end_pc; pc += 4)
733 int rt, ra, rb, rc, immed;
735 if (target_read_memory (pc, buf, 4))
737 insn = extract_unsigned_integer (buf, 4, byte_order);
739 /* AI is the typical instruction to set up a stack frame.
740 It is also used to initialize the frame pointer. */
741 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
743 if (rt == data->cfa_reg && ra == data->cfa_reg)
744 data->cfa_offset -= immed;
746 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
754 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
760 data->cfa_reg = SPU_FP_REGNUM;
761 data->cfa_offset -= immed;
765 /* A is used to set up stack frames of size >= 512 bytes.
766 If we have tracked the contents of the addend register,
767 we can handle this as well. */
768 else if (is_rr (insn, op_a, &rt, &ra, &rb))
770 if (rt == data->cfa_reg && ra == data->cfa_reg)
772 if (reg_immed[rb] != 0)
773 data->cfa_offset -= reg_immed[rb];
775 data->cfa_reg = -1; /* We don't know the CFA any more. */
778 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
784 if (reg_immed[rb] != 0)
785 data->size = -reg_immed[rb];
789 /* We need to track IL and ILA used to load immediate constants
790 in case they are later used as input to an A instruction. */
791 else if (is_ri16 (insn, op_il, &rt, &immed))
793 reg_immed[rt] = immed;
795 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
799 else if (is_ri18 (insn, op_ila, &rt, &immed))
801 reg_immed[rt] = immed & 0x3ffff;
803 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
807 /* STQD is used to save registers to the stack. */
808 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
810 if (ra == data->cfa_reg)
811 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
813 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
820 if (ra == SPU_RAW_SP_REGNUM
821 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
829 /* _start uses SELB to set up the stack pointer. */
830 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
832 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
836 /* We terminate if we find a branch. */
837 else if (is_branch (insn, &immed, &ra))
842 /* If we successfully parsed until here, and didn't find any instruction
843 modifying SP, we assume we have a frameless function. */
847 /* Return cooked instead of raw SP. */
848 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
849 data->cfa_reg = SPU_SP_REGNUM;
854 /* Return the first instruction after the prologue starting at PC. */
856 spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
858 struct spu_prologue_data data;
859 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
862 /* Return the frame pointer in use at address PC. */
864 spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
865 int *reg, LONGEST *offset)
867 struct spu_prologue_data data;
868 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
870 if (data.size != -1 && data.cfa_reg != -1)
872 /* The 'frame pointer' address is CFA minus frame size. */
874 *offset = data.cfa_offset - data.size;
878 /* ??? We don't really know ... */
879 *reg = SPU_SP_REGNUM;
884 /* Implement the stack_frame_destroyed_p gdbarch method.
886 1) scan forward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer
888 or transfers control (except a return), execution is not in
890 b) Stop scanning if you find a return instruction or reach the
891 end of the function or reach the hard limit for the size of
893 2) scan backward from the point of execution:
894 a) If you find an instruction that modifies the stack pointer,
895 execution *is* in an epilogue, return.
896 b) Stop scanning if you reach an instruction that transfers
897 control or the beginning of the function or reach the hard
898 limit for the size of an epilogue. */
901 spu_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
903 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
904 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
907 int rt, ra, rb, immed;
909 /* Find the search limits based on function boundaries and hard limit.
910 We assume the epilogue can be up to 64 instructions long. */
912 const int spu_max_epilogue_size = 64 * 4;
914 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
917 if (pc - func_start < spu_max_epilogue_size)
918 epilogue_start = func_start;
920 epilogue_start = pc - spu_max_epilogue_size;
922 if (func_end - pc < spu_max_epilogue_size)
923 epilogue_end = func_end;
925 epilogue_end = pc + spu_max_epilogue_size;
927 /* Scan forward until next 'bi $0'. */
929 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
931 if (target_read_memory (scan_pc, buf, 4))
933 insn = extract_unsigned_integer (buf, 4, byte_order);
935 if (is_branch (insn, &immed, &ra))
937 if (immed == 0 && ra == SPU_LR_REGNUM)
943 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
944 || is_rr (insn, op_a, &rt, &ra, &rb)
945 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
947 if (rt == SPU_RAW_SP_REGNUM)
952 if (scan_pc >= epilogue_end)
955 /* Scan backward until adjustment to stack pointer (R1). */
957 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
959 if (target_read_memory (scan_pc, buf, 4))
961 insn = extract_unsigned_integer (buf, 4, byte_order);
963 if (is_branch (insn, &immed, &ra))
966 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
967 || is_rr (insn, op_a, &rt, &ra, &rb)
968 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
970 if (rt == SPU_RAW_SP_REGNUM)
979 /* Normal stack frames. */
981 struct spu_unwind_cache
984 CORE_ADDR frame_base;
985 CORE_ADDR local_base;
987 struct trad_frame_saved_reg *saved_regs;
990 static struct spu_unwind_cache *
991 spu_frame_unwind_cache (struct frame_info *this_frame,
992 void **this_prologue_cache)
994 struct gdbarch *gdbarch = get_frame_arch (this_frame);
995 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
996 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
997 struct spu_unwind_cache *info;
998 struct spu_prologue_data data;
999 CORE_ADDR id = tdep->id;
1002 if (*this_prologue_cache)
1003 return (struct spu_unwind_cache *) *this_prologue_cache;
1005 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
1006 *this_prologue_cache = info;
1007 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1008 info->frame_base = 0;
1009 info->local_base = 0;
1011 /* Find the start of the current function, and analyze its prologue. */
1012 info->func = get_frame_func (this_frame);
1013 if (info->func == 0)
1015 /* Fall back to using the current PC as frame ID. */
1016 info->func = get_frame_pc (this_frame);
1020 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
1023 /* If successful, use prologue analysis data. */
1024 if (data.size != -1 && data.cfa_reg != -1)
1029 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
1030 get_frame_register (this_frame, data.cfa_reg, buf);
1031 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
1032 cfa = SPUADDR (id, cfa);
1034 /* Call-saved register slots. */
1035 for (i = 0; i < SPU_NUM_GPRS; i++)
1036 if (i == SPU_LR_REGNUM
1037 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
1038 if (data.reg_offset[i] != -1)
1039 info->saved_regs[i].addr = cfa - data.reg_offset[i];
1042 info->frame_base = cfa;
1043 info->local_base = cfa - data.size;
1046 /* Otherwise, fall back to reading the backchain link. */
1054 /* Get local store limit. */
1055 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1057 lslr = (ULONGEST) -1;
1059 /* Get the backchain. */
1060 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1061 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1064 /* A zero backchain terminates the frame chain. Also, sanity
1065 check against the local store size limit. */
1066 if (status && backchain > 0 && backchain <= lslr)
1068 /* Assume the link register is saved into its slot. */
1069 if (backchain + 16 <= lslr)
1070 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1074 info->frame_base = SPUADDR (id, backchain);
1075 info->local_base = SPUADDR (id, reg);
1079 /* If we didn't find a frame, we cannot determine SP / return address. */
1080 if (info->frame_base == 0)
1083 /* The previous SP is equal to the CFA. */
1084 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1085 SPUADDR_ADDR (info->frame_base));
1087 /* Read full contents of the unwound link register in order to
1088 be able to determine the return address. */
1089 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1090 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1092 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
1094 /* Normally, the return address is contained in the slot 0 of the
1095 link register, and slots 1-3 are zero. For an overlay return,
1096 slot 0 contains the address of the overlay manager return stub,
1097 slot 1 contains the partition number of the overlay section to
1098 be returned to, and slot 2 contains the return address within
1099 that section. Return the latter address in that case. */
1100 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
1101 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
1102 extract_unsigned_integer (buf + 8, 4, byte_order));
1104 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
1105 extract_unsigned_integer (buf, 4, byte_order));
1111 spu_frame_this_id (struct frame_info *this_frame,
1112 void **this_prologue_cache, struct frame_id *this_id)
1114 struct spu_unwind_cache *info =
1115 spu_frame_unwind_cache (this_frame, this_prologue_cache);
1117 if (info->frame_base == 0)
1120 *this_id = frame_id_build (info->frame_base, info->func);
1123 static struct value *
1124 spu_frame_prev_register (struct frame_info *this_frame,
1125 void **this_prologue_cache, int regnum)
1127 struct spu_unwind_cache *info
1128 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
1130 /* Special-case the stack pointer. */
1131 if (regnum == SPU_RAW_SP_REGNUM)
1132 regnum = SPU_SP_REGNUM;
1134 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1137 static const struct frame_unwind spu_frame_unwind = {
1139 default_frame_unwind_stop_reason,
1141 spu_frame_prev_register,
1143 default_frame_sniffer
1147 spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
1149 struct spu_unwind_cache *info
1150 = spu_frame_unwind_cache (this_frame, this_cache);
1151 return info->local_base;
1154 static const struct frame_base spu_frame_base = {
1156 spu_frame_base_address,
1157 spu_frame_base_address,
1158 spu_frame_base_address
1162 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1165 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1166 /* Mask off interrupt enable bit. */
1167 return SPUADDR (tdep->id, pc & -4);
1171 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1173 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1174 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1175 return SPUADDR (tdep->id, sp);
1179 spu_read_pc (readable_regcache *regcache)
1181 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
1184 regcache->cooked_read (SPU_PC_REGNUM, &pc);
1185 /* Mask off interrupt enable bit. */
1186 return SPUADDR (tdep->id, pc & -4);
1190 spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
1192 /* Keep interrupt enabled state unchanged. */
1195 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1196 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1197 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
1201 /* Cell/B.E. cross-architecture unwinder support. */
1203 struct spu2ppu_cache
1205 struct frame_id frame_id;
1206 readonly_detached_regcache *regcache;
1209 static struct gdbarch *
1210 spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1212 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
1213 return cache->regcache->arch ();
1217 spu2ppu_this_id (struct frame_info *this_frame,
1218 void **this_cache, struct frame_id *this_id)
1220 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
1221 *this_id = cache->frame_id;
1224 static struct value *
1225 spu2ppu_prev_register (struct frame_info *this_frame,
1226 void **this_cache, int regnum)
1228 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
1229 struct gdbarch *gdbarch = cache->regcache->arch ();
1232 buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1233 cache->regcache->cooked_read (regnum, buf);
1234 return frame_unwind_got_bytes (this_frame, regnum, buf);
1238 spu2ppu_sniffer (const struct frame_unwind *self,
1239 struct frame_info *this_frame, void **this_prologue_cache)
1241 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1242 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1243 CORE_ADDR base, func, backchain;
1246 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu)
1249 base = get_frame_sp (this_frame);
1250 func = get_frame_pc (this_frame);
1251 if (target_read_memory (base, buf, 4))
1253 backchain = extract_unsigned_integer (buf, 4, byte_order);
1257 struct frame_info *fi;
1259 struct spu2ppu_cache *cache
1260 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1262 cache->frame_id = frame_id_build (base + 16, func);
1264 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1265 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1270 cache->regcache = frame_save_as_regcache (fi).release ();
1271 *this_prologue_cache = cache;
1276 struct regcache *regcache;
1277 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ());
1278 cache->regcache = new readonly_detached_regcache (*regcache);
1279 *this_prologue_cache = cache;
1288 spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1290 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) this_cache;
1291 delete cache->regcache;
1294 static const struct frame_unwind spu2ppu_unwind = {
1296 default_frame_unwind_stop_reason,
1298 spu2ppu_prev_register,
1301 spu2ppu_dealloc_cache,
1306 /* Function calling convention. */
1309 spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1315 spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1316 struct value **args, int nargs, struct type *value_type,
1317 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1318 struct regcache *regcache)
1320 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1321 sp = (sp - 4) & ~15;
1322 /* Store the address of that breakpoint */
1324 /* The call starts at the callee's entry point. */
1331 spu_scalar_value_p (struct type *type)
1333 switch (TYPE_CODE (type))
1336 case TYPE_CODE_ENUM:
1337 case TYPE_CODE_RANGE:
1338 case TYPE_CODE_CHAR:
1339 case TYPE_CODE_BOOL:
1342 case TYPE_CODE_RVALUE_REF:
1343 return TYPE_LENGTH (type) <= 16;
1351 spu_value_to_regcache (struct regcache *regcache, int regnum,
1352 struct type *type, const gdb_byte *in)
1354 int len = TYPE_LENGTH (type);
1356 if (spu_scalar_value_p (type))
1358 int preferred_slot = len < 4 ? 4 - len : 0;
1359 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1365 regcache_cooked_write (regcache, regnum++, in);
1371 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1376 spu_regcache_to_value (struct regcache *regcache, int regnum,
1377 struct type *type, gdb_byte *out)
1379 int len = TYPE_LENGTH (type);
1381 if (spu_scalar_value_p (type))
1383 int preferred_slot = len < 4 ? 4 - len : 0;
1384 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1390 regcache_cooked_read (regcache, regnum++, out);
1396 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1401 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1402 struct regcache *regcache, CORE_ADDR bp_addr,
1403 int nargs, struct value **args, CORE_ADDR sp,
1404 int struct_return, CORE_ADDR struct_addr)
1406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1409 int regnum = SPU_ARG1_REGNUM;
1413 /* Set the return address. */
1414 memset (buf, 0, sizeof buf);
1415 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
1416 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1418 /* If STRUCT_RETURN is true, then the struct return address (in
1419 STRUCT_ADDR) will consume the first argument-passing register.
1420 Both adjust the register count and store that value. */
1423 memset (buf, 0, sizeof buf);
1424 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
1425 regcache_cooked_write (regcache, regnum++, buf);
1428 /* Fill in argument registers. */
1429 for (i = 0; i < nargs; i++)
1431 struct value *arg = args[i];
1432 struct type *type = check_typedef (value_type (arg));
1433 const gdb_byte *contents = value_contents (arg);
1434 int n_regs = align_up (TYPE_LENGTH (type), 16) / 16;
1436 /* If the argument doesn't wholly fit into registers, it and
1437 all subsequent arguments go to the stack. */
1438 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1444 spu_value_to_regcache (regcache, regnum, type, contents);
1448 /* Overflow arguments go to the stack. */
1449 if (stack_arg != -1)
1453 /* Allocate all required stack size. */
1454 for (i = stack_arg; i < nargs; i++)
1456 struct type *type = check_typedef (value_type (args[i]));
1457 sp -= align_up (TYPE_LENGTH (type), 16);
1460 /* Fill in stack arguments. */
1462 for (i = stack_arg; i < nargs; i++)
1464 struct value *arg = args[i];
1465 struct type *type = check_typedef (value_type (arg));
1466 int len = TYPE_LENGTH (type);
1469 if (spu_scalar_value_p (type))
1470 preferred_slot = len < 4 ? 4 - len : 0;
1474 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1475 ap += align_up (TYPE_LENGTH (type), 16);
1479 /* Allocate stack frame header. */
1482 /* Store stack back chain. */
1483 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1484 target_write_memory (sp, buf, 16);
1486 /* Finally, update all slots of the SP register. */
1487 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
1488 for (i = 0; i < 4; i++)
1490 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1491 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
1493 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
1498 static struct frame_id
1499 spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1502 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1503 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1504 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
1507 /* Function return value access. */
1509 static enum return_value_convention
1510 spu_return_value (struct gdbarch *gdbarch, struct value *function,
1511 struct type *type, struct regcache *regcache,
1512 gdb_byte *out, const gdb_byte *in)
1514 struct type *func_type = function ? value_type (function) : NULL;
1515 enum return_value_convention rvc;
1516 int opencl_vector = 0;
1520 func_type = check_typedef (func_type);
1522 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1523 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1525 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1526 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1527 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1528 && TYPE_VECTOR (type))
1532 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1533 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1535 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1541 case RETURN_VALUE_REGISTER_CONVENTION:
1542 if (opencl_vector && TYPE_LENGTH (type) == 2)
1543 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1545 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1548 case RETURN_VALUE_STRUCT_CONVENTION:
1549 error (_("Cannot set function return value."));
1557 case RETURN_VALUE_REGISTER_CONVENTION:
1558 if (opencl_vector && TYPE_LENGTH (type) == 2)
1559 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1561 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1564 case RETURN_VALUE_STRUCT_CONVENTION:
1565 error (_("Function return value unknown."));
1575 constexpr gdb_byte spu_break_insn[] = { 0x00, 0x00, 0x3f, 0xff };
1577 typedef BP_MANIPULATION (spu_break_insn) spu_breakpoint;
1580 spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1581 struct bp_target_info *bp_tgt)
1583 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1584 that in a combined application, we have some breakpoints inserted in SPU
1585 code, and now the application forks (on the PPU side). GDB common code
1586 will assume that the fork system call copied all breakpoints into the new
1587 process' address space, and that all those copies now need to be removed
1588 (see breakpoint.c:detach_breakpoints).
1590 While this is certainly true for PPU side breakpoints, it is not true
1591 for SPU side breakpoints. fork will clone the SPU context file
1592 descriptors, so that all the existing SPU contexts are in accessible
1593 in the new process. However, the contents of the SPU contexts themselves
1594 are *not* cloned. Therefore the effect of detach_breakpoints is to
1595 remove SPU breakpoints from the *original* SPU context's local store
1596 -- this is not the correct behaviour.
1598 The workaround is to check whether the PID we are asked to remove this
1599 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1600 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1601 true in the context of detach_breakpoints. If so, we simply do nothing.
1602 [ Note that for the fork child process, it does not matter if breakpoints
1603 remain inserted, because those SPU contexts are not runnable anyway --
1604 the Linux kernel allows only the original process to invoke spu_run. */
1606 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1609 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1613 /* Software single-stepping support. */
1615 static std::vector<CORE_ADDR>
1616 spu_software_single_step (struct regcache *regcache)
1618 struct gdbarch *gdbarch = regcache->arch ();
1619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1620 CORE_ADDR pc, next_pc;
1625 std::vector<CORE_ADDR> next_pcs;
1627 pc = regcache_read_pc (regcache);
1629 if (target_read_memory (pc, buf, 4))
1630 throw_error (MEMORY_ERROR, _("Could not read instruction at %s."),
1631 paddress (gdbarch, pc));
1633 insn = extract_unsigned_integer (buf, 4, byte_order);
1635 /* Get local store limit. */
1636 if ((regcache_cooked_read_unsigned (regcache, SPU_LSLR_REGNUM, &lslr)
1637 != REG_VALID) || !lslr)
1638 lslr = (ULONGEST) -1;
1640 /* Next sequential instruction is at PC + 4, except if the current
1641 instruction is a PPE-assisted call, in which case it is at PC + 8.
1642 Wrap around LS limit to be on the safe side. */
1643 if ((insn & 0xffffff00) == 0x00002100)
1644 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
1646 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
1648 next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), next_pc));
1650 if (is_branch (insn, &offset, ®))
1652 CORE_ADDR target = offset;
1654 if (reg == SPU_PC_REGNUM)
1655 target += SPUADDR_ADDR (pc);
1658 regcache_raw_read_part (regcache, reg, 0, 4, buf);
1659 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
1662 target = target & lslr;
1663 if (target != next_pc)
1664 next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), target));
1671 /* Longjmp support. */
1674 spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1676 struct gdbarch *gdbarch = get_frame_arch (frame);
1677 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1678 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1683 /* Jump buffer is pointed to by the argument register $r3. */
1684 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1688 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1689 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
1692 *pc = extract_unsigned_integer (buf, 4, byte_order);
1693 *pc = SPUADDR (tdep->id, *pc);
1700 struct spu_dis_asm_info : disassemble_info
1706 spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1708 struct spu_dis_asm_info *data = (struct spu_dis_asm_info *) info;
1709 gdb_disassembler *di
1710 = static_cast<gdb_disassembler *>(info->application_data);
1712 print_address (di->arch (), SPUADDR (data->id, addr),
1713 (struct ui_file *) info->stream);
1717 gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1719 /* The opcodes disassembler does 18-bit address arithmetic. Make
1720 sure the SPU ID encoded in the high bits is added back when we
1721 call print_address. */
1722 struct spu_dis_asm_info spu_info;
1724 memcpy (&spu_info, info, sizeof (*info));
1725 spu_info.id = SPUADDR_SPU (memaddr);
1726 spu_info.print_address_func = spu_dis_asm_print_address;
1727 return default_print_insn (memaddr, &spu_info);
1731 /* Target overlays for the SPU overlay manager.
1733 See the documentation of simple_overlay_update for how the
1734 interface is supposed to work.
1736 Data structures used by the overlay manager:
1744 } _ovly_table[]; -- one entry per overlay section
1746 struct ovly_buf_table
1749 } _ovly_buf_table[]; -- one entry per overlay buffer
1751 _ovly_table should never change.
1753 Both tables are aligned to a 16-byte boundary, the symbols
1754 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1755 size set to the size of the respective array. buf in _ovly_table is
1756 an index into _ovly_buf_table.
1758 mapped is an index into _ovly_table. Both the mapped and buf indices start
1759 from one to reference the first entry in their respective tables. */
1761 /* Using the per-objfile private data mechanism, we store for each
1762 objfile an array of "struct spu_overlay_table" structures, one
1763 for each obj_section of the objfile. This structure holds two
1764 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1765 is *not* an overlay section. If it is non-zero, it represents
1766 a target address. The overlay section is mapped iff the target
1767 integer at this location equals MAPPED_VAL. */
1769 static const struct objfile_data *spu_overlay_data;
1771 struct spu_overlay_table
1773 CORE_ADDR mapped_ptr;
1774 CORE_ADDR mapped_val;
1777 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1778 the _ovly_table data structure from the target and initialize the
1779 spu_overlay_table data structure from it. */
1780 static struct spu_overlay_table *
1781 spu_get_overlay_table (struct objfile *objfile)
1783 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1784 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
1785 struct bound_minimal_symbol ovly_table_msym, ovly_buf_table_msym;
1786 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1787 unsigned ovly_table_size, ovly_buf_table_size;
1788 struct spu_overlay_table *tbl;
1789 struct obj_section *osect;
1790 gdb_byte *ovly_table;
1793 tbl = (struct spu_overlay_table *) objfile_data (objfile, spu_overlay_data);
1797 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1798 if (!ovly_table_msym.minsym)
1801 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1803 if (!ovly_buf_table_msym.minsym)
1806 ovly_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_table_msym);
1807 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym.minsym);
1809 ovly_buf_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1810 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym.minsym);
1812 ovly_table = (gdb_byte *) xmalloc (ovly_table_size);
1813 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1815 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1816 objfile->sections_end - objfile->sections,
1817 struct spu_overlay_table);
1819 for (i = 0; i < ovly_table_size / 16; i++)
1821 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1823 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1825 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1827 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1830 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1833 ALL_OBJFILE_OSECTIONS (objfile, osect)
1834 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1835 && pos == osect->the_bfd_section->filepos)
1837 int ndx = osect - objfile->sections;
1838 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1839 tbl[ndx].mapped_val = i + 1;
1845 set_objfile_data (objfile, spu_overlay_data, tbl);
1849 /* Read _ovly_buf_table entry from the target to dermine whether
1850 OSECT is currently mapped, and update the mapped state. */
1852 spu_overlay_update_osect (struct obj_section *osect)
1854 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1855 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
1856 struct spu_overlay_table *ovly_table;
1859 ovly_table = spu_get_overlay_table (osect->objfile);
1863 ovly_table += osect - osect->objfile->sections;
1864 if (ovly_table->mapped_ptr == 0)
1867 id = SPUADDR_SPU (obj_section_addr (osect));
1868 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1870 osect->ovly_mapped = (val == ovly_table->mapped_val);
1873 /* If OSECT is NULL, then update all sections' mapped state.
1874 If OSECT is non-NULL, then update only OSECT's mapped state. */
1876 spu_overlay_update (struct obj_section *osect)
1878 /* Just one section. */
1880 spu_overlay_update_osect (osect);
1885 struct objfile *objfile;
1887 ALL_OBJSECTIONS (objfile, osect)
1888 if (section_is_overlay (osect))
1889 spu_overlay_update_osect (osect);
1893 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1894 If there is one, go through all sections and make sure for non-
1895 overlay sections LMA equals VMA, while for overlay sections LMA
1896 is larger than SPU_OVERLAY_LMA. */
1898 spu_overlay_new_objfile (struct objfile *objfile)
1900 struct spu_overlay_table *ovly_table;
1901 struct obj_section *osect;
1903 /* If we've already touched this file, do nothing. */
1904 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1907 /* Consider only SPU objfiles. */
1908 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1911 /* Check if this objfile has overlays. */
1912 ovly_table = spu_get_overlay_table (objfile);
1916 /* Now go and fiddle with all the LMAs. */
1917 ALL_OBJFILE_OSECTIONS (objfile, osect)
1919 asection *bsect = osect->the_bfd_section;
1920 int ndx = osect - objfile->sections;
1922 if (ovly_table[ndx].mapped_ptr == 0)
1923 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1925 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
1930 /* Insert temporary breakpoint on "main" function of newly loaded
1931 SPE context OBJFILE. */
1933 spu_catch_start (struct objfile *objfile)
1935 struct bound_minimal_symbol minsym;
1936 struct compunit_symtab *cust;
1939 /* Do this only if requested by "set spu stop-on-load on". */
1940 if (!spu_stop_on_load_p)
1943 /* Consider only SPU objfiles. */
1944 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1947 /* The main objfile is handled differently. */
1948 if (objfile == symfile_objfile)
1951 /* There can be multiple symbols named "main". Search for the
1952 "main" in *this* objfile. */
1953 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1957 /* If we have debugging information, try to use it -- this
1958 will allow us to properly skip the prologue. */
1959 pc = BMSYMBOL_VALUE_ADDRESS (minsym);
1961 = find_pc_sect_compunit_symtab (pc, MSYMBOL_OBJ_SECTION (minsym.objfile,
1965 const struct blockvector *bv = COMPUNIT_BLOCKVECTOR (cust);
1966 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1968 struct symtab_and_line sal;
1970 sym = block_lookup_symbol (block, "main",
1971 symbol_name_match_type::SEARCH_NAME,
1975 fixup_symbol_section (sym, objfile);
1976 sal = find_function_start_sal (sym, 1);
1981 /* Use a numerical address for the set_breakpoint command to avoid having
1982 the breakpoint re-set incorrectly. */
1983 event_location_up location = new_address_location (pc, NULL, 0);
1984 create_breakpoint (get_objfile_arch (objfile), location.get (),
1985 NULL /* cond_string */, -1 /* thread */,
1986 NULL /* extra_string */,
1987 0 /* parse_condition_and_thread */, 1 /* tempflag */,
1988 bp_breakpoint /* type_wanted */,
1989 0 /* ignore_count */,
1990 AUTO_BOOLEAN_FALSE /* pending_break_support */,
1991 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
1992 1 /* enabled */, 0 /* internal */, 0);
1996 /* Look up OBJFILE loaded into FRAME's SPU context. */
1997 static struct objfile *
1998 spu_objfile_from_frame (struct frame_info *frame)
2000 struct gdbarch *gdbarch = get_frame_arch (frame);
2001 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2002 struct objfile *obj;
2004 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2009 if (obj->sections != obj->sections_end
2010 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
2017 /* Flush cache for ea pointer access if available. */
2019 flush_ea_cache (void)
2021 struct bound_minimal_symbol msymbol;
2022 struct objfile *obj;
2024 if (!has_stack_frames ())
2027 obj = spu_objfile_from_frame (get_current_frame ());
2031 /* Lookup inferior function __cache_flush. */
2032 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
2033 if (msymbol.minsym != NULL)
2038 type = objfile_type (obj)->builtin_void;
2039 type = lookup_function_type (type);
2040 type = lookup_pointer_type (type);
2041 addr = BMSYMBOL_VALUE_ADDRESS (msymbol);
2043 call_function_by_hand (value_from_pointer (type, addr), NULL, 0, NULL);
2047 /* This handler is called when the inferior has stopped. If it is stopped in
2048 SPU architecture then flush the ea cache if used. */
2050 spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2052 if (!spu_auto_flush_cache_p)
2055 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2056 re-entering this function when __cache_flush stops. */
2057 spu_auto_flush_cache_p = 0;
2059 spu_auto_flush_cache_p = 1;
2063 /* "info spu" commands. */
2066 info_spu_event_command (const char *args, int from_tty)
2068 struct frame_info *frame = get_selected_frame (NULL);
2069 ULONGEST event_status = 0;
2070 ULONGEST event_mask = 0;
2076 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2077 error (_("\"info spu\" is only supported on the SPU architecture."));
2079 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2081 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2082 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2083 buf, 0, (sizeof (buf) - 1));
2085 error (_("Could not read event_status."));
2087 event_status = strtoulst ((char *) buf, NULL, 16);
2089 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2090 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2091 buf, 0, (sizeof (buf) - 1));
2093 error (_("Could not read event_mask."));
2095 event_mask = strtoulst ((char *) buf, NULL, 16);
2097 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoEvent");
2099 if (current_uiout->is_mi_like_p ())
2101 current_uiout->field_fmt ("event_status",
2102 "0x%s", phex_nz (event_status, 4));
2103 current_uiout->field_fmt ("event_mask",
2104 "0x%s", phex_nz (event_mask, 4));
2108 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2109 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2114 info_spu_signal_command (const char *args, int from_tty)
2116 struct frame_info *frame = get_selected_frame (NULL);
2117 struct gdbarch *gdbarch = get_frame_arch (frame);
2118 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2119 ULONGEST signal1 = 0;
2120 ULONGEST signal1_type = 0;
2121 int signal1_pending = 0;
2122 ULONGEST signal2 = 0;
2123 ULONGEST signal2_type = 0;
2124 int signal2_pending = 0;
2130 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2131 error (_("\"info spu\" is only supported on the SPU architecture."));
2133 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2135 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2136 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2138 error (_("Could not read signal1."));
2141 signal1 = extract_unsigned_integer (buf, 4, byte_order);
2142 signal1_pending = 1;
2145 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2146 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2147 buf, 0, (sizeof (buf) - 1));
2149 error (_("Could not read signal1_type."));
2151 signal1_type = strtoulst ((char *) buf, NULL, 16);
2153 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2154 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2156 error (_("Could not read signal2."));
2159 signal2 = extract_unsigned_integer (buf, 4, byte_order);
2160 signal2_pending = 1;
2163 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2164 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2165 buf, 0, (sizeof (buf) - 1));
2167 error (_("Could not read signal2_type."));
2169 signal2_type = strtoulst ((char *) buf, NULL, 16);
2171 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoSignal");
2173 if (current_uiout->is_mi_like_p ())
2175 current_uiout->field_int ("signal1_pending", signal1_pending);
2176 current_uiout->field_fmt ("signal1", "0x%s", phex_nz (signal1, 4));
2177 current_uiout->field_int ("signal1_type", signal1_type);
2178 current_uiout->field_int ("signal2_pending", signal2_pending);
2179 current_uiout->field_fmt ("signal2", "0x%s", phex_nz (signal2, 4));
2180 current_uiout->field_int ("signal2_type", signal2_type);
2184 if (signal1_pending)
2185 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2187 printf_filtered (_("Signal 1 not pending "));
2190 printf_filtered (_("(Type Or)\n"));
2192 printf_filtered (_("(Type Overwrite)\n"));
2194 if (signal2_pending)
2195 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2197 printf_filtered (_("Signal 2 not pending "));
2200 printf_filtered (_("(Type Or)\n"));
2202 printf_filtered (_("(Type Overwrite)\n"));
2207 info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
2208 const char *field, const char *msg)
2215 ui_out_emit_table table_emitter (current_uiout, 1, nr, "mbox");
2217 current_uiout->table_header (32, ui_left, field, msg);
2218 current_uiout->table_body ();
2220 for (i = 0; i < nr; i++)
2224 ui_out_emit_tuple tuple_emitter (current_uiout, "mbox");
2225 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
2226 current_uiout->field_fmt (field, "0x%s", phex (val, 4));
2229 if (!current_uiout->is_mi_like_p ())
2230 printf_filtered ("\n");
2235 info_spu_mailbox_command (const char *args, int from_tty)
2237 struct frame_info *frame = get_selected_frame (NULL);
2238 struct gdbarch *gdbarch = get_frame_arch (frame);
2239 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2245 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2246 error (_("\"info spu\" is only supported on the SPU architecture."));
2248 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2250 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoMailbox");
2252 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2253 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2254 buf, 0, sizeof buf);
2256 error (_("Could not read mbox_info."));
2258 info_spu_mailbox_list (buf, len / 4, byte_order,
2259 "mbox", "SPU Outbound Mailbox");
2261 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2262 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2263 buf, 0, sizeof buf);
2265 error (_("Could not read ibox_info."));
2267 info_spu_mailbox_list (buf, len / 4, byte_order,
2268 "ibox", "SPU Outbound Interrupt Mailbox");
2270 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2271 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2272 buf, 0, sizeof buf);
2274 error (_("Could not read wbox_info."));
2276 info_spu_mailbox_list (buf, len / 4, byte_order,
2277 "wbox", "SPU Inbound Mailbox");
2281 spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2283 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2284 return (word >> (63 - last)) & mask;
2288 info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
2290 static const char *spu_mfc_opcode[256] =
2292 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2293 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2294 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2295 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2296 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2297 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2298 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2299 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2300 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2301 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2302 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2303 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2304 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2305 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2306 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2307 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2308 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2309 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2310 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2311 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2312 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2313 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2314 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2315 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2316 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2317 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2318 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2319 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2320 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2321 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2322 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2323 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2326 int *seq = XALLOCAVEC (int, nr);
2331 /* Determine sequence in which to display (valid) entries. */
2332 for (i = 0; i < nr; i++)
2334 /* Search for the first valid entry all of whose
2335 dependencies are met. */
2336 for (j = 0; j < nr; j++)
2338 ULONGEST mfc_cq_dw3;
2339 ULONGEST dependencies;
2341 if (done & (1 << (nr - 1 - j)))
2345 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
2346 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2349 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2350 if ((dependencies & done) != dependencies)
2354 done |= 1 << (nr - 1 - j);
2365 ui_out_emit_table table_emitter (current_uiout, 10, nr, "dma_cmd");
2367 current_uiout->table_header (7, ui_left, "opcode", "Opcode");
2368 current_uiout->table_header (3, ui_left, "tag", "Tag");
2369 current_uiout->table_header (3, ui_left, "tid", "TId");
2370 current_uiout->table_header (3, ui_left, "rid", "RId");
2371 current_uiout->table_header (18, ui_left, "ea", "EA");
2372 current_uiout->table_header (7, ui_left, "lsa", "LSA");
2373 current_uiout->table_header (7, ui_left, "size", "Size");
2374 current_uiout->table_header (7, ui_left, "lstaddr", "LstAddr");
2375 current_uiout->table_header (7, ui_left, "lstsize", "LstSize");
2376 current_uiout->table_header (1, ui_left, "error_p", "E");
2378 current_uiout->table_body ();
2380 for (i = 0; i < nr; i++)
2382 ULONGEST mfc_cq_dw0;
2383 ULONGEST mfc_cq_dw1;
2384 ULONGEST mfc_cq_dw2;
2385 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2386 int list_lsa, list_size, mfc_lsa, mfc_size;
2388 int list_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2390 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2391 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2394 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2396 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2398 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
2400 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2401 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2402 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2403 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2404 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2405 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2406 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2408 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2409 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2411 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2412 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2413 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2414 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2415 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2418 ui_out_emit_tuple tuple_emitter (current_uiout, "cmd");
2420 if (spu_mfc_opcode[mfc_cmd_opcode])
2421 current_uiout->field_string ("opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2423 current_uiout->field_int ("opcode", mfc_cmd_opcode);
2425 current_uiout->field_int ("tag", mfc_cmd_tag);
2426 current_uiout->field_int ("tid", tclass_id);
2427 current_uiout->field_int ("rid", rclass_id);
2430 current_uiout->field_fmt ("ea", "0x%s", phex (mfc_ea, 8));
2432 current_uiout->field_skip ("ea");
2434 current_uiout->field_fmt ("lsa", "0x%05x", mfc_lsa << 4);
2436 current_uiout->field_fmt ("size", "0x%05x", mfc_size << 4);
2438 current_uiout->field_fmt ("size", "0x%05x", mfc_size);
2442 current_uiout->field_fmt ("lstaddr", "0x%05x", list_lsa << 3);
2443 current_uiout->field_fmt ("lstsize", "0x%05x", list_size << 3);
2447 current_uiout->field_skip ("lstaddr");
2448 current_uiout->field_skip ("lstsize");
2452 current_uiout->field_string ("error_p", "*");
2454 current_uiout->field_skip ("error_p");
2457 if (!current_uiout->is_mi_like_p ())
2458 printf_filtered ("\n");
2463 info_spu_dma_command (const char *args, int from_tty)
2465 struct frame_info *frame = get_selected_frame (NULL);
2466 struct gdbarch *gdbarch = get_frame_arch (frame);
2467 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2468 ULONGEST dma_info_type;
2469 ULONGEST dma_info_mask;
2470 ULONGEST dma_info_status;
2471 ULONGEST dma_info_stall_and_notify;
2472 ULONGEST dma_info_atomic_command_status;
2478 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2479 error (_("\"info spu\" is only supported on the SPU architecture."));
2481 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2483 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2484 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2485 buf, 0, 40 + 16 * 32);
2487 error (_("Could not read dma_info."));
2490 = extract_unsigned_integer (buf, 8, byte_order);
2492 = extract_unsigned_integer (buf + 8, 8, byte_order);
2494 = extract_unsigned_integer (buf + 16, 8, byte_order);
2495 dma_info_stall_and_notify
2496 = extract_unsigned_integer (buf + 24, 8, byte_order);
2497 dma_info_atomic_command_status
2498 = extract_unsigned_integer (buf + 32, 8, byte_order);
2500 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoDMA");
2502 if (current_uiout->is_mi_like_p ())
2504 current_uiout->field_fmt ("dma_info_type", "0x%s",
2505 phex_nz (dma_info_type, 4));
2506 current_uiout->field_fmt ("dma_info_mask", "0x%s",
2507 phex_nz (dma_info_mask, 4));
2508 current_uiout->field_fmt ("dma_info_status", "0x%s",
2509 phex_nz (dma_info_status, 4));
2510 current_uiout->field_fmt ("dma_info_stall_and_notify", "0x%s",
2511 phex_nz (dma_info_stall_and_notify, 4));
2512 current_uiout->field_fmt ("dma_info_atomic_command_status", "0x%s",
2513 phex_nz (dma_info_atomic_command_status, 4));
2517 const char *query_msg = _("no query pending");
2519 if (dma_info_type & 4)
2520 switch (dma_info_type & 3)
2522 case 1: query_msg = _("'any' query pending"); break;
2523 case 2: query_msg = _("'all' query pending"); break;
2524 default: query_msg = _("undefined query type"); break;
2527 printf_filtered (_("Tag-Group Status 0x%s\n"),
2528 phex (dma_info_status, 4));
2529 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2530 phex (dma_info_mask, 4), query_msg);
2531 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2532 phex (dma_info_stall_and_notify, 4));
2533 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2534 phex (dma_info_atomic_command_status, 4));
2535 printf_filtered ("\n");
2538 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
2542 info_spu_proxydma_command (const char *args, int from_tty)
2544 struct frame_info *frame = get_selected_frame (NULL);
2545 struct gdbarch *gdbarch = get_frame_arch (frame);
2546 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2547 ULONGEST dma_info_type;
2548 ULONGEST dma_info_mask;
2549 ULONGEST dma_info_status;
2555 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2556 error (_("\"info spu\" is only supported on the SPU architecture."));
2558 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2560 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2561 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2562 buf, 0, 24 + 8 * 32);
2564 error (_("Could not read proxydma_info."));
2566 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2567 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2568 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
2570 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoProxyDMA");
2572 if (current_uiout->is_mi_like_p ())
2574 current_uiout->field_fmt ("proxydma_info_type", "0x%s",
2575 phex_nz (dma_info_type, 4));
2576 current_uiout->field_fmt ("proxydma_info_mask", "0x%s",
2577 phex_nz (dma_info_mask, 4));
2578 current_uiout->field_fmt ("proxydma_info_status", "0x%s",
2579 phex_nz (dma_info_status, 4));
2583 const char *query_msg;
2585 switch (dma_info_type & 3)
2587 case 0: query_msg = _("no query pending"); break;
2588 case 1: query_msg = _("'any' query pending"); break;
2589 case 2: query_msg = _("'all' query pending"); break;
2590 default: query_msg = _("undefined query type"); break;
2593 printf_filtered (_("Tag-Group Status 0x%s\n"),
2594 phex (dma_info_status, 4));
2595 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2596 phex (dma_info_mask, 4), query_msg);
2597 printf_filtered ("\n");
2600 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
2604 info_spu_command (const char *args, int from_tty)
2606 printf_unfiltered (_("\"info spu\" must be followed by "
2607 "the name of an SPU facility.\n"));
2608 help_list (infospucmdlist, "info spu ", all_commands, gdb_stdout);
2612 /* Root of all "set spu "/"show spu " commands. */
2615 show_spu_command (const char *args, int from_tty)
2617 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2621 set_spu_command (const char *args, int from_tty)
2623 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2627 show_spu_stop_on_load (struct ui_file *file, int from_tty,
2628 struct cmd_list_element *c, const char *value)
2630 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2635 show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2636 struct cmd_list_element *c, const char *value)
2638 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2643 /* Set up gdbarch struct. */
2645 static struct gdbarch *
2646 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2648 struct gdbarch *gdbarch;
2649 struct gdbarch_tdep *tdep;
2652 /* Which spufs ID was requested as address space? */
2655 /* For objfile architectures of SPU solibs, decode the ID from the name.
2656 This assumes the filename convention employed by solib-spu.c. */
2659 const char *name = strrchr (info.abfd->filename, '@');
2661 sscanf (name, "@0x%*x <%d>", &id);
2664 /* Find a candidate among extant architectures. */
2665 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2667 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2669 tdep = gdbarch_tdep (arches->gdbarch);
2670 if (tdep && tdep->id == id)
2671 return arches->gdbarch;
2674 /* None found, so create a new architecture. */
2675 tdep = XCNEW (struct gdbarch_tdep);
2677 gdbarch = gdbarch_alloc (&info, tdep);
2680 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
2683 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2684 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2685 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2686 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
2687 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2688 set_gdbarch_write_pc (gdbarch, spu_write_pc);
2689 set_gdbarch_register_name (gdbarch, spu_register_name);
2690 set_gdbarch_register_type (gdbarch, spu_register_type);
2691 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2692 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
2693 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
2694 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2695 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, spu_dwarf_reg_to_regnum);
2696 set_gdbarch_ax_pseudo_register_collect
2697 (gdbarch, spu_ax_pseudo_register_collect);
2698 set_gdbarch_ax_pseudo_register_push_stack
2699 (gdbarch, spu_ax_pseudo_register_push_stack);
2702 set_gdbarch_char_signed (gdbarch, 0);
2703 set_gdbarch_ptr_bit (gdbarch, 32);
2704 set_gdbarch_addr_bit (gdbarch, 32);
2705 set_gdbarch_short_bit (gdbarch, 16);
2706 set_gdbarch_int_bit (gdbarch, 32);
2707 set_gdbarch_long_bit (gdbarch, 32);
2708 set_gdbarch_long_long_bit (gdbarch, 64);
2709 set_gdbarch_float_bit (gdbarch, 32);
2710 set_gdbarch_double_bit (gdbarch, 64);
2711 set_gdbarch_long_double_bit (gdbarch, 64);
2712 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2713 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2714 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2716 /* Address handling. */
2717 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
2718 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2719 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2720 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2721 set_gdbarch_address_class_type_flags_to_name
2722 (gdbarch, spu_address_class_type_flags_to_name);
2723 set_gdbarch_address_class_name_to_type_flags
2724 (gdbarch, spu_address_class_name_to_type_flags);
2726 /* We need to support more than "addr_bit" significant address bits
2727 in order to support SPUADDR_ADDR encoded values. */
2728 set_gdbarch_significant_addr_bit (gdbarch, 64);
2730 /* Inferior function calls. */
2731 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2732 set_gdbarch_frame_align (gdbarch, spu_frame_align);
2733 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
2734 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
2735 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
2736 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
2737 set_gdbarch_return_value (gdbarch, spu_return_value);
2739 /* Frame handling. */
2740 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2741 dwarf2_append_unwinders (gdbarch);
2742 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
2743 frame_base_set_default (gdbarch, &spu_frame_base);
2744 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2745 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2746 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2747 set_gdbarch_frame_args_skip (gdbarch, 0);
2748 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
2749 set_gdbarch_stack_frame_destroyed_p (gdbarch, spu_stack_frame_destroyed_p);
2751 /* Cell/B.E. cross-architecture unwinder support. */
2752 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2755 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2756 set_gdbarch_breakpoint_kind_from_pc (gdbarch, spu_breakpoint::kind_from_pc);
2757 set_gdbarch_sw_breakpoint_from_kind (gdbarch, spu_breakpoint::bp_from_kind);
2758 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
2759 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2760 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
2763 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2769 _initialize_spu_tdep (void)
2771 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
2773 /* Add ourselves to objfile event chain. */
2774 observer_attach_new_objfile (spu_overlay_new_objfile);
2775 spu_overlay_data = register_objfile_data ();
2777 /* Install spu stop-on-load handler. */
2778 observer_attach_new_objfile (spu_catch_start);
2780 /* Add ourselves to normal_stop event chain. */
2781 observer_attach_normal_stop (spu_attach_normal_stop);
2783 /* Add root prefix command for all "set spu"/"show spu" commands. */
2784 add_prefix_cmd ("spu", no_class, set_spu_command,
2785 _("Various SPU specific commands."),
2786 &setspucmdlist, "set spu ", 0, &setlist);
2787 add_prefix_cmd ("spu", no_class, show_spu_command,
2788 _("Various SPU specific commands."),
2789 &showspucmdlist, "show spu ", 0, &showlist);
2791 /* Toggle whether or not to add a temporary breakpoint at the "main"
2792 function of new SPE contexts. */
2793 add_setshow_boolean_cmd ("stop-on-load", class_support,
2794 &spu_stop_on_load_p, _("\
2795 Set whether to stop for new SPE threads."),
2797 Show whether to stop for new SPE threads."),
2799 Use \"on\" to give control to the user when a new SPE thread\n\
2800 enters its \"main\" function.\n\
2801 Use \"off\" to disable stopping for new SPE threads."),
2803 show_spu_stop_on_load,
2804 &setspucmdlist, &showspucmdlist);
2806 /* Toggle whether or not to automatically flush the software-managed
2807 cache whenever SPE execution stops. */
2808 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2809 &spu_auto_flush_cache_p, _("\
2810 Set whether to automatically flush the software-managed cache."),
2812 Show whether to automatically flush the software-managed cache."),
2814 Use \"on\" to automatically flush the software-managed cache\n\
2815 whenever SPE execution stops.\n\
2816 Use \"off\" to never automatically flush the software-managed cache."),
2818 show_spu_auto_flush_cache,
2819 &setspucmdlist, &showspucmdlist);
2821 /* Add root prefix command for all "info spu" commands. */
2822 add_prefix_cmd ("spu", class_info, info_spu_command,
2823 _("Various SPU specific commands."),
2824 &infospucmdlist, "info spu ", 0, &infolist);
2826 /* Add various "info spu" commands. */
2827 add_cmd ("event", class_info, info_spu_event_command,
2828 _("Display SPU event facility status.\n"),
2830 add_cmd ("signal", class_info, info_spu_signal_command,
2831 _("Display SPU signal notification facility status.\n"),
2833 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2834 _("Display SPU mailbox facility status.\n"),
2836 add_cmd ("dma", class_info, info_spu_dma_command,
2837 _("Display MFC DMA status.\n"),
2839 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2840 _("Display MFC Proxy-DMA status.\n"),