1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006-2017 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
40 #include "reggroups.h"
41 #include "floatformat.h"
46 #include "dwarf2-frame.h"
51 /* The list of available "set spu " and "show spu " commands. */
52 static struct cmd_list_element *setspucmdlist = NULL;
53 static struct cmd_list_element *showspucmdlist = NULL;
55 /* Whether to stop for new SPE contexts. */
56 static int spu_stop_on_load_p = 0;
57 /* Whether to automatically flush the SW-managed cache. */
58 static int spu_auto_flush_cache_p = 1;
61 /* The tdep structure. */
64 /* The spufs ID identifying our address space. */
67 /* SPU-specific vector type. */
68 struct type *spu_builtin_type_vec128;
72 /* SPU-specific vector type. */
74 spu_builtin_type_vec128 (struct gdbarch *gdbarch)
76 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
78 if (!tdep->spu_builtin_type_vec128)
80 const struct builtin_type *bt = builtin_type (gdbarch);
83 t = arch_composite_type (gdbarch,
84 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
85 append_composite_type_field (t, "uint128", bt->builtin_int128);
86 append_composite_type_field (t, "v2_int64",
87 init_vector_type (bt->builtin_int64, 2));
88 append_composite_type_field (t, "v4_int32",
89 init_vector_type (bt->builtin_int32, 4));
90 append_composite_type_field (t, "v8_int16",
91 init_vector_type (bt->builtin_int16, 8));
92 append_composite_type_field (t, "v16_int8",
93 init_vector_type (bt->builtin_int8, 16));
94 append_composite_type_field (t, "v2_double",
95 init_vector_type (bt->builtin_double, 2));
96 append_composite_type_field (t, "v4_float",
97 init_vector_type (bt->builtin_float, 4));
100 TYPE_NAME (t) = "spu_builtin_type_vec128";
102 tdep->spu_builtin_type_vec128 = t;
105 return tdep->spu_builtin_type_vec128;
109 /* The list of available "info spu " commands. */
110 static struct cmd_list_element *infospucmdlist = NULL;
115 spu_register_name (struct gdbarch *gdbarch, int reg_nr)
117 static const char *register_names[] =
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
122 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
123 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
124 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
125 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
126 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
127 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
128 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
129 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
130 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
131 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
132 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
133 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
134 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
135 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
140 if (reg_nr >= sizeof register_names / sizeof *register_names)
143 return register_names[reg_nr];
147 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
149 if (reg_nr < SPU_NUM_GPRS)
150 return spu_builtin_type_vec128 (gdbarch);
155 return builtin_type (gdbarch)->builtin_uint32;
158 return builtin_type (gdbarch)->builtin_func_ptr;
161 return builtin_type (gdbarch)->builtin_data_ptr;
163 case SPU_FPSCR_REGNUM:
164 return builtin_type (gdbarch)->builtin_uint128;
166 case SPU_SRR0_REGNUM:
167 return builtin_type (gdbarch)->builtin_uint32;
169 case SPU_LSLR_REGNUM:
170 return builtin_type (gdbarch)->builtin_uint32;
172 case SPU_DECR_REGNUM:
173 return builtin_type (gdbarch)->builtin_uint32;
175 case SPU_DECR_STATUS_REGNUM:
176 return builtin_type (gdbarch)->builtin_uint32;
179 internal_error (__FILE__, __LINE__, _("invalid regnum"));
183 /* Pseudo registers for preferred slots - stack pointer. */
185 static enum register_status
186 spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
189 struct gdbarch *gdbarch = get_regcache_arch (regcache);
190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
191 enum register_status status;
197 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
198 if (status != REG_VALID)
200 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
201 memset (reg, 0, sizeof reg);
202 target_read (¤t_target, TARGET_OBJECT_SPU, annex,
205 ul = strtoulst ((char *) reg, NULL, 16);
206 store_unsigned_integer (buf, 4, byte_order, ul);
210 static enum register_status
211 spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
212 int regnum, gdb_byte *buf)
217 enum register_status status;
222 status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
223 if (status != REG_VALID)
225 memcpy (buf, reg, 4);
228 case SPU_FPSCR_REGNUM:
229 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
230 if (status != REG_VALID)
232 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
233 target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
236 case SPU_SRR0_REGNUM:
237 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
239 case SPU_LSLR_REGNUM:
240 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
242 case SPU_DECR_REGNUM:
243 return spu_pseudo_register_read_spu (regcache, "decr", buf);
245 case SPU_DECR_STATUS_REGNUM:
246 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
249 internal_error (__FILE__, __LINE__, _("invalid regnum"));
254 spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
257 struct gdbarch *gdbarch = get_regcache_arch (regcache);
258 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
263 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
264 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
265 xsnprintf (reg, sizeof reg, "0x%s",
266 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
267 target_write (¤t_target, TARGET_OBJECT_SPU, annex,
268 (gdb_byte *) reg, 0, strlen (reg));
272 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
273 int regnum, const gdb_byte *buf)
282 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
283 memcpy (reg, buf, 4);
284 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
287 case SPU_FPSCR_REGNUM:
288 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
289 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
290 target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
293 case SPU_SRR0_REGNUM:
294 spu_pseudo_register_write_spu (regcache, "srr0", buf);
297 case SPU_LSLR_REGNUM:
298 spu_pseudo_register_write_spu (regcache, "lslr", buf);
301 case SPU_DECR_REGNUM:
302 spu_pseudo_register_write_spu (regcache, "decr", buf);
305 case SPU_DECR_STATUS_REGNUM:
306 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
310 internal_error (__FILE__, __LINE__, _("invalid regnum"));
315 spu_ax_pseudo_register_collect (struct gdbarch *gdbarch,
316 struct agent_expr *ax, int regnum)
321 ax_reg_mask (ax, SPU_RAW_SP_REGNUM);
324 case SPU_FPSCR_REGNUM:
325 case SPU_SRR0_REGNUM:
326 case SPU_LSLR_REGNUM:
327 case SPU_DECR_REGNUM:
328 case SPU_DECR_STATUS_REGNUM:
332 internal_error (__FILE__, __LINE__, _("invalid regnum"));
337 spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
338 struct agent_expr *ax, int regnum)
343 ax_reg (ax, SPU_RAW_SP_REGNUM);
346 case SPU_FPSCR_REGNUM:
347 case SPU_SRR0_REGNUM:
348 case SPU_LSLR_REGNUM:
349 case SPU_DECR_REGNUM:
350 case SPU_DECR_STATUS_REGNUM:
354 internal_error (__FILE__, __LINE__, _("invalid regnum"));
359 /* Value conversion -- access scalar values at the preferred slot. */
361 static struct value *
362 spu_value_from_register (struct gdbarch *gdbarch, struct type *type,
363 int regnum, struct frame_id frame_id)
365 struct value *value = default_value_from_register (gdbarch, type,
367 LONGEST len = TYPE_LENGTH (type);
369 if (regnum < SPU_NUM_GPRS && len < 16)
371 int preferred_slot = len < 4 ? 4 - len : 0;
372 set_value_offset (value, preferred_slot);
378 /* Register groups. */
381 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
382 struct reggroup *group)
384 /* Registers displayed via 'info regs'. */
385 if (group == general_reggroup)
388 /* Registers displayed via 'info float'. */
389 if (group == float_reggroup)
392 /* Registers that need to be saved/restored in order to
393 push or pop frames. */
394 if (group == save_reggroup || group == restore_reggroup)
397 return default_register_reggroup_p (gdbarch, regnum, group);
400 /* DWARF-2 register numbers. */
403 spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
405 /* Use cooked instead of raw SP. */
406 return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg;
410 /* Address handling. */
413 spu_gdbarch_id (struct gdbarch *gdbarch)
415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
418 /* The objfile architecture of a standalone SPU executable does not
419 provide an SPU ID. Retrieve it from the objfile's relocated
420 address range in this special case. */
422 && symfile_objfile && symfile_objfile->obfd
423 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
424 && symfile_objfile->sections != symfile_objfile->sections_end)
425 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
431 spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
433 if (dwarf2_addr_class == 1)
434 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
440 spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
442 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
449 spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
450 const char *name, int *type_flags_ptr)
452 if (strcmp (name, "__ea") == 0)
454 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
462 spu_address_to_pointer (struct gdbarch *gdbarch,
463 struct type *type, gdb_byte *buf, CORE_ADDR addr)
465 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
466 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
467 SPUADDR_ADDR (addr));
471 spu_pointer_to_address (struct gdbarch *gdbarch,
472 struct type *type, const gdb_byte *buf)
474 int id = spu_gdbarch_id (gdbarch);
475 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
477 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
479 /* Do not convert __ea pointers. */
480 if (TYPE_ADDRESS_CLASS_1 (type))
483 return addr? SPUADDR (id, addr) : 0;
487 spu_integer_to_address (struct gdbarch *gdbarch,
488 struct type *type, const gdb_byte *buf)
490 int id = spu_gdbarch_id (gdbarch);
491 ULONGEST addr = unpack_long (type, buf);
493 return SPUADDR (id, addr);
497 /* Decoding SPU instructions. */
534 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
536 if ((insn >> 21) == op)
539 *ra = (insn >> 7) & 127;
540 *rb = (insn >> 14) & 127;
548 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
550 if ((insn >> 28) == op)
552 *rt = (insn >> 21) & 127;
553 *ra = (insn >> 7) & 127;
554 *rb = (insn >> 14) & 127;
563 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
565 if ((insn >> 21) == op)
568 *ra = (insn >> 7) & 127;
569 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
577 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
579 if ((insn >> 24) == op)
582 *ra = (insn >> 7) & 127;
583 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
591 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
593 if ((insn >> 23) == op)
596 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
604 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
606 if ((insn >> 25) == op)
609 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
617 is_branch (unsigned int insn, int *offset, int *reg)
621 if (is_ri16 (insn, op_br, &rt, &i16)
622 || is_ri16 (insn, op_brsl, &rt, &i16)
623 || is_ri16 (insn, op_brnz, &rt, &i16)
624 || is_ri16 (insn, op_brz, &rt, &i16)
625 || is_ri16 (insn, op_brhnz, &rt, &i16)
626 || is_ri16 (insn, op_brhz, &rt, &i16))
628 *reg = SPU_PC_REGNUM;
633 if (is_ri16 (insn, op_bra, &rt, &i16)
634 || is_ri16 (insn, op_brasl, &rt, &i16))
641 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
642 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
643 || is_ri7 (insn, op_biz, &rt, reg, &i7)
644 || is_ri7 (insn, op_binz, &rt, reg, &i7)
645 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
646 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
656 /* Prolog parsing. */
658 struct spu_prologue_data
660 /* Stack frame size. -1 if analysis was unsuccessful. */
663 /* How to find the CFA. The CFA is equal to SP at function entry. */
667 /* Offset relative to CFA where a register is saved. -1 if invalid. */
668 int reg_offset[SPU_NUM_GPRS];
672 spu_analyze_prologue (struct gdbarch *gdbarch,
673 CORE_ADDR start_pc, CORE_ADDR end_pc,
674 struct spu_prologue_data *data)
676 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
681 int reg_immed[SPU_NUM_GPRS];
683 CORE_ADDR prolog_pc = start_pc;
688 /* Initialize DATA to default values. */
691 data->cfa_reg = SPU_RAW_SP_REGNUM;
692 data->cfa_offset = 0;
694 for (i = 0; i < SPU_NUM_GPRS; i++)
695 data->reg_offset[i] = -1;
697 /* Set up REG_IMMED array. This is non-zero for a register if we know its
698 preferred slot currently holds this immediate value. */
699 for (i = 0; i < SPU_NUM_GPRS; i++)
702 /* Scan instructions until the first branch.
704 The following instructions are important prolog components:
706 - The first instruction to set up the stack pointer.
707 - The first instruction to set up the frame pointer.
708 - The first instruction to save the link register.
709 - The first instruction to save the backchain.
711 We return the instruction after the latest of these four,
712 or the incoming PC if none is found. The first instruction
713 to set up the stack pointer also defines the frame size.
715 Note that instructions saving incoming arguments to their stack
716 slots are not counted as important, because they are hard to
717 identify with certainty. This should not matter much, because
718 arguments are relevant only in code compiled with debug data,
719 and in such code the GDB core will advance until the first source
720 line anyway, using SAL data.
722 For purposes of stack unwinding, we analyze the following types
723 of instructions in addition:
725 - Any instruction adding to the current frame pointer.
726 - Any instruction loading an immediate constant into a register.
727 - Any instruction storing a register onto the stack.
729 These are used to compute the CFA and REG_OFFSET output. */
731 for (pc = start_pc; pc < end_pc; pc += 4)
734 int rt, ra, rb, rc, immed;
736 if (target_read_memory (pc, buf, 4))
738 insn = extract_unsigned_integer (buf, 4, byte_order);
740 /* AI is the typical instruction to set up a stack frame.
741 It is also used to initialize the frame pointer. */
742 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
744 if (rt == data->cfa_reg && ra == data->cfa_reg)
745 data->cfa_offset -= immed;
747 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
755 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
761 data->cfa_reg = SPU_FP_REGNUM;
762 data->cfa_offset -= immed;
766 /* A is used to set up stack frames of size >= 512 bytes.
767 If we have tracked the contents of the addend register,
768 we can handle this as well. */
769 else if (is_rr (insn, op_a, &rt, &ra, &rb))
771 if (rt == data->cfa_reg && ra == data->cfa_reg)
773 if (reg_immed[rb] != 0)
774 data->cfa_offset -= reg_immed[rb];
776 data->cfa_reg = -1; /* We don't know the CFA any more. */
779 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
785 if (reg_immed[rb] != 0)
786 data->size = -reg_immed[rb];
790 /* We need to track IL and ILA used to load immediate constants
791 in case they are later used as input to an A instruction. */
792 else if (is_ri16 (insn, op_il, &rt, &immed))
794 reg_immed[rt] = immed;
796 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
800 else if (is_ri18 (insn, op_ila, &rt, &immed))
802 reg_immed[rt] = immed & 0x3ffff;
804 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
808 /* STQD is used to save registers to the stack. */
809 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
811 if (ra == data->cfa_reg)
812 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
814 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
821 if (ra == SPU_RAW_SP_REGNUM
822 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
830 /* _start uses SELB to set up the stack pointer. */
831 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
833 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
837 /* We terminate if we find a branch. */
838 else if (is_branch (insn, &immed, &ra))
843 /* If we successfully parsed until here, and didn't find any instruction
844 modifying SP, we assume we have a frameless function. */
848 /* Return cooked instead of raw SP. */
849 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
850 data->cfa_reg = SPU_SP_REGNUM;
855 /* Return the first instruction after the prologue starting at PC. */
857 spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
859 struct spu_prologue_data data;
860 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
863 /* Return the frame pointer in use at address PC. */
865 spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
866 int *reg, LONGEST *offset)
868 struct spu_prologue_data data;
869 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
871 if (data.size != -1 && data.cfa_reg != -1)
873 /* The 'frame pointer' address is CFA minus frame size. */
875 *offset = data.cfa_offset - data.size;
879 /* ??? We don't really know ... */
880 *reg = SPU_SP_REGNUM;
885 /* Implement the stack_frame_destroyed_p gdbarch method.
887 1) scan forward from the point of execution:
888 a) If you find an instruction that modifies the stack pointer
889 or transfers control (except a return), execution is not in
891 b) Stop scanning if you find a return instruction or reach the
892 end of the function or reach the hard limit for the size of
894 2) scan backward from the point of execution:
895 a) If you find an instruction that modifies the stack pointer,
896 execution *is* in an epilogue, return.
897 b) Stop scanning if you reach an instruction that transfers
898 control or the beginning of the function or reach the hard
899 limit for the size of an epilogue. */
902 spu_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
904 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
905 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
908 int rt, ra, rb, immed;
910 /* Find the search limits based on function boundaries and hard limit.
911 We assume the epilogue can be up to 64 instructions long. */
913 const int spu_max_epilogue_size = 64 * 4;
915 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
918 if (pc - func_start < spu_max_epilogue_size)
919 epilogue_start = func_start;
921 epilogue_start = pc - spu_max_epilogue_size;
923 if (func_end - pc < spu_max_epilogue_size)
924 epilogue_end = func_end;
926 epilogue_end = pc + spu_max_epilogue_size;
928 /* Scan forward until next 'bi $0'. */
930 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
932 if (target_read_memory (scan_pc, buf, 4))
934 insn = extract_unsigned_integer (buf, 4, byte_order);
936 if (is_branch (insn, &immed, &ra))
938 if (immed == 0 && ra == SPU_LR_REGNUM)
944 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
945 || is_rr (insn, op_a, &rt, &ra, &rb)
946 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
948 if (rt == SPU_RAW_SP_REGNUM)
953 if (scan_pc >= epilogue_end)
956 /* Scan backward until adjustment to stack pointer (R1). */
958 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
960 if (target_read_memory (scan_pc, buf, 4))
962 insn = extract_unsigned_integer (buf, 4, byte_order);
964 if (is_branch (insn, &immed, &ra))
967 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
968 || is_rr (insn, op_a, &rt, &ra, &rb)
969 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
971 if (rt == SPU_RAW_SP_REGNUM)
980 /* Normal stack frames. */
982 struct spu_unwind_cache
985 CORE_ADDR frame_base;
986 CORE_ADDR local_base;
988 struct trad_frame_saved_reg *saved_regs;
991 static struct spu_unwind_cache *
992 spu_frame_unwind_cache (struct frame_info *this_frame,
993 void **this_prologue_cache)
995 struct gdbarch *gdbarch = get_frame_arch (this_frame);
996 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
997 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
998 struct spu_unwind_cache *info;
999 struct spu_prologue_data data;
1000 CORE_ADDR id = tdep->id;
1003 if (*this_prologue_cache)
1004 return (struct spu_unwind_cache *) *this_prologue_cache;
1006 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
1007 *this_prologue_cache = info;
1008 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1009 info->frame_base = 0;
1010 info->local_base = 0;
1012 /* Find the start of the current function, and analyze its prologue. */
1013 info->func = get_frame_func (this_frame);
1014 if (info->func == 0)
1016 /* Fall back to using the current PC as frame ID. */
1017 info->func = get_frame_pc (this_frame);
1021 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
1024 /* If successful, use prologue analysis data. */
1025 if (data.size != -1 && data.cfa_reg != -1)
1030 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
1031 get_frame_register (this_frame, data.cfa_reg, buf);
1032 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
1033 cfa = SPUADDR (id, cfa);
1035 /* Call-saved register slots. */
1036 for (i = 0; i < SPU_NUM_GPRS; i++)
1037 if (i == SPU_LR_REGNUM
1038 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
1039 if (data.reg_offset[i] != -1)
1040 info->saved_regs[i].addr = cfa - data.reg_offset[i];
1043 info->frame_base = cfa;
1044 info->local_base = cfa - data.size;
1047 /* Otherwise, fall back to reading the backchain link. */
1055 /* Get local store limit. */
1056 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1058 lslr = (ULONGEST) -1;
1060 /* Get the backchain. */
1061 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1062 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1065 /* A zero backchain terminates the frame chain. Also, sanity
1066 check against the local store size limit. */
1067 if (status && backchain > 0 && backchain <= lslr)
1069 /* Assume the link register is saved into its slot. */
1070 if (backchain + 16 <= lslr)
1071 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1075 info->frame_base = SPUADDR (id, backchain);
1076 info->local_base = SPUADDR (id, reg);
1080 /* If we didn't find a frame, we cannot determine SP / return address. */
1081 if (info->frame_base == 0)
1084 /* The previous SP is equal to the CFA. */
1085 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1086 SPUADDR_ADDR (info->frame_base));
1088 /* Read full contents of the unwound link register in order to
1089 be able to determine the return address. */
1090 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1091 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1093 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
1095 /* Normally, the return address is contained in the slot 0 of the
1096 link register, and slots 1-3 are zero. For an overlay return,
1097 slot 0 contains the address of the overlay manager return stub,
1098 slot 1 contains the partition number of the overlay section to
1099 be returned to, and slot 2 contains the return address within
1100 that section. Return the latter address in that case. */
1101 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
1102 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
1103 extract_unsigned_integer (buf + 8, 4, byte_order));
1105 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
1106 extract_unsigned_integer (buf, 4, byte_order));
1112 spu_frame_this_id (struct frame_info *this_frame,
1113 void **this_prologue_cache, struct frame_id *this_id)
1115 struct spu_unwind_cache *info =
1116 spu_frame_unwind_cache (this_frame, this_prologue_cache);
1118 if (info->frame_base == 0)
1121 *this_id = frame_id_build (info->frame_base, info->func);
1124 static struct value *
1125 spu_frame_prev_register (struct frame_info *this_frame,
1126 void **this_prologue_cache, int regnum)
1128 struct spu_unwind_cache *info
1129 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
1131 /* Special-case the stack pointer. */
1132 if (regnum == SPU_RAW_SP_REGNUM)
1133 regnum = SPU_SP_REGNUM;
1135 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1138 static const struct frame_unwind spu_frame_unwind = {
1140 default_frame_unwind_stop_reason,
1142 spu_frame_prev_register,
1144 default_frame_sniffer
1148 spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
1150 struct spu_unwind_cache *info
1151 = spu_frame_unwind_cache (this_frame, this_cache);
1152 return info->local_base;
1155 static const struct frame_base spu_frame_base = {
1157 spu_frame_base_address,
1158 spu_frame_base_address,
1159 spu_frame_base_address
1163 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1166 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1167 /* Mask off interrupt enable bit. */
1168 return SPUADDR (tdep->id, pc & -4);
1172 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1176 return SPUADDR (tdep->id, sp);
1180 spu_read_pc (struct regcache *regcache)
1182 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1184 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
1185 /* Mask off interrupt enable bit. */
1186 return SPUADDR (tdep->id, pc & -4);
1190 spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
1192 /* Keep interrupt enabled state unchanged. */
1195 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1196 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1197 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
1201 /* Cell/B.E. cross-architecture unwinder support. */
1203 struct spu2ppu_cache
1205 struct frame_id frame_id;
1206 struct regcache *regcache;
1209 static struct gdbarch *
1210 spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1212 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
1213 return get_regcache_arch (cache->regcache);
1217 spu2ppu_this_id (struct frame_info *this_frame,
1218 void **this_cache, struct frame_id *this_id)
1220 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
1221 *this_id = cache->frame_id;
1224 static struct value *
1225 spu2ppu_prev_register (struct frame_info *this_frame,
1226 void **this_cache, int regnum)
1228 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
1229 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1232 buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1233 regcache_cooked_read (cache->regcache, regnum, buf);
1234 return frame_unwind_got_bytes (this_frame, regnum, buf);
1238 spu2ppu_sniffer (const struct frame_unwind *self,
1239 struct frame_info *this_frame, void **this_prologue_cache)
1241 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1242 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1243 CORE_ADDR base, func, backchain;
1246 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu)
1249 base = get_frame_sp (this_frame);
1250 func = get_frame_pc (this_frame);
1251 if (target_read_memory (base, buf, 4))
1253 backchain = extract_unsigned_integer (buf, 4, byte_order);
1257 struct frame_info *fi;
1259 struct spu2ppu_cache *cache
1260 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1262 cache->frame_id = frame_id_build (base + 16, func);
1264 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1265 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1270 cache->regcache = frame_save_as_regcache (fi);
1271 *this_prologue_cache = cache;
1276 struct regcache *regcache;
1277 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ());
1278 cache->regcache = regcache_dup (regcache);
1279 *this_prologue_cache = cache;
1288 spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1290 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) this_cache;
1291 delete cache->regcache;
1294 static const struct frame_unwind spu2ppu_unwind = {
1296 default_frame_unwind_stop_reason,
1298 spu2ppu_prev_register,
1301 spu2ppu_dealloc_cache,
1306 /* Function calling convention. */
1309 spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1315 spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1316 struct value **args, int nargs, struct type *value_type,
1317 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1318 struct regcache *regcache)
1320 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1321 sp = (sp - 4) & ~15;
1322 /* Store the address of that breakpoint */
1324 /* The call starts at the callee's entry point. */
1331 spu_scalar_value_p (struct type *type)
1333 switch (TYPE_CODE (type))
1336 case TYPE_CODE_ENUM:
1337 case TYPE_CODE_RANGE:
1338 case TYPE_CODE_CHAR:
1339 case TYPE_CODE_BOOL:
1342 case TYPE_CODE_RVALUE_REF:
1343 return TYPE_LENGTH (type) <= 16;
1351 spu_value_to_regcache (struct regcache *regcache, int regnum,
1352 struct type *type, const gdb_byte *in)
1354 int len = TYPE_LENGTH (type);
1356 if (spu_scalar_value_p (type))
1358 int preferred_slot = len < 4 ? 4 - len : 0;
1359 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1365 regcache_cooked_write (regcache, regnum++, in);
1371 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1376 spu_regcache_to_value (struct regcache *regcache, int regnum,
1377 struct type *type, gdb_byte *out)
1379 int len = TYPE_LENGTH (type);
1381 if (spu_scalar_value_p (type))
1383 int preferred_slot = len < 4 ? 4 - len : 0;
1384 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1390 regcache_cooked_read (regcache, regnum++, out);
1396 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1401 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1402 struct regcache *regcache, CORE_ADDR bp_addr,
1403 int nargs, struct value **args, CORE_ADDR sp,
1404 int struct_return, CORE_ADDR struct_addr)
1406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1409 int regnum = SPU_ARG1_REGNUM;
1413 /* Set the return address. */
1414 memset (buf, 0, sizeof buf);
1415 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
1416 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1418 /* If STRUCT_RETURN is true, then the struct return address (in
1419 STRUCT_ADDR) will consume the first argument-passing register.
1420 Both adjust the register count and store that value. */
1423 memset (buf, 0, sizeof buf);
1424 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
1425 regcache_cooked_write (regcache, regnum++, buf);
1428 /* Fill in argument registers. */
1429 for (i = 0; i < nargs; i++)
1431 struct value *arg = args[i];
1432 struct type *type = check_typedef (value_type (arg));
1433 const gdb_byte *contents = value_contents (arg);
1434 int n_regs = align_up (TYPE_LENGTH (type), 16) / 16;
1436 /* If the argument doesn't wholly fit into registers, it and
1437 all subsequent arguments go to the stack. */
1438 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1444 spu_value_to_regcache (regcache, regnum, type, contents);
1448 /* Overflow arguments go to the stack. */
1449 if (stack_arg != -1)
1453 /* Allocate all required stack size. */
1454 for (i = stack_arg; i < nargs; i++)
1456 struct type *type = check_typedef (value_type (args[i]));
1457 sp -= align_up (TYPE_LENGTH (type), 16);
1460 /* Fill in stack arguments. */
1462 for (i = stack_arg; i < nargs; i++)
1464 struct value *arg = args[i];
1465 struct type *type = check_typedef (value_type (arg));
1466 int len = TYPE_LENGTH (type);
1469 if (spu_scalar_value_p (type))
1470 preferred_slot = len < 4 ? 4 - len : 0;
1474 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1475 ap += align_up (TYPE_LENGTH (type), 16);
1479 /* Allocate stack frame header. */
1482 /* Store stack back chain. */
1483 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1484 target_write_memory (sp, buf, 16);
1486 /* Finally, update all slots of the SP register. */
1487 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
1488 for (i = 0; i < 4; i++)
1490 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1491 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
1493 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
1498 static struct frame_id
1499 spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1502 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1503 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1504 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
1507 /* Function return value access. */
1509 static enum return_value_convention
1510 spu_return_value (struct gdbarch *gdbarch, struct value *function,
1511 struct type *type, struct regcache *regcache,
1512 gdb_byte *out, const gdb_byte *in)
1514 struct type *func_type = function ? value_type (function) : NULL;
1515 enum return_value_convention rvc;
1516 int opencl_vector = 0;
1520 func_type = check_typedef (func_type);
1522 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1523 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1525 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1526 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1527 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1528 && TYPE_VECTOR (type))
1532 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1533 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1535 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1541 case RETURN_VALUE_REGISTER_CONVENTION:
1542 if (opencl_vector && TYPE_LENGTH (type) == 2)
1543 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1545 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1548 case RETURN_VALUE_STRUCT_CONVENTION:
1549 error (_("Cannot set function return value."));
1557 case RETURN_VALUE_REGISTER_CONVENTION:
1558 if (opencl_vector && TYPE_LENGTH (type) == 2)
1559 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1561 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1564 case RETURN_VALUE_STRUCT_CONVENTION:
1565 error (_("Function return value unknown."));
1575 constexpr gdb_byte spu_break_insn[] = { 0x00, 0x00, 0x3f, 0xff };
1577 typedef BP_MANIPULATION (spu_break_insn) spu_breakpoint;
1580 spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1581 struct bp_target_info *bp_tgt)
1583 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1584 that in a combined application, we have some breakpoints inserted in SPU
1585 code, and now the application forks (on the PPU side). GDB common code
1586 will assume that the fork system call copied all breakpoints into the new
1587 process' address space, and that all those copies now need to be removed
1588 (see breakpoint.c:detach_breakpoints).
1590 While this is certainly true for PPU side breakpoints, it is not true
1591 for SPU side breakpoints. fork will clone the SPU context file
1592 descriptors, so that all the existing SPU contexts are in accessible
1593 in the new process. However, the contents of the SPU contexts themselves
1594 are *not* cloned. Therefore the effect of detach_breakpoints is to
1595 remove SPU breakpoints from the *original* SPU context's local store
1596 -- this is not the correct behaviour.
1598 The workaround is to check whether the PID we are asked to remove this
1599 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1600 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1601 true in the context of detach_breakpoints. If so, we simply do nothing.
1602 [ Note that for the fork child process, it does not matter if breakpoints
1603 remain inserted, because those SPU contexts are not runnable anyway --
1604 the Linux kernel allows only the original process to invoke spu_run. */
1606 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1609 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1613 /* Software single-stepping support. */
1615 static std::vector<CORE_ADDR>
1616 spu_software_single_step (struct regcache *regcache)
1618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1620 CORE_ADDR pc, next_pc;
1625 std::vector<CORE_ADDR> next_pcs;
1627 pc = regcache_read_pc (regcache);
1629 if (target_read_memory (pc, buf, 4))
1630 throw_error (MEMORY_ERROR, _("Could not read instruction at %s."),
1631 paddress (gdbarch, pc));
1633 insn = extract_unsigned_integer (buf, 4, byte_order);
1635 /* Get local store limit. */
1636 lslr = regcache_raw_get_unsigned (regcache, SPU_LSLR_REGNUM);
1638 lslr = (ULONGEST) -1;
1640 /* Next sequential instruction is at PC + 4, except if the current
1641 instruction is a PPE-assisted call, in which case it is at PC + 8.
1642 Wrap around LS limit to be on the safe side. */
1643 if ((insn & 0xffffff00) == 0x00002100)
1644 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
1646 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
1648 next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), next_pc));
1650 if (is_branch (insn, &offset, ®))
1652 CORE_ADDR target = offset;
1654 if (reg == SPU_PC_REGNUM)
1655 target += SPUADDR_ADDR (pc);
1657 target += regcache_raw_get_unsigned (regcache, reg) & -4;
1659 target = target & lslr;
1660 if (target != next_pc)
1661 next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), target));
1668 /* Longjmp support. */
1671 spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1673 struct gdbarch *gdbarch = get_frame_arch (frame);
1674 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1675 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1680 /* Jump buffer is pointed to by the argument register $r3. */
1681 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1685 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1686 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
1689 *pc = extract_unsigned_integer (buf, 4, byte_order);
1690 *pc = SPUADDR (tdep->id, *pc);
1697 struct spu_dis_asm_info : disassemble_info
1703 spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1705 struct spu_dis_asm_info *data = (struct spu_dis_asm_info *) info;
1706 gdb_disassembler *di
1707 = static_cast<gdb_disassembler *>(info->application_data);
1709 print_address (di->arch (), SPUADDR (data->id, addr),
1710 (struct ui_file *) info->stream);
1714 gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1716 /* The opcodes disassembler does 18-bit address arithmetic. Make
1717 sure the SPU ID encoded in the high bits is added back when we
1718 call print_address. */
1719 struct spu_dis_asm_info spu_info;
1721 memcpy (&spu_info, info, sizeof (*info));
1722 spu_info.id = SPUADDR_SPU (memaddr);
1723 spu_info.print_address_func = spu_dis_asm_print_address;
1724 return default_print_insn (memaddr, &spu_info);
1728 /* Target overlays for the SPU overlay manager.
1730 See the documentation of simple_overlay_update for how the
1731 interface is supposed to work.
1733 Data structures used by the overlay manager:
1741 } _ovly_table[]; -- one entry per overlay section
1743 struct ovly_buf_table
1746 } _ovly_buf_table[]; -- one entry per overlay buffer
1748 _ovly_table should never change.
1750 Both tables are aligned to a 16-byte boundary, the symbols
1751 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1752 size set to the size of the respective array. buf in _ovly_table is
1753 an index into _ovly_buf_table.
1755 mapped is an index into _ovly_table. Both the mapped and buf indices start
1756 from one to reference the first entry in their respective tables. */
1758 /* Using the per-objfile private data mechanism, we store for each
1759 objfile an array of "struct spu_overlay_table" structures, one
1760 for each obj_section of the objfile. This structure holds two
1761 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1762 is *not* an overlay section. If it is non-zero, it represents
1763 a target address. The overlay section is mapped iff the target
1764 integer at this location equals MAPPED_VAL. */
1766 static const struct objfile_data *spu_overlay_data;
1768 struct spu_overlay_table
1770 CORE_ADDR mapped_ptr;
1771 CORE_ADDR mapped_val;
1774 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1775 the _ovly_table data structure from the target and initialize the
1776 spu_overlay_table data structure from it. */
1777 static struct spu_overlay_table *
1778 spu_get_overlay_table (struct objfile *objfile)
1780 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1781 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
1782 struct bound_minimal_symbol ovly_table_msym, ovly_buf_table_msym;
1783 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1784 unsigned ovly_table_size, ovly_buf_table_size;
1785 struct spu_overlay_table *tbl;
1786 struct obj_section *osect;
1787 gdb_byte *ovly_table;
1790 tbl = (struct spu_overlay_table *) objfile_data (objfile, spu_overlay_data);
1794 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1795 if (!ovly_table_msym.minsym)
1798 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1800 if (!ovly_buf_table_msym.minsym)
1803 ovly_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_table_msym);
1804 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym.minsym);
1806 ovly_buf_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1807 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym.minsym);
1809 ovly_table = (gdb_byte *) xmalloc (ovly_table_size);
1810 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1812 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1813 objfile->sections_end - objfile->sections,
1814 struct spu_overlay_table);
1816 for (i = 0; i < ovly_table_size / 16; i++)
1818 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1820 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1822 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1824 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1827 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1830 ALL_OBJFILE_OSECTIONS (objfile, osect)
1831 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1832 && pos == osect->the_bfd_section->filepos)
1834 int ndx = osect - objfile->sections;
1835 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1836 tbl[ndx].mapped_val = i + 1;
1842 set_objfile_data (objfile, spu_overlay_data, tbl);
1846 /* Read _ovly_buf_table entry from the target to dermine whether
1847 OSECT is currently mapped, and update the mapped state. */
1849 spu_overlay_update_osect (struct obj_section *osect)
1851 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1852 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
1853 struct spu_overlay_table *ovly_table;
1856 ovly_table = spu_get_overlay_table (osect->objfile);
1860 ovly_table += osect - osect->objfile->sections;
1861 if (ovly_table->mapped_ptr == 0)
1864 id = SPUADDR_SPU (obj_section_addr (osect));
1865 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1867 osect->ovly_mapped = (val == ovly_table->mapped_val);
1870 /* If OSECT is NULL, then update all sections' mapped state.
1871 If OSECT is non-NULL, then update only OSECT's mapped state. */
1873 spu_overlay_update (struct obj_section *osect)
1875 /* Just one section. */
1877 spu_overlay_update_osect (osect);
1882 struct objfile *objfile;
1884 ALL_OBJSECTIONS (objfile, osect)
1885 if (section_is_overlay (osect))
1886 spu_overlay_update_osect (osect);
1890 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1891 If there is one, go through all sections and make sure for non-
1892 overlay sections LMA equals VMA, while for overlay sections LMA
1893 is larger than SPU_OVERLAY_LMA. */
1895 spu_overlay_new_objfile (struct objfile *objfile)
1897 struct spu_overlay_table *ovly_table;
1898 struct obj_section *osect;
1900 /* If we've already touched this file, do nothing. */
1901 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1904 /* Consider only SPU objfiles. */
1905 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1908 /* Check if this objfile has overlays. */
1909 ovly_table = spu_get_overlay_table (objfile);
1913 /* Now go and fiddle with all the LMAs. */
1914 ALL_OBJFILE_OSECTIONS (objfile, osect)
1916 bfd *obfd = objfile->obfd;
1917 asection *bsect = osect->the_bfd_section;
1918 int ndx = osect - objfile->sections;
1920 if (ovly_table[ndx].mapped_ptr == 0)
1921 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1923 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
1928 /* Insert temporary breakpoint on "main" function of newly loaded
1929 SPE context OBJFILE. */
1931 spu_catch_start (struct objfile *objfile)
1933 struct bound_minimal_symbol minsym;
1934 struct compunit_symtab *cust;
1937 /* Do this only if requested by "set spu stop-on-load on". */
1938 if (!spu_stop_on_load_p)
1941 /* Consider only SPU objfiles. */
1942 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1945 /* The main objfile is handled differently. */
1946 if (objfile == symfile_objfile)
1949 /* There can be multiple symbols named "main". Search for the
1950 "main" in *this* objfile. */
1951 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1955 /* If we have debugging information, try to use it -- this
1956 will allow us to properly skip the prologue. */
1957 pc = BMSYMBOL_VALUE_ADDRESS (minsym);
1959 = find_pc_sect_compunit_symtab (pc, MSYMBOL_OBJ_SECTION (minsym.objfile,
1963 const struct blockvector *bv = COMPUNIT_BLOCKVECTOR (cust);
1964 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1966 struct symtab_and_line sal;
1968 sym = block_lookup_symbol (block, "main", VAR_DOMAIN);
1971 fixup_symbol_section (sym, objfile);
1972 sal = find_function_start_sal (sym, 1);
1977 /* Use a numerical address for the set_breakpoint command to avoid having
1978 the breakpoint re-set incorrectly. */
1979 event_location_up location = new_address_location (pc, NULL, 0);
1980 create_breakpoint (get_objfile_arch (objfile), location.get (),
1981 NULL /* cond_string */, -1 /* thread */,
1982 NULL /* extra_string */,
1983 0 /* parse_condition_and_thread */, 1 /* tempflag */,
1984 bp_breakpoint /* type_wanted */,
1985 0 /* ignore_count */,
1986 AUTO_BOOLEAN_FALSE /* pending_break_support */,
1987 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
1988 1 /* enabled */, 0 /* internal */, 0);
1992 /* Look up OBJFILE loaded into FRAME's SPU context. */
1993 static struct objfile *
1994 spu_objfile_from_frame (struct frame_info *frame)
1996 struct gdbarch *gdbarch = get_frame_arch (frame);
1997 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1998 struct objfile *obj;
2000 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2005 if (obj->sections != obj->sections_end
2006 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
2013 /* Flush cache for ea pointer access if available. */
2015 flush_ea_cache (void)
2017 struct bound_minimal_symbol msymbol;
2018 struct objfile *obj;
2020 if (!has_stack_frames ())
2023 obj = spu_objfile_from_frame (get_current_frame ());
2027 /* Lookup inferior function __cache_flush. */
2028 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
2029 if (msymbol.minsym != NULL)
2034 type = objfile_type (obj)->builtin_void;
2035 type = lookup_function_type (type);
2036 type = lookup_pointer_type (type);
2037 addr = BMSYMBOL_VALUE_ADDRESS (msymbol);
2039 call_function_by_hand (value_from_pointer (type, addr), NULL, 0, NULL);
2043 /* This handler is called when the inferior has stopped. If it is stopped in
2044 SPU architecture then flush the ea cache if used. */
2046 spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2048 if (!spu_auto_flush_cache_p)
2051 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2052 re-entering this function when __cache_flush stops. */
2053 spu_auto_flush_cache_p = 0;
2055 spu_auto_flush_cache_p = 1;
2059 /* "info spu" commands. */
2062 info_spu_event_command (char *args, int from_tty)
2064 struct frame_info *frame = get_selected_frame (NULL);
2065 ULONGEST event_status = 0;
2066 ULONGEST event_mask = 0;
2072 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2073 error (_("\"info spu\" is only supported on the SPU architecture."));
2075 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2077 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2078 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2079 buf, 0, (sizeof (buf) - 1));
2081 error (_("Could not read event_status."));
2083 event_status = strtoulst ((char *) buf, NULL, 16);
2085 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2086 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2087 buf, 0, (sizeof (buf) - 1));
2089 error (_("Could not read event_mask."));
2091 event_mask = strtoulst ((char *) buf, NULL, 16);
2093 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoEvent");
2095 if (current_uiout->is_mi_like_p ())
2097 current_uiout->field_fmt ("event_status",
2098 "0x%s", phex_nz (event_status, 4));
2099 current_uiout->field_fmt ("event_mask",
2100 "0x%s", phex_nz (event_mask, 4));
2104 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2105 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2110 info_spu_signal_command (char *args, int from_tty)
2112 struct frame_info *frame = get_selected_frame (NULL);
2113 struct gdbarch *gdbarch = get_frame_arch (frame);
2114 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2115 ULONGEST signal1 = 0;
2116 ULONGEST signal1_type = 0;
2117 int signal1_pending = 0;
2118 ULONGEST signal2 = 0;
2119 ULONGEST signal2_type = 0;
2120 int signal2_pending = 0;
2126 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2127 error (_("\"info spu\" is only supported on the SPU architecture."));
2129 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2131 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2132 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2134 error (_("Could not read signal1."));
2137 signal1 = extract_unsigned_integer (buf, 4, byte_order);
2138 signal1_pending = 1;
2141 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2142 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2143 buf, 0, (sizeof (buf) - 1));
2145 error (_("Could not read signal1_type."));
2147 signal1_type = strtoulst ((char *) buf, NULL, 16);
2149 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2150 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2152 error (_("Could not read signal2."));
2155 signal2 = extract_unsigned_integer (buf, 4, byte_order);
2156 signal2_pending = 1;
2159 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2160 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2161 buf, 0, (sizeof (buf) - 1));
2163 error (_("Could not read signal2_type."));
2165 signal2_type = strtoulst ((char *) buf, NULL, 16);
2167 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoSignal");
2169 if (current_uiout->is_mi_like_p ())
2171 current_uiout->field_int ("signal1_pending", signal1_pending);
2172 current_uiout->field_fmt ("signal1", "0x%s", phex_nz (signal1, 4));
2173 current_uiout->field_int ("signal1_type", signal1_type);
2174 current_uiout->field_int ("signal2_pending", signal2_pending);
2175 current_uiout->field_fmt ("signal2", "0x%s", phex_nz (signal2, 4));
2176 current_uiout->field_int ("signal2_type", signal2_type);
2180 if (signal1_pending)
2181 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2183 printf_filtered (_("Signal 1 not pending "));
2186 printf_filtered (_("(Type Or)\n"));
2188 printf_filtered (_("(Type Overwrite)\n"));
2190 if (signal2_pending)
2191 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2193 printf_filtered (_("Signal 2 not pending "));
2196 printf_filtered (_("(Type Or)\n"));
2198 printf_filtered (_("(Type Overwrite)\n"));
2203 info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
2204 const char *field, const char *msg)
2211 ui_out_emit_table table_emitter (current_uiout, 1, nr, "mbox");
2213 current_uiout->table_header (32, ui_left, field, msg);
2214 current_uiout->table_body ();
2216 for (i = 0; i < nr; i++)
2220 ui_out_emit_tuple tuple_emitter (current_uiout, "mbox");
2221 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
2222 current_uiout->field_fmt (field, "0x%s", phex (val, 4));
2225 if (!current_uiout->is_mi_like_p ())
2226 printf_filtered ("\n");
2231 info_spu_mailbox_command (char *args, int from_tty)
2233 struct frame_info *frame = get_selected_frame (NULL);
2234 struct gdbarch *gdbarch = get_frame_arch (frame);
2235 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2241 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2242 error (_("\"info spu\" is only supported on the SPU architecture."));
2244 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2246 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoMailbox");
2248 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2249 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2250 buf, 0, sizeof buf);
2252 error (_("Could not read mbox_info."));
2254 info_spu_mailbox_list (buf, len / 4, byte_order,
2255 "mbox", "SPU Outbound Mailbox");
2257 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2258 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2259 buf, 0, sizeof buf);
2261 error (_("Could not read ibox_info."));
2263 info_spu_mailbox_list (buf, len / 4, byte_order,
2264 "ibox", "SPU Outbound Interrupt Mailbox");
2266 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2267 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2268 buf, 0, sizeof buf);
2270 error (_("Could not read wbox_info."));
2272 info_spu_mailbox_list (buf, len / 4, byte_order,
2273 "wbox", "SPU Inbound Mailbox");
2277 spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2279 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2280 return (word >> (63 - last)) & mask;
2284 info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
2286 static const char *spu_mfc_opcode[256] =
2288 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2289 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2290 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2291 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2292 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2293 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2294 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2295 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2296 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2297 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2298 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2299 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2300 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2301 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2302 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2303 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2304 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2305 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2306 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2307 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2308 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2309 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2310 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2311 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2312 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2313 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2314 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2315 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2316 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2317 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2318 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2319 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2322 int *seq = XALLOCAVEC (int, nr);
2327 /* Determine sequence in which to display (valid) entries. */
2328 for (i = 0; i < nr; i++)
2330 /* Search for the first valid entry all of whose
2331 dependencies are met. */
2332 for (j = 0; j < nr; j++)
2334 ULONGEST mfc_cq_dw3;
2335 ULONGEST dependencies;
2337 if (done & (1 << (nr - 1 - j)))
2341 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
2342 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2345 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2346 if ((dependencies & done) != dependencies)
2350 done |= 1 << (nr - 1 - j);
2361 ui_out_emit_table table_emitter (current_uiout, 10, nr, "dma_cmd");
2363 current_uiout->table_header (7, ui_left, "opcode", "Opcode");
2364 current_uiout->table_header (3, ui_left, "tag", "Tag");
2365 current_uiout->table_header (3, ui_left, "tid", "TId");
2366 current_uiout->table_header (3, ui_left, "rid", "RId");
2367 current_uiout->table_header (18, ui_left, "ea", "EA");
2368 current_uiout->table_header (7, ui_left, "lsa", "LSA");
2369 current_uiout->table_header (7, ui_left, "size", "Size");
2370 current_uiout->table_header (7, ui_left, "lstaddr", "LstAddr");
2371 current_uiout->table_header (7, ui_left, "lstsize", "LstSize");
2372 current_uiout->table_header (1, ui_left, "error_p", "E");
2374 current_uiout->table_body ();
2376 for (i = 0; i < nr; i++)
2378 ULONGEST mfc_cq_dw0;
2379 ULONGEST mfc_cq_dw1;
2380 ULONGEST mfc_cq_dw2;
2381 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2382 int list_lsa, list_size, mfc_lsa, mfc_size;
2384 int list_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2386 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2387 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2390 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2392 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2394 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
2396 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2397 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2398 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2399 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2400 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2401 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2402 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2404 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2405 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2407 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2408 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2409 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2410 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2411 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2414 ui_out_emit_tuple tuple_emitter (current_uiout, "cmd");
2416 if (spu_mfc_opcode[mfc_cmd_opcode])
2417 current_uiout->field_string ("opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2419 current_uiout->field_int ("opcode", mfc_cmd_opcode);
2421 current_uiout->field_int ("tag", mfc_cmd_tag);
2422 current_uiout->field_int ("tid", tclass_id);
2423 current_uiout->field_int ("rid", rclass_id);
2426 current_uiout->field_fmt ("ea", "0x%s", phex (mfc_ea, 8));
2428 current_uiout->field_skip ("ea");
2430 current_uiout->field_fmt ("lsa", "0x%05x", mfc_lsa << 4);
2432 current_uiout->field_fmt ("size", "0x%05x", mfc_size << 4);
2434 current_uiout->field_fmt ("size", "0x%05x", mfc_size);
2438 current_uiout->field_fmt ("lstaddr", "0x%05x", list_lsa << 3);
2439 current_uiout->field_fmt ("lstsize", "0x%05x", list_size << 3);
2443 current_uiout->field_skip ("lstaddr");
2444 current_uiout->field_skip ("lstsize");
2448 current_uiout->field_string ("error_p", "*");
2450 current_uiout->field_skip ("error_p");
2453 if (!current_uiout->is_mi_like_p ())
2454 printf_filtered ("\n");
2459 info_spu_dma_command (char *args, int from_tty)
2461 struct frame_info *frame = get_selected_frame (NULL);
2462 struct gdbarch *gdbarch = get_frame_arch (frame);
2463 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2464 ULONGEST dma_info_type;
2465 ULONGEST dma_info_mask;
2466 ULONGEST dma_info_status;
2467 ULONGEST dma_info_stall_and_notify;
2468 ULONGEST dma_info_atomic_command_status;
2474 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2475 error (_("\"info spu\" is only supported on the SPU architecture."));
2477 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2479 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2480 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2481 buf, 0, 40 + 16 * 32);
2483 error (_("Could not read dma_info."));
2486 = extract_unsigned_integer (buf, 8, byte_order);
2488 = extract_unsigned_integer (buf + 8, 8, byte_order);
2490 = extract_unsigned_integer (buf + 16, 8, byte_order);
2491 dma_info_stall_and_notify
2492 = extract_unsigned_integer (buf + 24, 8, byte_order);
2493 dma_info_atomic_command_status
2494 = extract_unsigned_integer (buf + 32, 8, byte_order);
2496 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoDMA");
2498 if (current_uiout->is_mi_like_p ())
2500 current_uiout->field_fmt ("dma_info_type", "0x%s",
2501 phex_nz (dma_info_type, 4));
2502 current_uiout->field_fmt ("dma_info_mask", "0x%s",
2503 phex_nz (dma_info_mask, 4));
2504 current_uiout->field_fmt ("dma_info_status", "0x%s",
2505 phex_nz (dma_info_status, 4));
2506 current_uiout->field_fmt ("dma_info_stall_and_notify", "0x%s",
2507 phex_nz (dma_info_stall_and_notify, 4));
2508 current_uiout->field_fmt ("dma_info_atomic_command_status", "0x%s",
2509 phex_nz (dma_info_atomic_command_status, 4));
2513 const char *query_msg = _("no query pending");
2515 if (dma_info_type & 4)
2516 switch (dma_info_type & 3)
2518 case 1: query_msg = _("'any' query pending"); break;
2519 case 2: query_msg = _("'all' query pending"); break;
2520 default: query_msg = _("undefined query type"); break;
2523 printf_filtered (_("Tag-Group Status 0x%s\n"),
2524 phex (dma_info_status, 4));
2525 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2526 phex (dma_info_mask, 4), query_msg);
2527 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2528 phex (dma_info_stall_and_notify, 4));
2529 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2530 phex (dma_info_atomic_command_status, 4));
2531 printf_filtered ("\n");
2534 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
2538 info_spu_proxydma_command (char *args, int from_tty)
2540 struct frame_info *frame = get_selected_frame (NULL);
2541 struct gdbarch *gdbarch = get_frame_arch (frame);
2542 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2543 ULONGEST dma_info_type;
2544 ULONGEST dma_info_mask;
2545 ULONGEST dma_info_status;
2551 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2552 error (_("\"info spu\" is only supported on the SPU architecture."));
2554 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2556 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2557 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2558 buf, 0, 24 + 8 * 32);
2560 error (_("Could not read proxydma_info."));
2562 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2563 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2564 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
2566 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoProxyDMA");
2568 if (current_uiout->is_mi_like_p ())
2570 current_uiout->field_fmt ("proxydma_info_type", "0x%s",
2571 phex_nz (dma_info_type, 4));
2572 current_uiout->field_fmt ("proxydma_info_mask", "0x%s",
2573 phex_nz (dma_info_mask, 4));
2574 current_uiout->field_fmt ("proxydma_info_status", "0x%s",
2575 phex_nz (dma_info_status, 4));
2579 const char *query_msg;
2581 switch (dma_info_type & 3)
2583 case 0: query_msg = _("no query pending"); break;
2584 case 1: query_msg = _("'any' query pending"); break;
2585 case 2: query_msg = _("'all' query pending"); break;
2586 default: query_msg = _("undefined query type"); break;
2589 printf_filtered (_("Tag-Group Status 0x%s\n"),
2590 phex (dma_info_status, 4));
2591 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2592 phex (dma_info_mask, 4), query_msg);
2593 printf_filtered ("\n");
2596 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
2600 info_spu_command (char *args, int from_tty)
2602 printf_unfiltered (_("\"info spu\" must be followed by "
2603 "the name of an SPU facility.\n"));
2604 help_list (infospucmdlist, "info spu ", all_commands, gdb_stdout);
2608 /* Root of all "set spu "/"show spu " commands. */
2611 show_spu_command (char *args, int from_tty)
2613 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2617 set_spu_command (char *args, int from_tty)
2619 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2623 show_spu_stop_on_load (struct ui_file *file, int from_tty,
2624 struct cmd_list_element *c, const char *value)
2626 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2631 show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2632 struct cmd_list_element *c, const char *value)
2634 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2639 /* Set up gdbarch struct. */
2641 static struct gdbarch *
2642 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2644 struct gdbarch *gdbarch;
2645 struct gdbarch_tdep *tdep;
2648 /* Which spufs ID was requested as address space? */
2651 /* For objfile architectures of SPU solibs, decode the ID from the name.
2652 This assumes the filename convention employed by solib-spu.c. */
2655 const char *name = strrchr (info.abfd->filename, '@');
2657 sscanf (name, "@0x%*x <%d>", &id);
2660 /* Find a candidate among extant architectures. */
2661 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2663 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2665 tdep = gdbarch_tdep (arches->gdbarch);
2666 if (tdep && tdep->id == id)
2667 return arches->gdbarch;
2670 /* None found, so create a new architecture. */
2671 tdep = XCNEW (struct gdbarch_tdep);
2673 gdbarch = gdbarch_alloc (&info, tdep);
2676 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
2679 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2680 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2681 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2682 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
2683 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2684 set_gdbarch_write_pc (gdbarch, spu_write_pc);
2685 set_gdbarch_register_name (gdbarch, spu_register_name);
2686 set_gdbarch_register_type (gdbarch, spu_register_type);
2687 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2688 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
2689 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
2690 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2691 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, spu_dwarf_reg_to_regnum);
2692 set_gdbarch_ax_pseudo_register_collect
2693 (gdbarch, spu_ax_pseudo_register_collect);
2694 set_gdbarch_ax_pseudo_register_push_stack
2695 (gdbarch, spu_ax_pseudo_register_push_stack);
2698 set_gdbarch_char_signed (gdbarch, 0);
2699 set_gdbarch_ptr_bit (gdbarch, 32);
2700 set_gdbarch_addr_bit (gdbarch, 32);
2701 set_gdbarch_short_bit (gdbarch, 16);
2702 set_gdbarch_int_bit (gdbarch, 32);
2703 set_gdbarch_long_bit (gdbarch, 32);
2704 set_gdbarch_long_long_bit (gdbarch, 64);
2705 set_gdbarch_float_bit (gdbarch, 32);
2706 set_gdbarch_double_bit (gdbarch, 64);
2707 set_gdbarch_long_double_bit (gdbarch, 64);
2708 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2709 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2710 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2712 /* Address handling. */
2713 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
2714 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2715 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2716 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2717 set_gdbarch_address_class_type_flags_to_name
2718 (gdbarch, spu_address_class_type_flags_to_name);
2719 set_gdbarch_address_class_name_to_type_flags
2720 (gdbarch, spu_address_class_name_to_type_flags);
2723 /* Inferior function calls. */
2724 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2725 set_gdbarch_frame_align (gdbarch, spu_frame_align);
2726 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
2727 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
2728 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
2729 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
2730 set_gdbarch_return_value (gdbarch, spu_return_value);
2732 /* Frame handling. */
2733 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2734 dwarf2_append_unwinders (gdbarch);
2735 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
2736 frame_base_set_default (gdbarch, &spu_frame_base);
2737 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2738 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2739 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2740 set_gdbarch_frame_args_skip (gdbarch, 0);
2741 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
2742 set_gdbarch_stack_frame_destroyed_p (gdbarch, spu_stack_frame_destroyed_p);
2744 /* Cell/B.E. cross-architecture unwinder support. */
2745 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2748 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2749 set_gdbarch_breakpoint_kind_from_pc (gdbarch, spu_breakpoint::kind_from_pc);
2750 set_gdbarch_sw_breakpoint_from_kind (gdbarch, spu_breakpoint::bp_from_kind);
2751 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
2752 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2753 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
2756 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2762 _initialize_spu_tdep (void)
2764 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
2766 /* Add ourselves to objfile event chain. */
2767 observer_attach_new_objfile (spu_overlay_new_objfile);
2768 spu_overlay_data = register_objfile_data ();
2770 /* Install spu stop-on-load handler. */
2771 observer_attach_new_objfile (spu_catch_start);
2773 /* Add ourselves to normal_stop event chain. */
2774 observer_attach_normal_stop (spu_attach_normal_stop);
2776 /* Add root prefix command for all "set spu"/"show spu" commands. */
2777 add_prefix_cmd ("spu", no_class, set_spu_command,
2778 _("Various SPU specific commands."),
2779 &setspucmdlist, "set spu ", 0, &setlist);
2780 add_prefix_cmd ("spu", no_class, show_spu_command,
2781 _("Various SPU specific commands."),
2782 &showspucmdlist, "show spu ", 0, &showlist);
2784 /* Toggle whether or not to add a temporary breakpoint at the "main"
2785 function of new SPE contexts. */
2786 add_setshow_boolean_cmd ("stop-on-load", class_support,
2787 &spu_stop_on_load_p, _("\
2788 Set whether to stop for new SPE threads."),
2790 Show whether to stop for new SPE threads."),
2792 Use \"on\" to give control to the user when a new SPE thread\n\
2793 enters its \"main\" function.\n\
2794 Use \"off\" to disable stopping for new SPE threads."),
2796 show_spu_stop_on_load,
2797 &setspucmdlist, &showspucmdlist);
2799 /* Toggle whether or not to automatically flush the software-managed
2800 cache whenever SPE execution stops. */
2801 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2802 &spu_auto_flush_cache_p, _("\
2803 Set whether to automatically flush the software-managed cache."),
2805 Show whether to automatically flush the software-managed cache."),
2807 Use \"on\" to automatically flush the software-managed cache\n\
2808 whenever SPE execution stops.\n\
2809 Use \"off\" to never automatically flush the software-managed cache."),
2811 show_spu_auto_flush_cache,
2812 &setspucmdlist, &showspucmdlist);
2814 /* Add root prefix command for all "info spu" commands. */
2815 add_prefix_cmd ("spu", class_info, info_spu_command,
2816 _("Various SPU specific commands."),
2817 &infospucmdlist, "info spu ", 0, &infolist);
2819 /* Add various "info spu" commands. */
2820 add_cmd ("event", class_info, info_spu_event_command,
2821 _("Display SPU event facility status.\n"),
2823 add_cmd ("signal", class_info, info_spu_signal_command,
2824 _("Display SPU signal notification facility status.\n"),
2826 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2827 _("Display SPU mailbox facility status.\n"),
2829 add_cmd ("dma", class_info, info_spu_dma_command,
2830 _("Display MFC DMA status.\n"),
2832 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2833 _("Display MFC Proxy-DMA status.\n"),