1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
25 #include "arch-utils.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
43 #include "reggroups.h"
44 #include "floatformat.h"
52 spu_register_name (int reg_nr)
54 static char *register_names[] =
56 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
57 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
58 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
59 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
60 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
61 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
62 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
63 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
64 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
65 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
66 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
67 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
68 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
69 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
70 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
71 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
77 if (reg_nr >= sizeof register_names / sizeof *register_names)
80 return register_names[reg_nr];
84 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
86 if (reg_nr < SPU_NUM_GPRS)
87 return builtin_type_vec128;
92 return builtin_type_uint32;
95 return builtin_type_void_func_ptr;
98 return builtin_type_void_data_ptr;
101 internal_error (__FILE__, __LINE__, "invalid regnum");
105 /* Pseudo registers for preferred slots - stack pointer. */
108 spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
109 int regnum, gdb_byte *buf)
116 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
117 memcpy (buf, reg, 4);
121 internal_error (__FILE__, __LINE__, _("invalid regnum"));
126 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
127 int regnum, const gdb_byte *buf)
134 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
135 memcpy (reg, buf, 4);
136 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
140 internal_error (__FILE__, __LINE__, _("invalid regnum"));
144 /* Value conversion -- access scalar values at the preferred slot. */
147 spu_convert_register_p (int regno, struct type *type)
149 return regno < SPU_NUM_GPRS && TYPE_LENGTH (type) < 16;
153 spu_register_to_value (struct frame_info *frame, int regnum,
154 struct type *valtype, gdb_byte *out)
157 int len = TYPE_LENGTH (valtype);
158 int preferred_slot = len < 4 ? 4 - len : 0;
159 gdb_assert (len < 16);
161 get_frame_register (frame, regnum, in);
162 memcpy (out, in + preferred_slot, len);
166 spu_value_to_register (struct frame_info *frame, int regnum,
167 struct type *valtype, const gdb_byte *in)
170 int len = TYPE_LENGTH (valtype);
171 int preferred_slot = len < 4 ? 4 - len : 0;
172 gdb_assert (len < 16);
175 memcpy (out + preferred_slot, in, len);
176 put_frame_register (frame, regnum, out);
179 /* Register groups. */
182 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
183 struct reggroup *group)
185 /* Registers displayed via 'info regs'. */
186 if (group == general_reggroup)
189 /* Registers displayed via 'info float'. */
190 if (group == float_reggroup)
193 /* Registers that need to be saved/restored in order to
194 push or pop frames. */
195 if (group == save_reggroup || group == restore_reggroup)
198 return default_register_reggroup_p (gdbarch, regnum, group);
202 /* Decoding SPU instructions. */
239 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
241 if ((insn >> 21) == op)
244 *ra = (insn >> 7) & 127;
245 *rb = (insn >> 14) & 127;
253 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
255 if ((insn >> 28) == op)
257 *rt = (insn >> 21) & 127;
258 *ra = (insn >> 7) & 127;
259 *rb = (insn >> 14) & 127;
268 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
270 if ((insn >> 21) == op)
273 *ra = (insn >> 7) & 127;
274 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
282 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
284 if ((insn >> 24) == op)
287 *ra = (insn >> 7) & 127;
288 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
296 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
298 if ((insn >> 23) == op)
301 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
309 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
311 if ((insn >> 25) == op)
314 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
322 is_branch (unsigned int insn, int *offset, int *reg)
326 if (is_ri16 (insn, op_br, &rt, &i16)
327 || is_ri16 (insn, op_brsl, &rt, &i16)
328 || is_ri16 (insn, op_brnz, &rt, &i16)
329 || is_ri16 (insn, op_brz, &rt, &i16)
330 || is_ri16 (insn, op_brhnz, &rt, &i16)
331 || is_ri16 (insn, op_brhz, &rt, &i16))
333 *reg = SPU_PC_REGNUM;
338 if (is_ri16 (insn, op_bra, &rt, &i16)
339 || is_ri16 (insn, op_brasl, &rt, &i16))
346 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
347 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
348 || is_ri7 (insn, op_biz, &rt, reg, &i7)
349 || is_ri7 (insn, op_binz, &rt, reg, &i7)
350 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
351 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
361 /* Prolog parsing. */
363 struct spu_prologue_data
365 /* Stack frame size. -1 if analysis was unsuccessful. */
368 /* How to find the CFA. The CFA is equal to SP at function entry. */
372 /* Offset relative to CFA where a register is saved. -1 if invalid. */
373 int reg_offset[SPU_NUM_GPRS];
377 spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
378 struct spu_prologue_data *data)
383 int reg_immed[SPU_NUM_GPRS];
385 CORE_ADDR prolog_pc = start_pc;
390 /* Initialize DATA to default values. */
393 data->cfa_reg = SPU_RAW_SP_REGNUM;
394 data->cfa_offset = 0;
396 for (i = 0; i < SPU_NUM_GPRS; i++)
397 data->reg_offset[i] = -1;
399 /* Set up REG_IMMED array. This is non-zero for a register if we know its
400 preferred slot currently holds this immediate value. */
401 for (i = 0; i < SPU_NUM_GPRS; i++)
404 /* Scan instructions until the first branch.
406 The following instructions are important prolog components:
408 - The first instruction to set up the stack pointer.
409 - The first instruction to set up the frame pointer.
410 - The first instruction to save the link register.
412 We return the instruction after the latest of these three,
413 or the incoming PC if none is found. The first instruction
414 to set up the stack pointer also defines the frame size.
416 Note that instructions saving incoming arguments to their stack
417 slots are not counted as important, because they are hard to
418 identify with certainty. This should not matter much, because
419 arguments are relevant only in code compiled with debug data,
420 and in such code the GDB core will advance until the first source
421 line anyway, using SAL data.
423 For purposes of stack unwinding, we analyze the following types
424 of instructions in addition:
426 - Any instruction adding to the current frame pointer.
427 - Any instruction loading an immediate constant into a register.
428 - Any instruction storing a register onto the stack.
430 These are used to compute the CFA and REG_OFFSET output. */
432 for (pc = start_pc; pc < end_pc; pc += 4)
435 int rt, ra, rb, rc, immed;
437 if (target_read_memory (pc, buf, 4))
439 insn = extract_unsigned_integer (buf, 4);
441 /* AI is the typical instruction to set up a stack frame.
442 It is also used to initialize the frame pointer. */
443 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
445 if (rt == data->cfa_reg && ra == data->cfa_reg)
446 data->cfa_offset -= immed;
448 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
456 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
462 data->cfa_reg = SPU_FP_REGNUM;
463 data->cfa_offset -= immed;
467 /* A is used to set up stack frames of size >= 512 bytes.
468 If we have tracked the contents of the addend register,
469 we can handle this as well. */
470 else if (is_rr (insn, op_a, &rt, &ra, &rb))
472 if (rt == data->cfa_reg && ra == data->cfa_reg)
474 if (reg_immed[rb] != 0)
475 data->cfa_offset -= reg_immed[rb];
477 data->cfa_reg = -1; /* We don't know the CFA any more. */
480 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
486 if (reg_immed[rb] != 0)
487 data->size = -reg_immed[rb];
491 /* We need to track IL and ILA used to load immediate constants
492 in case they are later used as input to an A instruction. */
493 else if (is_ri16 (insn, op_il, &rt, &immed))
495 reg_immed[rt] = immed;
498 else if (is_ri18 (insn, op_ila, &rt, &immed))
500 reg_immed[rt] = immed & 0x3ffff;
503 /* STQD is used to save registers to the stack. */
504 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
506 if (ra == data->cfa_reg)
507 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
509 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
517 /* _start uses SELB to set up the stack pointer. */
518 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
520 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
524 /* We terminate if we find a branch. */
525 else if (is_branch (insn, &immed, &ra))
530 /* If we successfully parsed until here, and didn't find any instruction
531 modifying SP, we assume we have a frameless function. */
535 /* Return cooked instead of raw SP. */
536 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
537 data->cfa_reg = SPU_SP_REGNUM;
542 /* Return the first instruction after the prologue starting at PC. */
544 spu_skip_prologue (CORE_ADDR pc)
546 struct spu_prologue_data data;
547 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
550 /* Return the frame pointer in use at address PC. */
552 spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset)
554 struct spu_prologue_data data;
555 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
557 if (data.size != -1 && data.cfa_reg != -1)
559 /* The 'frame pointer' address is CFA minus frame size. */
561 *offset = data.cfa_offset - data.size;
565 /* ??? We don't really know ... */
566 *reg = SPU_SP_REGNUM;
571 /* Normal stack frames. */
573 struct spu_unwind_cache
576 CORE_ADDR frame_base;
577 CORE_ADDR local_base;
579 struct trad_frame_saved_reg *saved_regs;
582 static struct spu_unwind_cache *
583 spu_frame_unwind_cache (struct frame_info *next_frame,
584 void **this_prologue_cache)
586 struct spu_unwind_cache *info;
587 struct spu_prologue_data data;
589 if (*this_prologue_cache)
590 return *this_prologue_cache;
592 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
593 *this_prologue_cache = info;
594 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
595 info->frame_base = 0;
596 info->local_base = 0;
598 /* Find the start of the current function, and analyze its prologue. */
599 info->func = frame_func_unwind (next_frame);
602 /* Fall back to using the current PC as frame ID. */
603 info->func = frame_pc_unwind (next_frame);
607 spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data);
610 /* If successful, use prologue analysis data. */
611 if (data.size != -1 && data.cfa_reg != -1)
617 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
618 frame_unwind_register (next_frame, data.cfa_reg, buf);
619 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
621 /* Call-saved register slots. */
622 for (i = 0; i < SPU_NUM_GPRS; i++)
623 if (i == SPU_LR_REGNUM
624 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
625 if (data.reg_offset[i] != -1)
626 info->saved_regs[i].addr = cfa - data.reg_offset[i];
628 /* The previous PC comes from the link register. */
629 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
630 info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM];
632 info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM;
634 /* The previous SP is equal to the CFA. */
635 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, cfa);
638 info->frame_base = cfa;
639 info->local_base = cfa - data.size;
642 /* Otherwise, fall back to reading the backchain link. */
645 CORE_ADDR reg, backchain;
647 /* Get the backchain. */
648 reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
649 backchain = read_memory_unsigned_integer (reg, 4);
651 /* A zero backchain terminates the frame chain. Also, sanity
652 check against the local store size limit. */
653 if (backchain != 0 && backchain < SPU_LS_SIZE)
655 /* Assume the link register is saved into its slot. */
656 if (backchain + 16 < SPU_LS_SIZE)
657 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
659 /* This will also be the previous PC. */
660 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
661 info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM];
663 info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM;
665 /* The previous SP will equal the backchain value. */
666 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, backchain);
669 info->frame_base = backchain;
670 info->local_base = reg;
678 spu_frame_this_id (struct frame_info *next_frame,
679 void **this_prologue_cache, struct frame_id *this_id)
681 struct spu_unwind_cache *info =
682 spu_frame_unwind_cache (next_frame, this_prologue_cache);
684 if (info->frame_base == 0)
687 *this_id = frame_id_build (info->frame_base, info->func);
691 spu_frame_prev_register (struct frame_info *next_frame,
692 void **this_prologue_cache,
693 int regnum, int *optimizedp,
694 enum lval_type *lvalp, CORE_ADDR * addrp,
695 int *realnump, gdb_byte *bufferp)
697 struct spu_unwind_cache *info
698 = spu_frame_unwind_cache (next_frame, this_prologue_cache);
700 /* Special-case the stack pointer. */
701 if (regnum == SPU_RAW_SP_REGNUM)
702 regnum = SPU_SP_REGNUM;
704 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
705 optimizedp, lvalp, addrp, realnump, bufferp);
708 static const struct frame_unwind spu_frame_unwind = {
711 spu_frame_prev_register
714 const struct frame_unwind *
715 spu_frame_sniffer (struct frame_info *next_frame)
717 return &spu_frame_unwind;
721 spu_frame_base_address (struct frame_info *next_frame, void **this_cache)
723 struct spu_unwind_cache *info
724 = spu_frame_unwind_cache (next_frame, this_cache);
725 return info->local_base;
728 static const struct frame_base spu_frame_base = {
730 spu_frame_base_address,
731 spu_frame_base_address,
732 spu_frame_base_address
736 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
738 return frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
742 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
744 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
748 /* Function calling convention. */
751 spu_scalar_value_p (struct type *type)
753 switch (TYPE_CODE (type))
757 case TYPE_CODE_RANGE:
762 return TYPE_LENGTH (type) <= 16;
770 spu_value_to_regcache (struct regcache *regcache, int regnum,
771 struct type *type, const gdb_byte *in)
773 int len = TYPE_LENGTH (type);
775 if (spu_scalar_value_p (type))
777 int preferred_slot = len < 4 ? 4 - len : 0;
778 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
784 regcache_cooked_write (regcache, regnum++, in);
790 regcache_cooked_write_part (regcache, regnum, 0, len, in);
795 spu_regcache_to_value (struct regcache *regcache, int regnum,
796 struct type *type, gdb_byte *out)
798 int len = TYPE_LENGTH (type);
800 if (spu_scalar_value_p (type))
802 int preferred_slot = len < 4 ? 4 - len : 0;
803 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
809 regcache_cooked_read (regcache, regnum++, out);
815 regcache_cooked_read_part (regcache, regnum, 0, len, out);
820 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
821 struct regcache *regcache, CORE_ADDR bp_addr,
822 int nargs, struct value **args, CORE_ADDR sp,
823 int struct_return, CORE_ADDR struct_addr)
826 int regnum = SPU_ARG1_REGNUM;
830 /* Set the return address. */
831 memset (buf, 0, sizeof buf);
832 store_unsigned_integer (buf, 4, bp_addr);
833 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
835 /* If STRUCT_RETURN is true, then the struct return address (in
836 STRUCT_ADDR) will consume the first argument-passing register.
837 Both adjust the register count and store that value. */
840 memset (buf, 0, sizeof buf);
841 store_unsigned_integer (buf, 4, struct_addr);
842 regcache_cooked_write (regcache, regnum++, buf);
845 /* Fill in argument registers. */
846 for (i = 0; i < nargs; i++)
848 struct value *arg = args[i];
849 struct type *type = check_typedef (value_type (arg));
850 const gdb_byte *contents = value_contents (arg);
851 int len = TYPE_LENGTH (type);
852 int n_regs = align_up (len, 16) / 16;
854 /* If the argument doesn't wholly fit into registers, it and
855 all subsequent arguments go to the stack. */
856 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
862 spu_value_to_regcache (regcache, regnum, type, contents);
866 /* Overflow arguments go to the stack. */
871 /* Allocate all required stack size. */
872 for (i = stack_arg; i < nargs; i++)
874 struct type *type = check_typedef (value_type (args[i]));
875 sp -= align_up (TYPE_LENGTH (type), 16);
878 /* Fill in stack arguments. */
880 for (i = stack_arg; i < nargs; i++)
882 struct value *arg = args[i];
883 struct type *type = check_typedef (value_type (arg));
884 int len = TYPE_LENGTH (type);
887 if (spu_scalar_value_p (type))
888 preferred_slot = len < 4 ? 4 - len : 0;
892 target_write_memory (ap + preferred_slot, value_contents (arg), len);
893 ap += align_up (TYPE_LENGTH (type), 16);
897 /* Allocate stack frame header. */
900 /* Finally, update the SP register. */
901 regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp);
906 static struct frame_id
907 spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
909 return frame_id_build (spu_unwind_sp (gdbarch, next_frame),
910 spu_unwind_pc (gdbarch, next_frame));
913 /* Function return value access. */
915 static enum return_value_convention
916 spu_return_value (struct gdbarch *gdbarch, struct type *type,
917 struct regcache *regcache, gdb_byte *out, const gdb_byte *in)
919 enum return_value_convention rvc;
921 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
922 rvc = RETURN_VALUE_REGISTER_CONVENTION;
924 rvc = RETURN_VALUE_STRUCT_CONVENTION;
930 case RETURN_VALUE_REGISTER_CONVENTION:
931 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
934 case RETURN_VALUE_STRUCT_CONVENTION:
935 error ("Cannot set function return value.");
943 case RETURN_VALUE_REGISTER_CONVENTION:
944 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
947 case RETURN_VALUE_STRUCT_CONVENTION:
948 error ("Function return value unknown.");
959 static const gdb_byte *
960 spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
962 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
964 *lenptr = sizeof breakpoint;
969 /* Software single-stepping support. */
972 spu_software_single_step (enum target_signal signal, int insert_breakpoints_p)
974 if (insert_breakpoints_p)
976 CORE_ADDR pc, next_pc;
981 regcache_cooked_read (current_regcache, SPU_PC_REGNUM, buf);
982 pc = extract_unsigned_integer (buf, 4);
984 if (target_read_memory (pc, buf, 4))
986 insn = extract_unsigned_integer (buf, 4);
988 /* Next sequential instruction is at PC + 4, except if the current
989 instruction is a PPE-assisted call, in which case it is at PC + 8.
990 Wrap around LS limit to be on the safe side. */
991 if ((insn & 0xffffff00) == 0x00002100)
992 next_pc = (pc + 8) & (SPU_LS_SIZE - 1) & -4;
994 next_pc = (pc + 4) & (SPU_LS_SIZE - 1) & -4;
996 insert_single_step_breakpoint (next_pc);
998 if (is_branch (insn, &offset, ®))
1000 CORE_ADDR target = offset;
1002 if (reg == SPU_PC_REGNUM)
1006 regcache_cooked_read_part (current_regcache, reg, 0, 4, buf);
1007 target += extract_unsigned_integer (buf, 4);
1010 target = target & (SPU_LS_SIZE - 1) & -4;
1011 if (target != next_pc)
1012 insert_single_step_breakpoint (target);
1016 remove_single_step_breakpoints ();
1020 /* Set up gdbarch struct. */
1022 static struct gdbarch *
1023 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1025 struct gdbarch *gdbarch;
1027 /* Find a candidate among the list of pre-declared architectures. */
1028 arches = gdbarch_list_lookup_by_info (arches, &info);
1030 return arches->gdbarch;
1033 if (info.bfd_arch_info->mach != bfd_mach_spu)
1036 /* Yes, create a new architecture. */
1037 gdbarch = gdbarch_alloc (&info, NULL);
1040 set_gdbarch_print_insn (gdbarch, print_insn_spu);
1043 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
1044 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
1045 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
1046 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
1047 set_gdbarch_register_name (gdbarch, spu_register_name);
1048 set_gdbarch_register_type (gdbarch, spu_register_type);
1049 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
1050 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
1051 set_gdbarch_convert_register_p (gdbarch, spu_convert_register_p);
1052 set_gdbarch_register_to_value (gdbarch, spu_register_to_value);
1053 set_gdbarch_value_to_register (gdbarch, spu_value_to_register);
1054 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
1057 set_gdbarch_char_signed (gdbarch, 0);
1058 set_gdbarch_ptr_bit (gdbarch, 32);
1059 set_gdbarch_addr_bit (gdbarch, 32);
1060 set_gdbarch_short_bit (gdbarch, 16);
1061 set_gdbarch_int_bit (gdbarch, 32);
1062 set_gdbarch_long_bit (gdbarch, 32);
1063 set_gdbarch_long_long_bit (gdbarch, 64);
1064 set_gdbarch_float_bit (gdbarch, 32);
1065 set_gdbarch_double_bit (gdbarch, 64);
1066 set_gdbarch_long_double_bit (gdbarch, 64);
1067 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
1068 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
1069 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
1071 /* Inferior function calls. */
1072 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
1073 set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id);
1074 set_gdbarch_return_value (gdbarch, spu_return_value);
1076 /* Frame handling. */
1077 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1078 frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer);
1079 frame_base_set_default (gdbarch, &spu_frame_base);
1080 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
1081 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
1082 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
1083 set_gdbarch_frame_args_skip (gdbarch, 0);
1084 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
1087 set_gdbarch_decr_pc_after_break (gdbarch, 4);
1088 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
1089 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1090 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
1096 _initialize_spu_tdep (void)
1098 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);