1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
30 #include "frame-unwind.h"
31 #include "frame-base.h"
32 #include "trad-frame.h"
41 #include "reggroups.h"
42 #include "floatformat.h"
48 /* The tdep structure. */
51 /* SPU-specific vector type. */
52 struct type *spu_builtin_type_vec128;
56 /* SPU-specific vector type. */
58 spu_builtin_type_vec128 (struct gdbarch *gdbarch)
60 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
62 if (!tdep->spu_builtin_type_vec128)
66 t = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
67 append_composite_type_field (t, "uint128", builtin_type_int128);
68 append_composite_type_field (t, "v2_int64",
69 init_vector_type (builtin_type_int64, 2));
70 append_composite_type_field (t, "v4_int32",
71 init_vector_type (builtin_type_int32, 4));
72 append_composite_type_field (t, "v8_int16",
73 init_vector_type (builtin_type_int16, 8));
74 append_composite_type_field (t, "v16_int8",
75 init_vector_type (builtin_type_int8, 16));
76 append_composite_type_field (t, "v2_double",
77 init_vector_type (builtin_type_double, 2));
78 append_composite_type_field (t, "v4_float",
79 init_vector_type (builtin_type_float, 4));
82 TYPE_NAME (t) = "spu_builtin_type_vec128";
84 tdep->spu_builtin_type_vec128 = t;
87 return tdep->spu_builtin_type_vec128;
91 /* The list of available "info spu " commands. */
92 static struct cmd_list_element *infospucmdlist = NULL;
97 spu_register_name (struct gdbarch *gdbarch, int reg_nr)
99 static char *register_names[] =
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
104 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
105 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
106 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
107 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
108 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
109 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
110 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
111 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
112 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
113 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
114 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
115 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
116 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
117 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
122 if (reg_nr >= sizeof register_names / sizeof *register_names)
125 return register_names[reg_nr];
129 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
131 if (reg_nr < SPU_NUM_GPRS)
132 return spu_builtin_type_vec128 (gdbarch);
137 return builtin_type_uint32;
140 return builtin_type_void_func_ptr;
143 return builtin_type_void_data_ptr;
145 case SPU_FPSCR_REGNUM:
146 return builtin_type_uint128;
148 case SPU_SRR0_REGNUM:
149 return builtin_type_uint32;
151 case SPU_LSLR_REGNUM:
152 return builtin_type_uint32;
154 case SPU_DECR_REGNUM:
155 return builtin_type_uint32;
157 case SPU_DECR_STATUS_REGNUM:
158 return builtin_type_uint32;
161 internal_error (__FILE__, __LINE__, "invalid regnum");
165 /* Pseudo registers for preferred slots - stack pointer. */
168 spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
175 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
176 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
177 memset (reg, 0, sizeof reg);
178 target_read (¤t_target, TARGET_OBJECT_SPU, annex,
181 store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
185 spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
186 int regnum, gdb_byte *buf)
195 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
196 memcpy (buf, reg, 4);
199 case SPU_FPSCR_REGNUM:
200 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
201 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
202 target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
205 case SPU_SRR0_REGNUM:
206 spu_pseudo_register_read_spu (regcache, "srr0", buf);
209 case SPU_LSLR_REGNUM:
210 spu_pseudo_register_read_spu (regcache, "lslr", buf);
213 case SPU_DECR_REGNUM:
214 spu_pseudo_register_read_spu (regcache, "decr", buf);
217 case SPU_DECR_STATUS_REGNUM:
218 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
222 internal_error (__FILE__, __LINE__, _("invalid regnum"));
227 spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
234 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
235 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
236 xsnprintf (reg, sizeof reg, "0x%s",
237 phex_nz (extract_unsigned_integer (buf, 4), 4));
238 target_write (¤t_target, TARGET_OBJECT_SPU, annex,
239 reg, 0, strlen (reg));
243 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
244 int regnum, const gdb_byte *buf)
253 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
254 memcpy (reg, buf, 4);
255 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
258 case SPU_FPSCR_REGNUM:
259 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
260 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
261 target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
264 case SPU_SRR0_REGNUM:
265 spu_pseudo_register_write_spu (regcache, "srr0", buf);
268 case SPU_LSLR_REGNUM:
269 spu_pseudo_register_write_spu (regcache, "lslr", buf);
272 case SPU_DECR_REGNUM:
273 spu_pseudo_register_write_spu (regcache, "decr", buf);
276 case SPU_DECR_STATUS_REGNUM:
277 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
281 internal_error (__FILE__, __LINE__, _("invalid regnum"));
285 /* Value conversion -- access scalar values at the preferred slot. */
287 static struct value *
288 spu_value_from_register (struct type *type, int regnum,
289 struct frame_info *frame)
291 struct value *value = default_value_from_register (type, regnum, frame);
292 int len = TYPE_LENGTH (type);
294 if (regnum < SPU_NUM_GPRS && len < 16)
296 int preferred_slot = len < 4 ? 4 - len : 0;
297 set_value_offset (value, preferred_slot);
303 /* Register groups. */
306 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
307 struct reggroup *group)
309 /* Registers displayed via 'info regs'. */
310 if (group == general_reggroup)
313 /* Registers displayed via 'info float'. */
314 if (group == float_reggroup)
317 /* Registers that need to be saved/restored in order to
318 push or pop frames. */
319 if (group == save_reggroup || group == restore_reggroup)
322 return default_register_reggroup_p (gdbarch, regnum, group);
325 /* Address conversion. */
328 spu_pointer_to_address (struct type *type, const gdb_byte *buf)
330 ULONGEST addr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
331 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
333 if (target_has_registers && target_has_stack && target_has_memory)
334 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
341 spu_integer_to_address (struct gdbarch *gdbarch,
342 struct type *type, const gdb_byte *buf)
344 ULONGEST addr = unpack_long (type, buf);
345 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
347 if (target_has_registers && target_has_stack && target_has_memory)
348 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
355 /* Decoding SPU instructions. */
392 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
394 if ((insn >> 21) == op)
397 *ra = (insn >> 7) & 127;
398 *rb = (insn >> 14) & 127;
406 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
408 if ((insn >> 28) == op)
410 *rt = (insn >> 21) & 127;
411 *ra = (insn >> 7) & 127;
412 *rb = (insn >> 14) & 127;
421 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
423 if ((insn >> 21) == op)
426 *ra = (insn >> 7) & 127;
427 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
435 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
437 if ((insn >> 24) == op)
440 *ra = (insn >> 7) & 127;
441 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
449 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
451 if ((insn >> 23) == op)
454 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
462 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
464 if ((insn >> 25) == op)
467 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
475 is_branch (unsigned int insn, int *offset, int *reg)
479 if (is_ri16 (insn, op_br, &rt, &i16)
480 || is_ri16 (insn, op_brsl, &rt, &i16)
481 || is_ri16 (insn, op_brnz, &rt, &i16)
482 || is_ri16 (insn, op_brz, &rt, &i16)
483 || is_ri16 (insn, op_brhnz, &rt, &i16)
484 || is_ri16 (insn, op_brhz, &rt, &i16))
486 *reg = SPU_PC_REGNUM;
491 if (is_ri16 (insn, op_bra, &rt, &i16)
492 || is_ri16 (insn, op_brasl, &rt, &i16))
499 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
500 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
501 || is_ri7 (insn, op_biz, &rt, reg, &i7)
502 || is_ri7 (insn, op_binz, &rt, reg, &i7)
503 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
504 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
514 /* Prolog parsing. */
516 struct spu_prologue_data
518 /* Stack frame size. -1 if analysis was unsuccessful. */
521 /* How to find the CFA. The CFA is equal to SP at function entry. */
525 /* Offset relative to CFA where a register is saved. -1 if invalid. */
526 int reg_offset[SPU_NUM_GPRS];
530 spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
531 struct spu_prologue_data *data)
536 int reg_immed[SPU_NUM_GPRS];
538 CORE_ADDR prolog_pc = start_pc;
543 /* Initialize DATA to default values. */
546 data->cfa_reg = SPU_RAW_SP_REGNUM;
547 data->cfa_offset = 0;
549 for (i = 0; i < SPU_NUM_GPRS; i++)
550 data->reg_offset[i] = -1;
552 /* Set up REG_IMMED array. This is non-zero for a register if we know its
553 preferred slot currently holds this immediate value. */
554 for (i = 0; i < SPU_NUM_GPRS; i++)
557 /* Scan instructions until the first branch.
559 The following instructions are important prolog components:
561 - The first instruction to set up the stack pointer.
562 - The first instruction to set up the frame pointer.
563 - The first instruction to save the link register.
565 We return the instruction after the latest of these three,
566 or the incoming PC if none is found. The first instruction
567 to set up the stack pointer also defines the frame size.
569 Note that instructions saving incoming arguments to their stack
570 slots are not counted as important, because they are hard to
571 identify with certainty. This should not matter much, because
572 arguments are relevant only in code compiled with debug data,
573 and in such code the GDB core will advance until the first source
574 line anyway, using SAL data.
576 For purposes of stack unwinding, we analyze the following types
577 of instructions in addition:
579 - Any instruction adding to the current frame pointer.
580 - Any instruction loading an immediate constant into a register.
581 - Any instruction storing a register onto the stack.
583 These are used to compute the CFA and REG_OFFSET output. */
585 for (pc = start_pc; pc < end_pc; pc += 4)
588 int rt, ra, rb, rc, immed;
590 if (target_read_memory (pc, buf, 4))
592 insn = extract_unsigned_integer (buf, 4);
594 /* AI is the typical instruction to set up a stack frame.
595 It is also used to initialize the frame pointer. */
596 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
598 if (rt == data->cfa_reg && ra == data->cfa_reg)
599 data->cfa_offset -= immed;
601 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
609 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
615 data->cfa_reg = SPU_FP_REGNUM;
616 data->cfa_offset -= immed;
620 /* A is used to set up stack frames of size >= 512 bytes.
621 If we have tracked the contents of the addend register,
622 we can handle this as well. */
623 else if (is_rr (insn, op_a, &rt, &ra, &rb))
625 if (rt == data->cfa_reg && ra == data->cfa_reg)
627 if (reg_immed[rb] != 0)
628 data->cfa_offset -= reg_immed[rb];
630 data->cfa_reg = -1; /* We don't know the CFA any more. */
633 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
639 if (reg_immed[rb] != 0)
640 data->size = -reg_immed[rb];
644 /* We need to track IL and ILA used to load immediate constants
645 in case they are later used as input to an A instruction. */
646 else if (is_ri16 (insn, op_il, &rt, &immed))
648 reg_immed[rt] = immed;
650 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
654 else if (is_ri18 (insn, op_ila, &rt, &immed))
656 reg_immed[rt] = immed & 0x3ffff;
658 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
662 /* STQD is used to save registers to the stack. */
663 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
665 if (ra == data->cfa_reg)
666 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
668 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
676 /* _start uses SELB to set up the stack pointer. */
677 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
679 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
683 /* We terminate if we find a branch. */
684 else if (is_branch (insn, &immed, &ra))
689 /* If we successfully parsed until here, and didn't find any instruction
690 modifying SP, we assume we have a frameless function. */
694 /* Return cooked instead of raw SP. */
695 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
696 data->cfa_reg = SPU_SP_REGNUM;
701 /* Return the first instruction after the prologue starting at PC. */
703 spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
705 struct spu_prologue_data data;
706 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
709 /* Return the frame pointer in use at address PC. */
711 spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
712 int *reg, LONGEST *offset)
714 struct spu_prologue_data data;
715 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
717 if (data.size != -1 && data.cfa_reg != -1)
719 /* The 'frame pointer' address is CFA minus frame size. */
721 *offset = data.cfa_offset - data.size;
725 /* ??? We don't really know ... */
726 *reg = SPU_SP_REGNUM;
731 /* Return true if we are in the function's epilogue, i.e. after the
732 instruction that destroyed the function's stack frame.
734 1) scan forward from the point of execution:
735 a) If you find an instruction that modifies the stack pointer
736 or transfers control (except a return), execution is not in
738 b) Stop scanning if you find a return instruction or reach the
739 end of the function or reach the hard limit for the size of
741 2) scan backward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer,
743 execution *is* in an epilogue, return.
744 b) Stop scanning if you reach an instruction that transfers
745 control or the beginning of the function or reach the hard
746 limit for the size of an epilogue. */
749 spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
751 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
754 int rt, ra, rb, rc, immed;
756 /* Find the search limits based on function boundaries and hard limit.
757 We assume the epilogue can be up to 64 instructions long. */
759 const int spu_max_epilogue_size = 64 * 4;
761 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
764 if (pc - func_start < spu_max_epilogue_size)
765 epilogue_start = func_start;
767 epilogue_start = pc - spu_max_epilogue_size;
769 if (func_end - pc < spu_max_epilogue_size)
770 epilogue_end = func_end;
772 epilogue_end = pc + spu_max_epilogue_size;
774 /* Scan forward until next 'bi $0'. */
776 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
778 if (target_read_memory (scan_pc, buf, 4))
780 insn = extract_unsigned_integer (buf, 4);
782 if (is_branch (insn, &immed, &ra))
784 if (immed == 0 && ra == SPU_LR_REGNUM)
790 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
791 || is_rr (insn, op_a, &rt, &ra, &rb)
792 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
794 if (rt == SPU_RAW_SP_REGNUM)
799 if (scan_pc >= epilogue_end)
802 /* Scan backward until adjustment to stack pointer (R1). */
804 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
806 if (target_read_memory (scan_pc, buf, 4))
808 insn = extract_unsigned_integer (buf, 4);
810 if (is_branch (insn, &immed, &ra))
813 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
814 || is_rr (insn, op_a, &rt, &ra, &rb)
815 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
817 if (rt == SPU_RAW_SP_REGNUM)
826 /* Normal stack frames. */
828 struct spu_unwind_cache
831 CORE_ADDR frame_base;
832 CORE_ADDR local_base;
834 struct trad_frame_saved_reg *saved_regs;
837 static struct spu_unwind_cache *
838 spu_frame_unwind_cache (struct frame_info *this_frame,
839 void **this_prologue_cache)
841 struct spu_unwind_cache *info;
842 struct spu_prologue_data data;
845 if (*this_prologue_cache)
846 return *this_prologue_cache;
848 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
849 *this_prologue_cache = info;
850 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
851 info->frame_base = 0;
852 info->local_base = 0;
854 /* Find the start of the current function, and analyze its prologue. */
855 info->func = get_frame_func (this_frame);
858 /* Fall back to using the current PC as frame ID. */
859 info->func = get_frame_pc (this_frame);
863 spu_analyze_prologue (info->func, get_frame_pc (this_frame), &data);
866 /* If successful, use prologue analysis data. */
867 if (data.size != -1 && data.cfa_reg != -1)
872 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
873 get_frame_register (this_frame, data.cfa_reg, buf);
874 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
876 /* Call-saved register slots. */
877 for (i = 0; i < SPU_NUM_GPRS; i++)
878 if (i == SPU_LR_REGNUM
879 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
880 if (data.reg_offset[i] != -1)
881 info->saved_regs[i].addr = cfa - data.reg_offset[i];
884 info->frame_base = cfa;
885 info->local_base = cfa - data.size;
888 /* Otherwise, fall back to reading the backchain link. */
895 /* Get the backchain. */
896 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
897 status = safe_read_memory_integer (reg, 4, &backchain);
899 /* A zero backchain terminates the frame chain. Also, sanity
900 check against the local store size limit. */
901 if (status && backchain > 0 && backchain < SPU_LS_SIZE)
903 /* Assume the link register is saved into its slot. */
904 if (backchain + 16 < SPU_LS_SIZE)
905 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
908 info->frame_base = backchain;
909 info->local_base = reg;
913 /* If we didn't find a frame, we cannot determine SP / return address. */
914 if (info->frame_base == 0)
917 /* The previous SP is equal to the CFA. */
918 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
920 /* Read full contents of the unwound link register in order to
921 be able to determine the return address. */
922 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
923 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
925 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
927 /* Normally, the return address is contained in the slot 0 of the
928 link register, and slots 1-3 are zero. For an overlay return,
929 slot 0 contains the address of the overlay manager return stub,
930 slot 1 contains the partition number of the overlay section to
931 be returned to, and slot 2 contains the return address within
932 that section. Return the latter address in that case. */
933 if (extract_unsigned_integer (buf + 8, 4) != 0)
934 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
935 extract_unsigned_integer (buf + 8, 4));
937 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
938 extract_unsigned_integer (buf, 4));
944 spu_frame_this_id (struct frame_info *this_frame,
945 void **this_prologue_cache, struct frame_id *this_id)
947 struct spu_unwind_cache *info =
948 spu_frame_unwind_cache (this_frame, this_prologue_cache);
950 if (info->frame_base == 0)
953 *this_id = frame_id_build (info->frame_base, info->func);
956 static struct value *
957 spu_frame_prev_register (struct frame_info *this_frame,
958 void **this_prologue_cache, int regnum)
960 struct spu_unwind_cache *info
961 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
963 /* Special-case the stack pointer. */
964 if (regnum == SPU_RAW_SP_REGNUM)
965 regnum = SPU_SP_REGNUM;
967 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
970 static const struct frame_unwind spu_frame_unwind = {
973 spu_frame_prev_register,
975 default_frame_sniffer
979 spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
981 struct spu_unwind_cache *info
982 = spu_frame_unwind_cache (this_frame, this_cache);
983 return info->local_base;
986 static const struct frame_base spu_frame_base = {
988 spu_frame_base_address,
989 spu_frame_base_address,
990 spu_frame_base_address
994 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
996 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
997 /* Mask off interrupt enable bit. */
1002 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1004 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1008 spu_read_pc (struct regcache *regcache)
1011 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
1012 /* Mask off interrupt enable bit. */
1017 spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
1019 /* Keep interrupt enabled state unchanged. */
1021 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1022 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1023 (pc & -4) | (old_pc & 3));
1027 /* Function calling convention. */
1030 spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1036 spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1037 struct value **args, int nargs, struct type *value_type,
1038 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1039 struct regcache *regcache)
1041 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1042 sp = (sp - 4) & ~15;
1043 /* Store the address of that breakpoint */
1045 /* The call starts at the callee's entry point. */
1052 spu_scalar_value_p (struct type *type)
1054 switch (TYPE_CODE (type))
1057 case TYPE_CODE_ENUM:
1058 case TYPE_CODE_RANGE:
1059 case TYPE_CODE_CHAR:
1060 case TYPE_CODE_BOOL:
1063 return TYPE_LENGTH (type) <= 16;
1071 spu_value_to_regcache (struct regcache *regcache, int regnum,
1072 struct type *type, const gdb_byte *in)
1074 int len = TYPE_LENGTH (type);
1076 if (spu_scalar_value_p (type))
1078 int preferred_slot = len < 4 ? 4 - len : 0;
1079 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1085 regcache_cooked_write (regcache, regnum++, in);
1091 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1096 spu_regcache_to_value (struct regcache *regcache, int regnum,
1097 struct type *type, gdb_byte *out)
1099 int len = TYPE_LENGTH (type);
1101 if (spu_scalar_value_p (type))
1103 int preferred_slot = len < 4 ? 4 - len : 0;
1104 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1110 regcache_cooked_read (regcache, regnum++, out);
1116 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1121 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1122 struct regcache *regcache, CORE_ADDR bp_addr,
1123 int nargs, struct value **args, CORE_ADDR sp,
1124 int struct_return, CORE_ADDR struct_addr)
1128 int regnum = SPU_ARG1_REGNUM;
1132 /* Set the return address. */
1133 memset (buf, 0, sizeof buf);
1134 store_unsigned_integer (buf, 4, bp_addr);
1135 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1137 /* If STRUCT_RETURN is true, then the struct return address (in
1138 STRUCT_ADDR) will consume the first argument-passing register.
1139 Both adjust the register count and store that value. */
1142 memset (buf, 0, sizeof buf);
1143 store_unsigned_integer (buf, 4, struct_addr);
1144 regcache_cooked_write (regcache, regnum++, buf);
1147 /* Fill in argument registers. */
1148 for (i = 0; i < nargs; i++)
1150 struct value *arg = args[i];
1151 struct type *type = check_typedef (value_type (arg));
1152 const gdb_byte *contents = value_contents (arg);
1153 int len = TYPE_LENGTH (type);
1154 int n_regs = align_up (len, 16) / 16;
1156 /* If the argument doesn't wholly fit into registers, it and
1157 all subsequent arguments go to the stack. */
1158 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1164 spu_value_to_regcache (regcache, regnum, type, contents);
1168 /* Overflow arguments go to the stack. */
1169 if (stack_arg != -1)
1173 /* Allocate all required stack size. */
1174 for (i = stack_arg; i < nargs; i++)
1176 struct type *type = check_typedef (value_type (args[i]));
1177 sp -= align_up (TYPE_LENGTH (type), 16);
1180 /* Fill in stack arguments. */
1182 for (i = stack_arg; i < nargs; i++)
1184 struct value *arg = args[i];
1185 struct type *type = check_typedef (value_type (arg));
1186 int len = TYPE_LENGTH (type);
1189 if (spu_scalar_value_p (type))
1190 preferred_slot = len < 4 ? 4 - len : 0;
1194 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1195 ap += align_up (TYPE_LENGTH (type), 16);
1199 /* Allocate stack frame header. */
1202 /* Store stack back chain. */
1203 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1204 target_write_memory (sp, buf, 16);
1206 /* Finally, update all slots of the SP register. */
1207 sp_delta = sp - extract_unsigned_integer (buf, 4);
1208 for (i = 0; i < 4; i++)
1210 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4);
1211 store_unsigned_integer (buf + 4*i, 4, sp_slot + sp_delta);
1213 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
1218 static struct frame_id
1219 spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1221 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1222 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1223 return frame_id_build (sp, pc & -4);
1226 /* Function return value access. */
1228 static enum return_value_convention
1229 spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1230 struct type *type, struct regcache *regcache,
1231 gdb_byte *out, const gdb_byte *in)
1233 enum return_value_convention rvc;
1235 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1236 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1238 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1244 case RETURN_VALUE_REGISTER_CONVENTION:
1245 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1248 case RETURN_VALUE_STRUCT_CONVENTION:
1249 error ("Cannot set function return value.");
1257 case RETURN_VALUE_REGISTER_CONVENTION:
1258 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1261 case RETURN_VALUE_STRUCT_CONVENTION:
1262 error ("Function return value unknown.");
1273 static const gdb_byte *
1274 spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
1276 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1278 *lenptr = sizeof breakpoint;
1283 /* Software single-stepping support. */
1286 spu_software_single_step (struct frame_info *frame)
1288 CORE_ADDR pc, next_pc;
1293 pc = get_frame_pc (frame);
1295 if (target_read_memory (pc, buf, 4))
1297 insn = extract_unsigned_integer (buf, 4);
1299 /* Next sequential instruction is at PC + 4, except if the current
1300 instruction is a PPE-assisted call, in which case it is at PC + 8.
1301 Wrap around LS limit to be on the safe side. */
1302 if ((insn & 0xffffff00) == 0x00002100)
1303 next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1305 next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
1307 insert_single_step_breakpoint (next_pc);
1309 if (is_branch (insn, &offset, ®))
1311 CORE_ADDR target = offset;
1313 if (reg == SPU_PC_REGNUM)
1317 get_frame_register_bytes (frame, reg, 0, 4, buf);
1318 target += extract_unsigned_integer (buf, 4) & -4;
1321 target = target & (SPU_LS_SIZE - 1);
1322 if (target != next_pc)
1323 insert_single_step_breakpoint (target);
1329 /* Target overlays for the SPU overlay manager.
1331 See the documentation of simple_overlay_update for how the
1332 interface is supposed to work.
1334 Data structures used by the overlay manager:
1342 } _ovly_table[]; -- one entry per overlay section
1344 struct ovly_buf_table
1347 } _ovly_buf_table[]; -- one entry per overlay buffer
1349 _ovly_table should never change.
1351 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1352 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1353 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1355 mapped is an index into _ovly_table. Both the mapped and buf indices start
1356 from one to reference the first entry in their respective tables. */
1358 /* Using the per-objfile private data mechanism, we store for each
1359 objfile an array of "struct spu_overlay_table" structures, one
1360 for each obj_section of the objfile. This structure holds two
1361 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1362 is *not* an overlay section. If it is non-zero, it represents
1363 a target address. The overlay section is mapped iff the target
1364 integer at this location equals MAPPED_VAL. */
1366 static const struct objfile_data *spu_overlay_data;
1368 struct spu_overlay_table
1370 CORE_ADDR mapped_ptr;
1371 CORE_ADDR mapped_val;
1374 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1375 the _ovly_table data structure from the target and initialize the
1376 spu_overlay_table data structure from it. */
1377 static struct spu_overlay_table *
1378 spu_get_overlay_table (struct objfile *objfile)
1380 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1381 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1382 unsigned ovly_table_size, ovly_buf_table_size;
1383 struct spu_overlay_table *tbl;
1384 struct obj_section *osect;
1388 tbl = objfile_data (objfile, spu_overlay_data);
1392 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1393 if (!ovly_table_msym)
1396 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1397 if (!ovly_buf_table_msym)
1400 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1401 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1403 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1404 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1406 ovly_table = xmalloc (ovly_table_size);
1407 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1409 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1410 objfile->sections_end - objfile->sections,
1411 struct spu_overlay_table);
1413 for (i = 0; i < ovly_table_size / 16; i++)
1415 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1416 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1417 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1418 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1420 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1423 ALL_OBJFILE_OSECTIONS (objfile, osect)
1424 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1425 && pos == osect->the_bfd_section->filepos)
1427 int ndx = osect - objfile->sections;
1428 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1429 tbl[ndx].mapped_val = i + 1;
1435 set_objfile_data (objfile, spu_overlay_data, tbl);
1439 /* Read _ovly_buf_table entry from the target to dermine whether
1440 OSECT is currently mapped, and update the mapped state. */
1442 spu_overlay_update_osect (struct obj_section *osect)
1444 struct spu_overlay_table *ovly_table;
1447 ovly_table = spu_get_overlay_table (osect->objfile);
1451 ovly_table += osect - osect->objfile->sections;
1452 if (ovly_table->mapped_ptr == 0)
1455 val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1456 osect->ovly_mapped = (val == ovly_table->mapped_val);
1459 /* If OSECT is NULL, then update all sections' mapped state.
1460 If OSECT is non-NULL, then update only OSECT's mapped state. */
1462 spu_overlay_update (struct obj_section *osect)
1464 /* Just one section. */
1466 spu_overlay_update_osect (osect);
1471 struct objfile *objfile;
1473 ALL_OBJSECTIONS (objfile, osect)
1474 if (section_is_overlay (osect))
1475 spu_overlay_update_osect (osect);
1479 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1480 If there is one, go through all sections and make sure for non-
1481 overlay sections LMA equals VMA, while for overlay sections LMA
1482 is larger than local store size. */
1484 spu_overlay_new_objfile (struct objfile *objfile)
1486 struct spu_overlay_table *ovly_table;
1487 struct obj_section *osect;
1489 /* If we've already touched this file, do nothing. */
1490 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1493 /* Consider only SPU objfiles. */
1494 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1497 /* Check if this objfile has overlays. */
1498 ovly_table = spu_get_overlay_table (objfile);
1502 /* Now go and fiddle with all the LMAs. */
1503 ALL_OBJFILE_OSECTIONS (objfile, osect)
1505 bfd *obfd = objfile->obfd;
1506 asection *bsect = osect->the_bfd_section;
1507 int ndx = osect - objfile->sections;
1509 if (ovly_table[ndx].mapped_ptr == 0)
1510 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1512 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1517 /* "info spu" commands. */
1520 info_spu_event_command (char *args, int from_tty)
1522 struct frame_info *frame = get_selected_frame (NULL);
1523 ULONGEST event_status = 0;
1524 ULONGEST event_mask = 0;
1525 struct cleanup *chain;
1531 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1532 error (_("\"info spu\" is only supported on the SPU architecture."));
1534 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1536 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1537 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1538 buf, 0, (sizeof (buf) - 1));
1540 error (_("Could not read event_status."));
1542 event_status = strtoulst (buf, NULL, 16);
1544 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1545 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1546 buf, 0, (sizeof (buf) - 1));
1548 error (_("Could not read event_mask."));
1550 event_mask = strtoulst (buf, NULL, 16);
1552 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1554 if (ui_out_is_mi_like_p (uiout))
1556 ui_out_field_fmt (uiout, "event_status",
1557 "0x%s", phex_nz (event_status, 4));
1558 ui_out_field_fmt (uiout, "event_mask",
1559 "0x%s", phex_nz (event_mask, 4));
1563 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1564 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1567 do_cleanups (chain);
1571 info_spu_signal_command (char *args, int from_tty)
1573 struct frame_info *frame = get_selected_frame (NULL);
1574 ULONGEST signal1 = 0;
1575 ULONGEST signal1_type = 0;
1576 int signal1_pending = 0;
1577 ULONGEST signal2 = 0;
1578 ULONGEST signal2_type = 0;
1579 int signal2_pending = 0;
1580 struct cleanup *chain;
1586 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1587 error (_("\"info spu\" is only supported on the SPU architecture."));
1589 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1591 xsnprintf (annex, sizeof annex, "%d/signal1", id);
1592 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1594 error (_("Could not read signal1."));
1597 signal1 = extract_unsigned_integer (buf, 4);
1598 signal1_pending = 1;
1601 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1602 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1603 buf, 0, (sizeof (buf) - 1));
1605 error (_("Could not read signal1_type."));
1607 signal1_type = strtoulst (buf, NULL, 16);
1609 xsnprintf (annex, sizeof annex, "%d/signal2", id);
1610 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1612 error (_("Could not read signal2."));
1615 signal2 = extract_unsigned_integer (buf, 4);
1616 signal2_pending = 1;
1619 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1620 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1621 buf, 0, (sizeof (buf) - 1));
1623 error (_("Could not read signal2_type."));
1625 signal2_type = strtoulst (buf, NULL, 16);
1627 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1629 if (ui_out_is_mi_like_p (uiout))
1631 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1632 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1633 ui_out_field_int (uiout, "signal1_type", signal1_type);
1634 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1635 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1636 ui_out_field_int (uiout, "signal2_type", signal2_type);
1640 if (signal1_pending)
1641 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1643 printf_filtered (_("Signal 1 not pending "));
1646 printf_filtered (_("(Type Or)\n"));
1648 printf_filtered (_("(Type Overwrite)\n"));
1650 if (signal2_pending)
1651 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1653 printf_filtered (_("Signal 2 not pending "));
1656 printf_filtered (_("(Type Or)\n"));
1658 printf_filtered (_("(Type Overwrite)\n"));
1661 do_cleanups (chain);
1665 info_spu_mailbox_list (gdb_byte *buf, int nr,
1666 const char *field, const char *msg)
1668 struct cleanup *chain;
1674 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1676 ui_out_table_header (uiout, 32, ui_left, field, msg);
1677 ui_out_table_body (uiout);
1679 for (i = 0; i < nr; i++)
1681 struct cleanup *val_chain;
1683 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1684 val = extract_unsigned_integer (buf + 4*i, 4);
1685 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1686 do_cleanups (val_chain);
1688 if (!ui_out_is_mi_like_p (uiout))
1689 printf_filtered ("\n");
1692 do_cleanups (chain);
1696 info_spu_mailbox_command (char *args, int from_tty)
1698 struct frame_info *frame = get_selected_frame (NULL);
1699 struct cleanup *chain;
1705 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1706 error (_("\"info spu\" is only supported on the SPU architecture."));
1708 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1710 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1712 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1713 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1714 buf, 0, sizeof buf);
1716 error (_("Could not read mbox_info."));
1718 info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1720 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1721 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1722 buf, 0, sizeof buf);
1724 error (_("Could not read ibox_info."));
1726 info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1728 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1729 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1730 buf, 0, sizeof buf);
1732 error (_("Could not read wbox_info."));
1734 info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1736 do_cleanups (chain);
1740 spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1742 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1743 return (word >> (63 - last)) & mask;
1747 info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1749 static char *spu_mfc_opcode[256] =
1751 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1752 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1753 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1754 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1755 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1756 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1757 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1758 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1759 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1760 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1761 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1762 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1763 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1764 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1765 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1766 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1767 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1768 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1769 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1770 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1771 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1772 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1773 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1774 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1775 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1776 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1777 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1778 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1779 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1780 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1781 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1782 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1785 int *seq = alloca (nr * sizeof (int));
1787 struct cleanup *chain;
1791 /* Determine sequence in which to display (valid) entries. */
1792 for (i = 0; i < nr; i++)
1794 /* Search for the first valid entry all of whose
1795 dependencies are met. */
1796 for (j = 0; j < nr; j++)
1798 ULONGEST mfc_cq_dw3;
1799 ULONGEST dependencies;
1801 if (done & (1 << (nr - 1 - j)))
1804 mfc_cq_dw3 = extract_unsigned_integer (buf + 32*j + 24, 8);
1805 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
1808 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
1809 if ((dependencies & done) != dependencies)
1813 done |= 1 << (nr - 1 - j);
1824 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1826 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1827 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1828 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1829 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1830 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1831 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1832 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1833 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1834 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1835 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1837 ui_out_table_body (uiout);
1839 for (i = 0; i < nr; i++)
1841 struct cleanup *cmd_chain;
1842 ULONGEST mfc_cq_dw0;
1843 ULONGEST mfc_cq_dw1;
1844 ULONGEST mfc_cq_dw2;
1845 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1846 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1848 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1850 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1851 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1853 mfc_cq_dw0 = extract_unsigned_integer (buf + 32*seq[i], 8);
1854 mfc_cq_dw1 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8);
1855 mfc_cq_dw2 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8);
1857 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1858 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1859 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1860 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1861 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1862 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1863 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1865 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1866 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1868 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1869 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1870 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1871 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1872 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1873 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1875 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1877 if (spu_mfc_opcode[mfc_cmd_opcode])
1878 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1880 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1882 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1883 ui_out_field_int (uiout, "tid", tclass_id);
1884 ui_out_field_int (uiout, "rid", rclass_id);
1887 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1889 ui_out_field_skip (uiout, "ea");
1891 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1893 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1895 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1899 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1900 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1904 ui_out_field_skip (uiout, "lstaddr");
1905 ui_out_field_skip (uiout, "lstsize");
1909 ui_out_field_string (uiout, "error_p", "*");
1911 ui_out_field_skip (uiout, "error_p");
1913 do_cleanups (cmd_chain);
1915 if (!ui_out_is_mi_like_p (uiout))
1916 printf_filtered ("\n");
1919 do_cleanups (chain);
1923 info_spu_dma_command (char *args, int from_tty)
1925 struct frame_info *frame = get_selected_frame (NULL);
1926 ULONGEST dma_info_type;
1927 ULONGEST dma_info_mask;
1928 ULONGEST dma_info_status;
1929 ULONGEST dma_info_stall_and_notify;
1930 ULONGEST dma_info_atomic_command_status;
1931 struct cleanup *chain;
1937 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1938 error (_("\"info spu\" is only supported on the SPU architecture."));
1940 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1942 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1943 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1944 buf, 0, 40 + 16 * 32);
1946 error (_("Could not read dma_info."));
1948 dma_info_type = extract_unsigned_integer (buf, 8);
1949 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1950 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1951 dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1952 dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1954 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1956 if (ui_out_is_mi_like_p (uiout))
1958 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1959 phex_nz (dma_info_type, 4));
1960 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1961 phex_nz (dma_info_mask, 4));
1962 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1963 phex_nz (dma_info_status, 4));
1964 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1965 phex_nz (dma_info_stall_and_notify, 4));
1966 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1967 phex_nz (dma_info_atomic_command_status, 4));
1971 const char *query_msg = _("no query pending");
1973 if (dma_info_type & 4)
1974 switch (dma_info_type & 3)
1976 case 1: query_msg = _("'any' query pending"); break;
1977 case 2: query_msg = _("'all' query pending"); break;
1978 default: query_msg = _("undefined query type"); break;
1981 printf_filtered (_("Tag-Group Status 0x%s\n"),
1982 phex (dma_info_status, 4));
1983 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1984 phex (dma_info_mask, 4), query_msg);
1985 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1986 phex (dma_info_stall_and_notify, 4));
1987 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1988 phex (dma_info_atomic_command_status, 4));
1989 printf_filtered ("\n");
1992 info_spu_dma_cmdlist (buf + 40, 16);
1993 do_cleanups (chain);
1997 info_spu_proxydma_command (char *args, int from_tty)
1999 struct frame_info *frame = get_selected_frame (NULL);
2000 ULONGEST dma_info_type;
2001 ULONGEST dma_info_mask;
2002 ULONGEST dma_info_status;
2003 struct cleanup *chain;
2009 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2010 error (_("\"info spu\" is only supported on the SPU architecture."));
2012 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2014 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2015 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
2016 buf, 0, 24 + 8 * 32);
2018 error (_("Could not read proxydma_info."));
2020 dma_info_type = extract_unsigned_integer (buf, 8);
2021 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
2022 dma_info_status = extract_unsigned_integer (buf + 16, 8);
2024 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
2026 if (ui_out_is_mi_like_p (uiout))
2028 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
2029 phex_nz (dma_info_type, 4));
2030 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
2031 phex_nz (dma_info_mask, 4));
2032 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
2033 phex_nz (dma_info_status, 4));
2037 const char *query_msg;
2039 switch (dma_info_type & 3)
2041 case 0: query_msg = _("no query pending"); break;
2042 case 1: query_msg = _("'any' query pending"); break;
2043 case 2: query_msg = _("'all' query pending"); break;
2044 default: query_msg = _("undefined query type"); break;
2047 printf_filtered (_("Tag-Group Status 0x%s\n"),
2048 phex (dma_info_status, 4));
2049 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2050 phex (dma_info_mask, 4), query_msg);
2051 printf_filtered ("\n");
2054 info_spu_dma_cmdlist (buf + 24, 8);
2055 do_cleanups (chain);
2059 info_spu_command (char *args, int from_tty)
2061 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2062 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2066 /* Set up gdbarch struct. */
2068 static struct gdbarch *
2069 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2071 struct gdbarch *gdbarch;
2072 struct gdbarch_tdep *tdep;
2074 /* Find a candidate among the list of pre-declared architectures. */
2075 arches = gdbarch_list_lookup_by_info (arches, &info);
2077 return arches->gdbarch;
2080 if (info.bfd_arch_info->mach != bfd_mach_spu)
2083 /* Yes, create a new architecture. */
2084 tdep = XCALLOC (1, struct gdbarch_tdep);
2085 gdbarch = gdbarch_alloc (&info, tdep);
2088 set_gdbarch_print_insn (gdbarch, print_insn_spu);
2091 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2092 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2093 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2094 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
2095 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2096 set_gdbarch_write_pc (gdbarch, spu_write_pc);
2097 set_gdbarch_register_name (gdbarch, spu_register_name);
2098 set_gdbarch_register_type (gdbarch, spu_register_type);
2099 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2100 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
2101 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
2102 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2105 set_gdbarch_char_signed (gdbarch, 0);
2106 set_gdbarch_ptr_bit (gdbarch, 32);
2107 set_gdbarch_addr_bit (gdbarch, 32);
2108 set_gdbarch_short_bit (gdbarch, 16);
2109 set_gdbarch_int_bit (gdbarch, 32);
2110 set_gdbarch_long_bit (gdbarch, 32);
2111 set_gdbarch_long_long_bit (gdbarch, 64);
2112 set_gdbarch_float_bit (gdbarch, 32);
2113 set_gdbarch_double_bit (gdbarch, 64);
2114 set_gdbarch_long_double_bit (gdbarch, 64);
2115 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2116 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2117 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2119 /* Address conversion. */
2120 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2121 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2123 /* Inferior function calls. */
2124 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2125 set_gdbarch_frame_align (gdbarch, spu_frame_align);
2126 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
2127 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
2128 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
2129 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
2130 set_gdbarch_return_value (gdbarch, spu_return_value);
2132 /* Frame handling. */
2133 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2134 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
2135 frame_base_set_default (gdbarch, &spu_frame_base);
2136 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2137 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2138 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2139 set_gdbarch_frame_args_skip (gdbarch, 0);
2140 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
2141 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
2144 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2145 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2146 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2147 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2150 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2156 _initialize_spu_tdep (void)
2158 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
2160 /* Add ourselves to objfile event chain. */
2161 observer_attach_new_objfile (spu_overlay_new_objfile);
2162 spu_overlay_data = register_objfile_data ();
2164 /* Add root prefix command for all "info spu" commands. */
2165 add_prefix_cmd ("spu", class_info, info_spu_command,
2166 _("Various SPU specific commands."),
2167 &infospucmdlist, "info spu ", 0, &infolist);
2169 /* Add various "info spu" commands. */
2170 add_cmd ("event", class_info, info_spu_event_command,
2171 _("Display SPU event facility status.\n"),
2173 add_cmd ("signal", class_info, info_spu_signal_command,
2174 _("Display SPU signal notification facility status.\n"),
2176 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2177 _("Display SPU mailbox facility status.\n"),
2179 add_cmd ("dma", class_info, info_spu_dma_command,
2180 _("Display MFC DMA status.\n"),
2182 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2183 _("Display MFC Proxy-DMA status.\n"),