1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
25 #include "arch-utils.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
43 #include "reggroups.h"
44 #include "floatformat.h"
49 /* SPU-specific vector type. */
50 struct type *spu_builtin_type_vec128;
52 /* The list of available "info spu " commands. */
53 static struct cmd_list_element *infospucmdlist = NULL;
58 spu_register_name (int reg_nr)
60 static char *register_names[] =
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
63 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
64 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
65 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
66 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
67 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
68 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
69 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
70 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
71 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
73 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
74 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
75 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
76 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
77 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
78 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
83 if (reg_nr >= sizeof register_names / sizeof *register_names)
86 return register_names[reg_nr];
90 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
92 if (reg_nr < SPU_NUM_GPRS)
93 return spu_builtin_type_vec128;
98 return builtin_type_uint32;
101 return builtin_type_void_func_ptr;
104 return builtin_type_void_data_ptr;
106 case SPU_FPSCR_REGNUM:
107 return builtin_type_uint128;
109 case SPU_SRR0_REGNUM:
110 return builtin_type_uint32;
112 case SPU_LSLR_REGNUM:
113 return builtin_type_uint32;
115 case SPU_DECR_REGNUM:
116 return builtin_type_uint32;
118 case SPU_DECR_STATUS_REGNUM:
119 return builtin_type_uint32;
122 internal_error (__FILE__, __LINE__, "invalid regnum");
126 /* Pseudo registers for preferred slots - stack pointer. */
129 spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
136 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
137 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
138 memset (reg, 0, sizeof reg);
139 target_read (¤t_target, TARGET_OBJECT_SPU, annex,
142 store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
146 spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
147 int regnum, gdb_byte *buf)
156 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
157 memcpy (buf, reg, 4);
160 case SPU_FPSCR_REGNUM:
161 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
162 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
163 target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
166 case SPU_SRR0_REGNUM:
167 spu_pseudo_register_read_spu (regcache, "srr0", buf);
170 case SPU_LSLR_REGNUM:
171 spu_pseudo_register_read_spu (regcache, "lslr", buf);
174 case SPU_DECR_REGNUM:
175 spu_pseudo_register_read_spu (regcache, "decr", buf);
178 case SPU_DECR_STATUS_REGNUM:
179 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
183 internal_error (__FILE__, __LINE__, _("invalid regnum"));
188 spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
195 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
196 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
197 xsnprintf (reg, sizeof reg, "0x%s",
198 phex_nz (extract_unsigned_integer (buf, 4), 4));
199 target_write (¤t_target, TARGET_OBJECT_SPU, annex,
200 reg, 0, strlen (reg));
204 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
205 int regnum, const gdb_byte *buf)
214 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
215 memcpy (reg, buf, 4);
216 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
219 case SPU_FPSCR_REGNUM:
220 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
221 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
222 target_write (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
225 case SPU_SRR0_REGNUM:
226 spu_pseudo_register_write_spu (regcache, "srr0", buf);
229 case SPU_LSLR_REGNUM:
230 spu_pseudo_register_write_spu (regcache, "lslr", buf);
233 case SPU_DECR_REGNUM:
234 spu_pseudo_register_write_spu (regcache, "decr", buf);
237 case SPU_DECR_STATUS_REGNUM:
238 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
242 internal_error (__FILE__, __LINE__, _("invalid regnum"));
246 /* Value conversion -- access scalar values at the preferred slot. */
248 static struct value *
249 spu_value_from_register (struct type *type, int regnum,
250 struct frame_info *frame)
252 struct value *value = default_value_from_register (type, regnum, frame);
253 int len = TYPE_LENGTH (type);
255 if (regnum < SPU_NUM_GPRS && len < 16)
257 int preferred_slot = len < 4 ? 4 - len : 0;
258 set_value_offset (value, preferred_slot);
264 /* Register groups. */
267 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
268 struct reggroup *group)
270 /* Registers displayed via 'info regs'. */
271 if (group == general_reggroup)
274 /* Registers displayed via 'info float'. */
275 if (group == float_reggroup)
278 /* Registers that need to be saved/restored in order to
279 push or pop frames. */
280 if (group == save_reggroup || group == restore_reggroup)
283 return default_register_reggroup_p (gdbarch, regnum, group);
287 /* Decoding SPU instructions. */
324 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
326 if ((insn >> 21) == op)
329 *ra = (insn >> 7) & 127;
330 *rb = (insn >> 14) & 127;
338 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
340 if ((insn >> 28) == op)
342 *rt = (insn >> 21) & 127;
343 *ra = (insn >> 7) & 127;
344 *rb = (insn >> 14) & 127;
353 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
355 if ((insn >> 21) == op)
358 *ra = (insn >> 7) & 127;
359 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
367 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
369 if ((insn >> 24) == op)
372 *ra = (insn >> 7) & 127;
373 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
381 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
383 if ((insn >> 23) == op)
386 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
394 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
396 if ((insn >> 25) == op)
399 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
407 is_branch (unsigned int insn, int *offset, int *reg)
411 if (is_ri16 (insn, op_br, &rt, &i16)
412 || is_ri16 (insn, op_brsl, &rt, &i16)
413 || is_ri16 (insn, op_brnz, &rt, &i16)
414 || is_ri16 (insn, op_brz, &rt, &i16)
415 || is_ri16 (insn, op_brhnz, &rt, &i16)
416 || is_ri16 (insn, op_brhz, &rt, &i16))
418 *reg = SPU_PC_REGNUM;
423 if (is_ri16 (insn, op_bra, &rt, &i16)
424 || is_ri16 (insn, op_brasl, &rt, &i16))
431 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
432 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
433 || is_ri7 (insn, op_biz, &rt, reg, &i7)
434 || is_ri7 (insn, op_binz, &rt, reg, &i7)
435 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
436 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
446 /* Prolog parsing. */
448 struct spu_prologue_data
450 /* Stack frame size. -1 if analysis was unsuccessful. */
453 /* How to find the CFA. The CFA is equal to SP at function entry. */
457 /* Offset relative to CFA where a register is saved. -1 if invalid. */
458 int reg_offset[SPU_NUM_GPRS];
462 spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
463 struct spu_prologue_data *data)
468 int reg_immed[SPU_NUM_GPRS];
470 CORE_ADDR prolog_pc = start_pc;
475 /* Initialize DATA to default values. */
478 data->cfa_reg = SPU_RAW_SP_REGNUM;
479 data->cfa_offset = 0;
481 for (i = 0; i < SPU_NUM_GPRS; i++)
482 data->reg_offset[i] = -1;
484 /* Set up REG_IMMED array. This is non-zero for a register if we know its
485 preferred slot currently holds this immediate value. */
486 for (i = 0; i < SPU_NUM_GPRS; i++)
489 /* Scan instructions until the first branch.
491 The following instructions are important prolog components:
493 - The first instruction to set up the stack pointer.
494 - The first instruction to set up the frame pointer.
495 - The first instruction to save the link register.
497 We return the instruction after the latest of these three,
498 or the incoming PC if none is found. The first instruction
499 to set up the stack pointer also defines the frame size.
501 Note that instructions saving incoming arguments to their stack
502 slots are not counted as important, because they are hard to
503 identify with certainty. This should not matter much, because
504 arguments are relevant only in code compiled with debug data,
505 and in such code the GDB core will advance until the first source
506 line anyway, using SAL data.
508 For purposes of stack unwinding, we analyze the following types
509 of instructions in addition:
511 - Any instruction adding to the current frame pointer.
512 - Any instruction loading an immediate constant into a register.
513 - Any instruction storing a register onto the stack.
515 These are used to compute the CFA and REG_OFFSET output. */
517 for (pc = start_pc; pc < end_pc; pc += 4)
520 int rt, ra, rb, rc, immed;
522 if (target_read_memory (pc, buf, 4))
524 insn = extract_unsigned_integer (buf, 4);
526 /* AI is the typical instruction to set up a stack frame.
527 It is also used to initialize the frame pointer. */
528 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
530 if (rt == data->cfa_reg && ra == data->cfa_reg)
531 data->cfa_offset -= immed;
533 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
541 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
547 data->cfa_reg = SPU_FP_REGNUM;
548 data->cfa_offset -= immed;
552 /* A is used to set up stack frames of size >= 512 bytes.
553 If we have tracked the contents of the addend register,
554 we can handle this as well. */
555 else if (is_rr (insn, op_a, &rt, &ra, &rb))
557 if (rt == data->cfa_reg && ra == data->cfa_reg)
559 if (reg_immed[rb] != 0)
560 data->cfa_offset -= reg_immed[rb];
562 data->cfa_reg = -1; /* We don't know the CFA any more. */
565 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
571 if (reg_immed[rb] != 0)
572 data->size = -reg_immed[rb];
576 /* We need to track IL and ILA used to load immediate constants
577 in case they are later used as input to an A instruction. */
578 else if (is_ri16 (insn, op_il, &rt, &immed))
580 reg_immed[rt] = immed;
582 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
586 else if (is_ri18 (insn, op_ila, &rt, &immed))
588 reg_immed[rt] = immed & 0x3ffff;
590 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
594 /* STQD is used to save registers to the stack. */
595 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
597 if (ra == data->cfa_reg)
598 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
600 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
608 /* _start uses SELB to set up the stack pointer. */
609 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
611 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
615 /* We terminate if we find a branch. */
616 else if (is_branch (insn, &immed, &ra))
621 /* If we successfully parsed until here, and didn't find any instruction
622 modifying SP, we assume we have a frameless function. */
626 /* Return cooked instead of raw SP. */
627 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
628 data->cfa_reg = SPU_SP_REGNUM;
633 /* Return the first instruction after the prologue starting at PC. */
635 spu_skip_prologue (CORE_ADDR pc)
637 struct spu_prologue_data data;
638 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
641 /* Return the frame pointer in use at address PC. */
643 spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset)
645 struct spu_prologue_data data;
646 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
648 if (data.size != -1 && data.cfa_reg != -1)
650 /* The 'frame pointer' address is CFA minus frame size. */
652 *offset = data.cfa_offset - data.size;
656 /* ??? We don't really know ... */
657 *reg = SPU_SP_REGNUM;
662 /* Return true if we are in the function's epilogue, i.e. after the
663 instruction that destroyed the function's stack frame.
665 1) scan forward from the point of execution:
666 a) If you find an instruction that modifies the stack pointer
667 or transfers control (except a return), execution is not in
669 b) Stop scanning if you find a return instruction or reach the
670 end of the function or reach the hard limit for the size of
672 2) scan backward from the point of execution:
673 a) If you find an instruction that modifies the stack pointer,
674 execution *is* in an epilogue, return.
675 b) Stop scanning if you reach an instruction that transfers
676 control or the beginning of the function or reach the hard
677 limit for the size of an epilogue. */
680 spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
682 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
685 int rt, ra, rb, rc, immed;
687 /* Find the search limits based on function boundaries and hard limit.
688 We assume the epilogue can be up to 64 instructions long. */
690 const int spu_max_epilogue_size = 64 * 4;
692 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
695 if (pc - func_start < spu_max_epilogue_size)
696 epilogue_start = func_start;
698 epilogue_start = pc - spu_max_epilogue_size;
700 if (func_end - pc < spu_max_epilogue_size)
701 epilogue_end = func_end;
703 epilogue_end = pc + spu_max_epilogue_size;
705 /* Scan forward until next 'bi $0'. */
707 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
709 if (target_read_memory (scan_pc, buf, 4))
711 insn = extract_unsigned_integer (buf, 4);
713 if (is_branch (insn, &immed, &ra))
715 if (immed == 0 && ra == SPU_LR_REGNUM)
721 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
722 || is_rr (insn, op_a, &rt, &ra, &rb)
723 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
725 if (rt == SPU_RAW_SP_REGNUM)
730 if (scan_pc >= epilogue_end)
733 /* Scan backward until adjustment to stack pointer (R1). */
735 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
737 if (target_read_memory (scan_pc, buf, 4))
739 insn = extract_unsigned_integer (buf, 4);
741 if (is_branch (insn, &immed, &ra))
744 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
745 || is_rr (insn, op_a, &rt, &ra, &rb)
746 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
748 if (rt == SPU_RAW_SP_REGNUM)
757 /* Normal stack frames. */
759 struct spu_unwind_cache
762 CORE_ADDR frame_base;
763 CORE_ADDR local_base;
765 struct trad_frame_saved_reg *saved_regs;
768 static struct spu_unwind_cache *
769 spu_frame_unwind_cache (struct frame_info *next_frame,
770 void **this_prologue_cache)
772 struct spu_unwind_cache *info;
773 struct spu_prologue_data data;
776 if (*this_prologue_cache)
777 return *this_prologue_cache;
779 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
780 *this_prologue_cache = info;
781 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
782 info->frame_base = 0;
783 info->local_base = 0;
785 /* Find the start of the current function, and analyze its prologue. */
786 info->func = frame_func_unwind (next_frame, NORMAL_FRAME);
789 /* Fall back to using the current PC as frame ID. */
790 info->func = frame_pc_unwind (next_frame);
794 spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data);
797 /* If successful, use prologue analysis data. */
798 if (data.size != -1 && data.cfa_reg != -1)
803 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
804 frame_unwind_register (next_frame, data.cfa_reg, buf);
805 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
807 /* Call-saved register slots. */
808 for (i = 0; i < SPU_NUM_GPRS; i++)
809 if (i == SPU_LR_REGNUM
810 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
811 if (data.reg_offset[i] != -1)
812 info->saved_regs[i].addr = cfa - data.reg_offset[i];
815 info->frame_base = cfa;
816 info->local_base = cfa - data.size;
819 /* Otherwise, fall back to reading the backchain link. */
822 CORE_ADDR reg, backchain;
824 /* Get the backchain. */
825 reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
826 backchain = read_memory_unsigned_integer (reg, 4);
828 /* A zero backchain terminates the frame chain. Also, sanity
829 check against the local store size limit. */
830 if (backchain != 0 && backchain < SPU_LS_SIZE)
832 /* Assume the link register is saved into its slot. */
833 if (backchain + 16 < SPU_LS_SIZE)
834 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
837 info->frame_base = backchain;
838 info->local_base = reg;
842 /* The previous SP is equal to the CFA. */
843 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
845 /* Read full contents of the unwound link register in order to
846 be able to determine the return address. */
847 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
848 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
850 frame_unwind_register (next_frame, SPU_LR_REGNUM, buf);
852 /* Normally, the return address is contained in the slot 0 of the
853 link register, and slots 1-3 are zero. For an overlay return,
854 slot 0 contains the address of the overlay manager return stub,
855 slot 1 contains the partition number of the overlay section to
856 be returned to, and slot 2 contains the return address within
857 that section. Return the latter address in that case. */
858 if (extract_unsigned_integer (buf + 8, 4) != 0)
859 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
860 extract_unsigned_integer (buf + 8, 4));
862 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
863 extract_unsigned_integer (buf, 4));
869 spu_frame_this_id (struct frame_info *next_frame,
870 void **this_prologue_cache, struct frame_id *this_id)
872 struct spu_unwind_cache *info =
873 spu_frame_unwind_cache (next_frame, this_prologue_cache);
875 if (info->frame_base == 0)
878 *this_id = frame_id_build (info->frame_base, info->func);
882 spu_frame_prev_register (struct frame_info *next_frame,
883 void **this_prologue_cache,
884 int regnum, int *optimizedp,
885 enum lval_type *lvalp, CORE_ADDR * addrp,
886 int *realnump, gdb_byte *bufferp)
888 struct spu_unwind_cache *info
889 = spu_frame_unwind_cache (next_frame, this_prologue_cache);
891 /* Special-case the stack pointer. */
892 if (regnum == SPU_RAW_SP_REGNUM)
893 regnum = SPU_SP_REGNUM;
895 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
896 optimizedp, lvalp, addrp, realnump, bufferp);
899 static const struct frame_unwind spu_frame_unwind = {
902 spu_frame_prev_register
905 const struct frame_unwind *
906 spu_frame_sniffer (struct frame_info *next_frame)
908 return &spu_frame_unwind;
912 spu_frame_base_address (struct frame_info *next_frame, void **this_cache)
914 struct spu_unwind_cache *info
915 = spu_frame_unwind_cache (next_frame, this_cache);
916 return info->local_base;
919 static const struct frame_base spu_frame_base = {
921 spu_frame_base_address,
922 spu_frame_base_address,
923 spu_frame_base_address
927 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
929 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
930 /* Mask off interrupt enable bit. */
935 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
937 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
941 spu_read_pc (ptid_t ptid)
943 CORE_ADDR pc = read_register_pid (SPU_PC_REGNUM, ptid);
944 /* Mask off interrupt enable bit. */
949 spu_write_pc (CORE_ADDR pc, ptid_t ptid)
951 /* Keep interrupt enabled state unchanged. */
952 CORE_ADDR old_pc = read_register_pid (SPU_PC_REGNUM, ptid);
953 write_register_pid (SPU_PC_REGNUM, (pc & -4) | (old_pc & 3), ptid);
957 /* Function calling convention. */
960 spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
966 spu_scalar_value_p (struct type *type)
968 switch (TYPE_CODE (type))
972 case TYPE_CODE_RANGE:
977 return TYPE_LENGTH (type) <= 16;
985 spu_value_to_regcache (struct regcache *regcache, int regnum,
986 struct type *type, const gdb_byte *in)
988 int len = TYPE_LENGTH (type);
990 if (spu_scalar_value_p (type))
992 int preferred_slot = len < 4 ? 4 - len : 0;
993 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
999 regcache_cooked_write (regcache, regnum++, in);
1005 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1010 spu_regcache_to_value (struct regcache *regcache, int regnum,
1011 struct type *type, gdb_byte *out)
1013 int len = TYPE_LENGTH (type);
1015 if (spu_scalar_value_p (type))
1017 int preferred_slot = len < 4 ? 4 - len : 0;
1018 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1024 regcache_cooked_read (regcache, regnum++, out);
1030 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1035 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1036 struct regcache *regcache, CORE_ADDR bp_addr,
1037 int nargs, struct value **args, CORE_ADDR sp,
1038 int struct_return, CORE_ADDR struct_addr)
1041 int regnum = SPU_ARG1_REGNUM;
1045 /* Set the return address. */
1046 memset (buf, 0, sizeof buf);
1047 store_unsigned_integer (buf, 4, bp_addr);
1048 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1050 /* If STRUCT_RETURN is true, then the struct return address (in
1051 STRUCT_ADDR) will consume the first argument-passing register.
1052 Both adjust the register count and store that value. */
1055 memset (buf, 0, sizeof buf);
1056 store_unsigned_integer (buf, 4, struct_addr);
1057 regcache_cooked_write (regcache, regnum++, buf);
1060 /* Fill in argument registers. */
1061 for (i = 0; i < nargs; i++)
1063 struct value *arg = args[i];
1064 struct type *type = check_typedef (value_type (arg));
1065 const gdb_byte *contents = value_contents (arg);
1066 int len = TYPE_LENGTH (type);
1067 int n_regs = align_up (len, 16) / 16;
1069 /* If the argument doesn't wholly fit into registers, it and
1070 all subsequent arguments go to the stack. */
1071 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1077 spu_value_to_regcache (regcache, regnum, type, contents);
1081 /* Overflow arguments go to the stack. */
1082 if (stack_arg != -1)
1086 /* Allocate all required stack size. */
1087 for (i = stack_arg; i < nargs; i++)
1089 struct type *type = check_typedef (value_type (args[i]));
1090 sp -= align_up (TYPE_LENGTH (type), 16);
1093 /* Fill in stack arguments. */
1095 for (i = stack_arg; i < nargs; i++)
1097 struct value *arg = args[i];
1098 struct type *type = check_typedef (value_type (arg));
1099 int len = TYPE_LENGTH (type);
1102 if (spu_scalar_value_p (type))
1103 preferred_slot = len < 4 ? 4 - len : 0;
1107 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1108 ap += align_up (TYPE_LENGTH (type), 16);
1112 /* Allocate stack frame header. */
1115 /* Store stack back chain. */
1116 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1117 target_write_memory (sp, buf, 16);
1119 /* Finally, update the SP register. */
1120 regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp);
1125 static struct frame_id
1126 spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1128 return frame_id_build (spu_unwind_sp (gdbarch, next_frame),
1129 spu_unwind_pc (gdbarch, next_frame));
1132 /* Function return value access. */
1134 static enum return_value_convention
1135 spu_return_value (struct gdbarch *gdbarch, struct type *type,
1136 struct regcache *regcache, gdb_byte *out, const gdb_byte *in)
1138 enum return_value_convention rvc;
1140 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1141 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1143 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1149 case RETURN_VALUE_REGISTER_CONVENTION:
1150 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1153 case RETURN_VALUE_STRUCT_CONVENTION:
1154 error ("Cannot set function return value.");
1162 case RETURN_VALUE_REGISTER_CONVENTION:
1163 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1166 case RETURN_VALUE_STRUCT_CONVENTION:
1167 error ("Function return value unknown.");
1178 static const gdb_byte *
1179 spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
1181 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1183 *lenptr = sizeof breakpoint;
1188 /* Software single-stepping support. */
1191 spu_software_single_step (struct regcache *regcache)
1193 CORE_ADDR pc, next_pc;
1198 regcache_cooked_read (regcache, SPU_PC_REGNUM, buf);
1199 /* Mask off interrupt enable bit. */
1200 pc = extract_unsigned_integer (buf, 4) & -4;
1202 if (target_read_memory (pc, buf, 4))
1204 insn = extract_unsigned_integer (buf, 4);
1206 /* Next sequential instruction is at PC + 4, except if the current
1207 instruction is a PPE-assisted call, in which case it is at PC + 8.
1208 Wrap around LS limit to be on the safe side. */
1209 if ((insn & 0xffffff00) == 0x00002100)
1210 next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1212 next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
1214 insert_single_step_breakpoint (next_pc);
1216 if (is_branch (insn, &offset, ®))
1218 CORE_ADDR target = offset;
1220 if (reg == SPU_PC_REGNUM)
1224 regcache_cooked_read_part (regcache, reg, 0, 4, buf);
1225 target += extract_unsigned_integer (buf, 4) & -4;
1228 target = target & (SPU_LS_SIZE - 1);
1229 if (target != next_pc)
1230 insert_single_step_breakpoint (target);
1236 /* Target overlays for the SPU overlay manager.
1238 See the documentation of simple_overlay_update for how the
1239 interface is supposed to work.
1241 Data structures used by the overlay manager:
1249 } _ovly_table[]; -- one entry per overlay section
1251 struct ovly_buf_table
1254 } _ovly_buf_table[]; -- one entry per overlay buffer
1256 _ovly_table should never change.
1258 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1259 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1260 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1262 mapped is an index into _ovly_table. Both the mapped and buf indices start
1263 from one to reference the first entry in their respective tables. */
1265 /* Using the per-objfile private data mechanism, we store for each
1266 objfile an array of "struct spu_overlay_table" structures, one
1267 for each obj_section of the objfile. This structure holds two
1268 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1269 is *not* an overlay section. If it is non-zero, it represents
1270 a target address. The overlay section is mapped iff the target
1271 integer at this location equals MAPPED_VAL. */
1273 static const struct objfile_data *spu_overlay_data;
1275 struct spu_overlay_table
1277 CORE_ADDR mapped_ptr;
1278 CORE_ADDR mapped_val;
1281 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1282 the _ovly_table data structure from the target and initialize the
1283 spu_overlay_table data structure from it. */
1284 static struct spu_overlay_table *
1285 spu_get_overlay_table (struct objfile *objfile)
1287 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1288 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1289 unsigned ovly_table_size, ovly_buf_table_size;
1290 struct spu_overlay_table *tbl;
1291 struct obj_section *osect;
1295 tbl = objfile_data (objfile, spu_overlay_data);
1299 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1300 if (!ovly_table_msym)
1303 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1304 if (!ovly_buf_table_msym)
1307 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1308 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1310 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1311 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1313 ovly_table = xmalloc (ovly_table_size);
1314 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1316 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1317 objfile->sections_end - objfile->sections,
1318 struct spu_overlay_table);
1320 for (i = 0; i < ovly_table_size / 16; i++)
1322 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1323 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1324 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1325 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1327 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1330 ALL_OBJFILE_OSECTIONS (objfile, osect)
1331 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1332 && pos == osect->the_bfd_section->filepos)
1334 int ndx = osect - objfile->sections;
1335 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1336 tbl[ndx].mapped_val = i + 1;
1342 set_objfile_data (objfile, spu_overlay_data, tbl);
1346 /* Read _ovly_buf_table entry from the target to dermine whether
1347 OSECT is currently mapped, and update the mapped state. */
1349 spu_overlay_update_osect (struct obj_section *osect)
1351 struct spu_overlay_table *ovly_table;
1354 ovly_table = spu_get_overlay_table (osect->objfile);
1358 ovly_table += osect - osect->objfile->sections;
1359 if (ovly_table->mapped_ptr == 0)
1362 val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1363 osect->ovly_mapped = (val == ovly_table->mapped_val);
1366 /* If OSECT is NULL, then update all sections' mapped state.
1367 If OSECT is non-NULL, then update only OSECT's mapped state. */
1369 spu_overlay_update (struct obj_section *osect)
1371 /* Just one section. */
1373 spu_overlay_update_osect (osect);
1378 struct objfile *objfile;
1380 ALL_OBJSECTIONS (objfile, osect)
1381 if (section_is_overlay (osect->the_bfd_section))
1382 spu_overlay_update_osect (osect);
1386 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1387 If there is one, go through all sections and make sure for non-
1388 overlay sections LMA equals VMA, while for overlay sections LMA
1389 is larger than local store size. */
1391 spu_overlay_new_objfile (struct objfile *objfile)
1393 struct spu_overlay_table *ovly_table;
1394 struct obj_section *osect;
1396 /* If we've already touched this file, do nothing. */
1397 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1400 /* Check if this objfile has overlays. */
1401 ovly_table = spu_get_overlay_table (objfile);
1405 /* Now go and fiddle with all the LMAs. */
1406 ALL_OBJFILE_OSECTIONS (objfile, osect)
1408 bfd *obfd = objfile->obfd;
1409 asection *bsect = osect->the_bfd_section;
1410 int ndx = osect - objfile->sections;
1412 if (ovly_table[ndx].mapped_ptr == 0)
1413 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1415 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1420 /* "info spu" commands. */
1423 info_spu_event_command (char *args, int from_tty)
1425 struct frame_info *frame = get_selected_frame (NULL);
1426 ULONGEST event_status = 0;
1427 ULONGEST event_mask = 0;
1428 struct cleanup *chain;
1434 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1436 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1437 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1438 buf, 0, sizeof buf);
1440 error (_("Could not read event_status."));
1441 event_status = strtoulst (buf, NULL, 16);
1443 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1444 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1445 buf, 0, sizeof buf);
1447 error (_("Could not read event_mask."));
1448 event_mask = strtoulst (buf, NULL, 16);
1450 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1452 if (ui_out_is_mi_like_p (uiout))
1454 ui_out_field_fmt (uiout, "event_status",
1455 "0x%s", phex_nz (event_status, 4));
1456 ui_out_field_fmt (uiout, "event_mask",
1457 "0x%s", phex_nz (event_mask, 4));
1461 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1462 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1465 do_cleanups (chain);
1469 info_spu_signal_command (char *args, int from_tty)
1471 struct frame_info *frame = get_selected_frame (NULL);
1472 ULONGEST signal1 = 0;
1473 ULONGEST signal1_type = 0;
1474 int signal1_pending = 0;
1475 ULONGEST signal2 = 0;
1476 ULONGEST signal2_type = 0;
1477 int signal2_pending = 0;
1478 struct cleanup *chain;
1484 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1486 xsnprintf (annex, sizeof annex, "%d/signal1", id);
1487 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1489 error (_("Could not read signal1."));
1492 signal1 = extract_unsigned_integer (buf, 4);
1493 signal1_pending = 1;
1496 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1497 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1498 buf, 0, sizeof buf);
1500 error (_("Could not read signal1_type."));
1501 signal1_type = strtoulst (buf, NULL, 16);
1503 xsnprintf (annex, sizeof annex, "%d/signal2", id);
1504 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1506 error (_("Could not read signal2."));
1509 signal2 = extract_unsigned_integer (buf, 4);
1510 signal2_pending = 1;
1513 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1514 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1515 buf, 0, sizeof buf);
1517 error (_("Could not read signal2_type."));
1518 signal2_type = strtoulst (buf, NULL, 16);
1520 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1522 if (ui_out_is_mi_like_p (uiout))
1524 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1525 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1526 ui_out_field_int (uiout, "signal1_type", signal1_type);
1527 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1528 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1529 ui_out_field_int (uiout, "signal2_type", signal2_type);
1533 if (signal1_pending)
1534 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1536 printf_filtered (_("Signal 1 not pending "));
1539 printf_filtered (_("(Type Overwrite)\n"));
1541 printf_filtered (_("(Type Or)\n"));
1543 if (signal2_pending)
1544 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1546 printf_filtered (_("Signal 2 not pending "));
1549 printf_filtered (_("(Type Overwrite)\n"));
1551 printf_filtered (_("(Type Or)\n"));
1554 do_cleanups (chain);
1558 info_spu_mailbox_list (gdb_byte *buf, int nr,
1559 const char *field, const char *msg)
1561 struct cleanup *chain;
1567 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1569 ui_out_table_header (uiout, 32, ui_left, field, msg);
1570 ui_out_table_body (uiout);
1572 for (i = 0; i < nr; i++)
1574 struct cleanup *val_chain;
1576 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1577 val = extract_unsigned_integer (buf + 4*i, 4);
1578 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1579 do_cleanups (val_chain);
1581 if (!ui_out_is_mi_like_p (uiout))
1582 printf_filtered ("\n");
1585 do_cleanups (chain);
1589 info_spu_mailbox_command (char *args, int from_tty)
1591 struct frame_info *frame = get_selected_frame (NULL);
1592 struct cleanup *chain;
1598 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1600 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1602 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1603 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1604 buf, 0, sizeof buf);
1606 error (_("Could not read mbox_info."));
1608 info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1610 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1611 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1612 buf, 0, sizeof buf);
1614 error (_("Could not read ibox_info."));
1616 info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1618 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1619 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1620 buf, 0, sizeof buf);
1622 error (_("Could not read wbox_info."));
1624 info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1626 do_cleanups (chain);
1630 spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1632 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1633 return (word >> (63 - last)) & mask;
1637 info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1639 static char *spu_mfc_opcode[256] =
1641 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1642 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1643 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1644 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1645 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1646 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1647 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1648 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1649 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1650 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1651 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1652 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1653 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1654 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1655 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1656 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1657 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1658 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1659 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1660 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1661 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1662 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1663 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1664 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1665 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1666 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1667 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1668 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1669 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1670 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1671 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1672 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1675 struct cleanup *chain;
1678 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1680 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1681 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1682 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1683 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1684 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1685 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1686 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1687 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1688 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1689 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1691 ui_out_table_body (uiout);
1693 for (i = 0; i < nr; i++)
1695 struct cleanup *cmd_chain;
1696 ULONGEST mfc_cq_dw0;
1697 ULONGEST mfc_cq_dw1;
1698 ULONGEST mfc_cq_dw2;
1699 ULONGEST mfc_cq_dw3;
1700 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1701 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1703 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1705 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1706 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1708 mfc_cq_dw0 = extract_unsigned_integer (buf + 32*i, 8);
1709 mfc_cq_dw1 = extract_unsigned_integer (buf + 32*i + 8, 8);
1710 mfc_cq_dw2 = extract_unsigned_integer (buf + 32*i + 16, 8);
1711 mfc_cq_dw3 = extract_unsigned_integer (buf + 32*i + 24, 8);
1713 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1714 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1715 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1716 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1717 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1718 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1719 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1721 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1722 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1724 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1725 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1726 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1727 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1728 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1729 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1731 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1733 if (spu_mfc_opcode[mfc_cmd_opcode])
1734 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1736 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1738 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1739 ui_out_field_int (uiout, "tid", tclass_id);
1740 ui_out_field_int (uiout, "rid", rclass_id);
1743 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1745 ui_out_field_skip (uiout, "ea");
1747 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1749 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1751 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1755 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1756 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1760 ui_out_field_skip (uiout, "lstaddr");
1761 ui_out_field_skip (uiout, "lstsize");
1765 ui_out_field_string (uiout, "error_p", "*");
1767 ui_out_field_skip (uiout, "error_p");
1769 do_cleanups (cmd_chain);
1771 if (!ui_out_is_mi_like_p (uiout))
1772 printf_filtered ("\n");
1775 do_cleanups (chain);
1779 info_spu_dma_command (char *args, int from_tty)
1781 struct frame_info *frame = get_selected_frame (NULL);
1782 ULONGEST dma_info_type;
1783 ULONGEST dma_info_mask;
1784 ULONGEST dma_info_status;
1785 ULONGEST dma_info_stall_and_notify;
1786 ULONGEST dma_info_atomic_command_status;
1787 struct cleanup *chain;
1793 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1795 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1796 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1797 buf, 0, 40 + 16 * 32);
1799 error (_("Could not read dma_info."));
1801 dma_info_type = extract_unsigned_integer (buf, 8);
1802 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1803 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1804 dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1805 dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1807 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1809 if (ui_out_is_mi_like_p (uiout))
1811 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1812 phex_nz (dma_info_type, 4));
1813 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1814 phex_nz (dma_info_mask, 4));
1815 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1816 phex_nz (dma_info_status, 4));
1817 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1818 phex_nz (dma_info_stall_and_notify, 4));
1819 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1820 phex_nz (dma_info_atomic_command_status, 4));
1824 const char *query_msg;
1826 switch (dma_info_type)
1828 case 0: query_msg = _("no query pending"); break;
1829 case 1: query_msg = _("'any' query pending"); break;
1830 case 2: query_msg = _("'all' query pending"); break;
1831 default: query_msg = _("undefined query type"); break;
1834 printf_filtered (_("Tag-Group Status 0x%s\n"),
1835 phex (dma_info_status, 4));
1836 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1837 phex (dma_info_mask, 4), query_msg);
1838 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1839 phex (dma_info_stall_and_notify, 4));
1840 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1841 phex (dma_info_atomic_command_status, 4));
1842 printf_filtered ("\n");
1845 info_spu_dma_cmdlist (buf + 40, 16);
1846 do_cleanups (chain);
1850 info_spu_proxydma_command (char *args, int from_tty)
1852 struct frame_info *frame = get_selected_frame (NULL);
1853 ULONGEST dma_info_type;
1854 ULONGEST dma_info_mask;
1855 ULONGEST dma_info_status;
1856 struct cleanup *chain;
1862 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1864 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
1865 len = target_read (¤t_target, TARGET_OBJECT_SPU, annex,
1866 buf, 0, 24 + 8 * 32);
1868 error (_("Could not read proxydma_info."));
1870 dma_info_type = extract_unsigned_integer (buf, 8);
1871 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1872 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1874 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
1876 if (ui_out_is_mi_like_p (uiout))
1878 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
1879 phex_nz (dma_info_type, 4));
1880 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
1881 phex_nz (dma_info_mask, 4));
1882 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
1883 phex_nz (dma_info_status, 4));
1887 const char *query_msg;
1889 switch (dma_info_type)
1891 case 0: query_msg = _("no query pending"); break;
1892 case 1: query_msg = _("'any' query pending"); break;
1893 case 2: query_msg = _("'all' query pending"); break;
1894 default: query_msg = _("undefined query type"); break;
1897 printf_filtered (_("Tag-Group Status 0x%s\n"),
1898 phex (dma_info_status, 4));
1899 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1900 phex (dma_info_mask, 4), query_msg);
1901 printf_filtered ("\n");
1904 info_spu_dma_cmdlist (buf + 24, 8);
1905 do_cleanups (chain);
1909 info_spu_command (char *args, int from_tty)
1911 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
1912 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
1916 /* Set up gdbarch struct. */
1918 static struct gdbarch *
1919 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1921 struct gdbarch *gdbarch;
1923 /* Find a candidate among the list of pre-declared architectures. */
1924 arches = gdbarch_list_lookup_by_info (arches, &info);
1926 return arches->gdbarch;
1929 if (info.bfd_arch_info->mach != bfd_mach_spu)
1932 /* Yes, create a new architecture. */
1933 gdbarch = gdbarch_alloc (&info, NULL);
1936 set_gdbarch_print_insn (gdbarch, print_insn_spu);
1939 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
1940 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
1941 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
1942 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
1943 set_gdbarch_read_pc (gdbarch, spu_read_pc);
1944 set_gdbarch_write_pc (gdbarch, spu_write_pc);
1945 set_gdbarch_register_name (gdbarch, spu_register_name);
1946 set_gdbarch_register_type (gdbarch, spu_register_type);
1947 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
1948 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
1949 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
1950 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
1953 set_gdbarch_char_signed (gdbarch, 0);
1954 set_gdbarch_ptr_bit (gdbarch, 32);
1955 set_gdbarch_addr_bit (gdbarch, 32);
1956 set_gdbarch_short_bit (gdbarch, 16);
1957 set_gdbarch_int_bit (gdbarch, 32);
1958 set_gdbarch_long_bit (gdbarch, 32);
1959 set_gdbarch_long_long_bit (gdbarch, 64);
1960 set_gdbarch_float_bit (gdbarch, 32);
1961 set_gdbarch_double_bit (gdbarch, 64);
1962 set_gdbarch_long_double_bit (gdbarch, 64);
1963 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1964 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
1965 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1967 /* Inferior function calls. */
1968 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1969 set_gdbarch_frame_align (gdbarch, spu_frame_align);
1970 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
1971 set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id);
1972 set_gdbarch_return_value (gdbarch, spu_return_value);
1974 /* Frame handling. */
1975 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1976 frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer);
1977 frame_base_set_default (gdbarch, &spu_frame_base);
1978 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
1979 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
1980 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
1981 set_gdbarch_frame_args_skip (gdbarch, 0);
1982 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
1983 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
1986 set_gdbarch_decr_pc_after_break (gdbarch, 4);
1987 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
1988 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
1989 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
1992 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
1997 /* Implement a SPU-specific vector type as replacement
1998 for __gdb_builtin_type_vec128. */
2000 spu_init_vector_type (void)
2004 type = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
2005 append_composite_type_field (type, "uint128", builtin_type_int128);
2006 append_composite_type_field (type, "v2_int64", builtin_type_v2_int64);
2007 append_composite_type_field (type, "v4_int32", builtin_type_v4_int32);
2008 append_composite_type_field (type, "v8_int16", builtin_type_v8_int16);
2009 append_composite_type_field (type, "v16_int8", builtin_type_v16_int8);
2010 append_composite_type_field (type, "v2_double", builtin_type_v2_double);
2011 append_composite_type_field (type, "v4_float", builtin_type_v4_float);
2013 TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR;
2014 TYPE_NAME (type) = "spu_builtin_type_vec128";
2015 spu_builtin_type_vec128 = type;
2019 _initialize_spu_tdep (void)
2021 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
2023 spu_init_vector_type ();
2025 /* Add ourselves to objfile event chain. */
2026 observer_attach_new_objfile (spu_overlay_new_objfile);
2027 spu_overlay_data = register_objfile_data ();
2029 /* Add root prefix command for all "info spu" commands. */
2030 add_prefix_cmd ("spu", class_info, info_spu_command,
2031 _("Various SPU specific commands."),
2032 &infospucmdlist, "info spu ", 0, &infolist);
2034 /* Add various "info spu" commands. */
2035 add_cmd ("event", class_info, info_spu_event_command,
2036 _("Display SPU event facility status.\n"),
2038 add_cmd ("signal", class_info, info_spu_signal_command,
2039 _("Display SPU signal notification facility status.\n"),
2041 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2042 _("Display SPU mailbox facility status.\n"),
2044 add_cmd ("dma", class_info, info_spu_dma_command,
2045 _("Display MFC DMA status.\n"),
2047 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2048 _("Display MFC Proxy-DMA status.\n"),