1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "gdb_string.h"
42 #include "sparc-tdep.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-recision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc, buf, sizeof (buf)))
106 for (i = 0; i < sizeof (buf); i++)
107 insn = (insn << 8) | buf[i];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc)
118 const unsigned long insn = sparc_fetch_instruction (pc);
120 return ((insn & 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (void)
157 struct target_ops *ops = ¤t_target;
161 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
165 /* We should have either an 32-bit or an 64-bit cookie. */
166 gdb_assert (len == 4 || len == 8);
168 return extract_unsigned_integer (buf, len);
172 /* The functions on this page are intended to be used to classify
173 function arguments. */
175 /* Check whether TYPE is "Integral or Pointer". */
178 sparc_integral_or_pointer_p (const struct type *type)
180 int len = TYPE_LENGTH (type);
182 switch (TYPE_CODE (type))
188 case TYPE_CODE_RANGE:
189 /* We have byte, half-word, word and extended-word/doubleword
190 integral types. The doubleword is an extension to the
191 original 32-bit ABI by the SCD 2.4.x. */
192 return (len == 1 || len == 2 || len == 4 || len == 8);
195 /* Allow either 32-bit or 64-bit pointers. */
196 return (len == 4 || len == 8);
204 /* Check whether TYPE is "Floating". */
207 sparc_floating_p (const struct type *type)
209 switch (TYPE_CODE (type))
213 int len = TYPE_LENGTH (type);
214 return (len == 4 || len == 8 || len == 16);
223 /* Check whether TYPE is "Structure or Union". */
226 sparc_structure_or_union_p (const struct type *type)
228 switch (TYPE_CODE (type))
230 case TYPE_CODE_STRUCT:
231 case TYPE_CODE_UNION:
240 /* Register information. */
242 static const char *sparc32_register_names[] =
244 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
245 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
246 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
247 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
249 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
250 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
251 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
252 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
254 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
257 /* Total number of registers. */
258 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
260 /* We provide the aliases %d0..%d30 for the floating registers as
261 "psuedo" registers. */
263 static const char *sparc32_pseudo_register_names[] =
265 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
266 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
269 /* Total number of pseudo registers. */
270 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
272 /* Return the name of register REGNUM. */
275 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
277 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
278 return sparc32_register_names[regnum];
280 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
281 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
286 /* Construct types for ISA-specific registers. */
289 sparc_psr_type (struct gdbarch *gdbarch)
291 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
293 if (!tdep->sparc_psr_type)
297 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4);
298 append_flags_type_flag (type, 5, "ET");
299 append_flags_type_flag (type, 6, "PS");
300 append_flags_type_flag (type, 7, "S");
301 append_flags_type_flag (type, 12, "EF");
302 append_flags_type_flag (type, 13, "EC");
304 tdep->sparc_psr_type = type;
307 return tdep->sparc_psr_type;
311 sparc_fsr_type (struct gdbarch *gdbarch)
313 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
315 if (!tdep->sparc_fsr_type)
319 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4);
320 append_flags_type_flag (type, 0, "NXA");
321 append_flags_type_flag (type, 1, "DZA");
322 append_flags_type_flag (type, 2, "UFA");
323 append_flags_type_flag (type, 3, "OFA");
324 append_flags_type_flag (type, 4, "NVA");
325 append_flags_type_flag (type, 5, "NXC");
326 append_flags_type_flag (type, 6, "DZC");
327 append_flags_type_flag (type, 7, "UFC");
328 append_flags_type_flag (type, 8, "OFC");
329 append_flags_type_flag (type, 9, "NVC");
330 append_flags_type_flag (type, 22, "NS");
331 append_flags_type_flag (type, 23, "NXM");
332 append_flags_type_flag (type, 24, "DZM");
333 append_flags_type_flag (type, 25, "UFM");
334 append_flags_type_flag (type, 26, "OFM");
335 append_flags_type_flag (type, 27, "NVM");
337 tdep->sparc_fsr_type = type;
340 return tdep->sparc_fsr_type;
343 /* Return the GDB type object for the "standard" data type of data in
347 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
349 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
350 return builtin_type (gdbarch)->builtin_float;
352 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
353 return builtin_type (gdbarch)->builtin_double;
355 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
356 return builtin_type (gdbarch)->builtin_data_ptr;
358 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
359 return builtin_type (gdbarch)->builtin_func_ptr;
361 if (regnum == SPARC32_PSR_REGNUM)
362 return sparc_psr_type (gdbarch);
364 if (regnum == SPARC32_FSR_REGNUM)
365 return sparc_fsr_type (gdbarch);
367 return builtin_type (gdbarch)->builtin_int32;
371 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
372 struct regcache *regcache,
373 int regnum, gdb_byte *buf)
375 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
377 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
378 regcache_raw_read (regcache, regnum, buf);
379 regcache_raw_read (regcache, regnum + 1, buf + 4);
383 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
384 struct regcache *regcache,
385 int regnum, const gdb_byte *buf)
387 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
389 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
390 regcache_raw_write (regcache, regnum, buf);
391 regcache_raw_write (regcache, regnum + 1, buf + 4);
396 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
398 struct value **args, int nargs,
399 struct type *value_type,
400 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
401 struct regcache *regcache)
406 if (using_struct_return (gdbarch, NULL, value_type))
410 /* This is an UNIMP instruction. */
411 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
412 write_memory (sp - 8, buf, 4);
420 sparc32_store_arguments (struct regcache *regcache, int nargs,
421 struct value **args, CORE_ADDR sp,
422 int struct_return, CORE_ADDR struct_addr)
424 struct gdbarch *gdbarch = get_regcache_arch (regcache);
425 /* Number of words in the "parameter array". */
426 int num_elements = 0;
430 for (i = 0; i < nargs; i++)
432 struct type *type = value_type (args[i]);
433 int len = TYPE_LENGTH (type);
435 if (sparc_structure_or_union_p (type)
436 || (sparc_floating_p (type) && len == 16))
438 /* Structure, Union and Quad-Precision Arguments. */
441 /* Use doubleword alignment for these values. That's always
442 correct, and wasting a few bytes shouldn't be a problem. */
445 write_memory (sp, value_contents (args[i]), len);
446 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
449 else if (sparc_floating_p (type))
451 /* Floating arguments. */
452 gdb_assert (len == 4 || len == 8);
453 num_elements += (len / 4);
457 /* Integral and pointer arguments. */
458 gdb_assert (sparc_integral_or_pointer_p (type));
461 args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
463 num_elements += ((len + 3) / 4);
467 /* Always allocate at least six words. */
468 sp -= max (6, num_elements) * 4;
470 /* The psABI says that "Software convention requires space for the
471 struct/union return value pointer, even if the word is unused." */
474 /* The psABI says that "Although software convention and the
475 operating system require every stack frame to be doubleword
479 for (i = 0; i < nargs; i++)
481 const bfd_byte *valbuf = value_contents (args[i]);
482 struct type *type = value_type (args[i]);
483 int len = TYPE_LENGTH (type);
485 gdb_assert (len == 4 || len == 8);
489 int regnum = SPARC_O0_REGNUM + element;
491 regcache_cooked_write (regcache, regnum, valbuf);
492 if (len > 4 && element < 5)
493 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
496 /* Always store the argument in memory. */
497 write_memory (sp + 4 + element * 4, valbuf, len);
501 gdb_assert (element == num_elements);
507 store_unsigned_integer (buf, 4, struct_addr);
508 write_memory (sp, buf, 4);
515 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
516 struct regcache *regcache, CORE_ADDR bp_addr,
517 int nargs, struct value **args, CORE_ADDR sp,
518 int struct_return, CORE_ADDR struct_addr)
520 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
522 /* Set return address. */
523 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
525 /* Set up function arguments. */
526 sp = sparc32_store_arguments (regcache, nargs, args, sp,
527 struct_return, struct_addr);
529 /* Allocate the 16-word window save area. */
532 /* Stack should be doubleword aligned at this point. */
533 gdb_assert (sp % 8 == 0);
535 /* Finally, update the stack pointer. */
536 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
542 /* Use the program counter to determine the contents and size of a
543 breakpoint instruction. Return a pointer to a string of bytes that
544 encode a breakpoint instruction, store the length of the string in
545 *LEN and optionally adjust *PC to point to the correct memory
546 location for inserting the breakpoint. */
548 static const gdb_byte *
549 sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
551 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
553 *len = sizeof (break_insn);
558 /* Allocate and initialize a frame cache. */
560 static struct sparc_frame_cache *
561 sparc_alloc_frame_cache (void)
563 struct sparc_frame_cache *cache;
566 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
572 /* Frameless until proven otherwise. */
573 cache->frameless_p = 1;
575 cache->struct_return_p = 0;
580 /* GCC generates several well-known sequences of instructions at the begining
581 of each function prologue when compiling with -fstack-check. If one of
582 such sequences starts at START_PC, then return the address of the
583 instruction immediately past this sequence. Otherwise, return START_PC. */
586 sparc_skip_stack_check (const CORE_ADDR start_pc)
588 CORE_ADDR pc = start_pc;
590 int offset_stack_checking_sequence = 0;
592 /* With GCC, all stack checking sequences begin with the same two
595 /* sethi <some immediate>,%g1 */
596 insn = sparc_fetch_instruction (pc);
598 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
601 /* sub %sp, %g1, %g1 */
602 insn = sparc_fetch_instruction (pc);
604 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
605 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
608 insn = sparc_fetch_instruction (pc);
611 /* First possible sequence:
612 [first two instructions above]
613 clr [%g1 - some immediate] */
615 /* clr [%g1 - some immediate] */
616 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
617 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
619 /* Valid stack-check sequence, return the new PC. */
623 /* Second possible sequence: A small number of probes.
624 [first two instructions above]
626 add %g1, -<some immediate>, %g1
628 [repeat the two instructions above any (small) number of times]
629 clr [%g1 - some immediate] */
632 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
633 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
637 /* add %g1, -<some immediate>, %g1 */
638 insn = sparc_fetch_instruction (pc);
640 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
641 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
645 insn = sparc_fetch_instruction (pc);
647 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
648 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
652 /* clr [%g1 - some immediate] */
653 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
654 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
657 /* We found a valid stack-check sequence, return the new PC. */
661 /* Third sequence: A probing loop.
662 [first two instructions above]
663 sethi <some immediate>, %g4
667 add %g1, -<some immediate>, %g1
670 clr [%g4 - some immediate] */
672 /* sethi <some immediate>, %g4 */
673 else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
675 /* sub %g1, %g4, %g4 */
676 insn = sparc_fetch_instruction (pc);
678 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
679 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
683 insn = sparc_fetch_instruction (pc);
685 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
686 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
690 insn = sparc_fetch_instruction (pc);
692 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
695 /* add %g1, -<some immediate>, %g1 */
696 insn = sparc_fetch_instruction (pc);
698 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
699 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
703 insn = sparc_fetch_instruction (pc);
705 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
709 insn = sparc_fetch_instruction (pc);
711 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
712 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
715 /* clr [%g4 - some immediate] */
716 insn = sparc_fetch_instruction (pc);
718 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
719 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
722 /* We found a valid stack-check sequence, return the new PC. */
726 /* No stack check code in our prologue, return the start_pc. */
731 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
732 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
734 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
739 pc = sparc_skip_stack_check (pc);
741 if (current_pc <= pc)
744 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
745 SPARC the linker usually defines a symbol (typically
746 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
747 This symbol makes us end up here with PC pointing at the start of
748 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
749 would do our normal prologue analysis, we would probably conclude
750 that we've got a frame when in reality we don't, since the
751 dynamic linker patches up the first PLT with some code that
752 starts with a SAVE instruction. Patch up PC such that it points
753 at the start of our PLT entry. */
754 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
755 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
757 insn = sparc_fetch_instruction (pc);
759 /* Recognize a SETHI insn and record its destination. */
760 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
765 insn = sparc_fetch_instruction (pc + 4);
768 /* Allow for an arithmetic operation on DEST or %g1. */
769 if (X_OP (insn) == 2 && X_I (insn)
770 && (X_RD (insn) == 1 || X_RD (insn) == dest))
774 insn = sparc_fetch_instruction (pc + 8);
777 /* Check for the SAVE instruction that sets up the frame. */
778 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
780 cache->frameless_p = 0;
781 return pc + offset + 4;
788 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
790 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
791 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
794 /* Return PC of first real instruction of the function starting at
798 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
800 struct symtab_and_line sal;
801 CORE_ADDR func_start, func_end;
802 struct sparc_frame_cache cache;
804 /* This is the preferred method, find the end of the prologue by
805 using the debugging information. */
806 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
808 sal = find_pc_line (func_start, 0);
810 if (sal.end < func_end
811 && start_pc <= sal.end)
815 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
817 /* The psABI says that "Although the first 6 words of arguments
818 reside in registers, the standard stack frame reserves space for
819 them.". It also suggests that a function may use that space to
820 "write incoming arguments 0 to 5" into that space, and that's
821 indeed what GCC seems to be doing. In that case GCC will
822 generate debug information that points to the stack slots instead
823 of the registers, so we should consider the instructions that
824 write out these incoming arguments onto the stack. Of course we
825 only need to do this if we have a stack frame. */
827 while (!cache.frameless_p)
829 unsigned long insn = sparc_fetch_instruction (start_pc);
831 /* Recognize instructions that store incoming arguments in
832 %i0...%i5 into the corresponding stack slot. */
833 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
834 && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
835 && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
849 struct sparc_frame_cache *
850 sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
852 struct sparc_frame_cache *cache;
857 cache = sparc_alloc_frame_cache ();
860 cache->pc = get_frame_func (this_frame);
862 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
863 get_frame_pc (this_frame), cache);
865 if (cache->frameless_p)
867 /* This function is frameless, so %fp (%i6) holds the frame
868 pointer for our calling frame. Use %sp (%o6) as this frame's
871 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
875 /* For normal frames, %fp (%i6) holds the frame pointer, the
876 base address for the current stack frame. */
878 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
888 sparc32_struct_return_from_sym (struct symbol *sym)
890 struct type *type = check_typedef (SYMBOL_TYPE (sym));
891 enum type_code code = TYPE_CODE (type);
893 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
895 type = check_typedef (TYPE_TARGET_TYPE (type));
896 if (sparc_structure_or_union_p (type)
897 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
904 struct sparc_frame_cache *
905 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
907 struct sparc_frame_cache *cache;
913 cache = sparc_frame_cache (this_frame, this_cache);
915 sym = find_pc_function (cache->pc);
918 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
922 /* There is no debugging information for this function to
923 help us determine whether this function returns a struct
924 or not. So we rely on another heuristic which is to check
925 the instruction at the return address and see if this is
926 an "unimp" instruction. If it is, then it is a struct-return
929 int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
931 pc = get_frame_register_unsigned (this_frame, regnum) + 8;
932 if (sparc_is_unimp_insn (pc))
933 cache->struct_return_p = 1;
940 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
941 struct frame_id *this_id)
943 struct sparc_frame_cache *cache =
944 sparc32_frame_cache (this_frame, this_cache);
946 /* This marks the outermost frame. */
947 if (cache->base == 0)
950 (*this_id) = frame_id_build (cache->base, cache->pc);
953 static struct value *
954 sparc32_frame_prev_register (struct frame_info *this_frame,
955 void **this_cache, int regnum)
957 struct sparc_frame_cache *cache =
958 sparc32_frame_cache (this_frame, this_cache);
960 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
962 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
964 /* If this functions has a Structure, Union or Quad-Precision
965 return value, we have to skip the UNIMP instruction that encodes
966 the size of the structure. */
967 if (cache->struct_return_p)
970 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
971 pc += get_frame_register_unsigned (this_frame, regnum) + 8;
972 return frame_unwind_got_constant (this_frame, regnum, pc);
975 /* Handle StackGhost. */
977 ULONGEST wcookie = sparc_fetch_wcookie ();
979 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
981 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
984 /* Read the value in from memory. */
985 i7 = get_frame_memory_unsigned (this_frame, addr, 4);
986 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
990 /* The previous frame's `local' and `in' registers have been saved
991 in the register save area. */
992 if (!cache->frameless_p
993 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
995 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
997 return frame_unwind_got_memory (this_frame, regnum, addr);
1000 /* The previous frame's `out' registers are accessible as the
1001 current frame's `in' registers. */
1002 if (!cache->frameless_p
1003 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
1004 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1006 return frame_unwind_got_register (this_frame, regnum, regnum);
1009 static const struct frame_unwind sparc32_frame_unwind =
1012 sparc32_frame_this_id,
1013 sparc32_frame_prev_register,
1015 default_frame_sniffer
1020 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1022 struct sparc_frame_cache *cache =
1023 sparc32_frame_cache (this_frame, this_cache);
1028 static const struct frame_base sparc32_frame_base =
1030 &sparc32_frame_unwind,
1031 sparc32_frame_base_address,
1032 sparc32_frame_base_address,
1033 sparc32_frame_base_address
1036 static struct frame_id
1037 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1041 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1044 return frame_id_build (sp, get_frame_pc (this_frame));
1048 /* Extract a function return value of TYPE from REGCACHE, and copy
1049 that into VALBUF. */
1052 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1055 int len = TYPE_LENGTH (type);
1058 gdb_assert (!sparc_structure_or_union_p (type));
1059 gdb_assert (!(sparc_floating_p (type) && len == 16));
1061 if (sparc_floating_p (type))
1063 /* Floating return values. */
1064 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1066 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1067 memcpy (valbuf, buf, len);
1071 /* Integral and pointer return values. */
1072 gdb_assert (sparc_integral_or_pointer_p (type));
1074 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1077 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1078 gdb_assert (len == 8);
1079 memcpy (valbuf, buf, 8);
1083 /* Just stripping off any unused bytes should preserve the
1084 signed-ness just fine. */
1085 memcpy (valbuf, buf + 4 - len, len);
1090 /* Store the function return value of type TYPE from VALBUF into
1094 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1095 const gdb_byte *valbuf)
1097 int len = TYPE_LENGTH (type);
1100 gdb_assert (!sparc_structure_or_union_p (type));
1101 gdb_assert (!(sparc_floating_p (type) && len == 16));
1103 if (sparc_floating_p (type))
1105 /* Floating return values. */
1106 memcpy (buf, valbuf, len);
1107 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1109 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1113 /* Integral and pointer return values. */
1114 gdb_assert (sparc_integral_or_pointer_p (type));
1118 gdb_assert (len == 8);
1119 memcpy (buf, valbuf, 8);
1120 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1124 /* ??? Do we need to do any sign-extension here? */
1125 memcpy (buf + 4 - len, valbuf, len);
1127 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1131 static enum return_value_convention
1132 sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type,
1133 struct type *type, struct regcache *regcache,
1134 gdb_byte *readbuf, const gdb_byte *writebuf)
1136 /* The psABI says that "...every stack frame reserves the word at
1137 %fp+64. If a function returns a structure, union, or
1138 quad-precision value, this word should hold the address of the
1139 object into which the return value should be copied." This
1140 guarantees that we can always find the return value, not just
1141 before the function returns. */
1143 if (sparc_structure_or_union_p (type)
1144 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1151 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1152 addr = read_memory_unsigned_integer (sp + 64, 4);
1153 read_memory (addr, readbuf, TYPE_LENGTH (type));
1156 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1160 sparc32_extract_return_value (type, regcache, readbuf);
1162 sparc32_store_return_value (type, regcache, writebuf);
1164 return RETURN_VALUE_REGISTER_CONVENTION;
1168 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1170 return (sparc_structure_or_union_p (type)
1171 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1175 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1177 CORE_ADDR pc = get_frame_address_in_block (this_frame);
1178 struct symbol *sym = find_pc_function (pc);
1181 return sparc32_struct_return_from_sym (sym);
1186 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1187 struct dwarf2_frame_state_reg *reg,
1188 struct frame_info *this_frame)
1194 case SPARC_G0_REGNUM:
1195 /* Since %g0 is always zero, there is no point in saving it, and
1196 people will be inclined omit it from the CFI. Make sure we
1197 don't warn about that. */
1198 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1200 case SPARC_SP_REGNUM:
1201 reg->how = DWARF2_FRAME_REG_CFA;
1203 case SPARC32_PC_REGNUM:
1204 case SPARC32_NPC_REGNUM:
1205 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1207 if (sparc32_dwarf2_struct_return_p (this_frame))
1209 if (regnum == SPARC32_NPC_REGNUM)
1211 reg->loc.offset = off;
1217 /* The SPARC Architecture doesn't have hardware single-step support,
1218 and most operating systems don't implement it either, so we provide
1219 software single-step mechanism. */
1222 sparc_analyze_control_transfer (struct frame_info *frame,
1223 CORE_ADDR pc, CORE_ADDR *npc)
1225 unsigned long insn = sparc_fetch_instruction (pc);
1226 int conditional_p = X_COND (insn) & 0x7;
1228 long offset = 0; /* Must be signed for sign-extend. */
1230 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1232 /* Branch on Integer Register with Prediction (BPr). */
1236 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1238 /* Branch on Floating-Point Condition Codes (FBfcc). */
1240 offset = 4 * X_DISP22 (insn);
1242 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1244 /* Branch on Floating-Point Condition Codes with Prediction
1247 offset = 4 * X_DISP19 (insn);
1249 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1251 /* Branch on Integer Condition Codes (Bicc). */
1253 offset = 4 * X_DISP22 (insn);
1255 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1257 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1259 offset = 4 * X_DISP19 (insn);
1261 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1263 /* Trap instruction (TRAP). */
1264 return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1267 /* FIXME: Handle DONE and RETRY instructions. */
1273 /* For conditional branches, return nPC + 4 iff the annul
1275 return (X_A (insn) ? *npc + 4 : 0);
1279 /* For unconditional branches, return the target if its
1280 specified condition is "always" and return nPC + 4 if the
1281 condition is "never". If the annul bit is 1, set *NPC to
1283 if (X_COND (insn) == 0x0)
1284 pc = *npc, offset = 4;
1288 gdb_assert (offset != 0);
1297 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1303 sparc_software_single_step (struct frame_info *frame)
1305 struct gdbarch *arch = get_frame_arch (frame);
1306 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1307 CORE_ADDR npc, nnpc;
1309 CORE_ADDR pc, orig_npc;
1311 pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1312 orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1314 /* Analyze the instruction at PC. */
1315 nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1317 insert_single_step_breakpoint (npc);
1320 insert_single_step_breakpoint (nnpc);
1322 /* Assert that we have set at least one breakpoint, and that
1323 they're not set at the same spot - unless we're going
1324 from here straight to NULL, i.e. a call or jump to 0. */
1325 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1326 gdb_assert (nnpc != npc || orig_npc == 0);
1332 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1334 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1336 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1337 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1341 /* Return the appropriate register set for the core section identified
1342 by SECT_NAME and SECT_SIZE. */
1344 static const struct regset *
1345 sparc_regset_from_core_section (struct gdbarch *gdbarch,
1346 const char *sect_name, size_t sect_size)
1348 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1350 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1351 return tdep->gregset;
1353 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1354 return tdep->fpregset;
1360 static struct gdbarch *
1361 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1363 struct gdbarch_tdep *tdep;
1364 struct gdbarch *gdbarch;
1366 /* If there is already a candidate, use it. */
1367 arches = gdbarch_list_lookup_by_info (arches, &info);
1369 return arches->gdbarch;
1371 /* Allocate space for the new architecture. */
1372 tdep = XMALLOC (struct gdbarch_tdep);
1373 gdbarch = gdbarch_alloc (&info, tdep);
1375 tdep->pc_regnum = SPARC32_PC_REGNUM;
1376 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1377 tdep->gregset = NULL;
1378 tdep->sizeof_gregset = 0;
1379 tdep->fpregset = NULL;
1380 tdep->sizeof_fpregset = 0;
1381 tdep->plt_entry_size = 0;
1382 tdep->step_trap = sparc_step_trap;
1384 set_gdbarch_long_double_bit (gdbarch, 128);
1385 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1387 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1388 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1389 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1390 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1391 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1392 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1394 /* Register numbers of various important registers. */
1395 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1396 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1397 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1399 /* Call dummy code. */
1400 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1401 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1402 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1404 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1405 set_gdbarch_stabs_argument_has_addr
1406 (gdbarch, sparc32_stabs_argument_has_addr);
1408 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1410 /* Stack grows downward. */
1411 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1413 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1415 set_gdbarch_frame_args_skip (gdbarch, 8);
1417 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1419 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1420 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1422 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1424 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1426 frame_base_set_default (gdbarch, &sparc32_frame_base);
1428 /* Hook in the DWARF CFI frame unwinder. */
1429 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1430 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1431 StackGhost issues have been resolved. */
1433 /* Hook in ABI-specific overrides, if they have been registered. */
1434 gdbarch_init_osabi (info, gdbarch);
1436 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1438 /* If we have register sets, enable the generic core file support. */
1440 set_gdbarch_regset_from_core_section (gdbarch,
1441 sparc_regset_from_core_section);
1446 /* Helper functions for dealing with register windows. */
1449 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1457 /* Registers are 64-bit. */
1460 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1462 if (regnum == i || regnum == -1)
1464 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1466 /* Handle StackGhost. */
1467 if (i == SPARC_I7_REGNUM)
1469 ULONGEST wcookie = sparc_fetch_wcookie ();
1470 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1472 store_unsigned_integer (buf + offset, 8, i7 ^ wcookie);
1475 regcache_raw_supply (regcache, i, buf);
1481 /* Registers are 32-bit. Toss any sign-extension of the stack
1485 /* Clear out the top half of the temporary buffer, and put the
1486 register value in the bottom half if we're in 64-bit mode. */
1487 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1493 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1495 if (regnum == i || regnum == -1)
1497 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1500 /* Handle StackGhost. */
1501 if (i == SPARC_I7_REGNUM)
1503 ULONGEST wcookie = sparc_fetch_wcookie ();
1504 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1506 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1509 regcache_raw_supply (regcache, i, buf);
1516 sparc_collect_rwindow (const struct regcache *regcache,
1517 CORE_ADDR sp, int regnum)
1525 /* Registers are 64-bit. */
1528 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1530 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1532 regcache_raw_collect (regcache, i, buf);
1534 /* Handle StackGhost. */
1535 if (i == SPARC_I7_REGNUM)
1537 ULONGEST wcookie = sparc_fetch_wcookie ();
1538 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1540 store_unsigned_integer (buf, 8, i7 ^ wcookie);
1543 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1549 /* Registers are 32-bit. Toss any sign-extension of the stack
1553 /* Only use the bottom half if we're in 64-bit mode. */
1554 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1557 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1559 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1561 regcache_raw_collect (regcache, i, buf);
1563 /* Handle StackGhost. */
1564 if (i == SPARC_I7_REGNUM)
1566 ULONGEST wcookie = sparc_fetch_wcookie ();
1567 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1569 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1572 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1579 /* Helper functions for dealing with register sets. */
1582 sparc32_supply_gregset (const struct sparc_gregset *gregset,
1583 struct regcache *regcache,
1584 int regnum, const void *gregs)
1586 const gdb_byte *regs = gregs;
1589 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1590 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1591 regs + gregset->r_psr_offset);
1593 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1594 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1595 regs + gregset->r_pc_offset);
1597 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1598 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1599 regs + gregset->r_npc_offset);
1601 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1602 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1603 regs + gregset->r_y_offset);
1605 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1606 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1608 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1610 int offset = gregset->r_g1_offset;
1612 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1614 if (regnum == i || regnum == -1)
1615 regcache_raw_supply (regcache, i, regs + offset);
1620 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1622 /* Not all of the register set variants include Locals and
1623 Inputs. For those that don't, we read them off the stack. */
1624 if (gregset->r_l0_offset == -1)
1628 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1629 sparc_supply_rwindow (regcache, sp, regnum);
1633 int offset = gregset->r_l0_offset;
1635 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1637 if (regnum == i || regnum == -1)
1638 regcache_raw_supply (regcache, i, regs + offset);
1646 sparc32_collect_gregset (const struct sparc_gregset *gregset,
1647 const struct regcache *regcache,
1648 int regnum, void *gregs)
1650 gdb_byte *regs = gregs;
1653 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1654 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1655 regs + gregset->r_psr_offset);
1657 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1658 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1659 regs + gregset->r_pc_offset);
1661 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1662 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1663 regs + gregset->r_npc_offset);
1665 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1666 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1667 regs + gregset->r_y_offset);
1669 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1671 int offset = gregset->r_g1_offset;
1673 /* %g0 is always zero. */
1674 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1676 if (regnum == i || regnum == -1)
1677 regcache_raw_collect (regcache, i, regs + offset);
1682 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1684 /* Not all of the register set variants include Locals and
1685 Inputs. For those that don't, we read them off the stack. */
1686 if (gregset->r_l0_offset != -1)
1688 int offset = gregset->r_l0_offset;
1690 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1692 if (regnum == i || regnum == -1)
1693 regcache_raw_collect (regcache, i, regs + offset);
1701 sparc32_supply_fpregset (struct regcache *regcache,
1702 int regnum, const void *fpregs)
1704 const gdb_byte *regs = fpregs;
1707 for (i = 0; i < 32; i++)
1709 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1710 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1713 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1714 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1718 sparc32_collect_fpregset (const struct regcache *regcache,
1719 int regnum, void *fpregs)
1721 gdb_byte *regs = fpregs;
1724 for (i = 0; i < 32; i++)
1726 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1727 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1730 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1731 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1737 /* From <machine/reg.h>. */
1738 const struct sparc_gregset sparc32_sunos4_gregset =
1751 /* Provide a prototype to silence -Wmissing-prototypes. */
1752 void _initialize_sparc_tdep (void);
1755 _initialize_sparc_tdep (void)
1757 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);