1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "arch-utils.h"
25 #include "dwarf2-frame.h"
26 #include "floatformat.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
40 #include "gdb_assert.h"
41 #include "gdb_string.h"
43 #include "sparc-tdep.h"
47 /* This file implements the SPARC 32-bit ABI as defined by the section
48 "Low-Level System Information" of the SPARC Compliance Definition
49 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
50 lists changes with respect to the original 32-bit psABI as defined
51 in the "System V ABI, SPARC Processor Supplement".
53 Note that if we talk about SunOS, we mean SunOS 4.x, which was
54 BSD-based, which is sometimes (retroactively?) referred to as
55 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
56 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
57 suffering from severe version number inflation). Solaris 2.x is
58 also known as SunOS 5.x, since that's what uname(1) says. Solaris
61 /* Please use the sparc32_-prefix for 32-bit specific code, the
62 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
63 code that can handle both. The 64-bit specific code lives in
64 sparc64-tdep.c; don't add any here. */
66 /* The SPARC Floating-Point Quad-Precision format is similar to
67 big-endian IA-64 Quad-recision format. */
68 #define floatformat_sparc_quad floatformat_ia64_quad_big
70 /* The stack pointer is offset from the stack frame by a BIAS of 2047
71 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
72 hosts, so undefine it first. */
76 /* Macros to extract fields from SPARC instructions. */
77 #define X_OP(i) (((i) >> 30) & 0x3)
78 #define X_RD(i) (((i) >> 25) & 0x1f)
79 #define X_A(i) (((i) >> 29) & 1)
80 #define X_COND(i) (((i) >> 25) & 0xf)
81 #define X_OP2(i) (((i) >> 22) & 0x7)
82 #define X_IMM22(i) ((i) & 0x3fffff)
83 #define X_OP3(i) (((i) >> 19) & 0x3f)
84 #define X_RS1(i) (((i) >> 14) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc, buf, sizeof (buf)))
106 for (i = 0; i < sizeof (buf); i++)
107 insn = (insn << 8) | buf[i];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc)
118 const unsigned long insn = sparc_fetch_instruction (pc);
120 return ((insn & 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (void)
157 struct target_ops *ops = ¤t_target;
161 len = target_read_partial (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
165 /* We should have either an 32-bit or an 64-bit cookie. */
166 gdb_assert (len == 4 || len == 8);
168 return extract_unsigned_integer (buf, len);
172 /* Return the contents if register REGNUM as an address. */
175 sparc_address_from_register (int regnum)
179 regcache_cooked_read_unsigned (current_regcache, regnum, &addr);
184 /* The functions on this page are intended to be used to classify
185 function arguments. */
187 /* Check whether TYPE is "Integral or Pointer". */
190 sparc_integral_or_pointer_p (const struct type *type)
192 int len = TYPE_LENGTH (type);
194 switch (TYPE_CODE (type))
200 case TYPE_CODE_RANGE:
201 /* We have byte, half-word, word and extended-word/doubleword
202 integral types. The doubleword is an extension to the
203 original 32-bit ABI by the SCD 2.4.x. */
204 return (len == 1 || len == 2 || len == 4 || len == 8);
207 /* Allow either 32-bit or 64-bit pointers. */
208 return (len == 4 || len == 8);
216 /* Check whether TYPE is "Floating". */
219 sparc_floating_p (const struct type *type)
221 switch (TYPE_CODE (type))
225 int len = TYPE_LENGTH (type);
226 return (len == 4 || len == 8 || len == 16);
235 /* Check whether TYPE is "Structure or Union". */
238 sparc_structure_or_union_p (const struct type *type)
240 switch (TYPE_CODE (type))
242 case TYPE_CODE_STRUCT:
243 case TYPE_CODE_UNION:
252 /* Register information. */
254 static const char *sparc32_register_names[] =
256 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
257 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
258 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
259 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
261 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
262 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
263 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
264 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
266 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
269 /* Total number of registers. */
270 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
272 /* We provide the aliases %d0..%d30 for the floating registers as
273 "psuedo" registers. */
275 static const char *sparc32_pseudo_register_names[] =
277 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
278 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
281 /* Total number of pseudo registers. */
282 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
284 /* Return the name of register REGNUM. */
287 sparc32_register_name (int regnum)
289 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
290 return sparc32_register_names[regnum];
292 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
293 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
298 /* Return the GDB type object for the "standard" data type of data in
302 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
304 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
305 return builtin_type_float;
307 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
308 return builtin_type_double;
310 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
311 return builtin_type_void_data_ptr;
313 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
314 return builtin_type_void_func_ptr;
316 return builtin_type_int32;
320 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
321 struct regcache *regcache,
322 int regnum, gdb_byte *buf)
324 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
326 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
327 regcache_raw_read (regcache, regnum, buf);
328 regcache_raw_read (regcache, regnum + 1, buf + 4);
332 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
333 struct regcache *regcache,
334 int regnum, const gdb_byte *buf)
336 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
338 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
339 regcache_raw_write (regcache, regnum, buf);
340 regcache_raw_write (regcache, regnum + 1, buf + 4);
345 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
346 CORE_ADDR funcaddr, int using_gcc,
347 struct value **args, int nargs,
348 struct type *value_type,
349 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
354 if (using_struct_return (value_type, using_gcc))
358 /* This is an UNIMP instruction. */
359 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
360 write_memory (sp - 8, buf, 4);
368 sparc32_store_arguments (struct regcache *regcache, int nargs,
369 struct value **args, CORE_ADDR sp,
370 int struct_return, CORE_ADDR struct_addr)
372 /* Number of words in the "parameter array". */
373 int num_elements = 0;
377 for (i = 0; i < nargs; i++)
379 struct type *type = value_type (args[i]);
380 int len = TYPE_LENGTH (type);
382 if (sparc_structure_or_union_p (type)
383 || (sparc_floating_p (type) && len == 16))
385 /* Structure, Union and Quad-Precision Arguments. */
388 /* Use doubleword alignment for these values. That's always
389 correct, and wasting a few bytes shouldn't be a problem. */
392 write_memory (sp, value_contents (args[i]), len);
393 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
396 else if (sparc_floating_p (type))
398 /* Floating arguments. */
399 gdb_assert (len == 4 || len == 8);
400 num_elements += (len / 4);
404 /* Integral and pointer arguments. */
405 gdb_assert (sparc_integral_or_pointer_p (type));
408 args[i] = value_cast (builtin_type_int32, args[i]);
409 num_elements += ((len + 3) / 4);
413 /* Always allocate at least six words. */
414 sp -= max (6, num_elements) * 4;
416 /* The psABI says that "Software convention requires space for the
417 struct/union return value pointer, even if the word is unused." */
420 /* The psABI says that "Although software convention and the
421 operating system require every stack frame to be doubleword
425 for (i = 0; i < nargs; i++)
427 const bfd_byte *valbuf = value_contents (args[i]);
428 struct type *type = value_type (args[i]);
429 int len = TYPE_LENGTH (type);
431 gdb_assert (len == 4 || len == 8);
435 int regnum = SPARC_O0_REGNUM + element;
437 regcache_cooked_write (regcache, regnum, valbuf);
438 if (len > 4 && element < 5)
439 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
442 /* Always store the argument in memory. */
443 write_memory (sp + 4 + element * 4, valbuf, len);
447 gdb_assert (element == num_elements);
453 store_unsigned_integer (buf, 4, struct_addr);
454 write_memory (sp, buf, 4);
461 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
462 struct regcache *regcache, CORE_ADDR bp_addr,
463 int nargs, struct value **args, CORE_ADDR sp,
464 int struct_return, CORE_ADDR struct_addr)
466 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
468 /* Set return address. */
469 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
471 /* Set up function arguments. */
472 sp = sparc32_store_arguments (regcache, nargs, args, sp,
473 struct_return, struct_addr);
475 /* Allocate the 16-word window save area. */
478 /* Stack should be doubleword aligned at this point. */
479 gdb_assert (sp % 8 == 0);
481 /* Finally, update the stack pointer. */
482 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
488 /* Use the program counter to determine the contents and size of a
489 breakpoint instruction. Return a pointer to a string of bytes that
490 encode a breakpoint instruction, store the length of the string in
491 *LEN and optionally adjust *PC to point to the correct memory
492 location for inserting the breakpoint. */
494 static const gdb_byte *
495 sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
497 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
499 *len = sizeof (break_insn);
504 /* Allocate and initialize a frame cache. */
506 static struct sparc_frame_cache *
507 sparc_alloc_frame_cache (void)
509 struct sparc_frame_cache *cache;
512 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
518 /* Frameless until proven otherwise. */
519 cache->frameless_p = 1;
521 cache->struct_return_p = 0;
527 sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
528 struct sparc_frame_cache *cache)
530 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
535 if (current_pc <= pc)
538 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
539 SPARC the linker usually defines a symbol (typically
540 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
541 This symbol makes us end up here with PC pointing at the start of
542 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
543 would do our normal prologue analysis, we would probably conclude
544 that we've got a frame when in reality we don't, since the
545 dynamic linker patches up the first PLT with some code that
546 starts with a SAVE instruction. Patch up PC such that it points
547 at the start of our PLT entry. */
548 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
549 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
551 insn = sparc_fetch_instruction (pc);
553 /* Recognize a SETHI insn and record its destination. */
554 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
559 insn = sparc_fetch_instruction (pc + 4);
562 /* Allow for an arithmetic operation on DEST or %g1. */
563 if (X_OP (insn) == 2 && X_I (insn)
564 && (X_RD (insn) == 1 || X_RD (insn) == dest))
568 insn = sparc_fetch_instruction (pc + 8);
571 /* Check for the SAVE instruction that sets up the frame. */
572 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
574 cache->frameless_p = 0;
575 return pc + offset + 4;
582 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
584 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
585 return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
588 /* Return PC of first real instruction of the function starting at
592 sparc32_skip_prologue (CORE_ADDR start_pc)
594 struct symtab_and_line sal;
595 CORE_ADDR func_start, func_end;
596 struct sparc_frame_cache cache;
598 /* This is the preferred method, find the end of the prologue by
599 using the debugging information. */
600 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
602 sal = find_pc_line (func_start, 0);
604 if (sal.end < func_end
605 && start_pc <= sal.end)
609 start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache);
611 /* The psABI says that "Although the first 6 words of arguments
612 reside in registers, the standard stack frame reserves space for
613 them.". It also suggests that a function may use that space to
614 "write incoming arguments 0 to 5" into that space, and that's
615 indeed what GCC seems to be doing. In that case GCC will
616 generate debug information that points to the stack slots instead
617 of the registers, so we should consider the instructions that
618 write out these incoming arguments onto the stack. Of course we
619 only need to do this if we have a stack frame. */
621 while (!cache.frameless_p)
623 unsigned long insn = sparc_fetch_instruction (start_pc);
625 /* Recognize instructions that store incoming arguments in
626 %i0...%i5 into the corresponding stack slot. */
627 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
628 && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
629 && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
643 struct sparc_frame_cache *
644 sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
646 struct sparc_frame_cache *cache;
651 cache = sparc_alloc_frame_cache ();
654 cache->pc = frame_func_unwind (next_frame);
657 CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame);
658 sparc_analyze_prologue (cache->pc, addr_in_block, cache);
661 if (cache->frameless_p)
663 /* This function is frameless, so %fp (%i6) holds the frame
664 pointer for our calling frame. Use %sp (%o6) as this frame's
667 frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
671 /* For normal frames, %fp (%i6) holds the frame pointer, the
672 base address for the current stack frame. */
674 frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
684 sparc32_struct_return_from_sym (struct symbol *sym)
686 struct type *type = check_typedef (SYMBOL_TYPE (sym));
687 enum type_code code = TYPE_CODE (type);
689 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
691 type = check_typedef (TYPE_TARGET_TYPE (type));
692 if (sparc_structure_or_union_p (type)
693 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
700 struct sparc_frame_cache *
701 sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
703 struct sparc_frame_cache *cache;
709 cache = sparc_frame_cache (next_frame, this_cache);
711 sym = find_pc_function (cache->pc);
714 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
718 /* There is no debugging information for this function to
719 help us determine whether this function returns a struct
720 or not. So we rely on another heuristic which is to check
721 the instruction at the return address and see if this is
722 an "unimp" instruction. If it is, then it is a struct-return
725 int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
727 pc = frame_unwind_register_unsigned (next_frame, regnum) + 8;
728 if (sparc_is_unimp_insn (pc))
729 cache->struct_return_p = 1;
736 sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
737 struct frame_id *this_id)
739 struct sparc_frame_cache *cache =
740 sparc32_frame_cache (next_frame, this_cache);
742 /* This marks the outermost frame. */
743 if (cache->base == 0)
746 (*this_id) = frame_id_build (cache->base, cache->pc);
750 sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
751 int regnum, int *optimizedp,
752 enum lval_type *lvalp, CORE_ADDR *addrp,
753 int *realnump, gdb_byte *valuep)
755 struct sparc_frame_cache *cache =
756 sparc32_frame_cache (next_frame, this_cache);
758 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
766 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
768 /* If this functions has a Structure, Union or
769 Quad-Precision return value, we have to skip the UNIMP
770 instruction that encodes the size of the structure. */
771 if (cache->struct_return_p)
774 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
775 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
776 store_unsigned_integer (valuep, 4, pc);
781 /* Handle StackGhost. */
783 ULONGEST wcookie = sparc_fetch_wcookie ();
785 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
793 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
796 /* Read the value in from memory. */
797 i7 = get_frame_memory_unsigned (next_frame, addr, 4);
798 store_unsigned_integer (valuep, 4, i7 ^ wcookie);
804 /* The previous frame's `local' and `in' registers have been saved
805 in the register save area. */
806 if (!cache->frameless_p
807 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
810 *lvalp = lval_memory;
811 *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
815 struct gdbarch *gdbarch = get_frame_arch (next_frame);
817 /* Read the value in from memory. */
818 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
823 /* The previous frame's `out' registers are accessable as the
824 current frame's `in' registers. */
825 if (!cache->frameless_p
826 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
827 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
830 *lvalp = lval_register;
834 frame_unwind_register (next_frame, (*realnump), valuep);
837 static const struct frame_unwind sparc32_frame_unwind =
840 sparc32_frame_this_id,
841 sparc32_frame_prev_register
844 static const struct frame_unwind *
845 sparc32_frame_sniffer (struct frame_info *next_frame)
847 return &sparc32_frame_unwind;
852 sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
854 struct sparc_frame_cache *cache =
855 sparc32_frame_cache (next_frame, this_cache);
860 static const struct frame_base sparc32_frame_base =
862 &sparc32_frame_unwind,
863 sparc32_frame_base_address,
864 sparc32_frame_base_address,
865 sparc32_frame_base_address
868 static struct frame_id
869 sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
873 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
876 return frame_id_build (sp, frame_pc_unwind (next_frame));
880 /* Extract from an array REGBUF containing the (raw) register state, a
881 function return value of TYPE, and copy that into VALBUF. */
884 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
887 int len = TYPE_LENGTH (type);
890 gdb_assert (!sparc_structure_or_union_p (type));
891 gdb_assert (!(sparc_floating_p (type) && len == 16));
893 if (sparc_floating_p (type))
895 /* Floating return values. */
896 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
898 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
899 memcpy (valbuf, buf, len);
903 /* Integral and pointer return values. */
904 gdb_assert (sparc_integral_or_pointer_p (type));
906 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
909 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
910 gdb_assert (len == 8);
911 memcpy (valbuf, buf, 8);
915 /* Just stripping off any unused bytes should preserve the
916 signed-ness just fine. */
917 memcpy (valbuf, buf + 4 - len, len);
922 /* Write into the appropriate registers a function return value stored
923 in VALBUF of type TYPE. */
926 sparc32_store_return_value (struct type *type, struct regcache *regcache,
927 const gdb_byte *valbuf)
929 int len = TYPE_LENGTH (type);
932 gdb_assert (!sparc_structure_or_union_p (type));
933 gdb_assert (!(sparc_floating_p (type) && len == 16));
935 if (sparc_floating_p (type))
937 /* Floating return values. */
938 memcpy (buf, valbuf, len);
939 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
941 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
945 /* Integral and pointer return values. */
946 gdb_assert (sparc_integral_or_pointer_p (type));
950 gdb_assert (len == 8);
951 memcpy (buf, valbuf, 8);
952 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
956 /* ??? Do we need to do any sign-extension here? */
957 memcpy (buf + 4 - len, valbuf, len);
959 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
963 static enum return_value_convention
964 sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
965 struct regcache *regcache, gdb_byte *readbuf,
966 const gdb_byte *writebuf)
968 /* The psABI says that "...every stack frame reserves the word at
969 %fp+64. If a function returns a structure, union, or
970 quad-precision value, this word should hold the address of the
971 object into which the return value should be copied." This
972 guarantees that we can always find the return value, not just
973 before the function returns. */
975 if (sparc_structure_or_union_p (type)
976 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
983 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
984 addr = read_memory_unsigned_integer (sp + 64, 4);
985 read_memory (addr, readbuf, TYPE_LENGTH (type));
988 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
992 sparc32_extract_return_value (type, regcache, readbuf);
994 sparc32_store_return_value (type, regcache, writebuf);
996 return RETURN_VALUE_REGISTER_CONVENTION;
1000 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1002 return (sparc_structure_or_union_p (type)
1003 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1007 sparc32_dwarf2_struct_return_p (struct frame_info *next_frame)
1009 CORE_ADDR pc = frame_unwind_address_in_block (next_frame);
1010 struct symbol *sym = find_pc_function (pc);
1013 return sparc32_struct_return_from_sym (sym);
1018 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1019 struct dwarf2_frame_state_reg *reg,
1020 struct frame_info *next_frame)
1026 case SPARC_G0_REGNUM:
1027 /* Since %g0 is always zero, there is no point in saving it, and
1028 people will be inclined omit it from the CFI. Make sure we
1029 don't warn about that. */
1030 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1032 case SPARC_SP_REGNUM:
1033 reg->how = DWARF2_FRAME_REG_CFA;
1035 case SPARC32_PC_REGNUM:
1036 case SPARC32_NPC_REGNUM:
1037 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1039 if (sparc32_dwarf2_struct_return_p (next_frame))
1041 if (regnum == SPARC32_NPC_REGNUM)
1043 reg->loc.offset = off;
1049 /* The SPARC Architecture doesn't have hardware single-step support,
1050 and most operating systems don't implement it either, so we provide
1051 software single-step mechanism. */
1054 sparc_analyze_control_transfer (struct gdbarch *arch,
1055 CORE_ADDR pc, CORE_ADDR *npc)
1057 unsigned long insn = sparc_fetch_instruction (pc);
1058 int conditional_p = X_COND (insn) & 0x7;
1060 long offset = 0; /* Must be signed for sign-extend. */
1062 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1064 /* Branch on Integer Register with Prediction (BPr). */
1068 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1070 /* Branch on Floating-Point Condition Codes (FBfcc). */
1072 offset = 4 * X_DISP22 (insn);
1074 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1076 /* Branch on Floating-Point Condition Codes with Prediction
1079 offset = 4 * X_DISP19 (insn);
1081 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1083 /* Branch on Integer Condition Codes (Bicc). */
1085 offset = 4 * X_DISP22 (insn);
1087 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1089 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1091 offset = 4 * X_DISP19 (insn);
1093 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1095 /* Trap instruction (TRAP). */
1096 return gdbarch_tdep (arch)->step_trap (insn);
1099 /* FIXME: Handle DONE and RETRY instructions. */
1105 /* For conditional branches, return nPC + 4 iff the annul
1107 return (X_A (insn) ? *npc + 4 : 0);
1111 /* For unconditional branches, return the target if its
1112 specified condition is "always" and return nPC + 4 if the
1113 condition is "never". If the annul bit is 1, set *NPC to
1115 if (X_COND (insn) == 0x0)
1116 pc = *npc, offset = 4;
1120 gdb_assert (offset != 0);
1129 sparc_step_trap (unsigned long insn)
1135 sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1137 struct gdbarch *arch = current_gdbarch;
1138 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1139 static CORE_ADDR npc, nnpc;
1140 static gdb_byte npc_save[4], nnpc_save[4];
1142 if (insert_breakpoints_p)
1144 CORE_ADDR pc, orig_npc;
1146 pc = sparc_address_from_register (tdep->pc_regnum);
1147 orig_npc = npc = sparc_address_from_register (tdep->npc_regnum);
1149 /* Analyze the instruction at PC. */
1150 nnpc = sparc_analyze_control_transfer (arch, pc, &npc);
1152 target_insert_breakpoint (npc, npc_save);
1154 target_insert_breakpoint (nnpc, nnpc_save);
1156 /* Assert that we have set at least one breakpoint, and that
1157 they're not set at the same spot - unless we're going
1158 from here straight to NULL, i.e. a call or jump to 0. */
1159 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1160 gdb_assert (nnpc != npc || orig_npc == 0);
1165 target_remove_breakpoint (npc, npc_save);
1167 target_remove_breakpoint (nnpc, nnpc_save);
1172 sparc_write_pc (CORE_ADDR pc, ptid_t ptid)
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1176 write_register_pid (tdep->pc_regnum, pc, ptid);
1177 write_register_pid (tdep->npc_regnum, pc + 4, ptid);
1180 /* Unglobalize NAME. */
1183 sparc_stabs_unglobalize_name (char *name)
1185 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1186 SunPRO) convert file static variables into global values, a
1187 process known as globalization. In order to do this, the
1188 compiler will create a unique prefix and prepend it to each file
1189 static variable. For static variables within a function, this
1190 globalization prefix is followed by the function name (nested
1191 static variables within a function are supposed to generate a
1192 warning message, and are left alone). The procedure is
1193 documented in the Stabs Interface Manual, which is distrubuted
1194 with the compilers, although version 4.0 of the manual seems to
1195 be incorrect in some places, at least for SPARC. The
1196 globalization prefix is encoded into an N_OPT stab, with the form
1197 "G=<prefix>". The globalization prefix always seems to start
1198 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1199 simply strip everything up until the last dot. */
1203 char *p = strrchr (name, '.');
1212 /* Return the appropriate register set for the core section identified
1213 by SECT_NAME and SECT_SIZE. */
1215 const struct regset *
1216 sparc_regset_from_core_section (struct gdbarch *gdbarch,
1217 const char *sect_name, size_t sect_size)
1219 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1221 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1222 return tdep->gregset;
1224 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1225 return tdep->fpregset;
1231 static struct gdbarch *
1232 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1234 struct gdbarch_tdep *tdep;
1235 struct gdbarch *gdbarch;
1237 /* If there is already a candidate, use it. */
1238 arches = gdbarch_list_lookup_by_info (arches, &info);
1240 return arches->gdbarch;
1242 /* Allocate space for the new architecture. */
1243 tdep = XMALLOC (struct gdbarch_tdep);
1244 gdbarch = gdbarch_alloc (&info, tdep);
1246 tdep->pc_regnum = SPARC32_PC_REGNUM;
1247 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1248 tdep->gregset = NULL;
1249 tdep->sizeof_gregset = 0;
1250 tdep->fpregset = NULL;
1251 tdep->sizeof_fpregset = 0;
1252 tdep->plt_entry_size = 0;
1253 tdep->step_trap = sparc_step_trap;
1255 set_gdbarch_long_double_bit (gdbarch, 128);
1256 set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad);
1258 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1259 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1260 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1261 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1262 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1263 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1265 /* Register numbers of various important registers. */
1266 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1267 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1268 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1270 /* Call dummy code. */
1271 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1272 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1273 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1275 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1276 set_gdbarch_stabs_argument_has_addr
1277 (gdbarch, sparc32_stabs_argument_has_addr);
1279 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1281 /* Stack grows downward. */
1282 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1284 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1286 set_gdbarch_frame_args_skip (gdbarch, 8);
1288 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1290 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1291 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1293 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1295 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1297 frame_base_set_default (gdbarch, &sparc32_frame_base);
1299 /* Hook in ABI-specific overrides, if they have been registered. */
1300 gdbarch_init_osabi (info, gdbarch);
1302 /* Hook in the DWARF CFI frame unwinder. */
1303 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1304 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1305 StackGhost issues have been resolved. */
1307 frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1309 /* If we have register sets, enable the generic core file support. */
1311 set_gdbarch_regset_from_core_section (gdbarch,
1312 sparc_regset_from_core_section);
1317 /* Helper functions for dealing with register windows. */
1320 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1328 /* Registers are 64-bit. */
1331 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1333 if (regnum == i || regnum == -1)
1335 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1337 /* Handle StackGhost. */
1338 if (i == SPARC_I7_REGNUM)
1340 ULONGEST wcookie = sparc_fetch_wcookie ();
1341 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1343 store_unsigned_integer (buf + offset, 8, i7 ^ wcookie);
1346 regcache_raw_supply (regcache, i, buf);
1352 /* Registers are 32-bit. Toss any sign-extension of the stack
1356 /* Clear out the top half of the temporary buffer, and put the
1357 register value in the bottom half if we're in 64-bit mode. */
1358 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1364 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1366 if (regnum == i || regnum == -1)
1368 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1371 /* Handle StackGhost. */
1372 if (i == SPARC_I7_REGNUM)
1374 ULONGEST wcookie = sparc_fetch_wcookie ();
1375 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1377 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1380 regcache_raw_supply (regcache, i, buf);
1387 sparc_collect_rwindow (const struct regcache *regcache,
1388 CORE_ADDR sp, int regnum)
1396 /* Registers are 64-bit. */
1399 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1401 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1403 regcache_raw_collect (regcache, i, buf);
1405 /* Handle StackGhost. */
1406 if (i == SPARC_I7_REGNUM)
1408 ULONGEST wcookie = sparc_fetch_wcookie ();
1409 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1411 store_unsigned_integer (buf, 8, i7 ^ wcookie);
1414 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1420 /* Registers are 32-bit. Toss any sign-extension of the stack
1424 /* Only use the bottom half if we're in 64-bit mode. */
1425 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1428 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1430 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1432 regcache_raw_collect (regcache, i, buf);
1434 /* Handle StackGhost. */
1435 if (i == SPARC_I7_REGNUM)
1437 ULONGEST wcookie = sparc_fetch_wcookie ();
1438 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1440 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1443 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1450 /* Helper functions for dealing with register sets. */
1453 sparc32_supply_gregset (const struct sparc_gregset *gregset,
1454 struct regcache *regcache,
1455 int regnum, const void *gregs)
1457 const gdb_byte *regs = gregs;
1460 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1461 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1462 regs + gregset->r_psr_offset);
1464 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1465 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1466 regs + gregset->r_pc_offset);
1468 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1469 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1470 regs + gregset->r_npc_offset);
1472 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1473 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1474 regs + gregset->r_y_offset);
1476 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1477 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1479 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1481 int offset = gregset->r_g1_offset;
1483 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1485 if (regnum == i || regnum == -1)
1486 regcache_raw_supply (regcache, i, regs + offset);
1491 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1493 /* Not all of the register set variants include Locals and
1494 Inputs. For those that don't, we read them off the stack. */
1495 if (gregset->r_l0_offset == -1)
1499 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1500 sparc_supply_rwindow (regcache, sp, regnum);
1504 int offset = gregset->r_l0_offset;
1506 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1508 if (regnum == i || regnum == -1)
1509 regcache_raw_supply (regcache, i, regs + offset);
1517 sparc32_collect_gregset (const struct sparc_gregset *gregset,
1518 const struct regcache *regcache,
1519 int regnum, void *gregs)
1521 gdb_byte *regs = gregs;
1524 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1525 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1526 regs + gregset->r_psr_offset);
1528 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1529 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1530 regs + gregset->r_pc_offset);
1532 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1533 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1534 regs + gregset->r_npc_offset);
1536 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1537 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1538 regs + gregset->r_y_offset);
1540 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1542 int offset = gregset->r_g1_offset;
1544 /* %g0 is always zero. */
1545 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1547 if (regnum == i || regnum == -1)
1548 regcache_raw_collect (regcache, i, regs + offset);
1553 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1555 /* Not all of the register set variants include Locals and
1556 Inputs. For those that don't, we read them off the stack. */
1557 if (gregset->r_l0_offset != -1)
1559 int offset = gregset->r_l0_offset;
1561 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1563 if (regnum == i || regnum == -1)
1564 regcache_raw_collect (regcache, i, regs + offset);
1572 sparc32_supply_fpregset (struct regcache *regcache,
1573 int regnum, const void *fpregs)
1575 const gdb_byte *regs = fpregs;
1578 for (i = 0; i < 32; i++)
1580 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1581 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1584 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1585 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1589 sparc32_collect_fpregset (const struct regcache *regcache,
1590 int regnum, void *fpregs)
1592 gdb_byte *regs = fpregs;
1595 for (i = 0; i < 32; i++)
1597 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1598 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1601 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1602 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1608 /* From <machine/reg.h>. */
1609 const struct sparc_gregset sparc32_sunos4_gregset =
1622 /* Provide a prototype to silence -Wmissing-prototypes. */
1623 void _initialize_sparc_tdep (void);
1626 _initialize_sparc_tdep (void)
1628 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);