1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "sparc-tdep.h"
39 #include "sparc-ravenscar-thread.h"
44 /* This file implements the SPARC 32-bit ABI as defined by the section
45 "Low-Level System Information" of the SPARC Compliance Definition
46 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
47 lists changes with respect to the original 32-bit psABI as defined
48 in the "System V ABI, SPARC Processor Supplement".
50 Note that if we talk about SunOS, we mean SunOS 4.x, which was
51 BSD-based, which is sometimes (retroactively?) referred to as
52 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
53 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
54 suffering from severe version number inflation). Solaris 2.x is
55 also known as SunOS 5.x, since that's what uname(1) says. Solaris
58 /* Please use the sparc32_-prefix for 32-bit specific code, the
59 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
60 code that can handle both. The 64-bit specific code lives in
61 sparc64-tdep.c; don't add any here. */
63 /* The SPARC Floating-Point Quad-Precision format is similar to
64 big-endian IA-64 Quad-Precision format. */
65 #define floatformats_sparc_quad floatformats_ia64_quad
67 /* The stack pointer is offset from the stack frame by a BIAS of 2047
68 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
69 hosts, so undefine it first. */
73 /* Macros to extract fields from SPARC instructions. */
74 #define X_OP(i) (((i) >> 30) & 0x3)
75 #define X_RD(i) (((i) >> 25) & 0x1f)
76 #define X_A(i) (((i) >> 29) & 1)
77 #define X_COND(i) (((i) >> 25) & 0xf)
78 #define X_OP2(i) (((i) >> 22) & 0x7)
79 #define X_IMM22(i) ((i) & 0x3fffff)
80 #define X_OP3(i) (((i) >> 19) & 0x3f)
81 #define X_RS1(i) (((i) >> 14) & 0x1f)
82 #define X_RS2(i) ((i) & 0x1f)
83 #define X_I(i) (((i) >> 13) & 1)
84 /* Sign extension macros. */
85 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
86 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
87 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
88 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
89 /* Macros to identify some instructions. */
90 /* RETURN (RETT in V8) */
91 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
93 /* Fetch the instruction at PC. Instructions are always big-endian
94 even if the processor operates in little-endian mode. */
97 sparc_fetch_instruction (CORE_ADDR pc)
103 /* If we can't read the instruction at PC, return zero. */
104 if (target_read_memory (pc, buf, sizeof (buf)))
108 for (i = 0; i < sizeof (buf); i++)
109 insn = (insn << 8) | buf[i];
114 /* Return non-zero if the instruction corresponding to PC is an "unimp"
118 sparc_is_unimp_insn (CORE_ADDR pc)
120 const unsigned long insn = sparc_fetch_instruction (pc);
122 return ((insn & 0xc1c00000) == 0);
125 /* Return non-zero if the instruction corresponding to PC is an
126 "annulled" branch, i.e. the annul bit is set. */
129 sparc_is_annulled_branch_insn (CORE_ADDR pc)
131 /* The branch instructions featuring an annul bit can be identified
132 by the following bit patterns:
135 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
136 OP2=2: Branch on Integer Condition Codes (Bcc).
137 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
138 OP2=6: Branch on FP Condition Codes (FBcc).
140 Branch on Integer Register with Prediction (BPr).
142 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
143 coprocessor branch instructions (Op2=7). */
145 const unsigned long insn = sparc_fetch_instruction (pc);
146 const unsigned op2 = X_OP2 (insn);
148 if ((X_OP (insn) == 0)
149 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
150 || ((op2 == 3) && ((insn & 0x10000000) == 0))))
156 /* OpenBSD/sparc includes StackGhost, which according to the author's
157 website http://stackghost.cerias.purdue.edu "... transparently and
158 automatically protects applications' stack frames; more
159 specifically, it guards the return pointers. The protection
160 mechanisms require no application source or binary modification and
161 imposes only a negligible performance penalty."
163 The same website provides the following description of how
166 "StackGhost interfaces with the kernel trap handler that would
167 normally write out registers to the stack and the handler that
168 would read them back in. By XORing a cookie into the
169 return-address saved in the user stack when it is actually written
170 to the stack, and then XOR it out when the return-address is pulled
171 from the stack, StackGhost can cause attacker corrupted return
172 pointers to behave in a manner the attacker cannot predict.
173 StackGhost can also use several unused bits in the return pointer
174 to detect a smashed return pointer and abort the process."
176 For GDB this means that whenever we're reading %i7 from a stack
177 frame's window save area, we'll have to XOR the cookie.
179 More information on StackGuard can be found on in:
181 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
182 Stack Protection." 2001. Published in USENIX Security Symposium
185 /* Fetch StackGhost Per-Process XOR cookie. */
188 sparc_fetch_wcookie (struct gdbarch *gdbarch)
190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
191 struct target_ops *ops = ¤t_target;
195 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
199 /* We should have either an 32-bit or an 64-bit cookie. */
200 gdb_assert (len == 4 || len == 8);
202 return extract_unsigned_integer (buf, len, byte_order);
206 /* The functions on this page are intended to be used to classify
207 function arguments. */
209 /* Check whether TYPE is "Integral or Pointer". */
212 sparc_integral_or_pointer_p (const struct type *type)
214 int len = TYPE_LENGTH (type);
216 switch (TYPE_CODE (type))
222 case TYPE_CODE_RANGE:
223 /* We have byte, half-word, word and extended-word/doubleword
224 integral types. The doubleword is an extension to the
225 original 32-bit ABI by the SCD 2.4.x. */
226 return (len == 1 || len == 2 || len == 4 || len == 8);
229 /* Allow either 32-bit or 64-bit pointers. */
230 return (len == 4 || len == 8);
238 /* Check whether TYPE is "Floating". */
241 sparc_floating_p (const struct type *type)
243 switch (TYPE_CODE (type))
247 int len = TYPE_LENGTH (type);
248 return (len == 4 || len == 8 || len == 16);
257 /* Check whether TYPE is "Complex Floating". */
260 sparc_complex_floating_p (const struct type *type)
262 switch (TYPE_CODE (type))
264 case TYPE_CODE_COMPLEX:
266 int len = TYPE_LENGTH (type);
267 return (len == 8 || len == 16 || len == 32);
276 /* Check whether TYPE is "Structure or Union".
278 In terms of Ada subprogram calls, arrays are treated the same as
279 struct and union types. So this function also returns non-zero
283 sparc_structure_or_union_p (const struct type *type)
285 switch (TYPE_CODE (type))
287 case TYPE_CODE_STRUCT:
288 case TYPE_CODE_UNION:
289 case TYPE_CODE_ARRAY:
298 /* Register information. */
299 #define SPARC32_FPU_REGISTERS \
300 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
301 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
302 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
303 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
304 #define SPARC32_CP0_REGISTERS \
305 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
307 static const char *sparc32_register_names[] =
309 SPARC_CORE_REGISTERS,
310 SPARC32_FPU_REGISTERS,
311 SPARC32_CP0_REGISTERS
314 /* Total number of registers. */
315 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
317 /* We provide the aliases %d0..%d30 for the floating registers as
318 "psuedo" registers. */
320 static const char *sparc32_pseudo_register_names[] =
322 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
323 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
326 /* Total number of pseudo registers. */
327 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
329 /* Return the name of pseudo register REGNUM. */
332 sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
334 regnum -= gdbarch_num_regs (gdbarch);
336 if (regnum < SPARC32_NUM_PSEUDO_REGS)
337 return sparc32_pseudo_register_names[regnum];
339 internal_error (__FILE__, __LINE__,
340 _("sparc32_pseudo_register_name: bad register number %d"),
344 /* Return the name of register REGNUM. */
347 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
349 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
350 return sparc32_register_names[regnum];
352 return sparc32_pseudo_register_name (gdbarch, regnum);
355 /* Construct types for ISA-specific registers. */
358 sparc_psr_type (struct gdbarch *gdbarch)
360 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
362 if (!tdep->sparc_psr_type)
366 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4);
367 append_flags_type_flag (type, 5, "ET");
368 append_flags_type_flag (type, 6, "PS");
369 append_flags_type_flag (type, 7, "S");
370 append_flags_type_flag (type, 12, "EF");
371 append_flags_type_flag (type, 13, "EC");
373 tdep->sparc_psr_type = type;
376 return tdep->sparc_psr_type;
380 sparc_fsr_type (struct gdbarch *gdbarch)
382 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
384 if (!tdep->sparc_fsr_type)
388 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4);
389 append_flags_type_flag (type, 0, "NXA");
390 append_flags_type_flag (type, 1, "DZA");
391 append_flags_type_flag (type, 2, "UFA");
392 append_flags_type_flag (type, 3, "OFA");
393 append_flags_type_flag (type, 4, "NVA");
394 append_flags_type_flag (type, 5, "NXC");
395 append_flags_type_flag (type, 6, "DZC");
396 append_flags_type_flag (type, 7, "UFC");
397 append_flags_type_flag (type, 8, "OFC");
398 append_flags_type_flag (type, 9, "NVC");
399 append_flags_type_flag (type, 22, "NS");
400 append_flags_type_flag (type, 23, "NXM");
401 append_flags_type_flag (type, 24, "DZM");
402 append_flags_type_flag (type, 25, "UFM");
403 append_flags_type_flag (type, 26, "OFM");
404 append_flags_type_flag (type, 27, "NVM");
406 tdep->sparc_fsr_type = type;
409 return tdep->sparc_fsr_type;
412 /* Return the GDB type object for the "standard" data type of data in
413 pseudo register REGNUM. */
416 sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
418 regnum -= gdbarch_num_regs (gdbarch);
420 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
421 return builtin_type (gdbarch)->builtin_double;
423 internal_error (__FILE__, __LINE__,
424 _("sparc32_pseudo_register_type: bad register number %d"),
428 /* Return the GDB type object for the "standard" data type of data in
432 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
434 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
435 return builtin_type (gdbarch)->builtin_float;
437 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
438 return builtin_type (gdbarch)->builtin_data_ptr;
440 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
441 return builtin_type (gdbarch)->builtin_func_ptr;
443 if (regnum == SPARC32_PSR_REGNUM)
444 return sparc_psr_type (gdbarch);
446 if (regnum == SPARC32_FSR_REGNUM)
447 return sparc_fsr_type (gdbarch);
449 if (regnum >= gdbarch_num_regs (gdbarch))
450 return sparc32_pseudo_register_type (gdbarch, regnum);
452 return builtin_type (gdbarch)->builtin_int32;
455 static enum register_status
456 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
457 struct regcache *regcache,
458 int regnum, gdb_byte *buf)
460 enum register_status status;
462 regnum -= gdbarch_num_regs (gdbarch);
463 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
465 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
466 status = regcache_raw_read (regcache, regnum, buf);
467 if (status == REG_VALID)
468 status = regcache_raw_read (regcache, regnum + 1, buf + 4);
473 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
474 struct regcache *regcache,
475 int regnum, const gdb_byte *buf)
477 regnum -= gdbarch_num_regs (gdbarch);
478 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
480 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
481 regcache_raw_write (regcache, regnum, buf);
482 regcache_raw_write (regcache, regnum + 1, buf + 4);
485 /* Implement the stack_frame_destroyed_p gdbarch method. */
488 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
490 /* This function must return true if we are one instruction after an
491 instruction that destroyed the stack frame of the current
492 function. The SPARC instructions used to restore the callers
493 stack frame are RESTORE and RETURN/RETT.
495 Of these RETURN/RETT is a branch instruction and thus we return
496 true if we are in its delay slot.
498 RESTORE is almost always found in the delay slot of a branch
499 instruction that transfers control to the caller, such as JMPL.
500 Thus the next instruction is in the caller frame and we don't
501 need to do anything about it. */
503 unsigned int insn = sparc_fetch_instruction (pc - 4);
505 return X_RETTURN (insn);
510 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
512 /* The ABI requires double-word alignment. */
513 return address & ~0x7;
517 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
519 struct value **args, int nargs,
520 struct type *value_type,
521 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
522 struct regcache *regcache)
524 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
529 if (using_struct_return (gdbarch, NULL, value_type))
533 /* This is an UNIMP instruction. */
534 store_unsigned_integer (buf, 4, byte_order,
535 TYPE_LENGTH (value_type) & 0x1fff);
536 write_memory (sp - 8, buf, 4);
544 sparc32_store_arguments (struct regcache *regcache, int nargs,
545 struct value **args, CORE_ADDR sp,
546 int struct_return, CORE_ADDR struct_addr)
548 struct gdbarch *gdbarch = get_regcache_arch (regcache);
549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
550 /* Number of words in the "parameter array". */
551 int num_elements = 0;
555 for (i = 0; i < nargs; i++)
557 struct type *type = value_type (args[i]);
558 int len = TYPE_LENGTH (type);
560 if (sparc_structure_or_union_p (type)
561 || (sparc_floating_p (type) && len == 16)
562 || sparc_complex_floating_p (type))
564 /* Structure, Union and Quad-Precision Arguments. */
567 /* Use doubleword alignment for these values. That's always
568 correct, and wasting a few bytes shouldn't be a problem. */
571 write_memory (sp, value_contents (args[i]), len);
572 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
575 else if (sparc_floating_p (type))
577 /* Floating arguments. */
578 gdb_assert (len == 4 || len == 8);
579 num_elements += (len / 4);
583 /* Integral and pointer arguments. */
584 gdb_assert (sparc_integral_or_pointer_p (type));
587 args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
589 num_elements += ((len + 3) / 4);
593 /* Always allocate at least six words. */
594 sp -= std::max (6, num_elements) * 4;
596 /* The psABI says that "Software convention requires space for the
597 struct/union return value pointer, even if the word is unused." */
600 /* The psABI says that "Although software convention and the
601 operating system require every stack frame to be doubleword
605 for (i = 0; i < nargs; i++)
607 const bfd_byte *valbuf = value_contents (args[i]);
608 struct type *type = value_type (args[i]);
609 int len = TYPE_LENGTH (type);
611 gdb_assert (len == 4 || len == 8);
615 int regnum = SPARC_O0_REGNUM + element;
617 regcache_cooked_write (regcache, regnum, valbuf);
618 if (len > 4 && element < 5)
619 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
622 /* Always store the argument in memory. */
623 write_memory (sp + 4 + element * 4, valbuf, len);
627 gdb_assert (element == num_elements);
633 store_unsigned_integer (buf, 4, byte_order, struct_addr);
634 write_memory (sp, buf, 4);
641 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
642 struct regcache *regcache, CORE_ADDR bp_addr,
643 int nargs, struct value **args, CORE_ADDR sp,
644 int struct_return, CORE_ADDR struct_addr)
646 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
648 /* Set return address. */
649 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
651 /* Set up function arguments. */
652 sp = sparc32_store_arguments (regcache, nargs, args, sp,
653 struct_return, struct_addr);
655 /* Allocate the 16-word window save area. */
658 /* Stack should be doubleword aligned at this point. */
659 gdb_assert (sp % 8 == 0);
661 /* Finally, update the stack pointer. */
662 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
668 /* Use the program counter to determine the contents and size of a
669 breakpoint instruction. Return a pointer to a string of bytes that
670 encode a breakpoint instruction, store the length of the string in
671 *LEN and optionally adjust *PC to point to the correct memory
672 location for inserting the breakpoint. */
673 constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
675 typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint;
678 /* Allocate and initialize a frame cache. */
680 static struct sparc_frame_cache *
681 sparc_alloc_frame_cache (void)
683 struct sparc_frame_cache *cache;
685 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
691 /* Frameless until proven otherwise. */
692 cache->frameless_p = 1;
693 cache->frame_offset = 0;
694 cache->saved_regs_mask = 0;
695 cache->copied_regs_mask = 0;
696 cache->struct_return_p = 0;
701 /* GCC generates several well-known sequences of instructions at the begining
702 of each function prologue when compiling with -fstack-check. If one of
703 such sequences starts at START_PC, then return the address of the
704 instruction immediately past this sequence. Otherwise, return START_PC. */
707 sparc_skip_stack_check (const CORE_ADDR start_pc)
709 CORE_ADDR pc = start_pc;
711 int probing_loop = 0;
713 /* With GCC, all stack checking sequences begin with the same two
714 instructions, plus an optional one in the case of a probing loop:
716 sethi <some immediate>, %g1
721 sethi <some immediate>, %g1
722 sethi <some immediate>, %g4
727 sethi <some immediate>, %g1
729 sethi <some immediate>, %g4
731 If the optional instruction is found (setting g4), assume that a
732 probing loop will follow. */
734 /* sethi <some immediate>, %g1 */
735 insn = sparc_fetch_instruction (pc);
737 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
740 /* optional: sethi <some immediate>, %g4 */
741 insn = sparc_fetch_instruction (pc);
743 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
746 insn = sparc_fetch_instruction (pc);
750 /* sub %sp, %g1, %g1 */
751 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
752 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
755 insn = sparc_fetch_instruction (pc);
758 /* optional: sethi <some immediate>, %g4 */
759 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
762 insn = sparc_fetch_instruction (pc);
766 /* First possible sequence:
767 [first two instructions above]
768 clr [%g1 - some immediate] */
770 /* clr [%g1 - some immediate] */
771 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
772 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
774 /* Valid stack-check sequence, return the new PC. */
778 /* Second possible sequence: A small number of probes.
779 [first two instructions above]
781 add %g1, -<some immediate>, %g1
783 [repeat the two instructions above any (small) number of times]
784 clr [%g1 - some immediate] */
787 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
788 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
792 /* add %g1, -<some immediate>, %g1 */
793 insn = sparc_fetch_instruction (pc);
795 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
796 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
800 insn = sparc_fetch_instruction (pc);
802 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
803 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
807 /* clr [%g1 - some immediate] */
808 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
809 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
812 /* We found a valid stack-check sequence, return the new PC. */
816 /* Third sequence: A probing loop.
817 [first three instructions above]
821 add %g1, -<some immediate>, %g1
825 And an optional last probe for the remainder:
827 clr [%g4 - some immediate] */
831 /* sub %g1, %g4, %g4 */
832 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
833 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
837 insn = sparc_fetch_instruction (pc);
839 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
840 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
844 insn = sparc_fetch_instruction (pc);
846 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
849 /* add %g1, -<some immediate>, %g1 */
850 insn = sparc_fetch_instruction (pc);
852 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
853 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
857 insn = sparc_fetch_instruction (pc);
859 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
862 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
863 insn = sparc_fetch_instruction (pc);
865 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4
866 && X_RD (insn) == 0 && X_RS1 (insn) == 1
867 && (!X_I(insn) || X_SIMM13 (insn) == 0)))
870 /* We found a valid stack-check sequence, return the new PC. */
872 /* optional: clr [%g4 - some immediate] */
873 insn = sparc_fetch_instruction (pc);
875 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
876 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
882 /* No stack check code in our prologue, return the start_pc. */
886 /* Record the effect of a SAVE instruction on CACHE. */
889 sparc_record_save_insn (struct sparc_frame_cache *cache)
891 /* The frame is set up. */
892 cache->frameless_p = 0;
894 /* The frame pointer contains the CFA. */
895 cache->frame_offset = 0;
897 /* The `local' and `in' registers are all saved. */
898 cache->saved_regs_mask = 0xffff;
900 /* The `out' registers are all renamed. */
901 cache->copied_regs_mask = 0xff;
904 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
905 Bail out early if CURRENT_PC is reached. Return the address where
906 the analysis stopped.
908 We handle both the traditional register window model and the single
909 register window (aka flat) model. */
912 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
913 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
915 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
920 pc = sparc_skip_stack_check (pc);
922 if (current_pc <= pc)
925 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
926 SPARC the linker usually defines a symbol (typically
927 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
928 This symbol makes us end up here with PC pointing at the start of
929 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
930 would do our normal prologue analysis, we would probably conclude
931 that we've got a frame when in reality we don't, since the
932 dynamic linker patches up the first PLT with some code that
933 starts with a SAVE instruction. Patch up PC such that it points
934 at the start of our PLT entry. */
935 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc))
936 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
938 insn = sparc_fetch_instruction (pc);
940 /* Recognize store insns and record their sources. */
941 while (X_OP (insn) == 3
942 && (X_OP3 (insn) == 0x4 /* stw */
943 || X_OP3 (insn) == 0x7 /* std */
944 || X_OP3 (insn) == 0xe) /* stx */
945 && X_RS1 (insn) == SPARC_SP_REGNUM)
947 int regnum = X_RD (insn);
949 /* Recognize stores into the corresponding stack slots. */
950 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
952 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe
953 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS
954 : (regnum - SPARC_L0_REGNUM) * 4))
955 || (!X_I (insn) && regnum == SPARC_L0_REGNUM)))
957 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM));
958 if (X_OP3 (insn) == 0x7)
959 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM));
964 insn = sparc_fetch_instruction (pc + offset);
967 /* Recognize a SETHI insn and record its destination. */
968 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
973 insn = sparc_fetch_instruction (pc + offset);
976 /* Allow for an arithmetic operation on DEST or %g1. */
977 if (X_OP (insn) == 2 && X_I (insn)
978 && (X_RD (insn) == 1 || X_RD (insn) == dest))
982 insn = sparc_fetch_instruction (pc + offset);
985 /* Check for the SAVE instruction that sets up the frame. */
986 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
988 sparc_record_save_insn (cache);
993 /* Check for an arithmetic operation on %sp. */
995 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
996 && X_RS1 (insn) == SPARC_SP_REGNUM
997 && X_RD (insn) == SPARC_SP_REGNUM)
1001 cache->frame_offset = X_SIMM13 (insn);
1002 if (X_OP3 (insn) == 0)
1003 cache->frame_offset = -cache->frame_offset;
1007 insn = sparc_fetch_instruction (pc + offset);
1009 /* Check for an arithmetic operation that sets up the frame. */
1010 if (X_OP (insn) == 2
1011 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
1012 && X_RS1 (insn) == SPARC_SP_REGNUM
1013 && X_RD (insn) == SPARC_FP_REGNUM)
1015 cache->frameless_p = 0;
1016 cache->frame_offset = 0;
1017 /* We could check that the amount subtracted to %sp above is the
1018 same as the one added here, but this seems superfluous. */
1019 cache->copied_regs_mask |= 0x40;
1022 insn = sparc_fetch_instruction (pc + offset);
1025 /* Check for a move (or) operation that copies the return register. */
1026 if (X_OP (insn) == 2
1027 && X_OP3 (insn) == 0x2
1029 && X_RS1 (insn) == SPARC_G0_REGNUM
1030 && X_RS2 (insn) == SPARC_O7_REGNUM
1031 && X_RD (insn) == SPARC_I7_REGNUM)
1033 cache->copied_regs_mask |= 0x80;
1044 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1046 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1047 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
1050 /* Return PC of first real instruction of the function starting at
1054 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1056 struct symtab_and_line sal;
1057 CORE_ADDR func_start, func_end;
1058 struct sparc_frame_cache cache;
1060 /* This is the preferred method, find the end of the prologue by
1061 using the debugging information. */
1062 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
1064 sal = find_pc_line (func_start, 0);
1066 if (sal.end < func_end
1067 && start_pc <= sal.end)
1071 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
1073 /* The psABI says that "Although the first 6 words of arguments
1074 reside in registers, the standard stack frame reserves space for
1075 them.". It also suggests that a function may use that space to
1076 "write incoming arguments 0 to 5" into that space, and that's
1077 indeed what GCC seems to be doing. In that case GCC will
1078 generate debug information that points to the stack slots instead
1079 of the registers, so we should consider the instructions that
1080 write out these incoming arguments onto the stack. */
1084 unsigned long insn = sparc_fetch_instruction (start_pc);
1086 /* Recognize instructions that store incoming arguments into the
1087 corresponding stack slots. */
1088 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04
1089 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM)
1091 int regnum = X_RD (insn);
1093 /* Case of arguments still in %o[0..5]. */
1094 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM
1095 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))
1096 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4)
1102 /* Case of arguments copied into %i[0..5]. */
1103 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM
1104 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM)))
1105 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4)
1118 /* Normal frames. */
1120 struct sparc_frame_cache *
1121 sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
1123 struct sparc_frame_cache *cache;
1126 return (struct sparc_frame_cache *) *this_cache;
1128 cache = sparc_alloc_frame_cache ();
1129 *this_cache = cache;
1131 cache->pc = get_frame_func (this_frame);
1133 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
1134 get_frame_pc (this_frame), cache);
1136 if (cache->frameless_p)
1138 /* This function is frameless, so %fp (%i6) holds the frame
1139 pointer for our calling frame. Use %sp (%o6) as this frame's
1142 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1146 /* For normal frames, %fp (%i6) holds the frame pointer, the
1147 base address for the current stack frame. */
1149 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
1152 cache->base += cache->frame_offset;
1154 if (cache->base & 1)
1155 cache->base += BIAS;
1161 sparc32_struct_return_from_sym (struct symbol *sym)
1163 struct type *type = check_typedef (SYMBOL_TYPE (sym));
1164 enum type_code code = TYPE_CODE (type);
1166 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
1168 type = check_typedef (TYPE_TARGET_TYPE (type));
1169 if (sparc_structure_or_union_p (type)
1170 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1177 struct sparc_frame_cache *
1178 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
1180 struct sparc_frame_cache *cache;
1184 return (struct sparc_frame_cache *) *this_cache;
1186 cache = sparc_frame_cache (this_frame, this_cache);
1188 sym = find_pc_function (cache->pc);
1191 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
1195 /* There is no debugging information for this function to
1196 help us determine whether this function returns a struct
1197 or not. So we rely on another heuristic which is to check
1198 the instruction at the return address and see if this is
1199 an "unimp" instruction. If it is, then it is a struct-return
1203 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1205 pc = get_frame_register_unsigned (this_frame, regnum) + 8;
1206 if (sparc_is_unimp_insn (pc))
1207 cache->struct_return_p = 1;
1214 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
1215 struct frame_id *this_id)
1217 struct sparc_frame_cache *cache =
1218 sparc32_frame_cache (this_frame, this_cache);
1220 /* This marks the outermost frame. */
1221 if (cache->base == 0)
1224 (*this_id) = frame_id_build (cache->base, cache->pc);
1227 static struct value *
1228 sparc32_frame_prev_register (struct frame_info *this_frame,
1229 void **this_cache, int regnum)
1231 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1232 struct sparc_frame_cache *cache =
1233 sparc32_frame_cache (this_frame, this_cache);
1235 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
1237 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
1239 /* If this functions has a Structure, Union or Quad-Precision
1240 return value, we have to skip the UNIMP instruction that encodes
1241 the size of the structure. */
1242 if (cache->struct_return_p)
1246 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1247 pc += get_frame_register_unsigned (this_frame, regnum) + 8;
1248 return frame_unwind_got_constant (this_frame, regnum, pc);
1251 /* Handle StackGhost. */
1253 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1255 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
1257 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1260 /* Read the value in from memory. */
1261 i7 = get_frame_memory_unsigned (this_frame, addr, 4);
1262 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
1266 /* The previous frame's `local' and `in' registers may have been saved
1267 in the register save area. */
1268 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1269 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM))))
1271 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1273 return frame_unwind_got_memory (this_frame, regnum, addr);
1276 /* The previous frame's `out' registers may be accessible as the current
1277 frame's `in' registers. */
1278 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM
1279 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))))
1280 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1282 return frame_unwind_got_register (this_frame, regnum, regnum);
1285 static const struct frame_unwind sparc32_frame_unwind =
1288 default_frame_unwind_stop_reason,
1289 sparc32_frame_this_id,
1290 sparc32_frame_prev_register,
1292 default_frame_sniffer
1297 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1299 struct sparc_frame_cache *cache =
1300 sparc32_frame_cache (this_frame, this_cache);
1305 static const struct frame_base sparc32_frame_base =
1307 &sparc32_frame_unwind,
1308 sparc32_frame_base_address,
1309 sparc32_frame_base_address,
1310 sparc32_frame_base_address
1313 static struct frame_id
1314 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1318 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1321 return frame_id_build (sp, get_frame_pc (this_frame));
1325 /* Extract a function return value of TYPE from REGCACHE, and copy
1326 that into VALBUF. */
1329 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1332 int len = TYPE_LENGTH (type);
1335 gdb_assert (!sparc_structure_or_union_p (type));
1336 gdb_assert (!(sparc_floating_p (type) && len == 16));
1338 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1340 /* Floating return values. */
1341 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1343 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1346 regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8);
1347 regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12);
1351 regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16);
1352 regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20);
1353 regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24);
1354 regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28);
1356 memcpy (valbuf, buf, len);
1360 /* Integral and pointer return values. */
1361 gdb_assert (sparc_integral_or_pointer_p (type));
1363 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1366 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1367 gdb_assert (len == 8);
1368 memcpy (valbuf, buf, 8);
1372 /* Just stripping off any unused bytes should preserve the
1373 signed-ness just fine. */
1374 memcpy (valbuf, buf + 4 - len, len);
1379 /* Store the function return value of type TYPE from VALBUF into
1383 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1384 const gdb_byte *valbuf)
1386 int len = TYPE_LENGTH (type);
1389 gdb_assert (!sparc_structure_or_union_p (type));
1390 gdb_assert (!(sparc_floating_p (type) && len == 16));
1391 gdb_assert (len <= 8);
1393 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1395 /* Floating return values. */
1396 memcpy (buf, valbuf, len);
1397 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1399 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1402 regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8);
1403 regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12);
1407 regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16);
1408 regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20);
1409 regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24);
1410 regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28);
1415 /* Integral and pointer return values. */
1416 gdb_assert (sparc_integral_or_pointer_p (type));
1420 gdb_assert (len == 8);
1421 memcpy (buf, valbuf, 8);
1422 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1426 /* ??? Do we need to do any sign-extension here? */
1427 memcpy (buf + 4 - len, valbuf, len);
1429 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1433 static enum return_value_convention
1434 sparc32_return_value (struct gdbarch *gdbarch, struct value *function,
1435 struct type *type, struct regcache *regcache,
1436 gdb_byte *readbuf, const gdb_byte *writebuf)
1438 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1440 /* The psABI says that "...every stack frame reserves the word at
1441 %fp+64. If a function returns a structure, union, or
1442 quad-precision value, this word should hold the address of the
1443 object into which the return value should be copied." This
1444 guarantees that we can always find the return value, not just
1445 before the function returns. */
1447 if (sparc_structure_or_union_p (type)
1448 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1455 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1456 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1457 read_memory (addr, readbuf, TYPE_LENGTH (type));
1461 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1462 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1463 write_memory (addr, writebuf, TYPE_LENGTH (type));
1466 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1470 sparc32_extract_return_value (type, regcache, readbuf);
1472 sparc32_store_return_value (type, regcache, writebuf);
1474 return RETURN_VALUE_REGISTER_CONVENTION;
1478 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1480 return (sparc_structure_or_union_p (type)
1481 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
1482 || sparc_complex_floating_p (type));
1486 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1488 CORE_ADDR pc = get_frame_address_in_block (this_frame);
1489 struct symbol *sym = find_pc_function (pc);
1492 return sparc32_struct_return_from_sym (sym);
1497 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1498 struct dwarf2_frame_state_reg *reg,
1499 struct frame_info *this_frame)
1505 case SPARC_G0_REGNUM:
1506 /* Since %g0 is always zero, there is no point in saving it, and
1507 people will be inclined omit it from the CFI. Make sure we
1508 don't warn about that. */
1509 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1511 case SPARC_SP_REGNUM:
1512 reg->how = DWARF2_FRAME_REG_CFA;
1514 case SPARC32_PC_REGNUM:
1515 case SPARC32_NPC_REGNUM:
1516 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1518 if (sparc32_dwarf2_struct_return_p (this_frame))
1520 if (regnum == SPARC32_NPC_REGNUM)
1522 reg->loc.offset = off;
1528 /* The SPARC Architecture doesn't have hardware single-step support,
1529 and most operating systems don't implement it either, so we provide
1530 software single-step mechanism. */
1533 sparc_analyze_control_transfer (struct regcache *regcache,
1534 CORE_ADDR pc, CORE_ADDR *npc)
1536 unsigned long insn = sparc_fetch_instruction (pc);
1537 int conditional_p = X_COND (insn) & 0x7;
1538 int branch_p = 0, fused_p = 0;
1539 long offset = 0; /* Must be signed for sign-extend. */
1541 if (X_OP (insn) == 0 && X_OP2 (insn) == 3)
1543 if ((insn & 0x10000000) == 0)
1545 /* Branch on Integer Register with Prediction (BPr). */
1551 /* Compare and Branch */
1554 offset = 4 * X_DISP10 (insn);
1557 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1559 /* Branch on Floating-Point Condition Codes (FBfcc). */
1561 offset = 4 * X_DISP22 (insn);
1563 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1565 /* Branch on Floating-Point Condition Codes with Prediction
1568 offset = 4 * X_DISP19 (insn);
1570 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1572 /* Branch on Integer Condition Codes (Bicc). */
1574 offset = 4 * X_DISP22 (insn);
1576 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1578 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1580 offset = 4 * X_DISP19 (insn);
1582 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1584 struct frame_info *frame = get_current_frame ();
1586 /* Trap instruction (TRAP). */
1587 return gdbarch_tdep (get_regcache_arch (regcache))->step_trap (frame,
1591 /* FIXME: Handle DONE and RETRY instructions. */
1597 /* Fused compare-and-branch instructions are non-delayed,
1598 and do not have an annuling capability. So we need to
1599 always set a breakpoint on both the NPC and the branch
1601 gdb_assert (offset != 0);
1604 else if (conditional_p)
1606 /* For conditional branches, return nPC + 4 iff the annul
1608 return (X_A (insn) ? *npc + 4 : 0);
1612 /* For unconditional branches, return the target if its
1613 specified condition is "always" and return nPC + 4 if the
1614 condition is "never". If the annul bit is 1, set *NPC to
1616 if (X_COND (insn) == 0x0)
1617 pc = *npc, offset = 4;
1629 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1634 static VEC (CORE_ADDR) *
1635 sparc_software_single_step (struct regcache *regcache)
1637 struct gdbarch *arch = get_regcache_arch (regcache);
1638 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1639 CORE_ADDR npc, nnpc;
1641 CORE_ADDR pc, orig_npc;
1642 VEC (CORE_ADDR) *next_pcs = NULL;
1644 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum);
1645 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum);
1647 /* Analyze the instruction at PC. */
1648 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc);
1650 VEC_safe_push (CORE_ADDR, next_pcs, npc);
1653 VEC_safe_push (CORE_ADDR, next_pcs, nnpc);
1655 /* Assert that we have set at least one breakpoint, and that
1656 they're not set at the same spot - unless we're going
1657 from here straight to NULL, i.e. a call or jump to 0. */
1658 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1659 gdb_assert (nnpc != npc || orig_npc == 0);
1665 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1667 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1669 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1670 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1674 /* Iterate over core file register note sections. */
1677 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch,
1678 iterate_over_regset_sections_cb *cb,
1680 const struct regcache *regcache)
1682 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1684 cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
1685 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
1689 static struct gdbarch *
1690 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1692 struct gdbarch_tdep *tdep;
1693 struct gdbarch *gdbarch;
1695 /* If there is already a candidate, use it. */
1696 arches = gdbarch_list_lookup_by_info (arches, &info);
1698 return arches->gdbarch;
1700 /* Allocate space for the new architecture. */
1701 tdep = XCNEW (struct gdbarch_tdep);
1702 gdbarch = gdbarch_alloc (&info, tdep);
1704 tdep->pc_regnum = SPARC32_PC_REGNUM;
1705 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1706 tdep->step_trap = sparc_step_trap;
1708 set_gdbarch_long_double_bit (gdbarch, 128);
1709 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1711 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1712 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1713 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1714 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1715 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1716 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1718 /* Register numbers of various important registers. */
1719 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1720 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1721 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1723 /* Call dummy code. */
1724 set_gdbarch_frame_align (gdbarch, sparc32_frame_align);
1725 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1726 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1727 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1729 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1730 set_gdbarch_stabs_argument_has_addr
1731 (gdbarch, sparc32_stabs_argument_has_addr);
1733 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1735 /* Stack grows downward. */
1736 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1738 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1739 sparc_breakpoint::kind_from_pc);
1740 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1741 sparc_breakpoint::bp_from_kind);
1743 set_gdbarch_frame_args_skip (gdbarch, 8);
1745 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1747 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1748 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1750 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1752 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1754 frame_base_set_default (gdbarch, &sparc32_frame_base);
1756 /* Hook in the DWARF CFI frame unwinder. */
1757 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1758 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1759 StackGhost issues have been resolved. */
1761 /* Hook in ABI-specific overrides, if they have been registered. */
1762 gdbarch_init_osabi (info, gdbarch);
1764 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1766 /* If we have register sets, enable the generic core file support. */
1768 set_gdbarch_iterate_over_regset_sections
1769 (gdbarch, sparc_iterate_over_regset_sections);
1771 register_sparc_ravenscar_ops (gdbarch);
1776 /* Helper functions for dealing with register windows. */
1779 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1781 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1782 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1789 /* Registers are 64-bit. */
1792 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1794 if (regnum == i || regnum == -1)
1796 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1798 /* Handle StackGhost. */
1799 if (i == SPARC_I7_REGNUM)
1801 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1804 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1805 store_unsigned_integer (buf + offset, 8, byte_order,
1809 regcache_raw_supply (regcache, i, buf);
1815 /* Registers are 32-bit. Toss any sign-extension of the stack
1819 /* Clear out the top half of the temporary buffer, and put the
1820 register value in the bottom half if we're in 64-bit mode. */
1821 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1827 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1829 if (regnum == i || regnum == -1)
1831 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1834 /* Handle StackGhost. */
1835 if (i == SPARC_I7_REGNUM)
1837 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1840 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1841 store_unsigned_integer (buf + offset, 4, byte_order,
1845 regcache_raw_supply (regcache, i, buf);
1852 sparc_collect_rwindow (const struct regcache *regcache,
1853 CORE_ADDR sp, int regnum)
1855 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1856 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1863 /* Registers are 64-bit. */
1866 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1868 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1870 regcache_raw_collect (regcache, i, buf);
1872 /* Handle StackGhost. */
1873 if (i == SPARC_I7_REGNUM)
1875 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1878 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1879 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie);
1882 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1888 /* Registers are 32-bit. Toss any sign-extension of the stack
1892 /* Only use the bottom half if we're in 64-bit mode. */
1893 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1896 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1898 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1900 regcache_raw_collect (regcache, i, buf);
1902 /* Handle StackGhost. */
1903 if (i == SPARC_I7_REGNUM)
1905 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1908 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1909 store_unsigned_integer (buf + offset, 4, byte_order,
1913 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1920 /* Helper functions for dealing with register sets. */
1923 sparc32_supply_gregset (const struct sparc_gregmap *gregmap,
1924 struct regcache *regcache,
1925 int regnum, const void *gregs)
1927 const gdb_byte *regs = (const gdb_byte *) gregs;
1928 gdb_byte zero[4] = { 0 };
1931 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1932 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1933 regs + gregmap->r_psr_offset);
1935 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1936 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1937 regs + gregmap->r_pc_offset);
1939 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1940 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1941 regs + gregmap->r_npc_offset);
1943 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1944 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1945 regs + gregmap->r_y_offset);
1947 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1948 regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero);
1950 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1952 int offset = gregmap->r_g1_offset;
1954 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1956 if (regnum == i || regnum == -1)
1957 regcache_raw_supply (regcache, i, regs + offset);
1962 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1964 /* Not all of the register set variants include Locals and
1965 Inputs. For those that don't, we read them off the stack. */
1966 if (gregmap->r_l0_offset == -1)
1970 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1971 sparc_supply_rwindow (regcache, sp, regnum);
1975 int offset = gregmap->r_l0_offset;
1977 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1979 if (regnum == i || regnum == -1)
1980 regcache_raw_supply (regcache, i, regs + offset);
1988 sparc32_collect_gregset (const struct sparc_gregmap *gregmap,
1989 const struct regcache *regcache,
1990 int regnum, void *gregs)
1992 gdb_byte *regs = (gdb_byte *) gregs;
1995 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1996 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1997 regs + gregmap->r_psr_offset);
1999 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
2000 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
2001 regs + gregmap->r_pc_offset);
2003 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
2004 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
2005 regs + gregmap->r_npc_offset);
2007 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
2008 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
2009 regs + gregmap->r_y_offset);
2011 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
2013 int offset = gregmap->r_g1_offset;
2015 /* %g0 is always zero. */
2016 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
2018 if (regnum == i || regnum == -1)
2019 regcache_raw_collect (regcache, i, regs + offset);
2024 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
2026 /* Not all of the register set variants include Locals and
2027 Inputs. For those that don't, we read them off the stack. */
2028 if (gregmap->r_l0_offset != -1)
2030 int offset = gregmap->r_l0_offset;
2032 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2034 if (regnum == i || regnum == -1)
2035 regcache_raw_collect (regcache, i, regs + offset);
2043 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap,
2044 struct regcache *regcache,
2045 int regnum, const void *fpregs)
2047 const gdb_byte *regs = (const gdb_byte *) fpregs;
2050 for (i = 0; i < 32; i++)
2052 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2053 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i,
2054 regs + fpregmap->r_f0_offset + (i * 4));
2057 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2058 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM,
2059 regs + fpregmap->r_fsr_offset);
2063 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap,
2064 const struct regcache *regcache,
2065 int regnum, void *fpregs)
2067 gdb_byte *regs = (gdb_byte *) fpregs;
2070 for (i = 0; i < 32; i++)
2072 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2073 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i,
2074 regs + fpregmap->r_f0_offset + (i * 4));
2077 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2078 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM,
2079 regs + fpregmap->r_fsr_offset);
2085 /* From <machine/reg.h>. */
2086 const struct sparc_gregmap sparc32_sunos4_gregmap =
2098 const struct sparc_fpregmap sparc32_sunos4_fpregmap =
2104 const struct sparc_fpregmap sparc32_bsd_fpregmap =
2111 /* Provide a prototype to silence -Wmissing-prototypes. */
2112 void _initialize_sparc_tdep (void);
2115 _initialize_sparc_tdep (void)
2117 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);