1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
36 #include "target-descriptions.h"
39 #include "sparc-tdep.h"
40 #include "sparc-ravenscar-thread.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Macros to identify some instructions. */
91 /* RETURN (RETT in V8) */
92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
94 /* Fetch the instruction at PC. Instructions are always big-endian
95 even if the processor operates in little-endian mode. */
98 sparc_fetch_instruction (CORE_ADDR pc)
104 /* If we can't read the instruction at PC, return zero. */
105 if (target_read_memory (pc, buf, sizeof (buf)))
109 for (i = 0; i < sizeof (buf); i++)
110 insn = (insn << 8) | buf[i];
115 /* Return non-zero if the instruction corresponding to PC is an "unimp"
119 sparc_is_unimp_insn (CORE_ADDR pc)
121 const unsigned long insn = sparc_fetch_instruction (pc);
123 return ((insn & 0xc1c00000) == 0);
126 /* Return non-zero if the instruction corresponding to PC is an
127 "annulled" branch, i.e. the annul bit is set. */
130 sparc_is_annulled_branch_insn (CORE_ADDR pc)
132 /* The branch instructions featuring an annul bit can be identified
133 by the following bit patterns:
136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
137 OP2=2: Branch on Integer Condition Codes (Bcc).
138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
139 OP2=6: Branch on FP Condition Codes (FBcc).
141 Branch on Integer Register with Prediction (BPr).
143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
144 coprocessor branch instructions (Op2=7). */
146 const unsigned long insn = sparc_fetch_instruction (pc);
147 const unsigned op2 = X_OP2 (insn);
149 if ((X_OP (insn) == 0)
150 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
151 || ((op2 == 3) && ((insn & 0x10000000) == 0))))
157 /* OpenBSD/sparc includes StackGhost, which according to the author's
158 website http://stackghost.cerias.purdue.edu "... transparently and
159 automatically protects applications' stack frames; more
160 specifically, it guards the return pointers. The protection
161 mechanisms require no application source or binary modification and
162 imposes only a negligible performance penalty."
164 The same website provides the following description of how
167 "StackGhost interfaces with the kernel trap handler that would
168 normally write out registers to the stack and the handler that
169 would read them back in. By XORing a cookie into the
170 return-address saved in the user stack when it is actually written
171 to the stack, and then XOR it out when the return-address is pulled
172 from the stack, StackGhost can cause attacker corrupted return
173 pointers to behave in a manner the attacker cannot predict.
174 StackGhost can also use several unused bits in the return pointer
175 to detect a smashed return pointer and abort the process."
177 For GDB this means that whenever we're reading %i7 from a stack
178 frame's window save area, we'll have to XOR the cookie.
180 More information on StackGuard can be found on in:
182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
183 Stack Protection." 2001. Published in USENIX Security Symposium
186 /* Fetch StackGhost Per-Process XOR cookie. */
189 sparc_fetch_wcookie (struct gdbarch *gdbarch)
191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
192 struct target_ops *ops = target_stack;
196 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
200 /* We should have either an 32-bit or an 64-bit cookie. */
201 gdb_assert (len == 4 || len == 8);
203 return extract_unsigned_integer (buf, len, byte_order);
207 /* The functions on this page are intended to be used to classify
208 function arguments. */
210 /* Check whether TYPE is "Integral or Pointer". */
213 sparc_integral_or_pointer_p (const struct type *type)
215 int len = TYPE_LENGTH (type);
217 switch (TYPE_CODE (type))
223 case TYPE_CODE_RANGE:
224 /* We have byte, half-word, word and extended-word/doubleword
225 integral types. The doubleword is an extension to the
226 original 32-bit ABI by the SCD 2.4.x. */
227 return (len == 1 || len == 2 || len == 4 || len == 8);
230 case TYPE_CODE_RVALUE_REF:
231 /* Allow either 32-bit or 64-bit pointers. */
232 return (len == 4 || len == 8);
240 /* Check whether TYPE is "Floating". */
243 sparc_floating_p (const struct type *type)
245 switch (TYPE_CODE (type))
249 int len = TYPE_LENGTH (type);
250 return (len == 4 || len == 8 || len == 16);
259 /* Check whether TYPE is "Complex Floating". */
262 sparc_complex_floating_p (const struct type *type)
264 switch (TYPE_CODE (type))
266 case TYPE_CODE_COMPLEX:
268 int len = TYPE_LENGTH (type);
269 return (len == 8 || len == 16 || len == 32);
278 /* Check whether TYPE is "Structure or Union".
280 In terms of Ada subprogram calls, arrays are treated the same as
281 struct and union types. So this function also returns non-zero
285 sparc_structure_or_union_p (const struct type *type)
287 switch (TYPE_CODE (type))
289 case TYPE_CODE_STRUCT:
290 case TYPE_CODE_UNION:
291 case TYPE_CODE_ARRAY:
300 /* Return true if TYPE is returned by memory, false if returned by
304 sparc_structure_return_p (const struct type *type)
306 if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))
308 /* Float vectors are always returned by memory. */
309 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type))))
311 /* Integer vectors are returned by memory if the vector size
312 is greater than 8 bytes long. */
313 return (TYPE_LENGTH (type) > 8);
316 if (sparc_floating_p (type))
318 /* Floating point types are passed by register for size 4 and
319 8 bytes, and by memory for size 16 bytes. */
320 return (TYPE_LENGTH (type) == 16);
323 /* Other than that, only aggregates of all sizes get returned by
325 return sparc_structure_or_union_p (type);
328 /* Return true if arguments of the given TYPE are passed by
329 memory; false if returned by register. */
332 sparc_arg_by_memory_p (const struct type *type)
334 if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))
336 /* Float vectors are always passed by memory. */
337 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type))))
339 /* Integer vectors are passed by memory if the vector size
340 is greater than 8 bytes long. */
341 return (TYPE_LENGTH (type) > 8);
344 /* Floats are passed by register for size 4 and 8 bytes, and by memory
345 for size 16 bytes. */
346 if (sparc_floating_p (type))
347 return (TYPE_LENGTH (type) == 16);
349 /* Complex floats and aggregates of all sizes are passed by memory. */
350 if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type))
353 /* Everything else gets passed by register. */
357 /* Register information. */
358 #define SPARC32_FPU_REGISTERS \
359 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
360 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
361 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
362 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
363 #define SPARC32_CP0_REGISTERS \
364 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
366 static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS };
367 static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS };
368 static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS };
370 static const char *sparc32_register_names[] =
372 SPARC_CORE_REGISTERS,
373 SPARC32_FPU_REGISTERS,
374 SPARC32_CP0_REGISTERS
377 /* Total number of registers. */
378 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
380 /* We provide the aliases %d0..%d30 for the floating registers as
381 "psuedo" registers. */
383 static const char *sparc32_pseudo_register_names[] =
385 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
386 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
389 /* Total number of pseudo registers. */
390 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
392 /* Return the name of pseudo register REGNUM. */
395 sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
397 regnum -= gdbarch_num_regs (gdbarch);
399 if (regnum < SPARC32_NUM_PSEUDO_REGS)
400 return sparc32_pseudo_register_names[regnum];
402 internal_error (__FILE__, __LINE__,
403 _("sparc32_pseudo_register_name: bad register number %d"),
407 /* Return the name of register REGNUM. */
410 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
412 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
413 return tdesc_register_name (gdbarch, regnum);
415 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
416 return sparc32_register_names[regnum];
418 return sparc32_pseudo_register_name (gdbarch, regnum);
421 /* Construct types for ISA-specific registers. */
424 sparc_psr_type (struct gdbarch *gdbarch)
426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
428 if (!tdep->sparc_psr_type)
432 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32);
433 append_flags_type_flag (type, 5, "ET");
434 append_flags_type_flag (type, 6, "PS");
435 append_flags_type_flag (type, 7, "S");
436 append_flags_type_flag (type, 12, "EF");
437 append_flags_type_flag (type, 13, "EC");
439 tdep->sparc_psr_type = type;
442 return tdep->sparc_psr_type;
446 sparc_fsr_type (struct gdbarch *gdbarch)
448 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
450 if (!tdep->sparc_fsr_type)
454 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32);
455 append_flags_type_flag (type, 0, "NXA");
456 append_flags_type_flag (type, 1, "DZA");
457 append_flags_type_flag (type, 2, "UFA");
458 append_flags_type_flag (type, 3, "OFA");
459 append_flags_type_flag (type, 4, "NVA");
460 append_flags_type_flag (type, 5, "NXC");
461 append_flags_type_flag (type, 6, "DZC");
462 append_flags_type_flag (type, 7, "UFC");
463 append_flags_type_flag (type, 8, "OFC");
464 append_flags_type_flag (type, 9, "NVC");
465 append_flags_type_flag (type, 22, "NS");
466 append_flags_type_flag (type, 23, "NXM");
467 append_flags_type_flag (type, 24, "DZM");
468 append_flags_type_flag (type, 25, "UFM");
469 append_flags_type_flag (type, 26, "OFM");
470 append_flags_type_flag (type, 27, "NVM");
472 tdep->sparc_fsr_type = type;
475 return tdep->sparc_fsr_type;
478 /* Return the GDB type object for the "standard" data type of data in
479 pseudo register REGNUM. */
482 sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
484 regnum -= gdbarch_num_regs (gdbarch);
486 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
487 return builtin_type (gdbarch)->builtin_double;
489 internal_error (__FILE__, __LINE__,
490 _("sparc32_pseudo_register_type: bad register number %d"),
494 /* Return the GDB type object for the "standard" data type of data in
498 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
500 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
501 return tdesc_register_type (gdbarch, regnum);
503 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
504 return builtin_type (gdbarch)->builtin_float;
506 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
507 return builtin_type (gdbarch)->builtin_data_ptr;
509 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
510 return builtin_type (gdbarch)->builtin_func_ptr;
512 if (regnum == SPARC32_PSR_REGNUM)
513 return sparc_psr_type (gdbarch);
515 if (regnum == SPARC32_FSR_REGNUM)
516 return sparc_fsr_type (gdbarch);
518 if (regnum >= gdbarch_num_regs (gdbarch))
519 return sparc32_pseudo_register_type (gdbarch, regnum);
521 return builtin_type (gdbarch)->builtin_int32;
524 static enum register_status
525 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
526 readable_regcache *regcache,
527 int regnum, gdb_byte *buf)
529 enum register_status status;
531 regnum -= gdbarch_num_regs (gdbarch);
532 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
534 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
535 status = regcache->raw_read (regnum, buf);
536 if (status == REG_VALID)
537 status = regcache->raw_read (regnum + 1, buf + 4);
542 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
543 struct regcache *regcache,
544 int regnum, const gdb_byte *buf)
546 regnum -= gdbarch_num_regs (gdbarch);
547 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
549 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
550 regcache->raw_write (regnum, buf);
551 regcache->raw_write (regnum + 1, buf + 4);
554 /* Implement the stack_frame_destroyed_p gdbarch method. */
557 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
559 /* This function must return true if we are one instruction after an
560 instruction that destroyed the stack frame of the current
561 function. The SPARC instructions used to restore the callers
562 stack frame are RESTORE and RETURN/RETT.
564 Of these RETURN/RETT is a branch instruction and thus we return
565 true if we are in its delay slot.
567 RESTORE is almost always found in the delay slot of a branch
568 instruction that transfers control to the caller, such as JMPL.
569 Thus the next instruction is in the caller frame and we don't
570 need to do anything about it. */
572 unsigned int insn = sparc_fetch_instruction (pc - 4);
574 return X_RETTURN (insn);
579 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
581 /* The ABI requires double-word alignment. */
582 return address & ~0x7;
586 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
588 struct value **args, int nargs,
589 struct type *value_type,
590 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
591 struct regcache *regcache)
593 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
598 if (using_struct_return (gdbarch, NULL, value_type))
602 /* This is an UNIMP instruction. */
603 store_unsigned_integer (buf, 4, byte_order,
604 TYPE_LENGTH (value_type) & 0x1fff);
605 write_memory (sp - 8, buf, 4);
613 sparc32_store_arguments (struct regcache *regcache, int nargs,
614 struct value **args, CORE_ADDR sp,
615 int struct_return, CORE_ADDR struct_addr)
617 struct gdbarch *gdbarch = regcache->arch ();
618 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
619 /* Number of words in the "parameter array". */
620 int num_elements = 0;
624 for (i = 0; i < nargs; i++)
626 struct type *type = value_type (args[i]);
627 int len = TYPE_LENGTH (type);
629 if (sparc_arg_by_memory_p (type))
631 /* Structure, Union and Quad-Precision Arguments. */
634 /* Use doubleword alignment for these values. That's always
635 correct, and wasting a few bytes shouldn't be a problem. */
638 write_memory (sp, value_contents (args[i]), len);
639 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
642 else if (sparc_floating_p (type))
644 /* Floating arguments. */
645 gdb_assert (len == 4 || len == 8);
646 num_elements += (len / 4);
650 /* Arguments passed via the General Purpose Registers. */
651 num_elements += ((len + 3) / 4);
655 /* Always allocate at least six words. */
656 sp -= std::max (6, num_elements) * 4;
658 /* The psABI says that "Software convention requires space for the
659 struct/union return value pointer, even if the word is unused." */
662 /* The psABI says that "Although software convention and the
663 operating system require every stack frame to be doubleword
667 for (i = 0; i < nargs; i++)
669 const bfd_byte *valbuf = value_contents (args[i]);
670 struct type *type = value_type (args[i]);
671 int len = TYPE_LENGTH (type);
676 memset (buf, 0, 4 - len);
677 memcpy (buf + 4 - len, valbuf, len);
682 gdb_assert (len == 4 || len == 8);
686 int regnum = SPARC_O0_REGNUM + element;
688 regcache->cooked_write (regnum, valbuf);
689 if (len > 4 && element < 5)
690 regcache->cooked_write (regnum + 1, valbuf + 4);
693 /* Always store the argument in memory. */
694 write_memory (sp + 4 + element * 4, valbuf, len);
698 gdb_assert (element == num_elements);
704 store_unsigned_integer (buf, 4, byte_order, struct_addr);
705 write_memory (sp, buf, 4);
712 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
713 struct regcache *regcache, CORE_ADDR bp_addr,
714 int nargs, struct value **args, CORE_ADDR sp,
715 int struct_return, CORE_ADDR struct_addr)
717 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
719 /* Set return address. */
720 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
722 /* Set up function arguments. */
723 sp = sparc32_store_arguments (regcache, nargs, args, sp,
724 struct_return, struct_addr);
726 /* Allocate the 16-word window save area. */
729 /* Stack should be doubleword aligned at this point. */
730 gdb_assert (sp % 8 == 0);
732 /* Finally, update the stack pointer. */
733 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
739 /* Use the program counter to determine the contents and size of a
740 breakpoint instruction. Return a pointer to a string of bytes that
741 encode a breakpoint instruction, store the length of the string in
742 *LEN and optionally adjust *PC to point to the correct memory
743 location for inserting the breakpoint. */
744 constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
746 typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint;
749 /* Allocate and initialize a frame cache. */
751 static struct sparc_frame_cache *
752 sparc_alloc_frame_cache (void)
754 struct sparc_frame_cache *cache;
756 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
762 /* Frameless until proven otherwise. */
763 cache->frameless_p = 1;
764 cache->frame_offset = 0;
765 cache->saved_regs_mask = 0;
766 cache->copied_regs_mask = 0;
767 cache->struct_return_p = 0;
772 /* GCC generates several well-known sequences of instructions at the begining
773 of each function prologue when compiling with -fstack-check. If one of
774 such sequences starts at START_PC, then return the address of the
775 instruction immediately past this sequence. Otherwise, return START_PC. */
778 sparc_skip_stack_check (const CORE_ADDR start_pc)
780 CORE_ADDR pc = start_pc;
782 int probing_loop = 0;
784 /* With GCC, all stack checking sequences begin with the same two
785 instructions, plus an optional one in the case of a probing loop:
787 sethi <some immediate>, %g1
792 sethi <some immediate>, %g1
793 sethi <some immediate>, %g4
798 sethi <some immediate>, %g1
800 sethi <some immediate>, %g4
802 If the optional instruction is found (setting g4), assume that a
803 probing loop will follow. */
805 /* sethi <some immediate>, %g1 */
806 insn = sparc_fetch_instruction (pc);
808 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
811 /* optional: sethi <some immediate>, %g4 */
812 insn = sparc_fetch_instruction (pc);
814 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
817 insn = sparc_fetch_instruction (pc);
821 /* sub %sp, %g1, %g1 */
822 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
823 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
826 insn = sparc_fetch_instruction (pc);
829 /* optional: sethi <some immediate>, %g4 */
830 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
833 insn = sparc_fetch_instruction (pc);
837 /* First possible sequence:
838 [first two instructions above]
839 clr [%g1 - some immediate] */
841 /* clr [%g1 - some immediate] */
842 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
843 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
845 /* Valid stack-check sequence, return the new PC. */
849 /* Second possible sequence: A small number of probes.
850 [first two instructions above]
852 add %g1, -<some immediate>, %g1
854 [repeat the two instructions above any (small) number of times]
855 clr [%g1 - some immediate] */
858 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
859 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
863 /* add %g1, -<some immediate>, %g1 */
864 insn = sparc_fetch_instruction (pc);
866 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
867 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
871 insn = sparc_fetch_instruction (pc);
873 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
874 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
878 /* clr [%g1 - some immediate] */
879 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
880 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
883 /* We found a valid stack-check sequence, return the new PC. */
887 /* Third sequence: A probing loop.
888 [first three instructions above]
892 add %g1, -<some immediate>, %g1
896 And an optional last probe for the remainder:
898 clr [%g4 - some immediate] */
902 /* sub %g1, %g4, %g4 */
903 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
904 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
908 insn = sparc_fetch_instruction (pc);
910 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
911 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
915 insn = sparc_fetch_instruction (pc);
917 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
920 /* add %g1, -<some immediate>, %g1 */
921 insn = sparc_fetch_instruction (pc);
923 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
924 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
928 insn = sparc_fetch_instruction (pc);
930 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
933 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
934 insn = sparc_fetch_instruction (pc);
936 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4
937 && X_RD (insn) == 0 && X_RS1 (insn) == 1
938 && (!X_I(insn) || X_SIMM13 (insn) == 0)))
941 /* We found a valid stack-check sequence, return the new PC. */
943 /* optional: clr [%g4 - some immediate] */
944 insn = sparc_fetch_instruction (pc);
946 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
947 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
953 /* No stack check code in our prologue, return the start_pc. */
957 /* Record the effect of a SAVE instruction on CACHE. */
960 sparc_record_save_insn (struct sparc_frame_cache *cache)
962 /* The frame is set up. */
963 cache->frameless_p = 0;
965 /* The frame pointer contains the CFA. */
966 cache->frame_offset = 0;
968 /* The `local' and `in' registers are all saved. */
969 cache->saved_regs_mask = 0xffff;
971 /* The `out' registers are all renamed. */
972 cache->copied_regs_mask = 0xff;
975 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
976 Bail out early if CURRENT_PC is reached. Return the address where
977 the analysis stopped.
979 We handle both the traditional register window model and the single
980 register window (aka flat) model. */
983 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
984 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
986 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
991 pc = sparc_skip_stack_check (pc);
993 if (current_pc <= pc)
996 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
997 SPARC the linker usually defines a symbol (typically
998 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
999 This symbol makes us end up here with PC pointing at the start of
1000 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
1001 would do our normal prologue analysis, we would probably conclude
1002 that we've got a frame when in reality we don't, since the
1003 dynamic linker patches up the first PLT with some code that
1004 starts with a SAVE instruction. Patch up PC such that it points
1005 at the start of our PLT entry. */
1006 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc))
1007 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
1009 insn = sparc_fetch_instruction (pc);
1011 /* Recognize store insns and record their sources. */
1012 while (X_OP (insn) == 3
1013 && (X_OP3 (insn) == 0x4 /* stw */
1014 || X_OP3 (insn) == 0x7 /* std */
1015 || X_OP3 (insn) == 0xe) /* stx */
1016 && X_RS1 (insn) == SPARC_SP_REGNUM)
1018 int regnum = X_RD (insn);
1020 /* Recognize stores into the corresponding stack slots. */
1021 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1023 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe
1024 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS
1025 : (regnum - SPARC_L0_REGNUM) * 4))
1026 || (!X_I (insn) && regnum == SPARC_L0_REGNUM)))
1028 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM));
1029 if (X_OP3 (insn) == 0x7)
1030 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM));
1035 insn = sparc_fetch_instruction (pc + offset);
1038 /* Recognize a SETHI insn and record its destination. */
1039 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
1044 insn = sparc_fetch_instruction (pc + offset);
1047 /* Allow for an arithmetic operation on DEST or %g1. */
1048 if (X_OP (insn) == 2 && X_I (insn)
1049 && (X_RD (insn) == 1 || X_RD (insn) == dest))
1053 insn = sparc_fetch_instruction (pc + offset);
1056 /* Check for the SAVE instruction that sets up the frame. */
1057 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
1059 sparc_record_save_insn (cache);
1064 /* Check for an arithmetic operation on %sp. */
1065 if (X_OP (insn) == 2
1066 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
1067 && X_RS1 (insn) == SPARC_SP_REGNUM
1068 && X_RD (insn) == SPARC_SP_REGNUM)
1072 cache->frame_offset = X_SIMM13 (insn);
1073 if (X_OP3 (insn) == 0)
1074 cache->frame_offset = -cache->frame_offset;
1078 insn = sparc_fetch_instruction (pc + offset);
1080 /* Check for an arithmetic operation that sets up the frame. */
1081 if (X_OP (insn) == 2
1082 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
1083 && X_RS1 (insn) == SPARC_SP_REGNUM
1084 && X_RD (insn) == SPARC_FP_REGNUM)
1086 cache->frameless_p = 0;
1087 cache->frame_offset = 0;
1088 /* We could check that the amount subtracted to %sp above is the
1089 same as the one added here, but this seems superfluous. */
1090 cache->copied_regs_mask |= 0x40;
1093 insn = sparc_fetch_instruction (pc + offset);
1096 /* Check for a move (or) operation that copies the return register. */
1097 if (X_OP (insn) == 2
1098 && X_OP3 (insn) == 0x2
1100 && X_RS1 (insn) == SPARC_G0_REGNUM
1101 && X_RS2 (insn) == SPARC_O7_REGNUM
1102 && X_RD (insn) == SPARC_I7_REGNUM)
1104 cache->copied_regs_mask |= 0x80;
1115 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1117 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1118 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
1121 /* Return PC of first real instruction of the function starting at
1125 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1127 struct symtab_and_line sal;
1128 CORE_ADDR func_start, func_end;
1129 struct sparc_frame_cache cache;
1131 /* This is the preferred method, find the end of the prologue by
1132 using the debugging information. */
1133 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
1135 sal = find_pc_line (func_start, 0);
1137 if (sal.end < func_end
1138 && start_pc <= sal.end)
1142 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
1144 /* The psABI says that "Although the first 6 words of arguments
1145 reside in registers, the standard stack frame reserves space for
1146 them.". It also suggests that a function may use that space to
1147 "write incoming arguments 0 to 5" into that space, and that's
1148 indeed what GCC seems to be doing. In that case GCC will
1149 generate debug information that points to the stack slots instead
1150 of the registers, so we should consider the instructions that
1151 write out these incoming arguments onto the stack. */
1155 unsigned long insn = sparc_fetch_instruction (start_pc);
1157 /* Recognize instructions that store incoming arguments into the
1158 corresponding stack slots. */
1159 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04
1160 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM)
1162 int regnum = X_RD (insn);
1164 /* Case of arguments still in %o[0..5]. */
1165 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM
1166 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))
1167 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4)
1173 /* Case of arguments copied into %i[0..5]. */
1174 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM
1175 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM)))
1176 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4)
1189 /* Normal frames. */
1191 struct sparc_frame_cache *
1192 sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
1194 struct sparc_frame_cache *cache;
1197 return (struct sparc_frame_cache *) *this_cache;
1199 cache = sparc_alloc_frame_cache ();
1200 *this_cache = cache;
1202 cache->pc = get_frame_func (this_frame);
1204 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
1205 get_frame_pc (this_frame), cache);
1207 if (cache->frameless_p)
1209 /* This function is frameless, so %fp (%i6) holds the frame
1210 pointer for our calling frame. Use %sp (%o6) as this frame's
1213 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1217 /* For normal frames, %fp (%i6) holds the frame pointer, the
1218 base address for the current stack frame. */
1220 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
1223 cache->base += cache->frame_offset;
1225 if (cache->base & 1)
1226 cache->base += BIAS;
1232 sparc32_struct_return_from_sym (struct symbol *sym)
1234 struct type *type = check_typedef (SYMBOL_TYPE (sym));
1235 enum type_code code = TYPE_CODE (type);
1237 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
1239 type = check_typedef (TYPE_TARGET_TYPE (type));
1240 if (sparc_structure_or_union_p (type)
1241 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1248 struct sparc_frame_cache *
1249 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
1251 struct sparc_frame_cache *cache;
1255 return (struct sparc_frame_cache *) *this_cache;
1257 cache = sparc_frame_cache (this_frame, this_cache);
1259 sym = find_pc_function (cache->pc);
1262 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
1266 /* There is no debugging information for this function to
1267 help us determine whether this function returns a struct
1268 or not. So we rely on another heuristic which is to check
1269 the instruction at the return address and see if this is
1270 an "unimp" instruction. If it is, then it is a struct-return
1274 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1276 pc = get_frame_register_unsigned (this_frame, regnum) + 8;
1277 if (sparc_is_unimp_insn (pc))
1278 cache->struct_return_p = 1;
1285 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
1286 struct frame_id *this_id)
1288 struct sparc_frame_cache *cache =
1289 sparc32_frame_cache (this_frame, this_cache);
1291 /* This marks the outermost frame. */
1292 if (cache->base == 0)
1295 (*this_id) = frame_id_build (cache->base, cache->pc);
1298 static struct value *
1299 sparc32_frame_prev_register (struct frame_info *this_frame,
1300 void **this_cache, int regnum)
1302 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1303 struct sparc_frame_cache *cache =
1304 sparc32_frame_cache (this_frame, this_cache);
1306 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
1308 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
1310 /* If this functions has a Structure, Union or Quad-Precision
1311 return value, we have to skip the UNIMP instruction that encodes
1312 the size of the structure. */
1313 if (cache->struct_return_p)
1317 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1318 pc += get_frame_register_unsigned (this_frame, regnum) + 8;
1319 return frame_unwind_got_constant (this_frame, regnum, pc);
1322 /* Handle StackGhost. */
1324 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1326 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
1328 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1331 /* Read the value in from memory. */
1332 i7 = get_frame_memory_unsigned (this_frame, addr, 4);
1333 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
1337 /* The previous frame's `local' and `in' registers may have been saved
1338 in the register save area. */
1339 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1340 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM))))
1342 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1344 return frame_unwind_got_memory (this_frame, regnum, addr);
1347 /* The previous frame's `out' registers may be accessible as the current
1348 frame's `in' registers. */
1349 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM
1350 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))))
1351 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1353 return frame_unwind_got_register (this_frame, regnum, regnum);
1356 static const struct frame_unwind sparc32_frame_unwind =
1359 default_frame_unwind_stop_reason,
1360 sparc32_frame_this_id,
1361 sparc32_frame_prev_register,
1363 default_frame_sniffer
1368 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1370 struct sparc_frame_cache *cache =
1371 sparc32_frame_cache (this_frame, this_cache);
1376 static const struct frame_base sparc32_frame_base =
1378 &sparc32_frame_unwind,
1379 sparc32_frame_base_address,
1380 sparc32_frame_base_address,
1381 sparc32_frame_base_address
1384 static struct frame_id
1385 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1389 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1392 return frame_id_build (sp, get_frame_pc (this_frame));
1396 /* Extract a function return value of TYPE from REGCACHE, and copy
1397 that into VALBUF. */
1400 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1403 int len = TYPE_LENGTH (type);
1406 gdb_assert (!sparc_structure_return_p (type));
1408 if (sparc_floating_p (type) || sparc_complex_floating_p (type)
1409 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
1411 /* Floating return values. */
1412 regcache->cooked_read (SPARC_F0_REGNUM, buf);
1414 regcache->cooked_read (SPARC_F1_REGNUM, buf + 4);
1417 regcache->cooked_read (SPARC_F2_REGNUM, buf + 8);
1418 regcache->cooked_read (SPARC_F3_REGNUM, buf + 12);
1422 regcache->cooked_read (SPARC_F4_REGNUM, buf + 16);
1423 regcache->cooked_read (SPARC_F5_REGNUM, buf + 20);
1424 regcache->cooked_read (SPARC_F6_REGNUM, buf + 24);
1425 regcache->cooked_read (SPARC_F7_REGNUM, buf + 28);
1427 memcpy (valbuf, buf, len);
1431 /* Integral and pointer return values. */
1432 gdb_assert (sparc_integral_or_pointer_p (type));
1434 regcache->cooked_read (SPARC_O0_REGNUM, buf);
1437 regcache->cooked_read (SPARC_O1_REGNUM, buf + 4);
1438 gdb_assert (len == 8);
1439 memcpy (valbuf, buf, 8);
1443 /* Just stripping off any unused bytes should preserve the
1444 signed-ness just fine. */
1445 memcpy (valbuf, buf + 4 - len, len);
1450 /* Store the function return value of type TYPE from VALBUF into
1454 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1455 const gdb_byte *valbuf)
1457 int len = TYPE_LENGTH (type);
1460 gdb_assert (!sparc_structure_return_p (type));
1462 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1464 /* Floating return values. */
1465 memcpy (buf, valbuf, len);
1466 regcache->cooked_write (SPARC_F0_REGNUM, buf);
1468 regcache->cooked_write (SPARC_F1_REGNUM, buf + 4);
1471 regcache->cooked_write (SPARC_F2_REGNUM, buf + 8);
1472 regcache->cooked_write (SPARC_F3_REGNUM, buf + 12);
1476 regcache->cooked_write (SPARC_F4_REGNUM, buf + 16);
1477 regcache->cooked_write (SPARC_F5_REGNUM, buf + 20);
1478 regcache->cooked_write (SPARC_F6_REGNUM, buf + 24);
1479 regcache->cooked_write (SPARC_F7_REGNUM, buf + 28);
1484 /* Integral and pointer return values. */
1485 gdb_assert (sparc_integral_or_pointer_p (type));
1489 gdb_assert (len == 8);
1490 memcpy (buf, valbuf, 8);
1491 regcache->cooked_write (SPARC_O1_REGNUM, buf + 4);
1495 /* ??? Do we need to do any sign-extension here? */
1496 memcpy (buf + 4 - len, valbuf, len);
1498 regcache->cooked_write (SPARC_O0_REGNUM, buf);
1502 static enum return_value_convention
1503 sparc32_return_value (struct gdbarch *gdbarch, struct value *function,
1504 struct type *type, struct regcache *regcache,
1505 gdb_byte *readbuf, const gdb_byte *writebuf)
1507 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1509 /* The psABI says that "...every stack frame reserves the word at
1510 %fp+64. If a function returns a structure, union, or
1511 quad-precision value, this word should hold the address of the
1512 object into which the return value should be copied." This
1513 guarantees that we can always find the return value, not just
1514 before the function returns. */
1516 if (sparc_structure_return_p (type))
1523 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1524 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1525 read_memory (addr, readbuf, TYPE_LENGTH (type));
1529 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1530 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1531 write_memory (addr, writebuf, TYPE_LENGTH (type));
1534 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1538 sparc32_extract_return_value (type, regcache, readbuf);
1540 sparc32_store_return_value (type, regcache, writebuf);
1542 return RETURN_VALUE_REGISTER_CONVENTION;
1546 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1548 return (sparc_structure_or_union_p (type)
1549 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
1550 || sparc_complex_floating_p (type));
1554 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1556 CORE_ADDR pc = get_frame_address_in_block (this_frame);
1557 struct symbol *sym = find_pc_function (pc);
1560 return sparc32_struct_return_from_sym (sym);
1565 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1566 struct dwarf2_frame_state_reg *reg,
1567 struct frame_info *this_frame)
1573 case SPARC_G0_REGNUM:
1574 /* Since %g0 is always zero, there is no point in saving it, and
1575 people will be inclined omit it from the CFI. Make sure we
1576 don't warn about that. */
1577 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1579 case SPARC_SP_REGNUM:
1580 reg->how = DWARF2_FRAME_REG_CFA;
1582 case SPARC32_PC_REGNUM:
1583 case SPARC32_NPC_REGNUM:
1584 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1586 if (sparc32_dwarf2_struct_return_p (this_frame))
1588 if (regnum == SPARC32_NPC_REGNUM)
1590 reg->loc.offset = off;
1595 /* Implement the execute_dwarf_cfa_vendor_op method. */
1598 sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1599 struct dwarf2_frame_state *fs)
1601 /* Only DW_CFA_GNU_window_save is expected on SPARC. */
1602 if (op != DW_CFA_GNU_window_save)
1606 int size = register_size (gdbarch, 0);
1608 fs->regs.alloc_regs (32);
1609 for (reg = 8; reg < 16; reg++)
1611 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG;
1612 fs->regs.reg[reg].loc.reg = reg + 16;
1614 for (reg = 16; reg < 32; reg++)
1616 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET;
1617 fs->regs.reg[reg].loc.offset = (reg - 16) * size;
1624 /* The SPARC Architecture doesn't have hardware single-step support,
1625 and most operating systems don't implement it either, so we provide
1626 software single-step mechanism. */
1629 sparc_analyze_control_transfer (struct regcache *regcache,
1630 CORE_ADDR pc, CORE_ADDR *npc)
1632 unsigned long insn = sparc_fetch_instruction (pc);
1633 int conditional_p = X_COND (insn) & 0x7;
1634 int branch_p = 0, fused_p = 0;
1635 long offset = 0; /* Must be signed for sign-extend. */
1637 if (X_OP (insn) == 0 && X_OP2 (insn) == 3)
1639 if ((insn & 0x10000000) == 0)
1641 /* Branch on Integer Register with Prediction (BPr). */
1647 /* Compare and Branch */
1650 offset = 4 * X_DISP10 (insn);
1653 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1655 /* Branch on Floating-Point Condition Codes (FBfcc). */
1657 offset = 4 * X_DISP22 (insn);
1659 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1661 /* Branch on Floating-Point Condition Codes with Prediction
1664 offset = 4 * X_DISP19 (insn);
1666 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1668 /* Branch on Integer Condition Codes (Bicc). */
1670 offset = 4 * X_DISP22 (insn);
1672 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1674 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1676 offset = 4 * X_DISP19 (insn);
1678 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1680 struct frame_info *frame = get_current_frame ();
1682 /* Trap instruction (TRAP). */
1683 return gdbarch_tdep (regcache->arch ())->step_trap (frame,
1687 /* FIXME: Handle DONE and RETRY instructions. */
1693 /* Fused compare-and-branch instructions are non-delayed,
1694 and do not have an annuling capability. So we need to
1695 always set a breakpoint on both the NPC and the branch
1697 gdb_assert (offset != 0);
1700 else if (conditional_p)
1702 /* For conditional branches, return nPC + 4 iff the annul
1704 return (X_A (insn) ? *npc + 4 : 0);
1708 /* For unconditional branches, return the target if its
1709 specified condition is "always" and return nPC + 4 if the
1710 condition is "never". If the annul bit is 1, set *NPC to
1712 if (X_COND (insn) == 0x0)
1713 pc = *npc, offset = 4;
1725 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1730 static std::vector<CORE_ADDR>
1731 sparc_software_single_step (struct regcache *regcache)
1733 struct gdbarch *arch = regcache->arch ();
1734 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1735 CORE_ADDR npc, nnpc;
1737 CORE_ADDR pc, orig_npc;
1738 std::vector<CORE_ADDR> next_pcs;
1740 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum);
1741 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum);
1743 /* Analyze the instruction at PC. */
1744 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc);
1746 next_pcs.push_back (npc);
1749 next_pcs.push_back (nnpc);
1751 /* Assert that we have set at least one breakpoint, and that
1752 they're not set at the same spot - unless we're going
1753 from here straight to NULL, i.e. a call or jump to 0. */
1754 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1755 gdb_assert (nnpc != npc || orig_npc == 0);
1761 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1763 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
1765 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1766 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1770 /* Iterate over core file register note sections. */
1773 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch,
1774 iterate_over_regset_sections_cb *cb,
1776 const struct regcache *regcache)
1778 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1780 cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
1781 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
1786 validate_tdesc_registers (const struct target_desc *tdesc,
1787 struct tdesc_arch_data *tdesc_data,
1788 const char *feature_name,
1789 const char *register_names[],
1790 unsigned int registers_num,
1791 unsigned int reg_start)
1794 const struct tdesc_feature *feature;
1796 feature = tdesc_find_feature (tdesc, feature_name);
1797 if (feature == NULL)
1800 for (unsigned int i = 0; i < registers_num; i++)
1801 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1808 static struct gdbarch *
1809 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1811 struct gdbarch_tdep *tdep;
1812 const struct target_desc *tdesc = info.target_desc;
1813 struct gdbarch *gdbarch;
1816 /* If there is already a candidate, use it. */
1817 arches = gdbarch_list_lookup_by_info (arches, &info);
1819 return arches->gdbarch;
1821 /* Allocate space for the new architecture. */
1822 tdep = XCNEW (struct gdbarch_tdep);
1823 gdbarch = gdbarch_alloc (&info, tdep);
1825 tdep->pc_regnum = SPARC32_PC_REGNUM;
1826 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1827 tdep->step_trap = sparc_step_trap;
1828 tdep->fpu_register_names = sparc32_fpu_register_names;
1829 tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names);
1830 tdep->cp0_register_names = sparc32_cp0_register_names;
1831 tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names);
1833 set_gdbarch_long_double_bit (gdbarch, 128);
1834 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1836 set_gdbarch_wchar_bit (gdbarch, 16);
1837 set_gdbarch_wchar_signed (gdbarch, 1);
1839 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1840 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1841 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1842 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1843 set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name);
1844 set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type);
1845 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1846 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1848 /* Register numbers of various important registers. */
1849 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1850 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1851 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1853 /* Call dummy code. */
1854 set_gdbarch_frame_align (gdbarch, sparc32_frame_align);
1855 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1856 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1857 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1859 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1860 set_gdbarch_stabs_argument_has_addr
1861 (gdbarch, sparc32_stabs_argument_has_addr);
1863 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1865 /* Stack grows downward. */
1866 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1868 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1869 sparc_breakpoint::kind_from_pc);
1870 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1871 sparc_breakpoint::bp_from_kind);
1873 set_gdbarch_frame_args_skip (gdbarch, 8);
1875 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1876 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1878 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1880 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1882 frame_base_set_default (gdbarch, &sparc32_frame_base);
1884 /* Hook in the DWARF CFI frame unwinder. */
1885 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1886 /* Register DWARF vendor CFI handler. */
1887 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
1888 sparc_execute_dwarf_cfa_vendor_op);
1889 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1890 StackGhost issues have been resolved. */
1892 /* Hook in ABI-specific overrides, if they have been registered. */
1893 gdbarch_init_osabi (info, gdbarch);
1895 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1897 if (tdesc_has_registers (tdesc))
1899 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
1901 /* Validate that the descriptor provides the mandatory registers
1902 and allocate their numbers. */
1903 valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
1904 "org.gnu.gdb.sparc.cpu",
1905 sparc_core_register_names,
1906 ARRAY_SIZE (sparc_core_register_names),
1908 valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
1909 "org.gnu.gdb.sparc.fpu",
1910 tdep->fpu_register_names,
1911 tdep->fpu_registers_num,
1913 valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
1914 "org.gnu.gdb.sparc.cp0",
1915 tdep->cp0_register_names,
1916 tdep->cp0_registers_num,
1918 + tdep->fpu_registers_num);
1921 tdesc_data_cleanup (tdesc_data);
1925 /* Target description may have changed. */
1926 info.tdesc_data = tdesc_data;
1927 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1930 /* If we have register sets, enable the generic core file support. */
1932 set_gdbarch_iterate_over_regset_sections
1933 (gdbarch, sparc_iterate_over_regset_sections);
1935 register_sparc_ravenscar_ops (gdbarch);
1940 /* Helper functions for dealing with register windows. */
1943 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1945 struct gdbarch *gdbarch = regcache->arch ();
1946 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1953 /* Registers are 64-bit. */
1956 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1958 if (regnum == i || regnum == -1)
1960 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1962 /* Handle StackGhost. */
1963 if (i == SPARC_I7_REGNUM)
1965 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1968 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1969 store_unsigned_integer (buf + offset, 8, byte_order,
1973 regcache->raw_supply (i, buf);
1979 /* Registers are 32-bit. Toss any sign-extension of the stack
1983 /* Clear out the top half of the temporary buffer, and put the
1984 register value in the bottom half if we're in 64-bit mode. */
1985 if (gdbarch_ptr_bit (regcache->arch ()) == 64)
1991 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1993 if (regnum == i || regnum == -1)
1995 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1998 /* Handle StackGhost. */
1999 if (i == SPARC_I7_REGNUM)
2001 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
2004 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
2005 store_unsigned_integer (buf + offset, 4, byte_order,
2009 regcache->raw_supply (i, buf);
2016 sparc_collect_rwindow (const struct regcache *regcache,
2017 CORE_ADDR sp, int regnum)
2019 struct gdbarch *gdbarch = regcache->arch ();
2020 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2027 /* Registers are 64-bit. */
2030 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2032 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
2034 regcache_raw_collect (regcache, i, buf);
2036 /* Handle StackGhost. */
2037 if (i == SPARC_I7_REGNUM)
2039 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
2042 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
2043 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie);
2046 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
2052 /* Registers are 32-bit. Toss any sign-extension of the stack
2056 /* Only use the bottom half if we're in 64-bit mode. */
2057 if (gdbarch_ptr_bit (regcache->arch ()) == 64)
2060 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2062 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
2064 regcache_raw_collect (regcache, i, buf);
2066 /* Handle StackGhost. */
2067 if (i == SPARC_I7_REGNUM)
2069 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
2072 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
2073 store_unsigned_integer (buf + offset, 4, byte_order,
2077 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
2084 /* Helper functions for dealing with register sets. */
2087 sparc32_supply_gregset (const struct sparc_gregmap *gregmap,
2088 struct regcache *regcache,
2089 int regnum, const void *gregs)
2091 const gdb_byte *regs = (const gdb_byte *) gregs;
2092 gdb_byte zero[4] = { 0 };
2095 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
2096 regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset);
2098 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
2099 regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset);
2101 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
2102 regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset);
2104 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
2105 regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset);
2107 if (regnum == SPARC_G0_REGNUM || regnum == -1)
2108 regcache->raw_supply (SPARC_G0_REGNUM, &zero);
2110 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
2112 int offset = gregmap->r_g1_offset;
2114 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
2116 if (regnum == i || regnum == -1)
2117 regcache->raw_supply (i, regs + offset);
2122 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
2124 /* Not all of the register set variants include Locals and
2125 Inputs. For those that don't, we read them off the stack. */
2126 if (gregmap->r_l0_offset == -1)
2130 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
2131 sparc_supply_rwindow (regcache, sp, regnum);
2135 int offset = gregmap->r_l0_offset;
2137 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2139 if (regnum == i || regnum == -1)
2140 regcache->raw_supply (i, regs + offset);
2148 sparc32_collect_gregset (const struct sparc_gregmap *gregmap,
2149 const struct regcache *regcache,
2150 int regnum, void *gregs)
2152 gdb_byte *regs = (gdb_byte *) gregs;
2155 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
2156 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
2157 regs + gregmap->r_psr_offset);
2159 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
2160 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
2161 regs + gregmap->r_pc_offset);
2163 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
2164 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
2165 regs + gregmap->r_npc_offset);
2167 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
2168 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
2169 regs + gregmap->r_y_offset);
2171 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
2173 int offset = gregmap->r_g1_offset;
2175 /* %g0 is always zero. */
2176 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
2178 if (regnum == i || regnum == -1)
2179 regcache_raw_collect (regcache, i, regs + offset);
2184 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
2186 /* Not all of the register set variants include Locals and
2187 Inputs. For those that don't, we read them off the stack. */
2188 if (gregmap->r_l0_offset != -1)
2190 int offset = gregmap->r_l0_offset;
2192 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2194 if (regnum == i || regnum == -1)
2195 regcache_raw_collect (regcache, i, regs + offset);
2203 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap,
2204 struct regcache *regcache,
2205 int regnum, const void *fpregs)
2207 const gdb_byte *regs = (const gdb_byte *) fpregs;
2210 for (i = 0; i < 32; i++)
2212 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2213 regcache->raw_supply (SPARC_F0_REGNUM + i,
2214 regs + fpregmap->r_f0_offset + (i * 4));
2217 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2218 regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset);
2222 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap,
2223 const struct regcache *regcache,
2224 int regnum, void *fpregs)
2226 gdb_byte *regs = (gdb_byte *) fpregs;
2229 for (i = 0; i < 32; i++)
2231 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2232 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i,
2233 regs + fpregmap->r_f0_offset + (i * 4));
2236 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2237 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM,
2238 regs + fpregmap->r_fsr_offset);
2244 /* From <machine/reg.h>. */
2245 const struct sparc_gregmap sparc32_sunos4_gregmap =
2257 const struct sparc_fpregmap sparc32_sunos4_fpregmap =
2263 const struct sparc_fpregmap sparc32_bsd_fpregmap =
2270 _initialize_sparc_tdep (void)
2272 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);