1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "gdb_string.h"
42 #include "sparc-tdep.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-recision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc, buf, sizeof (buf)))
106 for (i = 0; i < sizeof (buf); i++)
107 insn = (insn << 8) | buf[i];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc)
118 const unsigned long insn = sparc_fetch_instruction (pc);
120 return ((insn & 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (void)
157 struct target_ops *ops = ¤t_target;
161 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
165 /* We should have either an 32-bit or an 64-bit cookie. */
166 gdb_assert (len == 4 || len == 8);
168 return extract_unsigned_integer (buf, len);
172 /* The functions on this page are intended to be used to classify
173 function arguments. */
175 /* Check whether TYPE is "Integral or Pointer". */
178 sparc_integral_or_pointer_p (const struct type *type)
180 int len = TYPE_LENGTH (type);
182 switch (TYPE_CODE (type))
188 case TYPE_CODE_RANGE:
189 /* We have byte, half-word, word and extended-word/doubleword
190 integral types. The doubleword is an extension to the
191 original 32-bit ABI by the SCD 2.4.x. */
192 return (len == 1 || len == 2 || len == 4 || len == 8);
195 /* Allow either 32-bit or 64-bit pointers. */
196 return (len == 4 || len == 8);
204 /* Check whether TYPE is "Floating". */
207 sparc_floating_p (const struct type *type)
209 switch (TYPE_CODE (type))
213 int len = TYPE_LENGTH (type);
214 return (len == 4 || len == 8 || len == 16);
223 /* Check whether TYPE is "Structure or Union". */
226 sparc_structure_or_union_p (const struct type *type)
228 switch (TYPE_CODE (type))
230 case TYPE_CODE_STRUCT:
231 case TYPE_CODE_UNION:
240 /* Register information. */
242 static const char *sparc32_register_names[] =
244 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
245 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
246 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
247 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
249 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
250 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
251 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
252 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
254 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
257 /* Total number of registers. */
258 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
260 /* We provide the aliases %d0..%d30 for the floating registers as
261 "psuedo" registers. */
263 static const char *sparc32_pseudo_register_names[] =
265 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
266 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
269 /* Total number of pseudo registers. */
270 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
272 /* Return the name of register REGNUM. */
275 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
277 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
278 return sparc32_register_names[regnum];
280 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
281 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
288 struct type *sparc_psr_type;
291 struct type *sparc_fsr_type;
293 /* Construct types for ISA-specific registers. */
296 sparc_init_types (void)
300 type = init_flags_type ("builtin_type_sparc_psr", 4);
301 append_flags_type_flag (type, 5, "ET");
302 append_flags_type_flag (type, 6, "PS");
303 append_flags_type_flag (type, 7, "S");
304 append_flags_type_flag (type, 12, "EF");
305 append_flags_type_flag (type, 13, "EC");
306 sparc_psr_type = type;
308 type = init_flags_type ("builtin_type_sparc_fsr", 4);
309 append_flags_type_flag (type, 0, "NXA");
310 append_flags_type_flag (type, 1, "DZA");
311 append_flags_type_flag (type, 2, "UFA");
312 append_flags_type_flag (type, 3, "OFA");
313 append_flags_type_flag (type, 4, "NVA");
314 append_flags_type_flag (type, 5, "NXC");
315 append_flags_type_flag (type, 6, "DZC");
316 append_flags_type_flag (type, 7, "UFC");
317 append_flags_type_flag (type, 8, "OFC");
318 append_flags_type_flag (type, 9, "NVC");
319 append_flags_type_flag (type, 22, "NS");
320 append_flags_type_flag (type, 23, "NXM");
321 append_flags_type_flag (type, 24, "DZM");
322 append_flags_type_flag (type, 25, "UFM");
323 append_flags_type_flag (type, 26, "OFM");
324 append_flags_type_flag (type, 27, "NVM");
325 sparc_fsr_type = type;
328 /* Return the GDB type object for the "standard" data type of data in
332 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
334 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
335 return builtin_type_float;
337 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
338 return builtin_type_double;
340 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
341 return builtin_type_void_data_ptr;
343 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
344 return builtin_type_void_func_ptr;
346 if (regnum == SPARC32_PSR_REGNUM)
347 return sparc_psr_type;
349 if (regnum == SPARC32_FSR_REGNUM)
350 return sparc_fsr_type;
352 return builtin_type_int32;
356 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
357 struct regcache *regcache,
358 int regnum, gdb_byte *buf)
360 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
362 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
363 regcache_raw_read (regcache, regnum, buf);
364 regcache_raw_read (regcache, regnum + 1, buf + 4);
368 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
369 struct regcache *regcache,
370 int regnum, const gdb_byte *buf)
372 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
374 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
375 regcache_raw_write (regcache, regnum, buf);
376 regcache_raw_write (regcache, regnum + 1, buf + 4);
381 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
383 struct value **args, int nargs,
384 struct type *value_type,
385 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
386 struct regcache *regcache)
391 if (using_struct_return (NULL, value_type))
395 /* This is an UNIMP instruction. */
396 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
397 write_memory (sp - 8, buf, 4);
405 sparc32_store_arguments (struct regcache *regcache, int nargs,
406 struct value **args, CORE_ADDR sp,
407 int struct_return, CORE_ADDR struct_addr)
409 /* Number of words in the "parameter array". */
410 int num_elements = 0;
414 for (i = 0; i < nargs; i++)
416 struct type *type = value_type (args[i]);
417 int len = TYPE_LENGTH (type);
419 if (sparc_structure_or_union_p (type)
420 || (sparc_floating_p (type) && len == 16))
422 /* Structure, Union and Quad-Precision Arguments. */
425 /* Use doubleword alignment for these values. That's always
426 correct, and wasting a few bytes shouldn't be a problem. */
429 write_memory (sp, value_contents (args[i]), len);
430 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
433 else if (sparc_floating_p (type))
435 /* Floating arguments. */
436 gdb_assert (len == 4 || len == 8);
437 num_elements += (len / 4);
441 /* Integral and pointer arguments. */
442 gdb_assert (sparc_integral_or_pointer_p (type));
445 args[i] = value_cast (builtin_type_int32, args[i]);
446 num_elements += ((len + 3) / 4);
450 /* Always allocate at least six words. */
451 sp -= max (6, num_elements) * 4;
453 /* The psABI says that "Software convention requires space for the
454 struct/union return value pointer, even if the word is unused." */
457 /* The psABI says that "Although software convention and the
458 operating system require every stack frame to be doubleword
462 for (i = 0; i < nargs; i++)
464 const bfd_byte *valbuf = value_contents (args[i]);
465 struct type *type = value_type (args[i]);
466 int len = TYPE_LENGTH (type);
468 gdb_assert (len == 4 || len == 8);
472 int regnum = SPARC_O0_REGNUM + element;
474 regcache_cooked_write (regcache, regnum, valbuf);
475 if (len > 4 && element < 5)
476 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
479 /* Always store the argument in memory. */
480 write_memory (sp + 4 + element * 4, valbuf, len);
484 gdb_assert (element == num_elements);
490 store_unsigned_integer (buf, 4, struct_addr);
491 write_memory (sp, buf, 4);
498 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
499 struct regcache *regcache, CORE_ADDR bp_addr,
500 int nargs, struct value **args, CORE_ADDR sp,
501 int struct_return, CORE_ADDR struct_addr)
503 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
505 /* Set return address. */
506 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
508 /* Set up function arguments. */
509 sp = sparc32_store_arguments (regcache, nargs, args, sp,
510 struct_return, struct_addr);
512 /* Allocate the 16-word window save area. */
515 /* Stack should be doubleword aligned at this point. */
516 gdb_assert (sp % 8 == 0);
518 /* Finally, update the stack pointer. */
519 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
525 /* Use the program counter to determine the contents and size of a
526 breakpoint instruction. Return a pointer to a string of bytes that
527 encode a breakpoint instruction, store the length of the string in
528 *LEN and optionally adjust *PC to point to the correct memory
529 location for inserting the breakpoint. */
531 static const gdb_byte *
532 sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
534 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
536 *len = sizeof (break_insn);
541 /* Allocate and initialize a frame cache. */
543 static struct sparc_frame_cache *
544 sparc_alloc_frame_cache (void)
546 struct sparc_frame_cache *cache;
549 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
555 /* Frameless until proven otherwise. */
556 cache->frameless_p = 1;
558 cache->struct_return_p = 0;
563 /* GCC generates several well-known sequences of instructions at the begining
564 of each function prologue when compiling with -fstack-check. If one of
565 such sequences starts at START_PC, then return the address of the
566 instruction immediately past this sequence. Otherwise, return START_PC. */
569 sparc_skip_stack_check (const CORE_ADDR start_pc)
571 CORE_ADDR pc = start_pc;
573 int offset_stack_checking_sequence = 0;
575 /* With GCC, all stack checking sequences begin with the same two
578 /* sethi <some immediate>,%g1 */
579 insn = sparc_fetch_instruction (pc);
581 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
584 /* sub %sp, %g1, %g1 */
585 insn = sparc_fetch_instruction (pc);
587 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
588 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
591 insn = sparc_fetch_instruction (pc);
594 /* First possible sequence:
595 [first two instructions above]
596 clr [%g1 - some immediate] */
598 /* clr [%g1 - some immediate] */
599 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
600 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
602 /* Valid stack-check sequence, return the new PC. */
606 /* Second possible sequence: A small number of probes.
607 [first two instructions above]
609 add %g1, -<some immediate>, %g1
611 [repeat the two instructions above any (small) number of times]
612 clr [%g1 - some immediate] */
615 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
616 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
620 /* add %g1, -<some immediate>, %g1 */
621 insn = sparc_fetch_instruction (pc);
623 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
624 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
628 insn = sparc_fetch_instruction (pc);
630 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
631 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
635 /* clr [%g1 - some immediate] */
636 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
637 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
640 /* We found a valid stack-check sequence, return the new PC. */
644 /* Third sequence: A probing loop.
645 [first two instructions above]
646 sethi <some immediate>, %g4
650 add %g1, -<some immediate>, %g1
653 clr [%g4 - some immediate] */
655 /* sethi <some immediate>, %g4 */
656 else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
658 /* sub %g1, %g4, %g4 */
659 insn = sparc_fetch_instruction (pc);
661 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
662 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
666 insn = sparc_fetch_instruction (pc);
668 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
669 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
673 insn = sparc_fetch_instruction (pc);
675 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
678 /* add %g1, -<some immediate>, %g1 */
679 insn = sparc_fetch_instruction (pc);
681 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
682 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
686 insn = sparc_fetch_instruction (pc);
688 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
692 insn = sparc_fetch_instruction (pc);
694 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
695 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
698 /* clr [%g4 - some immediate] */
699 insn = sparc_fetch_instruction (pc);
701 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
702 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
705 /* We found a valid stack-check sequence, return the new PC. */
709 /* No stack check code in our prologue, return the start_pc. */
714 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
715 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
717 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
722 pc = sparc_skip_stack_check (pc);
724 if (current_pc <= pc)
727 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
728 SPARC the linker usually defines a symbol (typically
729 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
730 This symbol makes us end up here with PC pointing at the start of
731 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
732 would do our normal prologue analysis, we would probably conclude
733 that we've got a frame when in reality we don't, since the
734 dynamic linker patches up the first PLT with some code that
735 starts with a SAVE instruction. Patch up PC such that it points
736 at the start of our PLT entry. */
737 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
738 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
740 insn = sparc_fetch_instruction (pc);
742 /* Recognize a SETHI insn and record its destination. */
743 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
748 insn = sparc_fetch_instruction (pc + 4);
751 /* Allow for an arithmetic operation on DEST or %g1. */
752 if (X_OP (insn) == 2 && X_I (insn)
753 && (X_RD (insn) == 1 || X_RD (insn) == dest))
757 insn = sparc_fetch_instruction (pc + 8);
760 /* Check for the SAVE instruction that sets up the frame. */
761 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
763 cache->frameless_p = 0;
764 return pc + offset + 4;
771 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
773 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
774 return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
777 /* Return PC of first real instruction of the function starting at
781 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
783 struct symtab_and_line sal;
784 CORE_ADDR func_start, func_end;
785 struct sparc_frame_cache cache;
787 /* This is the preferred method, find the end of the prologue by
788 using the debugging information. */
789 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
791 sal = find_pc_line (func_start, 0);
793 if (sal.end < func_end
794 && start_pc <= sal.end)
798 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
800 /* The psABI says that "Although the first 6 words of arguments
801 reside in registers, the standard stack frame reserves space for
802 them.". It also suggests that a function may use that space to
803 "write incoming arguments 0 to 5" into that space, and that's
804 indeed what GCC seems to be doing. In that case GCC will
805 generate debug information that points to the stack slots instead
806 of the registers, so we should consider the instructions that
807 write out these incoming arguments onto the stack. Of course we
808 only need to do this if we have a stack frame. */
810 while (!cache.frameless_p)
812 unsigned long insn = sparc_fetch_instruction (start_pc);
814 /* Recognize instructions that store incoming arguments in
815 %i0...%i5 into the corresponding stack slot. */
816 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
817 && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
818 && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
832 struct sparc_frame_cache *
833 sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
835 struct sparc_frame_cache *cache;
840 cache = sparc_alloc_frame_cache ();
843 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
845 sparc_analyze_prologue (get_frame_arch (next_frame), cache->pc,
846 frame_pc_unwind (next_frame), cache);
848 if (cache->frameless_p)
850 /* This function is frameless, so %fp (%i6) holds the frame
851 pointer for our calling frame. Use %sp (%o6) as this frame's
854 frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
858 /* For normal frames, %fp (%i6) holds the frame pointer, the
859 base address for the current stack frame. */
861 frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
871 sparc32_struct_return_from_sym (struct symbol *sym)
873 struct type *type = check_typedef (SYMBOL_TYPE (sym));
874 enum type_code code = TYPE_CODE (type);
876 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
878 type = check_typedef (TYPE_TARGET_TYPE (type));
879 if (sparc_structure_or_union_p (type)
880 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
887 struct sparc_frame_cache *
888 sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
890 struct sparc_frame_cache *cache;
896 cache = sparc_frame_cache (next_frame, this_cache);
898 sym = find_pc_function (cache->pc);
901 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
905 /* There is no debugging information for this function to
906 help us determine whether this function returns a struct
907 or not. So we rely on another heuristic which is to check
908 the instruction at the return address and see if this is
909 an "unimp" instruction. If it is, then it is a struct-return
912 int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
914 pc = frame_unwind_register_unsigned (next_frame, regnum) + 8;
915 if (sparc_is_unimp_insn (pc))
916 cache->struct_return_p = 1;
923 sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
924 struct frame_id *this_id)
926 struct sparc_frame_cache *cache =
927 sparc32_frame_cache (next_frame, this_cache);
929 /* This marks the outermost frame. */
930 if (cache->base == 0)
933 (*this_id) = frame_id_build (cache->base, cache->pc);
937 sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
938 int regnum, int *optimizedp,
939 enum lval_type *lvalp, CORE_ADDR *addrp,
940 int *realnump, gdb_byte *valuep)
942 struct sparc_frame_cache *cache =
943 sparc32_frame_cache (next_frame, this_cache);
945 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
953 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
955 /* If this functions has a Structure, Union or
956 Quad-Precision return value, we have to skip the UNIMP
957 instruction that encodes the size of the structure. */
958 if (cache->struct_return_p)
961 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
962 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
963 store_unsigned_integer (valuep, 4, pc);
968 /* Handle StackGhost. */
970 ULONGEST wcookie = sparc_fetch_wcookie ();
972 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
980 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
983 /* Read the value in from memory. */
984 i7 = get_frame_memory_unsigned (next_frame, addr, 4);
985 store_unsigned_integer (valuep, 4, i7 ^ wcookie);
991 /* The previous frame's `local' and `in' registers have been saved
992 in the register save area. */
993 if (!cache->frameless_p
994 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
997 *lvalp = lval_memory;
998 *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1002 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1004 /* Read the value in from memory. */
1005 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1010 /* The previous frame's `out' registers are accessable as the
1011 current frame's `in' registers. */
1012 if (!cache->frameless_p
1013 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
1014 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1017 *lvalp = lval_register;
1021 frame_unwind_register (next_frame, (*realnump), valuep);
1024 static const struct frame_unwind sparc32_frame_unwind =
1027 sparc32_frame_this_id,
1028 sparc32_frame_prev_register
1031 static const struct frame_unwind *
1032 sparc32_frame_sniffer (struct frame_info *next_frame)
1034 return &sparc32_frame_unwind;
1039 sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
1041 struct sparc_frame_cache *cache =
1042 sparc32_frame_cache (next_frame, this_cache);
1047 static const struct frame_base sparc32_frame_base =
1049 &sparc32_frame_unwind,
1050 sparc32_frame_base_address,
1051 sparc32_frame_base_address,
1052 sparc32_frame_base_address
1055 static struct frame_id
1056 sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1060 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
1063 return frame_id_build (sp, frame_pc_unwind (next_frame));
1067 /* Extract from an array REGBUF containing the (raw) register state, a
1068 function return value of TYPE, and copy that into VALBUF. */
1071 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1074 int len = TYPE_LENGTH (type);
1077 gdb_assert (!sparc_structure_or_union_p (type));
1078 gdb_assert (!(sparc_floating_p (type) && len == 16));
1080 if (sparc_floating_p (type))
1082 /* Floating return values. */
1083 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1085 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1086 memcpy (valbuf, buf, len);
1090 /* Integral and pointer return values. */
1091 gdb_assert (sparc_integral_or_pointer_p (type));
1093 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1096 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1097 gdb_assert (len == 8);
1098 memcpy (valbuf, buf, 8);
1102 /* Just stripping off any unused bytes should preserve the
1103 signed-ness just fine. */
1104 memcpy (valbuf, buf + 4 - len, len);
1109 /* Write into the appropriate registers a function return value stored
1110 in VALBUF of type TYPE. */
1113 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1114 const gdb_byte *valbuf)
1116 int len = TYPE_LENGTH (type);
1119 gdb_assert (!sparc_structure_or_union_p (type));
1120 gdb_assert (!(sparc_floating_p (type) && len == 16));
1122 if (sparc_floating_p (type))
1124 /* Floating return values. */
1125 memcpy (buf, valbuf, len);
1126 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1128 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1132 /* Integral and pointer return values. */
1133 gdb_assert (sparc_integral_or_pointer_p (type));
1137 gdb_assert (len == 8);
1138 memcpy (buf, valbuf, 8);
1139 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1143 /* ??? Do we need to do any sign-extension here? */
1144 memcpy (buf + 4 - len, valbuf, len);
1146 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1150 static enum return_value_convention
1151 sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type,
1152 struct type *type, struct regcache *regcache,
1153 gdb_byte *readbuf, const gdb_byte *writebuf)
1155 /* The psABI says that "...every stack frame reserves the word at
1156 %fp+64. If a function returns a structure, union, or
1157 quad-precision value, this word should hold the address of the
1158 object into which the return value should be copied." This
1159 guarantees that we can always find the return value, not just
1160 before the function returns. */
1162 if (sparc_structure_or_union_p (type)
1163 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1170 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1171 addr = read_memory_unsigned_integer (sp + 64, 4);
1172 read_memory (addr, readbuf, TYPE_LENGTH (type));
1175 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1179 sparc32_extract_return_value (type, regcache, readbuf);
1181 sparc32_store_return_value (type, regcache, writebuf);
1183 return RETURN_VALUE_REGISTER_CONVENTION;
1187 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1189 return (sparc_structure_or_union_p (type)
1190 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1194 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1196 CORE_ADDR pc = get_frame_address_in_block (this_frame, NORMAL_FRAME);
1197 struct symbol *sym = find_pc_function (pc);
1200 return sparc32_struct_return_from_sym (sym);
1205 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1206 struct dwarf2_frame_state_reg *reg,
1207 struct frame_info *this_frame)
1213 case SPARC_G0_REGNUM:
1214 /* Since %g0 is always zero, there is no point in saving it, and
1215 people will be inclined omit it from the CFI. Make sure we
1216 don't warn about that. */
1217 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1219 case SPARC_SP_REGNUM:
1220 reg->how = DWARF2_FRAME_REG_CFA;
1222 case SPARC32_PC_REGNUM:
1223 case SPARC32_NPC_REGNUM:
1224 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1226 if (sparc32_dwarf2_struct_return_p (this_frame))
1228 if (regnum == SPARC32_NPC_REGNUM)
1230 reg->loc.offset = off;
1236 /* The SPARC Architecture doesn't have hardware single-step support,
1237 and most operating systems don't implement it either, so we provide
1238 software single-step mechanism. */
1241 sparc_analyze_control_transfer (struct frame_info *frame,
1242 CORE_ADDR pc, CORE_ADDR *npc)
1244 unsigned long insn = sparc_fetch_instruction (pc);
1245 int conditional_p = X_COND (insn) & 0x7;
1247 long offset = 0; /* Must be signed for sign-extend. */
1249 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1251 /* Branch on Integer Register with Prediction (BPr). */
1255 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1257 /* Branch on Floating-Point Condition Codes (FBfcc). */
1259 offset = 4 * X_DISP22 (insn);
1261 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1263 /* Branch on Floating-Point Condition Codes with Prediction
1266 offset = 4 * X_DISP19 (insn);
1268 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1270 /* Branch on Integer Condition Codes (Bicc). */
1272 offset = 4 * X_DISP22 (insn);
1274 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1276 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1278 offset = 4 * X_DISP19 (insn);
1280 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1282 /* Trap instruction (TRAP). */
1283 return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1286 /* FIXME: Handle DONE and RETRY instructions. */
1292 /* For conditional branches, return nPC + 4 iff the annul
1294 return (X_A (insn) ? *npc + 4 : 0);
1298 /* For unconditional branches, return the target if its
1299 specified condition is "always" and return nPC + 4 if the
1300 condition is "never". If the annul bit is 1, set *NPC to
1302 if (X_COND (insn) == 0x0)
1303 pc = *npc, offset = 4;
1307 gdb_assert (offset != 0);
1316 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1322 sparc_software_single_step (struct frame_info *frame)
1324 struct gdbarch *arch = get_frame_arch (frame);
1325 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1326 CORE_ADDR npc, nnpc;
1328 CORE_ADDR pc, orig_npc;
1330 pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1331 orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1333 /* Analyze the instruction at PC. */
1334 nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1336 insert_single_step_breakpoint (npc);
1339 insert_single_step_breakpoint (nnpc);
1341 /* Assert that we have set at least one breakpoint, and that
1342 they're not set at the same spot - unless we're going
1343 from here straight to NULL, i.e. a call or jump to 0. */
1344 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1345 gdb_assert (nnpc != npc || orig_npc == 0);
1351 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1353 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1355 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1356 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1360 /* Return the appropriate register set for the core section identified
1361 by SECT_NAME and SECT_SIZE. */
1363 const struct regset *
1364 sparc_regset_from_core_section (struct gdbarch *gdbarch,
1365 const char *sect_name, size_t sect_size)
1367 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1369 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1370 return tdep->gregset;
1372 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1373 return tdep->fpregset;
1379 static struct gdbarch *
1380 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1382 struct gdbarch_tdep *tdep;
1383 struct gdbarch *gdbarch;
1385 /* If there is already a candidate, use it. */
1386 arches = gdbarch_list_lookup_by_info (arches, &info);
1388 return arches->gdbarch;
1390 /* Allocate space for the new architecture. */
1391 tdep = XMALLOC (struct gdbarch_tdep);
1392 gdbarch = gdbarch_alloc (&info, tdep);
1394 tdep->pc_regnum = SPARC32_PC_REGNUM;
1395 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1396 tdep->gregset = NULL;
1397 tdep->sizeof_gregset = 0;
1398 tdep->fpregset = NULL;
1399 tdep->sizeof_fpregset = 0;
1400 tdep->plt_entry_size = 0;
1401 tdep->step_trap = sparc_step_trap;
1403 set_gdbarch_long_double_bit (gdbarch, 128);
1404 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1406 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1407 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1408 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1409 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1410 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1411 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1413 /* Register numbers of various important registers. */
1414 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1415 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1416 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1418 /* Call dummy code. */
1419 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1420 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1421 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1423 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1424 set_gdbarch_stabs_argument_has_addr
1425 (gdbarch, sparc32_stabs_argument_has_addr);
1427 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1429 /* Stack grows downward. */
1430 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1432 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1434 set_gdbarch_frame_args_skip (gdbarch, 8);
1436 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1438 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1439 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1441 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1443 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1445 frame_base_set_default (gdbarch, &sparc32_frame_base);
1447 /* Hook in the DWARF CFI frame unwinder. */
1448 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1449 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1450 StackGhost issues have been resolved. */
1452 /* Hook in ABI-specific overrides, if they have been registered. */
1453 gdbarch_init_osabi (info, gdbarch);
1455 frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1457 /* If we have register sets, enable the generic core file support. */
1459 set_gdbarch_regset_from_core_section (gdbarch,
1460 sparc_regset_from_core_section);
1465 /* Helper functions for dealing with register windows. */
1468 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1476 /* Registers are 64-bit. */
1479 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1481 if (regnum == i || regnum == -1)
1483 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1485 /* Handle StackGhost. */
1486 if (i == SPARC_I7_REGNUM)
1488 ULONGEST wcookie = sparc_fetch_wcookie ();
1489 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1491 store_unsigned_integer (buf + offset, 8, i7 ^ wcookie);
1494 regcache_raw_supply (regcache, i, buf);
1500 /* Registers are 32-bit. Toss any sign-extension of the stack
1504 /* Clear out the top half of the temporary buffer, and put the
1505 register value in the bottom half if we're in 64-bit mode. */
1506 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1512 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1514 if (regnum == i || regnum == -1)
1516 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1519 /* Handle StackGhost. */
1520 if (i == SPARC_I7_REGNUM)
1522 ULONGEST wcookie = sparc_fetch_wcookie ();
1523 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1525 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1528 regcache_raw_supply (regcache, i, buf);
1535 sparc_collect_rwindow (const struct regcache *regcache,
1536 CORE_ADDR sp, int regnum)
1544 /* Registers are 64-bit. */
1547 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1549 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1551 regcache_raw_collect (regcache, i, buf);
1553 /* Handle StackGhost. */
1554 if (i == SPARC_I7_REGNUM)
1556 ULONGEST wcookie = sparc_fetch_wcookie ();
1557 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1559 store_unsigned_integer (buf, 8, i7 ^ wcookie);
1562 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1568 /* Registers are 32-bit. Toss any sign-extension of the stack
1572 /* Only use the bottom half if we're in 64-bit mode. */
1573 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1576 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1578 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1580 regcache_raw_collect (regcache, i, buf);
1582 /* Handle StackGhost. */
1583 if (i == SPARC_I7_REGNUM)
1585 ULONGEST wcookie = sparc_fetch_wcookie ();
1586 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1588 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1591 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1598 /* Helper functions for dealing with register sets. */
1601 sparc32_supply_gregset (const struct sparc_gregset *gregset,
1602 struct regcache *regcache,
1603 int regnum, const void *gregs)
1605 const gdb_byte *regs = gregs;
1608 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1609 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1610 regs + gregset->r_psr_offset);
1612 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1613 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1614 regs + gregset->r_pc_offset);
1616 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1617 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1618 regs + gregset->r_npc_offset);
1620 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1621 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1622 regs + gregset->r_y_offset);
1624 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1625 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1627 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1629 int offset = gregset->r_g1_offset;
1631 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1633 if (regnum == i || regnum == -1)
1634 regcache_raw_supply (regcache, i, regs + offset);
1639 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1641 /* Not all of the register set variants include Locals and
1642 Inputs. For those that don't, we read them off the stack. */
1643 if (gregset->r_l0_offset == -1)
1647 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1648 sparc_supply_rwindow (regcache, sp, regnum);
1652 int offset = gregset->r_l0_offset;
1654 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1656 if (regnum == i || regnum == -1)
1657 regcache_raw_supply (regcache, i, regs + offset);
1665 sparc32_collect_gregset (const struct sparc_gregset *gregset,
1666 const struct regcache *regcache,
1667 int regnum, void *gregs)
1669 gdb_byte *regs = gregs;
1672 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1673 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1674 regs + gregset->r_psr_offset);
1676 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1677 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1678 regs + gregset->r_pc_offset);
1680 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1681 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1682 regs + gregset->r_npc_offset);
1684 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1685 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1686 regs + gregset->r_y_offset);
1688 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1690 int offset = gregset->r_g1_offset;
1692 /* %g0 is always zero. */
1693 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1695 if (regnum == i || regnum == -1)
1696 regcache_raw_collect (regcache, i, regs + offset);
1701 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1703 /* Not all of the register set variants include Locals and
1704 Inputs. For those that don't, we read them off the stack. */
1705 if (gregset->r_l0_offset != -1)
1707 int offset = gregset->r_l0_offset;
1709 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1711 if (regnum == i || regnum == -1)
1712 regcache_raw_collect (regcache, i, regs + offset);
1720 sparc32_supply_fpregset (struct regcache *regcache,
1721 int regnum, const void *fpregs)
1723 const gdb_byte *regs = fpregs;
1726 for (i = 0; i < 32; i++)
1728 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1729 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1732 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1733 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1737 sparc32_collect_fpregset (const struct regcache *regcache,
1738 int regnum, void *fpregs)
1740 gdb_byte *regs = fpregs;
1743 for (i = 0; i < 32; i++)
1745 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1746 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1749 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1750 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1756 /* From <machine/reg.h>. */
1757 const struct sparc_gregset sparc32_sunos4_gregset =
1770 /* Provide a prototype to silence -Wmissing-prototypes. */
1771 void _initialize_sparc_tdep (void);
1774 _initialize_sparc_tdep (void)
1776 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1778 /* Initialize the SPARC-specific register types. */