1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "sparc-tdep.h"
39 #include "sparc-ravenscar-thread.h"
43 /* This file implements the SPARC 32-bit ABI as defined by the section
44 "Low-Level System Information" of the SPARC Compliance Definition
45 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
46 lists changes with respect to the original 32-bit psABI as defined
47 in the "System V ABI, SPARC Processor Supplement".
49 Note that if we talk about SunOS, we mean SunOS 4.x, which was
50 BSD-based, which is sometimes (retroactively?) referred to as
51 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
52 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
53 suffering from severe version number inflation). Solaris 2.x is
54 also known as SunOS 5.x, since that's what uname(1) says. Solaris
57 /* Please use the sparc32_-prefix for 32-bit specific code, the
58 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
59 code that can handle both. The 64-bit specific code lives in
60 sparc64-tdep.c; don't add any here. */
62 /* The SPARC Floating-Point Quad-Precision format is similar to
63 big-endian IA-64 Quad-Precision format. */
64 #define floatformats_sparc_quad floatformats_ia64_quad
66 /* The stack pointer is offset from the stack frame by a BIAS of 2047
67 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
68 hosts, so undefine it first. */
72 /* Macros to extract fields from SPARC instructions. */
73 #define X_OP(i) (((i) >> 30) & 0x3)
74 #define X_RD(i) (((i) >> 25) & 0x1f)
75 #define X_A(i) (((i) >> 29) & 1)
76 #define X_COND(i) (((i) >> 25) & 0xf)
77 #define X_OP2(i) (((i) >> 22) & 0x7)
78 #define X_IMM22(i) ((i) & 0x3fffff)
79 #define X_OP3(i) (((i) >> 19) & 0x3f)
80 #define X_RS1(i) (((i) >> 14) & 0x1f)
81 #define X_RS2(i) ((i) & 0x1f)
82 #define X_I(i) (((i) >> 13) & 1)
83 /* Sign extension macros. */
84 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
85 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
86 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
87 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
88 /* Macros to identify some instructions. */
89 /* RETURN (RETT in V8) */
90 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
92 /* Fetch the instruction at PC. Instructions are always big-endian
93 even if the processor operates in little-endian mode. */
96 sparc_fetch_instruction (CORE_ADDR pc)
102 /* If we can't read the instruction at PC, return zero. */
103 if (target_read_memory (pc, buf, sizeof (buf)))
107 for (i = 0; i < sizeof (buf); i++)
108 insn = (insn << 8) | buf[i];
113 /* Return non-zero if the instruction corresponding to PC is an "unimp"
117 sparc_is_unimp_insn (CORE_ADDR pc)
119 const unsigned long insn = sparc_fetch_instruction (pc);
121 return ((insn & 0xc1c00000) == 0);
124 /* Return non-zero if the instruction corresponding to PC is an
125 "annulled" branch, i.e. the annul bit is set. */
128 sparc_is_annulled_branch_insn (CORE_ADDR pc)
130 /* The branch instructions featuring an annul bit can be identified
131 by the following bit patterns:
134 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
135 OP2=2: Branch on Integer Condition Codes (Bcc).
136 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
137 OP2=6: Branch on FP Condition Codes (FBcc).
139 Branch on Integer Register with Prediction (BPr).
141 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
142 coprocessor branch instructions (Op2=7). */
144 const unsigned long insn = sparc_fetch_instruction (pc);
145 const unsigned op2 = X_OP2 (insn);
147 if ((X_OP (insn) == 0)
148 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
149 || ((op2 == 3) && ((insn & 0x10000000) == 0))))
155 /* OpenBSD/sparc includes StackGhost, which according to the author's
156 website http://stackghost.cerias.purdue.edu "... transparently and
157 automatically protects applications' stack frames; more
158 specifically, it guards the return pointers. The protection
159 mechanisms require no application source or binary modification and
160 imposes only a negligible performance penalty."
162 The same website provides the following description of how
165 "StackGhost interfaces with the kernel trap handler that would
166 normally write out registers to the stack and the handler that
167 would read them back in. By XORing a cookie into the
168 return-address saved in the user stack when it is actually written
169 to the stack, and then XOR it out when the return-address is pulled
170 from the stack, StackGhost can cause attacker corrupted return
171 pointers to behave in a manner the attacker cannot predict.
172 StackGhost can also use several unused bits in the return pointer
173 to detect a smashed return pointer and abort the process."
175 For GDB this means that whenever we're reading %i7 from a stack
176 frame's window save area, we'll have to XOR the cookie.
178 More information on StackGuard can be found on in:
180 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
181 Stack Protection." 2001. Published in USENIX Security Symposium
184 /* Fetch StackGhost Per-Process XOR cookie. */
187 sparc_fetch_wcookie (struct gdbarch *gdbarch)
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 struct target_ops *ops = ¤t_target;
194 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
198 /* We should have either an 32-bit or an 64-bit cookie. */
199 gdb_assert (len == 4 || len == 8);
201 return extract_unsigned_integer (buf, len, byte_order);
205 /* The functions on this page are intended to be used to classify
206 function arguments. */
208 /* Check whether TYPE is "Integral or Pointer". */
211 sparc_integral_or_pointer_p (const struct type *type)
213 int len = TYPE_LENGTH (type);
215 switch (TYPE_CODE (type))
221 case TYPE_CODE_RANGE:
222 /* We have byte, half-word, word and extended-word/doubleword
223 integral types. The doubleword is an extension to the
224 original 32-bit ABI by the SCD 2.4.x. */
225 return (len == 1 || len == 2 || len == 4 || len == 8);
228 /* Allow either 32-bit or 64-bit pointers. */
229 return (len == 4 || len == 8);
237 /* Check whether TYPE is "Floating". */
240 sparc_floating_p (const struct type *type)
242 switch (TYPE_CODE (type))
246 int len = TYPE_LENGTH (type);
247 return (len == 4 || len == 8 || len == 16);
256 /* Check whether TYPE is "Complex Floating". */
259 sparc_complex_floating_p (const struct type *type)
261 switch (TYPE_CODE (type))
263 case TYPE_CODE_COMPLEX:
265 int len = TYPE_LENGTH (type);
266 return (len == 8 || len == 16 || len == 32);
275 /* Check whether TYPE is "Structure or Union".
277 In terms of Ada subprogram calls, arrays are treated the same as
278 struct and union types. So this function also returns non-zero
282 sparc_structure_or_union_p (const struct type *type)
284 switch (TYPE_CODE (type))
286 case TYPE_CODE_STRUCT:
287 case TYPE_CODE_UNION:
288 case TYPE_CODE_ARRAY:
297 /* Register information. */
299 static const char *sparc32_register_names[] =
301 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
302 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
303 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
304 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
306 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
307 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
308 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
309 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
311 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
314 /* Total number of registers. */
315 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
317 /* We provide the aliases %d0..%d30 for the floating registers as
318 "psuedo" registers. */
320 static const char *sparc32_pseudo_register_names[] =
322 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
323 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
326 /* Total number of pseudo registers. */
327 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
329 /* Return the name of register REGNUM. */
332 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
334 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
335 return sparc32_register_names[regnum];
337 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
338 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
343 /* Construct types for ISA-specific registers. */
346 sparc_psr_type (struct gdbarch *gdbarch)
348 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
350 if (!tdep->sparc_psr_type)
354 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4);
355 append_flags_type_flag (type, 5, "ET");
356 append_flags_type_flag (type, 6, "PS");
357 append_flags_type_flag (type, 7, "S");
358 append_flags_type_flag (type, 12, "EF");
359 append_flags_type_flag (type, 13, "EC");
361 tdep->sparc_psr_type = type;
364 return tdep->sparc_psr_type;
368 sparc_fsr_type (struct gdbarch *gdbarch)
370 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
372 if (!tdep->sparc_fsr_type)
376 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4);
377 append_flags_type_flag (type, 0, "NXA");
378 append_flags_type_flag (type, 1, "DZA");
379 append_flags_type_flag (type, 2, "UFA");
380 append_flags_type_flag (type, 3, "OFA");
381 append_flags_type_flag (type, 4, "NVA");
382 append_flags_type_flag (type, 5, "NXC");
383 append_flags_type_flag (type, 6, "DZC");
384 append_flags_type_flag (type, 7, "UFC");
385 append_flags_type_flag (type, 8, "OFC");
386 append_flags_type_flag (type, 9, "NVC");
387 append_flags_type_flag (type, 22, "NS");
388 append_flags_type_flag (type, 23, "NXM");
389 append_flags_type_flag (type, 24, "DZM");
390 append_flags_type_flag (type, 25, "UFM");
391 append_flags_type_flag (type, 26, "OFM");
392 append_flags_type_flag (type, 27, "NVM");
394 tdep->sparc_fsr_type = type;
397 return tdep->sparc_fsr_type;
400 /* Return the GDB type object for the "standard" data type of data in
404 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
406 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
407 return builtin_type (gdbarch)->builtin_float;
409 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
410 return builtin_type (gdbarch)->builtin_double;
412 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
413 return builtin_type (gdbarch)->builtin_data_ptr;
415 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
416 return builtin_type (gdbarch)->builtin_func_ptr;
418 if (regnum == SPARC32_PSR_REGNUM)
419 return sparc_psr_type (gdbarch);
421 if (regnum == SPARC32_FSR_REGNUM)
422 return sparc_fsr_type (gdbarch);
424 return builtin_type (gdbarch)->builtin_int32;
427 static enum register_status
428 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
429 struct regcache *regcache,
430 int regnum, gdb_byte *buf)
432 enum register_status status;
434 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
436 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
437 status = regcache_raw_read (regcache, regnum, buf);
438 if (status == REG_VALID)
439 status = regcache_raw_read (regcache, regnum + 1, buf + 4);
444 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
445 struct regcache *regcache,
446 int regnum, const gdb_byte *buf)
448 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
450 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
451 regcache_raw_write (regcache, regnum, buf);
452 regcache_raw_write (regcache, regnum + 1, buf + 4);
455 /* Implement "in_function_epilogue_p". */
458 sparc_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
460 /* This function must return true if we are one instruction after an
461 instruction that destroyed the stack frame of the current
462 function. The SPARC instructions used to restore the callers
463 stack frame are RESTORE and RETURN/RETT.
465 Of these RETURN/RETT is a branch instruction and thus we return
466 true if we are in its delay slot.
468 RESTORE is almost always found in the delay slot of a branch
469 instruction that transfers control to the caller, such as JMPL.
470 Thus the next instruction is in the caller frame and we don't
471 need to do anything about it. */
473 unsigned int insn = sparc_fetch_instruction (pc - 4);
475 return X_RETTURN (insn);
480 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
482 /* The ABI requires double-word alignment. */
483 return address & ~0x7;
487 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
489 struct value **args, int nargs,
490 struct type *value_type,
491 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
492 struct regcache *regcache)
494 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
499 if (using_struct_return (gdbarch, NULL, value_type))
503 /* This is an UNIMP instruction. */
504 store_unsigned_integer (buf, 4, byte_order,
505 TYPE_LENGTH (value_type) & 0x1fff);
506 write_memory (sp - 8, buf, 4);
514 sparc32_store_arguments (struct regcache *regcache, int nargs,
515 struct value **args, CORE_ADDR sp,
516 int struct_return, CORE_ADDR struct_addr)
518 struct gdbarch *gdbarch = get_regcache_arch (regcache);
519 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
520 /* Number of words in the "parameter array". */
521 int num_elements = 0;
525 for (i = 0; i < nargs; i++)
527 struct type *type = value_type (args[i]);
528 int len = TYPE_LENGTH (type);
530 if (sparc_structure_or_union_p (type)
531 || (sparc_floating_p (type) && len == 16)
532 || sparc_complex_floating_p (type))
534 /* Structure, Union and Quad-Precision Arguments. */
537 /* Use doubleword alignment for these values. That's always
538 correct, and wasting a few bytes shouldn't be a problem. */
541 write_memory (sp, value_contents (args[i]), len);
542 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
545 else if (sparc_floating_p (type))
547 /* Floating arguments. */
548 gdb_assert (len == 4 || len == 8);
549 num_elements += (len / 4);
553 /* Integral and pointer arguments. */
554 gdb_assert (sparc_integral_or_pointer_p (type));
557 args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
559 num_elements += ((len + 3) / 4);
563 /* Always allocate at least six words. */
564 sp -= max (6, num_elements) * 4;
566 /* The psABI says that "Software convention requires space for the
567 struct/union return value pointer, even if the word is unused." */
570 /* The psABI says that "Although software convention and the
571 operating system require every stack frame to be doubleword
575 for (i = 0; i < nargs; i++)
577 const bfd_byte *valbuf = value_contents (args[i]);
578 struct type *type = value_type (args[i]);
579 int len = TYPE_LENGTH (type);
581 gdb_assert (len == 4 || len == 8);
585 int regnum = SPARC_O0_REGNUM + element;
587 regcache_cooked_write (regcache, regnum, valbuf);
588 if (len > 4 && element < 5)
589 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
592 /* Always store the argument in memory. */
593 write_memory (sp + 4 + element * 4, valbuf, len);
597 gdb_assert (element == num_elements);
603 store_unsigned_integer (buf, 4, byte_order, struct_addr);
604 write_memory (sp, buf, 4);
611 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
612 struct regcache *regcache, CORE_ADDR bp_addr,
613 int nargs, struct value **args, CORE_ADDR sp,
614 int struct_return, CORE_ADDR struct_addr)
616 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
618 /* Set return address. */
619 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
621 /* Set up function arguments. */
622 sp = sparc32_store_arguments (regcache, nargs, args, sp,
623 struct_return, struct_addr);
625 /* Allocate the 16-word window save area. */
628 /* Stack should be doubleword aligned at this point. */
629 gdb_assert (sp % 8 == 0);
631 /* Finally, update the stack pointer. */
632 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
638 /* Use the program counter to determine the contents and size of a
639 breakpoint instruction. Return a pointer to a string of bytes that
640 encode a breakpoint instruction, store the length of the string in
641 *LEN and optionally adjust *PC to point to the correct memory
642 location for inserting the breakpoint. */
644 static const gdb_byte *
645 sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
647 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
649 *len = sizeof (break_insn);
654 /* Allocate and initialize a frame cache. */
656 static struct sparc_frame_cache *
657 sparc_alloc_frame_cache (void)
659 struct sparc_frame_cache *cache;
661 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
667 /* Frameless until proven otherwise. */
668 cache->frameless_p = 1;
669 cache->frame_offset = 0;
670 cache->saved_regs_mask = 0;
671 cache->copied_regs_mask = 0;
672 cache->struct_return_p = 0;
677 /* GCC generates several well-known sequences of instructions at the begining
678 of each function prologue when compiling with -fstack-check. If one of
679 such sequences starts at START_PC, then return the address of the
680 instruction immediately past this sequence. Otherwise, return START_PC. */
683 sparc_skip_stack_check (const CORE_ADDR start_pc)
685 CORE_ADDR pc = start_pc;
687 int offset_stack_checking_sequence = 0;
688 int probing_loop = 0;
690 /* With GCC, all stack checking sequences begin with the same two
691 instructions, plus an optional one in the case of a probing loop:
693 sethi <some immediate>, %g1
698 sethi <some immediate>, %g1
699 sethi <some immediate>, %g4
704 sethi <some immediate>, %g1
706 sethi <some immediate>, %g4
708 If the optional instruction is found (setting g4), assume that a
709 probing loop will follow. */
711 /* sethi <some immediate>, %g1 */
712 insn = sparc_fetch_instruction (pc);
714 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
717 /* optional: sethi <some immediate>, %g4 */
718 insn = sparc_fetch_instruction (pc);
720 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
723 insn = sparc_fetch_instruction (pc);
727 /* sub %sp, %g1, %g1 */
728 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
729 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
732 insn = sparc_fetch_instruction (pc);
735 /* optional: sethi <some immediate>, %g4 */
736 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
739 insn = sparc_fetch_instruction (pc);
743 /* First possible sequence:
744 [first two instructions above]
745 clr [%g1 - some immediate] */
747 /* clr [%g1 - some immediate] */
748 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
749 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
751 /* Valid stack-check sequence, return the new PC. */
755 /* Second possible sequence: A small number of probes.
756 [first two instructions above]
758 add %g1, -<some immediate>, %g1
760 [repeat the two instructions above any (small) number of times]
761 clr [%g1 - some immediate] */
764 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
765 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
769 /* add %g1, -<some immediate>, %g1 */
770 insn = sparc_fetch_instruction (pc);
772 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
773 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
777 insn = sparc_fetch_instruction (pc);
779 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
780 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
784 /* clr [%g1 - some immediate] */
785 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
786 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
789 /* We found a valid stack-check sequence, return the new PC. */
793 /* Third sequence: A probing loop.
794 [first three instructions above]
798 add %g1, -<some immediate>, %g1
802 And an optional last probe for the remainder:
804 clr [%g4 - some immediate] */
808 /* sub %g1, %g4, %g4 */
809 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
810 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
814 insn = sparc_fetch_instruction (pc);
816 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
817 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
821 insn = sparc_fetch_instruction (pc);
823 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
826 /* add %g1, -<some immediate>, %g1 */
827 insn = sparc_fetch_instruction (pc);
829 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
830 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
834 insn = sparc_fetch_instruction (pc);
836 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
839 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
840 insn = sparc_fetch_instruction (pc);
842 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4
843 && X_RD (insn) == 0 && X_RS1 (insn) == 1
844 && (!X_I(insn) || X_SIMM13 (insn) == 0)))
847 /* We found a valid stack-check sequence, return the new PC. */
849 /* optional: clr [%g4 - some immediate] */
850 insn = sparc_fetch_instruction (pc);
852 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
853 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
859 /* No stack check code in our prologue, return the start_pc. */
863 /* Record the effect of a SAVE instruction on CACHE. */
866 sparc_record_save_insn (struct sparc_frame_cache *cache)
868 /* The frame is set up. */
869 cache->frameless_p = 0;
871 /* The frame pointer contains the CFA. */
872 cache->frame_offset = 0;
874 /* The `local' and `in' registers are all saved. */
875 cache->saved_regs_mask = 0xffff;
877 /* The `out' registers are all renamed. */
878 cache->copied_regs_mask = 0xff;
881 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
882 Bail out early if CURRENT_PC is reached. Return the address where
883 the analysis stopped.
885 We handle both the traditional register window model and the single
886 register window (aka flat) model. */
889 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
890 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
892 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
897 pc = sparc_skip_stack_check (pc);
899 if (current_pc <= pc)
902 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
903 SPARC the linker usually defines a symbol (typically
904 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
905 This symbol makes us end up here with PC pointing at the start of
906 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
907 would do our normal prologue analysis, we would probably conclude
908 that we've got a frame when in reality we don't, since the
909 dynamic linker patches up the first PLT with some code that
910 starts with a SAVE instruction. Patch up PC such that it points
911 at the start of our PLT entry. */
912 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc))
913 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
915 insn = sparc_fetch_instruction (pc);
917 /* Recognize store insns and record their sources. */
918 while (X_OP (insn) == 3
919 && (X_OP3 (insn) == 0x4 /* stw */
920 || X_OP3 (insn) == 0x7 /* std */
921 || X_OP3 (insn) == 0xe) /* stx */
922 && X_RS1 (insn) == SPARC_SP_REGNUM)
924 int regnum = X_RD (insn);
926 /* Recognize stores into the corresponding stack slots. */
927 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
929 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe
930 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS
931 : (regnum - SPARC_L0_REGNUM) * 4))
932 || (!X_I (insn) && regnum == SPARC_L0_REGNUM)))
934 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM));
935 if (X_OP3 (insn) == 0x7)
936 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM));
941 insn = sparc_fetch_instruction (pc + offset);
944 /* Recognize a SETHI insn and record its destination. */
945 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
950 insn = sparc_fetch_instruction (pc + offset);
953 /* Allow for an arithmetic operation on DEST or %g1. */
954 if (X_OP (insn) == 2 && X_I (insn)
955 && (X_RD (insn) == 1 || X_RD (insn) == dest))
959 insn = sparc_fetch_instruction (pc + offset);
962 /* Check for the SAVE instruction that sets up the frame. */
963 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
965 sparc_record_save_insn (cache);
970 /* Check for an arithmetic operation on %sp. */
972 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
973 && X_RS1 (insn) == SPARC_SP_REGNUM
974 && X_RD (insn) == SPARC_SP_REGNUM)
978 cache->frame_offset = X_SIMM13 (insn);
979 if (X_OP3 (insn) == 0)
980 cache->frame_offset = -cache->frame_offset;
984 insn = sparc_fetch_instruction (pc + offset);
986 /* Check for an arithmetic operation that sets up the frame. */
988 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
989 && X_RS1 (insn) == SPARC_SP_REGNUM
990 && X_RD (insn) == SPARC_FP_REGNUM)
992 cache->frameless_p = 0;
993 cache->frame_offset = 0;
994 /* We could check that the amount subtracted to %sp above is the
995 same as the one added here, but this seems superfluous. */
996 cache->copied_regs_mask |= 0x40;
999 insn = sparc_fetch_instruction (pc + offset);
1002 /* Check for a move (or) operation that copies the return register. */
1003 if (X_OP (insn) == 2
1004 && X_OP3 (insn) == 0x2
1006 && X_RS1 (insn) == SPARC_G0_REGNUM
1007 && X_RS2 (insn) == SPARC_O7_REGNUM
1008 && X_RD (insn) == SPARC_I7_REGNUM)
1010 cache->copied_regs_mask |= 0x80;
1021 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1023 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1024 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
1027 /* Return PC of first real instruction of the function starting at
1031 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1033 struct symtab_and_line sal;
1034 CORE_ADDR func_start, func_end;
1035 struct sparc_frame_cache cache;
1037 /* This is the preferred method, find the end of the prologue by
1038 using the debugging information. */
1039 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
1041 sal = find_pc_line (func_start, 0);
1043 if (sal.end < func_end
1044 && start_pc <= sal.end)
1048 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
1050 /* The psABI says that "Although the first 6 words of arguments
1051 reside in registers, the standard stack frame reserves space for
1052 them.". It also suggests that a function may use that space to
1053 "write incoming arguments 0 to 5" into that space, and that's
1054 indeed what GCC seems to be doing. In that case GCC will
1055 generate debug information that points to the stack slots instead
1056 of the registers, so we should consider the instructions that
1057 write out these incoming arguments onto the stack. */
1061 unsigned long insn = sparc_fetch_instruction (start_pc);
1063 /* Recognize instructions that store incoming arguments into the
1064 corresponding stack slots. */
1065 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04
1066 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM)
1068 int regnum = X_RD (insn);
1070 /* Case of arguments still in %o[0..5]. */
1071 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM
1072 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))
1073 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4)
1079 /* Case of arguments copied into %i[0..5]. */
1080 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM
1081 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM)))
1082 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4)
1095 /* Normal frames. */
1097 struct sparc_frame_cache *
1098 sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
1100 struct sparc_frame_cache *cache;
1105 cache = sparc_alloc_frame_cache ();
1106 *this_cache = cache;
1108 cache->pc = get_frame_func (this_frame);
1110 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
1111 get_frame_pc (this_frame), cache);
1113 if (cache->frameless_p)
1115 /* This function is frameless, so %fp (%i6) holds the frame
1116 pointer for our calling frame. Use %sp (%o6) as this frame's
1119 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1123 /* For normal frames, %fp (%i6) holds the frame pointer, the
1124 base address for the current stack frame. */
1126 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
1129 cache->base += cache->frame_offset;
1131 if (cache->base & 1)
1132 cache->base += BIAS;
1138 sparc32_struct_return_from_sym (struct symbol *sym)
1140 struct type *type = check_typedef (SYMBOL_TYPE (sym));
1141 enum type_code code = TYPE_CODE (type);
1143 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
1145 type = check_typedef (TYPE_TARGET_TYPE (type));
1146 if (sparc_structure_or_union_p (type)
1147 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1154 struct sparc_frame_cache *
1155 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
1157 struct sparc_frame_cache *cache;
1163 cache = sparc_frame_cache (this_frame, this_cache);
1165 sym = find_pc_function (cache->pc);
1168 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
1172 /* There is no debugging information for this function to
1173 help us determine whether this function returns a struct
1174 or not. So we rely on another heuristic which is to check
1175 the instruction at the return address and see if this is
1176 an "unimp" instruction. If it is, then it is a struct-return
1180 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1182 pc = get_frame_register_unsigned (this_frame, regnum) + 8;
1183 if (sparc_is_unimp_insn (pc))
1184 cache->struct_return_p = 1;
1191 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
1192 struct frame_id *this_id)
1194 struct sparc_frame_cache *cache =
1195 sparc32_frame_cache (this_frame, this_cache);
1197 /* This marks the outermost frame. */
1198 if (cache->base == 0)
1201 (*this_id) = frame_id_build (cache->base, cache->pc);
1204 static struct value *
1205 sparc32_frame_prev_register (struct frame_info *this_frame,
1206 void **this_cache, int regnum)
1208 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1209 struct sparc_frame_cache *cache =
1210 sparc32_frame_cache (this_frame, this_cache);
1212 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
1214 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
1216 /* If this functions has a Structure, Union or Quad-Precision
1217 return value, we have to skip the UNIMP instruction that encodes
1218 the size of the structure. */
1219 if (cache->struct_return_p)
1223 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1224 pc += get_frame_register_unsigned (this_frame, regnum) + 8;
1225 return frame_unwind_got_constant (this_frame, regnum, pc);
1228 /* Handle StackGhost. */
1230 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1232 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
1234 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1237 /* Read the value in from memory. */
1238 i7 = get_frame_memory_unsigned (this_frame, addr, 4);
1239 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
1243 /* The previous frame's `local' and `in' registers may have been saved
1244 in the register save area. */
1245 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1246 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM))))
1248 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1250 return frame_unwind_got_memory (this_frame, regnum, addr);
1253 /* The previous frame's `out' registers may be accessible as the current
1254 frame's `in' registers. */
1255 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM
1256 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))))
1257 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1259 return frame_unwind_got_register (this_frame, regnum, regnum);
1262 static const struct frame_unwind sparc32_frame_unwind =
1265 default_frame_unwind_stop_reason,
1266 sparc32_frame_this_id,
1267 sparc32_frame_prev_register,
1269 default_frame_sniffer
1274 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1276 struct sparc_frame_cache *cache =
1277 sparc32_frame_cache (this_frame, this_cache);
1282 static const struct frame_base sparc32_frame_base =
1284 &sparc32_frame_unwind,
1285 sparc32_frame_base_address,
1286 sparc32_frame_base_address,
1287 sparc32_frame_base_address
1290 static struct frame_id
1291 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1295 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1298 return frame_id_build (sp, get_frame_pc (this_frame));
1302 /* Extract a function return value of TYPE from REGCACHE, and copy
1303 that into VALBUF. */
1306 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1309 int len = TYPE_LENGTH (type);
1312 gdb_assert (!sparc_structure_or_union_p (type));
1313 gdb_assert (!(sparc_floating_p (type) && len == 16));
1315 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1317 /* Floating return values. */
1318 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1320 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1323 regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8);
1324 regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12);
1328 regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16);
1329 regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20);
1330 regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24);
1331 regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28);
1333 memcpy (valbuf, buf, len);
1337 /* Integral and pointer return values. */
1338 gdb_assert (sparc_integral_or_pointer_p (type));
1340 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1343 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1344 gdb_assert (len == 8);
1345 memcpy (valbuf, buf, 8);
1349 /* Just stripping off any unused bytes should preserve the
1350 signed-ness just fine. */
1351 memcpy (valbuf, buf + 4 - len, len);
1356 /* Store the function return value of type TYPE from VALBUF into
1360 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1361 const gdb_byte *valbuf)
1363 int len = TYPE_LENGTH (type);
1366 gdb_assert (!sparc_structure_or_union_p (type));
1367 gdb_assert (!(sparc_floating_p (type) && len == 16));
1368 gdb_assert (len <= 8);
1370 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1372 /* Floating return values. */
1373 memcpy (buf, valbuf, len);
1374 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1376 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1379 regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8);
1380 regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12);
1384 regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16);
1385 regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20);
1386 regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24);
1387 regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28);
1392 /* Integral and pointer return values. */
1393 gdb_assert (sparc_integral_or_pointer_p (type));
1397 gdb_assert (len == 8);
1398 memcpy (buf, valbuf, 8);
1399 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1403 /* ??? Do we need to do any sign-extension here? */
1404 memcpy (buf + 4 - len, valbuf, len);
1406 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1410 static enum return_value_convention
1411 sparc32_return_value (struct gdbarch *gdbarch, struct value *function,
1412 struct type *type, struct regcache *regcache,
1413 gdb_byte *readbuf, const gdb_byte *writebuf)
1415 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1417 /* The psABI says that "...every stack frame reserves the word at
1418 %fp+64. If a function returns a structure, union, or
1419 quad-precision value, this word should hold the address of the
1420 object into which the return value should be copied." This
1421 guarantees that we can always find the return value, not just
1422 before the function returns. */
1424 if (sparc_structure_or_union_p (type)
1425 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1432 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1433 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1434 read_memory (addr, readbuf, TYPE_LENGTH (type));
1438 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1439 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1440 write_memory (addr, writebuf, TYPE_LENGTH (type));
1443 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1447 sparc32_extract_return_value (type, regcache, readbuf);
1449 sparc32_store_return_value (type, regcache, writebuf);
1451 return RETURN_VALUE_REGISTER_CONVENTION;
1455 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1457 return (sparc_structure_or_union_p (type)
1458 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
1459 || sparc_complex_floating_p (type));
1463 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1465 CORE_ADDR pc = get_frame_address_in_block (this_frame);
1466 struct symbol *sym = find_pc_function (pc);
1469 return sparc32_struct_return_from_sym (sym);
1474 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1475 struct dwarf2_frame_state_reg *reg,
1476 struct frame_info *this_frame)
1482 case SPARC_G0_REGNUM:
1483 /* Since %g0 is always zero, there is no point in saving it, and
1484 people will be inclined omit it from the CFI. Make sure we
1485 don't warn about that. */
1486 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1488 case SPARC_SP_REGNUM:
1489 reg->how = DWARF2_FRAME_REG_CFA;
1491 case SPARC32_PC_REGNUM:
1492 case SPARC32_NPC_REGNUM:
1493 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1495 if (sparc32_dwarf2_struct_return_p (this_frame))
1497 if (regnum == SPARC32_NPC_REGNUM)
1499 reg->loc.offset = off;
1505 /* The SPARC Architecture doesn't have hardware single-step support,
1506 and most operating systems don't implement it either, so we provide
1507 software single-step mechanism. */
1510 sparc_analyze_control_transfer (struct frame_info *frame,
1511 CORE_ADDR pc, CORE_ADDR *npc)
1513 unsigned long insn = sparc_fetch_instruction (pc);
1514 int conditional_p = X_COND (insn) & 0x7;
1515 int branch_p = 0, fused_p = 0;
1516 long offset = 0; /* Must be signed for sign-extend. */
1518 if (X_OP (insn) == 0 && X_OP2 (insn) == 3)
1520 if ((insn & 0x10000000) == 0)
1522 /* Branch on Integer Register with Prediction (BPr). */
1528 /* Compare and Branch */
1531 offset = 4 * X_DISP10 (insn);
1534 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1536 /* Branch on Floating-Point Condition Codes (FBfcc). */
1538 offset = 4 * X_DISP22 (insn);
1540 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1542 /* Branch on Floating-Point Condition Codes with Prediction
1545 offset = 4 * X_DISP19 (insn);
1547 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1549 /* Branch on Integer Condition Codes (Bicc). */
1551 offset = 4 * X_DISP22 (insn);
1553 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1555 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1557 offset = 4 * X_DISP19 (insn);
1559 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1561 /* Trap instruction (TRAP). */
1562 return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1565 /* FIXME: Handle DONE and RETRY instructions. */
1571 /* Fused compare-and-branch instructions are non-delayed,
1572 and do not have an annuling capability. So we need to
1573 always set a breakpoint on both the NPC and the branch
1575 gdb_assert (offset != 0);
1578 else if (conditional_p)
1580 /* For conditional branches, return nPC + 4 iff the annul
1582 return (X_A (insn) ? *npc + 4 : 0);
1586 /* For unconditional branches, return the target if its
1587 specified condition is "always" and return nPC + 4 if the
1588 condition is "never". If the annul bit is 1, set *NPC to
1590 if (X_COND (insn) == 0x0)
1591 pc = *npc, offset = 4;
1603 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1609 sparc_software_single_step (struct frame_info *frame)
1611 struct gdbarch *arch = get_frame_arch (frame);
1612 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1613 struct address_space *aspace = get_frame_address_space (frame);
1614 CORE_ADDR npc, nnpc;
1616 CORE_ADDR pc, orig_npc;
1618 pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1619 orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1621 /* Analyze the instruction at PC. */
1622 nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1624 insert_single_step_breakpoint (arch, aspace, npc);
1627 insert_single_step_breakpoint (arch, aspace, nnpc);
1629 /* Assert that we have set at least one breakpoint, and that
1630 they're not set at the same spot - unless we're going
1631 from here straight to NULL, i.e. a call or jump to 0. */
1632 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1633 gdb_assert (nnpc != npc || orig_npc == 0);
1639 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1641 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1643 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1644 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1648 /* Iterate over core file register note sections. */
1651 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch,
1652 iterate_over_regset_sections_cb *cb,
1654 const struct regcache *regcache)
1656 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1658 cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
1659 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
1663 static struct gdbarch *
1664 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1666 struct gdbarch_tdep *tdep;
1667 struct gdbarch *gdbarch;
1669 /* If there is already a candidate, use it. */
1670 arches = gdbarch_list_lookup_by_info (arches, &info);
1672 return arches->gdbarch;
1674 /* Allocate space for the new architecture. */
1675 tdep = XCNEW (struct gdbarch_tdep);
1676 gdbarch = gdbarch_alloc (&info, tdep);
1678 tdep->pc_regnum = SPARC32_PC_REGNUM;
1679 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1680 tdep->step_trap = sparc_step_trap;
1682 set_gdbarch_long_double_bit (gdbarch, 128);
1683 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1685 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1686 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1687 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1688 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1689 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1690 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1692 /* Register numbers of various important registers. */
1693 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1694 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1695 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1697 /* Call dummy code. */
1698 set_gdbarch_frame_align (gdbarch, sparc32_frame_align);
1699 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1700 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1701 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1703 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1704 set_gdbarch_stabs_argument_has_addr
1705 (gdbarch, sparc32_stabs_argument_has_addr);
1707 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1709 /* Stack grows downward. */
1710 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1712 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1714 set_gdbarch_frame_args_skip (gdbarch, 8);
1716 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1718 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1719 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1721 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1723 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1725 frame_base_set_default (gdbarch, &sparc32_frame_base);
1727 /* Hook in the DWARF CFI frame unwinder. */
1728 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1729 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1730 StackGhost issues have been resolved. */
1732 /* Hook in ABI-specific overrides, if they have been registered. */
1733 gdbarch_init_osabi (info, gdbarch);
1735 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1737 /* If we have register sets, enable the generic core file support. */
1739 set_gdbarch_iterate_over_regset_sections
1740 (gdbarch, sparc_iterate_over_regset_sections);
1742 register_sparc_ravenscar_ops (gdbarch);
1747 /* Helper functions for dealing with register windows. */
1750 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1752 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1753 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1760 /* Registers are 64-bit. */
1763 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1765 if (regnum == i || regnum == -1)
1767 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1769 /* Handle StackGhost. */
1770 if (i == SPARC_I7_REGNUM)
1772 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1775 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1776 store_unsigned_integer (buf + offset, 8, byte_order,
1780 regcache_raw_supply (regcache, i, buf);
1786 /* Registers are 32-bit. Toss any sign-extension of the stack
1790 /* Clear out the top half of the temporary buffer, and put the
1791 register value in the bottom half if we're in 64-bit mode. */
1792 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1798 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1800 if (regnum == i || regnum == -1)
1802 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1805 /* Handle StackGhost. */
1806 if (i == SPARC_I7_REGNUM)
1808 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1811 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1812 store_unsigned_integer (buf + offset, 4, byte_order,
1816 regcache_raw_supply (regcache, i, buf);
1823 sparc_collect_rwindow (const struct regcache *regcache,
1824 CORE_ADDR sp, int regnum)
1826 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1827 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1834 /* Registers are 64-bit. */
1837 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1839 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1841 regcache_raw_collect (regcache, i, buf);
1843 /* Handle StackGhost. */
1844 if (i == SPARC_I7_REGNUM)
1846 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1849 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1850 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie);
1853 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1859 /* Registers are 32-bit. Toss any sign-extension of the stack
1863 /* Only use the bottom half if we're in 64-bit mode. */
1864 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1867 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1869 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1871 regcache_raw_collect (regcache, i, buf);
1873 /* Handle StackGhost. */
1874 if (i == SPARC_I7_REGNUM)
1876 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1879 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1880 store_unsigned_integer (buf + offset, 4, byte_order,
1884 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1891 /* Helper functions for dealing with register sets. */
1894 sparc32_supply_gregset (const struct sparc_gregmap *gregmap,
1895 struct regcache *regcache,
1896 int regnum, const void *gregs)
1898 const gdb_byte *regs = gregs;
1899 gdb_byte zero[4] = { 0 };
1902 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1903 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1904 regs + gregmap->r_psr_offset);
1906 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1907 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1908 regs + gregmap->r_pc_offset);
1910 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1911 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1912 regs + gregmap->r_npc_offset);
1914 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1915 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1916 regs + gregmap->r_y_offset);
1918 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1919 regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero);
1921 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1923 int offset = gregmap->r_g1_offset;
1925 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1927 if (regnum == i || regnum == -1)
1928 regcache_raw_supply (regcache, i, regs + offset);
1933 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1935 /* Not all of the register set variants include Locals and
1936 Inputs. For those that don't, we read them off the stack. */
1937 if (gregmap->r_l0_offset == -1)
1941 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1942 sparc_supply_rwindow (regcache, sp, regnum);
1946 int offset = gregmap->r_l0_offset;
1948 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1950 if (regnum == i || regnum == -1)
1951 regcache_raw_supply (regcache, i, regs + offset);
1959 sparc32_collect_gregset (const struct sparc_gregmap *gregmap,
1960 const struct regcache *regcache,
1961 int regnum, void *gregs)
1963 gdb_byte *regs = gregs;
1966 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1967 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1968 regs + gregmap->r_psr_offset);
1970 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1971 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1972 regs + gregmap->r_pc_offset);
1974 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1975 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1976 regs + gregmap->r_npc_offset);
1978 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1979 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1980 regs + gregmap->r_y_offset);
1982 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1984 int offset = gregmap->r_g1_offset;
1986 /* %g0 is always zero. */
1987 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1989 if (regnum == i || regnum == -1)
1990 regcache_raw_collect (regcache, i, regs + offset);
1995 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1997 /* Not all of the register set variants include Locals and
1998 Inputs. For those that don't, we read them off the stack. */
1999 if (gregmap->r_l0_offset != -1)
2001 int offset = gregmap->r_l0_offset;
2003 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2005 if (regnum == i || regnum == -1)
2006 regcache_raw_collect (regcache, i, regs + offset);
2014 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap,
2015 struct regcache *regcache,
2016 int regnum, const void *fpregs)
2018 const gdb_byte *regs = fpregs;
2021 for (i = 0; i < 32; i++)
2023 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2024 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i,
2025 regs + fpregmap->r_f0_offset + (i * 4));
2028 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2029 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM,
2030 regs + fpregmap->r_fsr_offset);
2034 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap,
2035 const struct regcache *regcache,
2036 int regnum, void *fpregs)
2038 gdb_byte *regs = fpregs;
2041 for (i = 0; i < 32; i++)
2043 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2044 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i,
2045 regs + fpregmap->r_f0_offset + (i * 4));
2048 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2049 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM,
2050 regs + fpregmap->r_fsr_offset);
2056 /* From <machine/reg.h>. */
2057 const struct sparc_gregmap sparc32_sunos4_gregmap =
2069 const struct sparc_fpregmap sparc32_sunos4_fpregmap =
2075 const struct sparc_fpregmap sparc32_bsd_fpregmap =
2082 /* Provide a prototype to silence -Wmissing-prototypes. */
2083 void _initialize_sparc_tdep (void);
2086 _initialize_sparc_tdep (void)
2088 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);